A scheduling method applied to a directed acyclic graph and related equipment

Abstract

The embodiment of the application belongs to the technical field of resource scheduling optimization of artificial intelligence, and relates to a scheduling method and device applied to a directed acyclic graph, computer equipment and a storage medium. The method considers a DAG of a simple memory model. In each iteration process, the next node is selected based on the scheduling scheme of the current state, but the states required for participating in the next iteration are limited to the optimal limited number of states obtained in the current iteration. The application only retains the k states with the most potential to enter the next iteration, which greatly reduces the search space and reduces the time complexity of the algorithm. In the iteration process, the algorithm continuously selects the node with the minimum memory peak value influence to join the execution sequence, ensuring that the scheduling path close to the optimal solution can still be explored under limited computing resources. This strategy not only improves the execution efficiency of the algorithm, but also guarantees the quality of the scheduling scheme, and realizes the optimization balance of memory use and computing time.

Description

TECHNICAL FIELD

[0001] The present application relates to the resource scheduling optimization technical field of artificial intelligence, and in particular to a scheduling method applied to a directed acyclic graph and related equipment. BACKGROUND

[0002] With the increasing complexity of scientific research, the automation of scientific data management and computing tasks has become a key factor in improving research efficiency. In this context, scientific workflows are widely used and are often modeled by directed acyclic graphs (DAG). The DAG model effectively represents computing modules (tasks) and their dependencies, which are often embodied as data generated by one task being used by another task. This approach not only clearly demonstrates the workflow, but also facilitates the collaborative execution and resource management between tasks. Based on DAG, the system can dynamically allocate tasks to various resources on the computing platform, especially for complex and heterogeneous computing environments. Through scheduling algorithms, the execution order of tasks and resource allocation strategies can be automatically optimized according to the dependencies between tasks, resource availability, and task execution requirements, thereby improving computing efficiency and resource utilization.

[0003] However, the applicant found that the traditional task scheduling algorithm is difficult to adapt to the solution of the scheduling sequence of "large data, low memory peak, and less time". SUMMARY

[0004] The purpose of the embodiments of the present application is to propose a scheduling method, device, computer equipment and storage medium applied to a directed acyclic graph, to solve the problem that the traditional task scheduling algorithm is difficult to adapt to the solution of the scheduling sequence of "large data, low memory peak, and less time".

[0005] To solve the above technical problems, the embodiments of the present application provide a scheduling method applied to a directed acyclic graph, which is applied to a data processing model and adopts the following technical solutions:

[0006] Real-time acquisition of state set information of the current round of the data processing model, wherein the state set information is represented as:

[0007] M i [z i ]←(s i ,μ i ,μ peak,i )

[0008] Wherein, represents when i nodes have been selected, the current in-degree of the node set z i is 0, the execution sequence is si , current memory is μ i , historical memory peak is μ peak,i ;

[0009] When a new task node corresponding to the data processing model is received, the new task node is added to the execution sequence, and a memory update operation is performed on the state set information to obtain an updated state set;

[0010] According to a preset filtering number, a filtering operation is performed on the updated state set to obtain an optimal state set;

[0011] The optimal state set is taken as state set information of a next round.

[0012] Further, the memory μ new of the updated state set is represented as:

[0013] μ new ← μ old -in_sum(u) + out_sum(u)

[0014] Wherein, μ new represents an updated memory, μ old represents a memory before updating, in_sum(u) represents a sum of edge weights of all incoming edges of node u, and out_sum(u) represents a sum of edge weights of all outgoing edges of node u.

[0015] Further, the step of performing a filtering operation on the updated state set according to a preset filtering number to obtain an optimal state set specifically includes the following steps:

[0016] Obtaining a memory change amount of each execution node in the updated state set;

[0017] Performing a sorting operation on the execution nodes according to the memory change amount, and taking a preset filtering number of execution nodes with the least memory change amount as a scheduling sequence of the optimal state set.

[0018] Further, the step of performing a filtering operation on the updated state set according to a preset filtering number to obtain an optimal state set specifically includes the following steps:

[0019] Obtaining a memory occupation amount of each execution node in the updated state set;

[0020] Performing a sorting operation on the execution nodes according to the memory occupation amount, and taking a preset filtering number of execution nodes with the least memory occupation amount as a scheduling sequence of the optimal state set.

[0021] To solve the above technical problems, the embodiment of the present application further provides a scheduling device applied to a directed acyclic graph, which is applied to a data processing model and adopts the following technical scheme:

[0022] a state information acquisition module, configured to acquire state set information of a current round of the data processing model in real time, wherein the state set information is represented as:

[0023] M i [z i ]←(s i ,μ i ,μ peak,i )

[0024] wherein z i represents a set of nodes with a current in-degree of 0 when i nodes have been selected, s i represents an execution sequence, μ i represents a current memory, and μ peak,i represents a historical memory peak value;

[0025] a memory updating module, configured to add a new task node corresponding to the data processing model to the execution sequence and perform a memory updating operation on the state set information to obtain an updated state set when the new task node is received;

[0026] a screening module, configured to perform a screening operation on the updated state set according to a preset screening quantity to obtain an optimal state set;

[0027] a next round state confirmation module, configured to take the optimal state set as state set information of a next round.

[0028] Further, the memory μ new of the updated state set is represented as:

[0029] μ new ←μ old -in_sum(u)+out_sum(u)

[0030] wherein μ new represents an updated memory, μ old represents a memory before updating, in_sum(u) represents a sum of edge weights of all in-edges of a node u, and out_sum(u) represents a sum of edge weights of all out-edges of the node u.

[0031] Further, the screening module comprises:

[0032] a memory change amount acquisition submodule, configured to acquire a memory change amount of each execution node in the updated state set;

[0033] The memory change amount ordering submodule is configured to sort the execution nodes according to the memory change amount, and select a preset number of execution nodes with the smallest memory change amount as the scheduling sequence of the optimal state set.

[0034] Further, the screening module comprises:

[0035] The memory occupation amount obtaining submodule is configured to obtain the memory occupation amount of each execution node in the update state set.

[0036] The memory occupation amount ordering submodule is configured to sort the execution nodes according to the memory occupation amount, and select a preset number of execution nodes with the smallest memory occupation amount as the scheduling sequence of the optimal state set.

[0037] To solve the above technical problems, the embodiment of the application further provides a computer device, which adopts the technical scheme as follows:

[0038] The computer device comprises a memory and a processor, and the memory stores computer readable instructions, and the processor implements the steps of the scheduling method for a directed acyclic graph when executing the computer readable instructions.

[0039] To solve the above technical problems, the embodiment of the application further provides a computer readable storage medium, which adopts the technical scheme as follows:

[0040] The computer readable storage medium stores computer readable instructions, and the computer readable instructions are executed by the processor to implement the steps of the scheduling method for a directed acyclic graph.

[0041] The application provides a scheduling method for a directed acyclic graph, which is applied to a data processing model and comprises the following steps: i [z i ]←(s i ,μ i ,μ peak,i ), wherein s i represents the execution sequence, μ i represents the current memory, μ i represents the historical memory peak value, and z peak,iWhen a new task node corresponding to the data processing model is received, the new task node is added to the execution sequence, and a memory update operation is performed on the state set information to obtain an updated state set; the updated state set is subjected to a screening operation according to a preset screening quantity to obtain an optimal state set; and the optimal state set is taken as state set information of a next round. Compared with the prior art, the present application only retains k states with the most potential to enter the next round of iteration, which greatly reduces the search space and reduces the time complexity of the algorithm. In the iteration process, the algorithm constantly screens out nodes with the smallest influence on the memory peak value to join the execution sequence, ensuring that the scheduling path close to the optimal solution can still be explored under limited computing resources. This strategy not only improves the execution efficiency of the algorithm, but also guarantees the quality of the scheduling scheme, achieving an optimized balance between memory usage and computing time. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the scheme in the present application, the drawings needed in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0043] Figure 1 is an exemplary system architecture diagram to which the present application can be applied;

[0044] Figure 2 is an implementation flowchart of the scheduling method applied to the directed acyclic graph provided by Embodiment One of the present application;

[0045] Figure 3 is a structural schematic diagram of one embodiment of the data processing model provided by Embodiment One of the present application;

[0046] Figure 4 is a schematic diagram of experimental data of the memory peak value of the scheduling scheme obtained by running the dynamic programming algorithm and the approximate dynamic programming algorithm on a large-scale random graph provided by Embodiment One of the present application;

[0047] Figure 5 is a structural schematic diagram of the scheduling device applied to the directed acyclic graph provided by Embodiment Two of the present application;

[0048] Figure 6 is a structural schematic diagram of one embodiment of the computer device according to the present application. DETAILED DESCRIPTION

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application; the use herein of terms such as "comprise" and "comprising", "have" and "having", "include" and "including" and "contain" and "containing" are to be construed in an open, non-exhaustive way, i.e. in the sense of "including, but not limited to"; the use herein of terms such as "first", "second", and "other" are used to distinguish one object from another, and are not used to describe a particular sequential order.

[0050] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another.

[0051] For better understanding of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings.

[0052] As shown in Figure 1 The system architecture 100 can include terminal devices 101, 102, 103, a network 104, and a server 105. The network 104 is a medium for providing a communication link between the terminal devices 101, 102, 103 and the server 105. The network 104 can include various connection types, such as wired, wireless communication links, or optical fiber cables, etc.

[0053] A user can use the terminal devices 101, 102, 103 to interact with the server 105 through the network 104 to receive or send messages, etc. Various communication client applications can be installed on the terminal devices 101, 102, 103, such as web browser applications, shopping applications, search applications, instant messaging tools, email clients, social platform software, etc.

[0054] The terminal devices 101, 102, 103 can be various electronic devices with display screens and supporting web browsing, including but not limited to smartphones, tablet computers, e-book readers, MP3 (Moving Picture Experts Group Audio Layer III) players, MP4 (Moving Picture Experts Group Audio Layer IV) players, laptop portable computers, and desktop computers, etc.

[0055] The server 105 can be a server providing various services, for example, a background server providing support for a page displayed on the terminal device 101, 102, 103.

[0056] It should be noted that the scheduling method applied to the directed acyclic graph provided in the embodiments of the present application is generally executed by a server / terminal device, and accordingly, the scheduling device applied to the directed acyclic graph is generally arranged in the server / terminal device.

[0057] It should be understood that Figure 1 The number of terminal devices, networks and servers in the foregoing is merely illustrative. According to the implementation needs, there can be any number of terminal devices, networks and servers.

[0058] With reference to the foregoing Figure 2 , a flowchart of one embodiment of the scheduling method applied to the directed acyclic graph according to the present application is shown. The scheduling method applied to the directed acyclic graph of the foregoing is applied to a data processing model, and the method comprises steps S201, S202, S203, S204, S205, S206 and S207.

[0059] In step S201, the state set information of the current round of the data processing model is acquired in real time, wherein the state set information is represented as:

[0060] M i [z i ]←(s i ,μ i ,μ peak,i )

[0061] Wherein, represents when i nodes have been selected, the set of nodes with a current in-degree of 0 is z i , the execution sequence is s i , the current memory is μ i , and the historical memory peak value is μ peak,i .

[0062] In the embodiments of the present application, the data processing model refers to a simple memory model, specifically, the data processing model can be a simple data flow model defined by Lor is Marchal et al. in the paper Parallel scheduling of DAGs under memory constraints. Specifically, the simple memory model is a simplified data processing model designed for large-scale data processing. Its main goal is to enable developers to focus on the logical part of data processing, without having to worry about the specific implementation details of parallel computing.

[0063] In the embodiments of the present application, a directed acyclic graph DAG=(V, E) is defined based on the data processing model, where tasks i are represented by nodes i∈V and the dependencies between tasks are represented by directed edges e∈E. For an edge e=(i, j), the edge weight w e or w i,j represents the amount of data that needs to be transferred from task node i to task node j after the execution of task node i. It is assumed that when task i starts execution, all input data of i is immediately deleted from memory, and all output data of i is allocated to memory. Then we define all data that needs to be produced and consumed by the execution of task node u as follows:

[0064]

[0065] In the embodiments of the present application, a directed acyclic graph (DAG) is a graph data structure composed of vertices and edges, where each edge is directed from one vertex to another, and there is no cycle in the graph (i.e., there is no path that starts and ends at the same vertex). DAG has a wide range of applications in computer science and many other fields, especially in scheduling and dependency management using DAG. In the application of DAG scheduling, the vertices of DAG usually represent tasks that need to be executed, and the edges represent the dependencies between tasks. For example, task c depends on the completion of task a, so there will be an edge from vertex c to vertex a in DAG, as shown in Figure 3 Since DAG does not contain cycles, the execution order of tasks can be easily determined by topological sorting and other algorithms to satisfy all dependencies.

[0066] In the embodiments of the present application, the state of the data processing model can be defined as:

[0067] M i [z i ]←(s i ,μ i ,μ peak,i )

[0068] where z i represents the set of nodes with in-degree 0 after i nodes have been selected, s i is the execution sequence, μ i is the current memory, and μ peak,i is the historical memory peak.

[0069] The boundary conditions of the data processing model are:

[0070] s0←[], μ0←0, μ peak,0 ←0, z0←zero_indegree(s0, G)

[0071] M0[z0]←(s0, μ0, μ peak,0 )

[0072] where zero-indegree(s, G) returns the set of nodes with in-degree zero after removing the set of nodes s from the directed acyclic graph (G).

[0073] In step S202, when a new task node corresponding to the data processing model is received, the new task node is added to the execution sequence, and a memory update operation is performed on the state set information, to obtain an updated state set.

[0074] In an embodiment of the present application, updating the current memory can be performed according to the following manner:

[0075] μ new ← μ old -in_sum(u) + out_sum(u)

[0076] where μ new represents the updated memory, μ old represents the memory before updating, in_sum(u) represents the sum of edge weights of all incoming edges of node u, and out_sum(u) represents the sum of edge weights of all outgoing edges of node u.

[0077] In step S203, a filtering operation is performed on the updated state set according to a preset filtering number, to obtain an optimal state set.

[0078] In an embodiment of the present application, the preset filtering number is mainly used to determine the number of states with the minimum current memory participating in the generation of the state set Mi+1 in the next round.

[0079] In step S204, the optimal state set is taken as the state set information in the next round.

[0080] In an embodiment of the present application, the pseudo code is as follows:

[0081]

[0082]

[0083]

[0084] In an embodiment of the present application, a scheduling method applied to a directed acyclic graph is provided, including: acquiring, in real time, state set information of a current round of a data processing model, where the state set information is represented as: M i [zi ]←(s i ,μ i ,μ peak,i ), wherein represents when i nodes have been selected, the set of nodes with the current in-degree of 0 is z i , the execution sequence is s i , the current memory is μ i , and the historical memory peak value is μ peak,i ; when a new task node corresponding to the data processing model is received, the new task node is added to the execution sequence, and a memory updating operation is performed on the state set information to obtain an updated state set; a filtering operation is performed on the updated state set according to a preset filtering quantity to obtain an optimal state set; and the optimal state set is taken as state set information of a next round. Compared with the prior art, the present application only retains k states with the most potential to enter the next iteration, which greatly reduces the search space and reduces the time complexity of the algorithm. In the iteration process, the algorithm constantly filters out nodes with the smallest impact on the memory peak value to join the execution sequence, ensuring that the scheduling path close to the optimal solution can still be explored under limited computing resources. This strategy not only improves the execution efficiency of the algorithm, but also guarantees the quality of the scheduling scheme, achieving an optimized balance between memory usage and computing time.

[0085] In some optional implementation manners of the embodiment, step S203 specifically includes the following steps:

[0086] Obtain the memory change amount of each execution node in the updated state set;

[0087] Perform a sorting operation on the execution nodes according to the memory change amount, and take the preset filtering quantity of execution nodes with the smallest memory change amount as the scheduling sequence of the optimal state set.

[0088] In the embodiment, the sensitivity analysis of the memory peak value change is integrated when the next execution node is selected. By giving priority to the nodes with the smallest impact on the current memory peak value, it is ensured that the generated scheduling sequence can meet the task dependency while minimizing the memory peak value, which is an important supplement to the traditional dynamic programming method. This strategy significantly reduces memory usage in practice, especially in memory resource-constrained scenarios.

[0089] In some optional implementation manners of the embodiment, step S203 specifically includes the following steps:

[0090] Obtain the memory usage of each execution node in the updated state set;

[0091] Perform a sorting operation on the execution nodes according to the memory usage, and take the preset filtering quantity of execution nodes with the smallest memory usage as the scheduling sequence of the optimal state set.

[0092] In the embodiments of the present application, in order to further improve the efficiency of the algorithm, the mechanism of dynamically managing the state set is introduced to ensure that only the k states with the lowest memory consumption are focused on in each iteration stage. This mechanism not only reduces the computational burden, but also excludes a large number of non-optimal solution paths through effective state pruning, so that the algorithm can concentrate resources on the most promising solution space and accelerate convergence to a high-quality solution.

[0093] In practical applications, Table 1 below shows experimental data of memory peak values of scheduling schemes obtained by running different algorithms on random graphs of different sizes. The present application can determine that the memory peak value is close to the theoretically optimal scheduling scheme, while the memory peak values obtained by other algorithms deviate greatly from the theoretically optimal value.

[0094]

[0095] Table 1 Experimental data of memory peak values of scheduling schemes obtained by running different algorithms on random graphs of different sizes

[0096] In practical applications, Table 2 below shows experimental data of time consumed by running the dynamic programming algorithm and the approximate dynamic programming algorithm on random graphs of different sizes (in seconds). The present application can determine that the memory peak value is close to the theoretically optimal scheduling scheme, while the memory peak values obtained by other algorithms deviate greatly from the theoretically optimal value.

[0097]

[0098] Table 2 Experimental data of time consumed by running the dynamic programming algorithm and the approximate dynamic programming algorithm on random graphs of different sizes

[0099] In practical applications, Figure 4 shows experimental data of memory peak values of scheduling schemes obtained by running the dynamic programming algorithm and the approximate dynamic programming algorithm on large-scale random graphs. The memory peak value determined by the present application is very close to the memory peak value determined by the theoretically optimal scheduling scheme.

[0100] In summary, the essence of the present application lies in developing an innovative approximate dynamic programming algorithm designed specifically for solving directed graph scheduling problems, especially for complex computing tasks under memory-limited conditions, wherein:

[0101] 1) Iterative state pruning and efficient exploration: This application uses a carefully designed iterative strategy, retaining only the most promising k states for the next round of iteration, which greatly reduces the search space and reduces the time complexity of the algorithm. During the iteration process, the algorithm constantly filters out the nodes with the smallest impact on memory peak to join the execution sequence, ensuring that near-optimal solutions can still be explored under limited computing resources. This strategy not only improves the efficiency of the algorithm, but also guarantees the quality of the scheduling scheme, achieving an optimal balance between memory usage and computing time.

[0102] 2) Memory peak-sensitive node selection logic: When selecting the next execution node, the algorithm incorporates sensitivity analysis of memory peak changes. By prioritizing nodes that have the least impact on the current memory peak, the generated scheduling sequence can minimize memory usage while meeting task dependencies. This is an important complement to traditional dynamic programming methods. This strategy significantly reduces memory usage in practice, especially in memory-constrained scenarios.

[0103] 3) Dynamic state set management and pruning mechanism: To further improve algorithm efficiency, this application introduces a dynamic state set management mechanism, ensuring that only the k states with the lowest memory consumption are considered at each iteration stage. This mechanism not only reduces computational burden, but also eliminates a large number of non-optimal solution paths through effective state pruning, allowing the algorithm to concentrate resources on the most promising solution space and accelerate convergence to high-quality solutions.

[0104] 4) Generalization and robustness enhancement: This application performs well under different graph patterns and graph sparsity, thanks to its effective state exploration and optimization strategies. Even in complex or extremely sparse graphs, this algorithm can still find near-optimal scheduling solutions in a short time, demonstrating its excellent generalization ability and robustness. This is crucial for handling diverse computational task scheduling problems in the real world.

[0105] 5) Flexible applicability of memory models: Although this application is based on a simple memory model, its algorithm design is flexible and can be applied to ordinary memory models. Through the conversion method mentioned in the paper, the approximate dynamic programming algorithm of this application can seamlessly integrate different memory management mechanisms, expanding its application range and providing an effective task scheduling tool for cloud computing, edge computing, and other diverse computing environments.

[0106] The approximate dynamic programming algorithm of the present application realizes technical innovations in the memory-constrained directed graph scheduling problem, from state selection optimization, memory sensitivity enhancement, intelligent management of state sets, to generalization and robustness improvement of the algorithm, each of which is an important breakthrough over the prior art, providing a powerful tool for solving the contradiction between memory and computing efficiency.

[0107] Embodiments of the present application can acquire and process related data based on artificial intelligence technology. Among them, artificial intelligence (Artificial Intelligence, AI) is to use digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results.

[0108] Artificial intelligence basic technologies generally include technologies such as sensors, special artificial intelligence chips, cloud computing, distributed storage, big data processing technology, operation / interaction system, mechatronics, etc. Artificial intelligence software technology mainly includes computer vision technology, robot technology, biometric technology, speech processing technology, natural language processing technology, and machine learning / deep learning, etc. The present application can be applied to the field of directed acyclic graph scheduling X, thereby promoting the construction of smart cities.

[0109] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by computer readable instructions instructing related hardware, and the computer readable instructions can be stored in a computer readable storage medium. The program can include the processes of the above-mentioned embodiments when executed, wherein the storage medium can be a non-volatile storage medium such as a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0110] It should be understood that although each step in the flowchart of the accompanying drawings is shown in sequence according to the direction of the arrow, these steps are not necessarily executed in sequence according to the direction of the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and they can be executed in other orders. Moreover, at least part of the steps in the flowchart of the accompanying drawings can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or sub-steps or stages of other steps.

[0111] Embodiment two

[0112] Further reference Figure 5 As a response to the above Figure 2 The implementation of the method shown in this application provides an embodiment of a scheduling device applied to a directed acyclic graph, which is similar to... Figure 2 Corresponding to the method embodiments shown, this device can be specifically applied to various electronic devices.

[0113] like Figure 5 As shown, the scheduling device 200 applied to a directed acyclic graph in this embodiment includes:

[0114] The state information acquisition module 210 is used to acquire the state set information of the current round of the data processing model in real time, wherein the state set information is represented as follows:

[0115] M i [z i ]←(s i ,μ i ,μ peak,i )

[0116] Where z represents the set of nodes with an in-degree of 0 after i nodes have been selected. i When the execution sequence is s i The current memory is μ i Historical peak memory usage was μ peak,i ;

[0117] The memory update module 220 is used to add the new task node to the execution sequence and perform a memory update operation on the state set information when a new task node corresponding to the data processing model is received, so as to obtain an updated state set.

[0118] The filtering module 230 is used to filter the updated state set according to a preset filtering quantity to obtain the optimal state set;

[0119] The next round state confirmation module 240 is used to use the optimal state set as the state set information for the next round.

[0120] In this embodiment, a scheduling device 200 for directed acyclic graphs is provided, including: a state information acquisition module 210, used to acquire the state set information of the current round of the data processing model in real time, wherein the state set information is represented as: M i [z i ]←(s i ,μ i ,μ peak,i ), where z represents the set of nodes with an in-degree of 0 after i nodes have been selected. i When the execution sequence is s i The current memory is μi , the historical memory peak is μ peak,i ; the memory updating module 220 is configured to add a new task node to the execution sequence when receiving the new task node corresponding to the data processing model, and perform a memory updating operation on the state set information to obtain an updated state set; the screening module 230 is configured to perform a screening operation on the updated state set according to a preset screening quantity to obtain an optimal state set; and the next round state confirming module 240 is configured to take the optimal state set as the state set information of the next round. Compared with the prior art, the present application only retains k states with the most potential to enter the next round of iteration, which greatly reduces the search space and reduces the time complexity of the algorithm. In the iteration process, the algorithm constantly screens out nodes with the smallest memory peak influence to join the execution sequence, ensuring that the scheduling path close to the optimal solution can still be explored under limited computing resources. This strategy not only improves the execution efficiency of the algorithm, but also guarantees the quality of the scheduling scheme, achieving an optimized balance between memory usage and computing time.

[0121] In some optional implementations of the present embodiment, the memory μ new of the updated state set is represented as:

[0122] μ new ← μ old -in_sum(u) + out_sum(u)

[0123] wherein μ new represents the updated memory, μ old represents the memory before updating, in_sum(u) represents the edge weight sum of all incoming edges of node u, and out_sum(u) represents the edge weight sum of all outgoing edges of node u.

[0124] In some optional implementations of the present embodiment, the screening module comprises:

[0125] a memory change amount obtaining submodule configured to obtain the memory change amount of each execution node in the updated state set;

[0126] a memory change amount sorting submodule configured to sort the execution nodes according to the memory change amount, and take the preset screening quantity of execution nodes with the smallest memory change amount as the scheduling sequence of the optimal state set.

[0127] In some optional implementations of the present embodiment, the screening module comprises:

[0128] a memory occupation amount obtaining submodule configured to obtain the memory occupation amount of each execution node in the updated state set;

[0129] The memory occupation amount sorting submodule is configured to sort the execution nodes according to the memory occupation amount, and take the preset screening number of execution nodes with the least memory occupation amount as the scheduling sequence of the optimal state set.

[0130] To solve the above technical problems, the embodiment of the present application further provides a computer device. For details, please refer to Figure 6 , Figure 6 The basic structure block diagram of the computer device of the embodiment is shown in the figure.

[0131] The computer device 300 comprises a memory 310, a processor 320 and a network interface 330 which are connected to each other through a system bus. It should be noted that only the computer device 300 with components 310-330 is shown in the figure, but it should be understood that all the shown components are not required to be implemented, and more or less components can be alternatively implemented. Among them, the computer device herein is a device capable of automatically performing numerical calculation and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), digital signal processor (DSP), embedded device, etc.

[0132] The computer device can be a desktop computer, a notebook computer, a palm computer, a cloud server and other computing devices. The computer device can interact with the user through a keyboard, a mouse, a remote controller, a touchpad or a voice control device.

[0133] The memory 310 includes at least one type of readable storage medium, including flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory, etc.), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 310 can be an internal storage unit of the computer device 300, such as a hard disk or memory of the computer device 300. In other embodiments, the memory 310 can also be an external storage device of the computer device 300, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device 300. Of course, the memory 310 can also include both the internal storage unit and the external storage device of the computer device 300. In this embodiment, the memory 310 is generally used to store an operating system and various application software installed on the computer device 300, such as computer readable instructions for the DAG scheduling method, etc. In addition, the memory 310 can also be used to temporarily store various data that has been output or will be output.

[0134] The processor 320 can be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip in some embodiments. The processor 320 is generally used to control the overall operation of the computer device 300. In this embodiment, the processor 320 is used to run computer readable instructions or process data stored in the memory 310, such as running computer readable instructions for the DAG scheduling method.

[0135] The network interface 330 can include a wireless network interface or a wired network interface, which is generally used to establish a communication connection between the computer device 300 and other electronic devices.

[0136] The computer device provided in the present application only retains the most potential k states to enter the next round of iteration, which greatly reduces the search space and reduces the time complexity of the algorithm. During the iteration process, the algorithm continuously filters out the nodes with the smallest impact on memory peak to join the execution sequence, ensuring that the scheduling path close to the optimal solution can still be explored under limited computing resources. This strategy not only improves the execution efficiency of the algorithm, but also guarantees the quality of the scheduling scheme, achieving an optimized balance between memory usage and computing time.

[0137] The application also provides another implementation, that is, providing a computer readable storage medium, which stores computer readable instructions, the computer readable instructions can be executed by at least one processor to make the at least one processor execute the steps of the scheduling method applied to the directed acyclic graph as described above.

[0138] The computer readable storage medium provided by the application only retains the k states with the most potential to enter the next round of iteration, which greatly reduces the search space and reduces the time complexity of the algorithm. In the iteration process, the algorithm constantly filters out the nodes with the smallest impact on the memory peak to join the execution sequence, ensuring that the scheduling path close to the optimal solution can still be explored under limited computing resources. This strategy not only improves the execution efficiency of the algorithm, but also guarantees the quality of the scheduling scheme, achieving an optimized balance between memory usage and computing time.

[0139] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) execute the method described in each embodiment of the application.

[0140] Obviously, the above-described embodiments are only some of the embodiments of the application, not all the embodiments, and the preferred embodiments of the application are given in the drawings, but do not limit the patent scope of the application. The application can be implemented in many different forms, and conversely, the purpose of providing these embodiments is to make the disclosure of the application more thorough and comprehensive. Although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing specific embodiments, or make equivalent replacements to some technical features. Any equivalent structure made by using the content of the specification and drawings, directly or indirectly applied to other related technical fields, is also within the scope of the patent protection of the application.

Claims

1. A scheduling method applied to a directed acyclic graph, characterized in that, The method is applied to a data processing model and includes the following steps: Real-time acquisition of state set information of a current round of the data processing model, wherein the state set information is represented as: Wherein, represents the set of nodes with current in-degree 0 selected from i nodes The execution sequence is , the current memory is , and the historical memory peak is ; When a new task node corresponding to the data processing model is received, the new task node is added to the execution sequence, and a memory update operation is performed on the state set information to obtain an updated state set; According to a preset filtering number, a filtering operation is performed on the updated state set to obtain an optimal state set; The optimal state set is used as state set information of a next round; memory of the update state set is represented as: wherein denotes the updated memory, denotes the updated memory, in_sum(u) denotes the sum of edge weights of all incoming edges of node u, and out_sum(u) denotes the sum of edge weights of all outgoing edges of node u. The step of performing the filtering operation on the updated state set according to the preset filtering number to obtain the optimal state set specifically includes the following steps: Acquisition of memory change amounts of each execution node in the updated state set; According to the memory change amount, the execution nodes are sorted, and a preset filtering number of execution nodes with the smallest memory change amount are used as a scheduling sequence of the optimal state set.

2. The scheduling method applied to a directed acyclic graph according to claim 1, characterized in that, The step of performing the filtering operation on the updated state set according to the preset filtering number to obtain the optimal state set specifically includes the following steps: Acquisition of memory occupation amounts of each execution node in the updated state set; According to the memory occupation amount, the execution nodes are sorted, and a preset filtering number of execution nodes with the smallest memory occupation amount are used as a scheduling sequence of the optimal state set.

3. A scheduling apparatus applied to a directed acyclic graph, characterized by, The device is applied to a data processing model, and the device includes: A state information acquisition module for real-time acquisition of state set information of a current round of the data processing model, wherein the state set information is represented as: Wherein, represents the set of nodes with current in-degree 0 after i nodes have been selected The execution sequence is , the current memory is , and the historical memory peak is ; A memory update module for, when a new task node corresponding to the data processing model is received, adding the new task node to the execution sequence and performing a memory update operation on the state set information to obtain an updated state set; A filtering module for performing a filtering operation on the updated state set according to a preset filtering number to obtain an optimal state set; A next round state confirmation module for using the optimal state set as state set information of a next round; memory of the update state set is represented as: wherein denotes the updated memory, denotes the updated memory, in_sum(u) denotes the sum of edge weights of all incoming edges of node u, and out_sum(u) denotes the sum of edge weights of all outgoing edges of node u. The filtering module includes: A memory change amount acquisition submodule for acquisition of memory change amounts of each execution node in the updated state set; A memory change amount sorting submodule for sorting the execution nodes according to the memory change amount and using a preset filtering number of execution nodes with the smallest memory change amount as a scheduling sequence of the optimal state set.

4. The scheduling apparatus for a directed acyclic graph according to claim 3, wherein, The filtering module includes: A memory occupation amount acquisition submodule for acquisition of memory occupation amounts of each execution node in the updated state set; A memory occupation amount sorting submodule for sorting the execution nodes according to the memory occupation amount and using a preset filtering number of execution nodes with the smallest memory occupation amount as a scheduling sequence of the optimal state set.

5. A computer device including a memory and a processor, the memory storing computer readable instructions, and the processor implementing the steps of the scheduling method for a directed acyclic graph according to any one of claims 1 to 2 when executing the computer readable instructions.

6. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer readable instructions which, when executed by a processor, implement the steps of the scheduling method for a directed acyclic graph according to any one of claims 1 to 2.

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