Low power lcd liquid crystal display driver controller

Abstract

The application provides a low-power-consumption LCD liquid crystal display driving controller, which comprises a charge pump, a comparator, a discrete-time enable controller and a voltage sampler. The charge pump outputs a first voltage; the output end of the comparator is electrically connected with the enable end of the charge pump; the input interface of the discrete-time enable controller receives a clock signal; the discrete-time enable controller outputs a reference enable signal and a comparison enable signal to the comparator; the third output interface of the discrete-time enable controller outputs a sampling enable signal; the voltage sampler outputs a second voltage, a third voltage and a fourth voltage by voltage division on an LCD voltage source; the fourth voltage is input into the negative phase interface of the comparator; the LCD voltage source is electrically connected with the output end of the charge pump; and a voltage selection circuit is used for selecting the LCD voltage source, receiving the second voltage, the third voltage and a ground voltage and outputting to the connection segment code port. The application provides the low-power-consumption LCD liquid crystal display driving controller, which can effectively reduce the chip power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a low-power LCD liquid crystal display driving controller. BACKGROUND

[0002] The application range of LCD liquid crystal display is more and more extensive, and the requirement of power consumption is also higher and higher, especially in battery-powered devices, such as water meter, gas meter in instrument equipment, sphygmomanometer, blood glucose meter in health products, etc. The LCD liquid crystal display adopts segment code type liquid crystal panel, which is composed of an array of numerous pixels, and a driving controller is needed to drive the array. In the existing products, the chip area required by the driving controller is large, the design cost is high, the feedback loop design is difficult, and the power consumption is difficult to meet the increasingly high requirements of the market. SUMMARY

[0003] The low-power LCD liquid crystal display driving controller provided by the present application can effectively reduce the power consumption of the chip.

[0004] The present application provides a low-power LCD liquid crystal display driving controller, comprising:

[0005] A charge pump for outputting a first voltage;

[0006] A comparator, the output end of the comparator is electrically connected with the charge pump enable end, the output end of the comparator outputs a charge pump enable signal to enable the charge pump;

[0007] A discrete-time enable controller, the input interface of the discrete-time enable controller is used for receiving a clock signal, the first output interface of the discrete-time enable controller is used for outputting a reference enable signal to the comparator, the second output interface of the discrete-time enable controller is used for outputting a comparison enable signal to the comparator, and the third output interface of the discrete-time enable controller is used for outputting a sampling enable signal;

[0008] A voltage sampler, the voltage sampler samples and holds the LCD voltage according to the sampling enable signal; the voltage sampler is used for outputting a second voltage, a third voltage and a fourth voltage to the outside through voltage division of the LCD voltage source, wherein the fourth voltage is input to the negative phase interface of the comparator, and the LCD voltage source is electrically connected with the output end of the charge pump.

[0009] A voltage selection circuit, the first input interface of the voltage selection circuit is electrically connected with the LCD voltage source, the second input interface of the voltage selection circuit is used for receiving the second voltage, the third input interface of the voltage selection circuit is used for receiving the third voltage, the fourth input interface of the low-voltage selection circuit is grounded, and the output interface of the voltage selection circuit is used for connecting a segment code port.

[0010] Optionally, the second input interface of the voltage selection circuit receives the second voltage through a first voltage stabilizer, and the third input interface of the voltage selection circuit receives the third voltage through a second voltage stabilizer.

[0011] Optionally, the non-inverting input terminal of the first voltage stabilizer is electrically connected with the second voltage output interface, and the output interface of the first voltage stabilizer is electrically connected with the second input interface of the voltage selection circuit; the inverting input terminal of the first voltage stabilizer is electrically connected with the output terminal of the first voltage stabilizer.

[0012] The non-inverting input terminal of the second voltage stabilizer is electrically connected with the third voltage output interface, and the output interface of the second voltage stabilizer is electrically connected with the third input interface of the voltage selection circuit; the inverting input terminal of the second voltage stabilizer is electrically connected with the output terminal of the second voltage stabilizer.

[0013] Optionally, the non-inverting input terminal of the first voltage stabilizer is electrically connected with the inverting input terminal of the first voltage stabilizer through a switch; and the non-inverting input terminal of the second voltage stabilizer is electrically connected with the inverting input terminal of the second voltage stabilizer through a switch.

[0014] Optionally, the charge pump comprises:

[0015] an oscillator, the oscillator being electrically connected with the comparator output terminal, the oscillator having a first output port, a second output port, a third output port and a fourth output port, wherein the first output port, the second output port and the fourth output port are opposite to the level of the third output port;

[0016] a first MOS transistor, a first end of the first MOS transistor being connected with a power supply voltage source, a gate of the first MOS transistor being electrically connected with the first output port of the oscillator;

[0017] a second MOS transistor, a first end of the second MOS transistor being electrically connected with a second end of the first MOS transistor, a second end of the second MOS transistor being grounded, a gate of the second MOS transistor being electrically connected with the second output port of the oscillator;

[0018] a third MOS transistor, a first end of the third MOS transistor being connected with the power supply voltage source, a gate of the third MOS transistor being electrically connected with the third output port of the oscillator;

[0019] a fourth MOS transistor, a first end of the fourth MOS transistor being electrically connected with a second end of the third MOS transistor, a gate of the fourth MOS transistor being electrically connected with the fourth output port of the oscillator;

[0020] a boosting capacitor, a first end of the boosting capacitor is electrically connected with a second end of the first MOS tube, a second end of the boosting capacitor is electrically connected with a second end of the third MOS tube;

[0021] a first capacitor, a first end of the first capacitor is electrically connected with a second end of the fourth MOS tube, a second end of the first capacitor is grounded.

[0022] Optionally, the oscillator is a 4-step adjustable frequency ring oscillator.

[0023] Optionally, the voltage sampler comprises:

[0024] a voltage dividing resistor string, one end of the voltage dividing resistor string is electrically connected with an LCD voltage source, the other end of the voltage dividing resistor string is grounded;

[0025] a first switch, the first switch is used to control the on-off of the voltage dividing resistor string and the LCD voltage source; the first switch is controlled by the sampling enable signal;

[0026] a second switch, the second switch is used to control the on-off of a second voltage output formed by voltage dividing of a plurality of resistors, the number of the plurality of resistors is at least one less than the total number of the voltage dividing resistor string; the second switch is controlled by the sampling enable signal;

[0027] a third switch, the third switch is used to control the on-off of a third resistor output formed by voltage dividing of one or more resistors; the third switch is controlled by the sampling enable signal;

[0028] a selection switch group, the selection switch group has a plurality of switches, each switch is used to control the on-off of a fourth voltage formed by voltage dividing of a corresponding number of resistors, by changing the on-off of the plurality of switches, the fourth voltage can be controlled to change;

[0029] a second capacitor, a first end of the second capacitor is connected to a second input interface of the voltage selection circuit, a second end of the second capacitor is grounded;

[0030] a third capacitor, a first end of the third capacitor is connected to a third input interface of the voltage selection circuit, a second end of the third capacitor is grounded.

[0031] Optionally, the comparator comprises:

[0032] a built-in bandgap reference module, the built-in bandgap reference module is used to generate a predetermined reference voltage and a predetermined bias current; the built-in bandgap reference module is controlled by the reference enable signal;

[0033] A comparison module, a positive input terminal of the comparison module is electrically connected with the reference voltage, and the bias current is used for providing a bias condition for the comparison module; and the comparison module is controlled by the comparison enable signal.

[0034] Optionally, the reference enable signal, the comparison enable signal and the sampling enable signal generated by the discrete-time enable controller have the same frequency as the clock signal, and the duty cycle of the reference enable signal, the comparison enable signal and the sampling enable signal is 10% to 90%.

[0035] Optionally, the ratio of the fourth voltage to the LCD voltage is 0.1 to 0.9.

[0036] In the technical solution provided by the present application, the discrete-time enable control greatly reduces the power consumption compared with the ordinary continuous-time control mechanism, from tens of muA to several muA; the discrete-time enable control can control the duty cycle of the resistance path conduction time of the voltage selector, thereby reducing the resistance value and reducing the chip area (from the order of MΩ to kΩ) ; after the discrete-time enable control, the low-power design difficulty of the comparator and the reference module is greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 The system block diagram of the low-power LCD liquid crystal display drive controller of an embodiment of the present application is shown in the figure.

[0038] Figure 2 The control timing diagram of the discrete-time enable controller of another embodiment of the low-power LCD liquid crystal display drive controller of the present application is shown in the figure.

[0039] Figure 3 The MOS tube switching timing diagram of the charge pump of another embodiment of the low-power LCD liquid crystal display drive controller of the present application is shown in the figure. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be described clearly and completely below in combination with the drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0041] The embodiments of the present application provide a low-power LCD liquid crystal display drive controller, as shown in the figure, which comprises: Figures 1-3

[0042] A charge pump, the charge pump is used for outputting a first voltage;

[0043] ​a comparator, an output terminal of the comparator being electrically connected with the charge pump enable terminal, and the output terminal of the comparator outputting a charge pump enable signal to enable the charge pump;

[0044] a discrete-time enable controller, an input interface of the discrete-time enable controller being used to receive a clock signal, a first output interface of the discrete-time enable controller being used to output a reference enable signal to the comparator, a second output interface of the discrete-time enable controller being used to output a comparison enable signal to the comparator, and a third output interface of the discrete-time enable controller being used to output a sampling enable signal;

[0045] a voltage sampler, the voltage sampler sampling and holding an LCD voltage according to the sampling enable signal, and the voltage sampler being used to output a second voltage, a third voltage and a fourth voltage to the outside by voltage division of an LCD voltage source, wherein the fourth voltage is input to a negative phase interface of the comparator, and the LCD voltage source is electrically connected with an output terminal of the charge pump.

[0046] a voltage selection circuit, a first input interface of the voltage selection circuit being electrically connected with the LCD voltage source, a second input interface of the voltage selection circuit being used to receive the second voltage, a third input interface of the voltage selection circuit being used to receive the third voltage, a fourth input interface of the low-voltage selection circuit being grounded, and an output interface of the voltage selection circuit being used to connect a segment code port.

[0047] In the technical scheme provided by the embodiment of the present application, the discrete-time enable control greatly reduces power consumption relative to the common continuous-time control mechanism, from tens of μA to several μA; the discrete-time enable control can control the duty cycle of the resistance path conduction time of the voltage selector, thereby reducing the resistance value and reducing the chip area (from MΩ to kΩ); and the discrete-time enable control greatly reduces the difficulty of low-power design of the comparator and the reference module. Through the above technical scheme, the embodiment of the present application generates different LCD voltages, i.e., different VLCD, by selecting different loop negative feedback coefficients.

[0048] As an optional implementation, the second input interface of the voltage selection circuit receives the second voltage through a first voltage stabilizer, and the third input interface of the voltage selection circuit receives the third voltage through a second voltage stabilizer.

[0049] As an optional implementation, a positive phase input terminal of the first voltage stabilizer is electrically connected with the second voltage output interface, an output interface of the first voltage stabilizer is electrically connected with the second input interface of the voltage selection circuit, a negative phase input terminal of the first voltage stabilizer is electrically connected with the output terminal of the first voltage stabilizer, and the second voltage stabilizer is electrically connected with the third input interface of the voltage selection circuit.

[0050] The positive phase input end of the second voltage stabilizer is electrically connected with the third voltage output interface, and the output interface of the second voltage stabilizer is electrically connected with the third input interface of the voltage selection circuit; and the negative phase input end of the second voltage stabilizer is electrically connected with the output end of the second voltage stabilizer.

[0051] As an optional implementation, the positive phase input end of the first voltage stabilizer is electrically connected with the negative phase input end of the first voltage stabilizer through a switch; and the positive phase input end of the second voltage stabilizer is electrically connected with the negative phase input end of the second voltage stabilizer through a switch.

[0052] In some embodiments, the voltage stabilizer is a two-stage AB class folded differential input rail-to-rail OPAMP operational amplifier, and the output end is connected to the negative phase input end to form a unit gain negative feedback output gain; according to different requirements of driving capability, the voltage stabilizer can be enabled to be closed, and the input and output are short-circuited.

[0053] As an optional implementation, the charge pump comprises:

[0054] An oscillator, which is electrically connected with the comparator output end, has a first output port, a second output port, a third output port and a fourth output port, wherein the first output port, the second output port and the fourth output port are opposite to the level of the third output port;

[0055] A first MOS tube, whose first end is connected with a power supply voltage source, and whose gate is electrically connected with the first output port of the oscillator;

[0056] A second MOS tube, whose first end is electrically connected with the second end of the first MOS tube, and whose second end is grounded, and whose gate is electrically connected with the second output end of the oscillator;

[0057] A third MOS tube, whose first end is connected with a power supply voltage source, and whose gate is electrically connected with the third output port of the oscillator;

[0058] A fourth MOS tube, whose first end is electrically connected with the second end of the third MOS tube, and whose gate is electrically connected with the fourth output port of the oscillator;

[0059] A boost capacitor, whose first end is electrically connected with the second end of the first MOS tube, and whose second end is electrically connected with the second end of the third MOS tube

[0060] A first capacitor, whose first end is electrically connected with the second end of the fourth MOS tube, and whose second end is grounded.

[0061] In some embodiments, the low-power charge pump works in discrete time state, the PUMP_EN is enabled after being high, the oscillator is started, the first MOS K1 / second MOS K2 / fourth MOS K4 become high, and the third MOS K3 is low. At this time, the voltage V0 across the boost capacitor C0 is 0, and V1=VDD. Then K1 / K2 / K4 become low, and K3 becomes high. At this time, V0=VDD, wherein VDD is the supply voltage. According to the law of conservation of charge, V1=VLCD=2VDD*C0 / (C0+C1) can be obtained, wherein C0 is the boost capacitor, and C1 is the first capacitor. Each cycle increases the voltage of VLCD by VDD*C0 / (C0+C1). After the voltage value of VLCD reaches the preset value, the charge pump enable signal PUMP_EN output by the comparator module is low, and the charge pump module is turned off. At this time, K1 / K3 / K4 are high, and K2 is low. The connection between VLCD and the charge pump is disconnected until the voltage of VLCD drops below the preset value, and the comparator module CMP detects it. Then, the PUMP_EN signal is pulled high, and then the above charging process is repeated. The oscillator frequency has four adjustable frequencies. The faster the frequency F, the shorter the establishment time of VLCD. The establishment time formula is T=[ΔV / (VDD*F)]*(1+C1 / C0). The specific switching control timing is shown in FIG. 8, wherein ΔV is the total voltage of the voltage rise of VLCD. The capacitor used for charge transfer in the charge pump module is an internal capacitor, which reduces the cost of actual application and saves the area of the system board compared with the external capacitor in the conventional design. Figure 3

[0062] As an optional implementation, the oscillator is a 4-gear adjustable frequency ring oscillator.

[0063] As an optional implementation, the voltage sampler comprises:

[0064] a voltage divider resistor string, one end of the voltage divider resistor string being electrically connected with the LCD voltage source, and the other end of the voltage divider resistor string being grounded;

[0065] a first switch, the first switch being used for controlling the on-off of the voltage divider resistor string and the LCD voltage source; and the first switch being controlled by the sampling enable signal;

[0066] a second switch, the second switch being used for controlling the on-off of a second voltage output formed by the voltage division of a plurality of resistors, the number of the plurality of resistors being at least one less than the total number of the voltage divider resistor string; and the second switch being controlled by the sampling enable signal;

[0067] a third switch, the third switch being used for controlling the on-off of a third resistor output formed by the voltage division of one or more resistors; and the third switch being controlled by the sampling enable signal.​

[0068] The switch group is selected, and has a plurality of switches, each of which is used for controlling the on-off of a fourth voltage formed by voltage division of a corresponding number of resistors, and the fourth voltage can be controlled to change by changing the on-off of the plurality of switches;

[0069] The second capacitor has a first end connected to the second input interface of the voltage selection circuit and a second end grounded;

[0070] The third capacitor has a first end connected to the third input interface of the voltage selection circuit and a second end grounded.

[0071] In some embodiments, a low-power programmable sample-and-hold voltage selector, i.e., a voltage sampler, can select an output from 2 to 16 voltages, the feedback coefficient V4 / VLCD can be configured in a range of 0.1 to 0.9, the selected output voltage can be sampled and held in the capacitors C2 and C3, the switches S1, S2, and S3 are disconnected, and the resistance series voltage division path is disconnected, thereby reducing power consumption. The resistance value is of the order of kΩ, which well controls the area occupied by the resistance. The voltage sampler can select an output from a plurality of voltages, the selected output voltage can be sampled and held in the capacitors C2 and C3, the switches S1, S2, and S3 are disconnected, and the resistance series voltage division path is disconnected.

[0072] As an optional implementation, the comparator comprises:

[0073] A built-in bandgap reference module for generating a predetermined reference voltage and a predetermined bias current; the built-in bandgap reference module is controlled by the reference enable signal;

[0074] A comparison module, a positive input end of the comparison module is electrically connected with the reference voltage, and the bias current is used to provide a bias condition for the comparison module; the comparison module is controlled by the comparison enable signal.

[0075] In some embodiments, a low-power built-in reference comparator has a built-in bandgap reference, which generates a reference voltage of about 1.2V connected to the positive end of the comparator, and generates a reference current to provide a bias current for the comparator. The comparator is a two-stage differential discrete-time enable controller, and the enablement of the bandgap reference and the comparator is controlled by the discrete-time controller. The module is in a discrete-time state, which well reduces the power consumption of the module by controlling the module through external signals, and also reduces the difficulty of low-power design of the bandgap reference and the comparator.

[0076] As an optional implementation, the reference enable signal, the comparison enable signal and the sampling enable signal generated by the discrete-time enable controller have the same frequency as the clock signal, and the duty cycle of the reference enable signal, the comparison enable signal and the sampling enable signal is 10% to 90%.

[0077] In some embodiments, the input clock of the discrete-time enable controller is a clock after frequency division of a system clock source, and the system clock is generated by a built-in or external resonant oscillator or a relaxation oscillator. The discrete-time enable controller outputs an enable control signal with the same frequency as the input clock, and the duty cycle can be 10% to 90%. The specific output enable signal control timing is as shown in Figure 2

[0078] As an optional implementation, the ratio of the fourth voltage to the LCD voltage is 0.1 to 0.9.

[0079] The following provides a specific implementation of the technical solution circuit of the present application:

[0080] VDD is powered on, the external clock is turned on, the driving controller of the present application is enabled, the low-power programmable voltage selector, i.e. the voltage sampler, selects a negative feedback loop coefficient, for example, 0.5. Since the reference voltage is 1.2V, the VLCD voltage generated by the charge pump is 1.2÷0.5=2.4V. At the same time, V2 and V3 voltages are obtained through a resistance voltage dividing path, and finally a voltage is selected from VLCD, V2, V3 and GND through the driving voltage selector. The low-power implementation is realized through the enable control timing output by the discrete-time enable controller. The specific timing is as shown in Figure 2 The low-power built-in reference comparator, the low-power programmable sample-and-hold voltage selector and the low-power charge pump are in working state only for a part of time in a clock CLK cycle.

[0081] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical range disclosed by the present application can be easily thought of by those skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.​

Claims

1. A low power consumption LCD liquid crystal display driving controller, characterized by, The low-power LCD liquid crystal display driving controller comprises: a charge pump configured to output a first voltage; a comparator, an output terminal of the comparator being electrically connected to an enable terminal of the charge pump, and the output terminal of the comparator outputting a charge pump enable signal to enable the charge pump; a discrete-time enable controller, an input interface of the discrete-time enable controller being configured to receive a clock signal, a first output interface of the discrete-time enable controller being configured to output a reference enable signal to the comparator, a second output interface of the discrete-time enable controller being configured to output a comparison enable signal to the comparator, and a third output interface of the discrete-time enable controller being configured to output a sampling enable signal; the reference enable signal, the comparison enable signal and the sampling enable signal generated by the discrete-time enable controller have the same frequency as the clock signal, and the duty cycle of the reference enable signal, the comparison enable signal and the sampling enable signal is 10% to 90%; a voltage sampler configured to sample and hold an LCD voltage according to the sampling enable signal, and configured to output a second voltage, a third voltage and a fourth voltage to the outside by voltage division of an LCD voltage source, wherein the fourth voltage is input to a negative phase interface of the comparator, and the LCD voltage source is electrically connected to an output terminal of the charge pump; a voltage selection circuit, a first input interface of the voltage selection circuit being electrically connected to the LCD voltage source, a second input interface of the voltage selection circuit being configured to receive the second voltage, a third input interface of the voltage selection circuit being configured to receive the third voltage, a fourth input interface of the voltage selection circuit being grounded, and an output interface of the voltage selection circuit being configured to be connected to a segment code port.

2. The low power consumption LCD liquid crystal display driving controller according to claim 1, wherein, The second input interface of the voltage selection circuit receives the second voltage through a first voltage stabilizer, and the third input interface of the voltage selection circuit receives the third voltage through a second voltage stabilizer.

3. The low-power LCD liquid crystal display driving controller according to claim 2, wherein a positive phase input terminal of the first voltage stabilizer is electrically connected to the second voltage output interface, an output interface of the first voltage stabilizer is electrically connected to the second input interface of the voltage selection circuit, and a negative phase input terminal of the first voltage stabilizer is electrically connected to the output terminal of the first voltage stabilizer; a positive phase input terminal of the second voltage stabilizer is electrically connected to the third voltage output interface, an output interface of the second voltage stabilizer is electrically connected to the third input interface of the voltage selection circuit, and a negative phase input terminal of the second voltage stabilizer is electrically connected to the output terminal of the second voltage stabilizer.

4. The low power consumption LCD liquid crystal display driving controller according to claim 3, wherein, The positive phase input terminal of the first voltage stabilizer and the negative phase input terminal of the first voltage stabilizer are electrically connected through a switch, and the positive phase input terminal of the second voltage stabilizer and the negative phase input terminal of the second voltage stabilizer are electrically connected through a switch.

5. The low power LCD liquid crystal display driver controller of claim 1, wherein, The charge pump comprises: an oscillator, the oscillator being electrically connected to the output terminal of the comparator, and the oscillator having a first output port, a second output port, a third output port and a fourth output port, wherein the first output port, the second output port and the fourth output port have opposite levels to the third output port. a first MOS transistor, a first end of the first MOS transistor is connected to a power supply, a gate of the first MOS transistor is electrically connected to a first output port of the oscillator; a second MOS transistor, a first end of the second MOS transistor is electrically connected to a second end of the first MOS transistor, a second end of the second MOS transistor is grounded, a gate of the second MOS transistor is electrically connected to a second output port of the oscillator; a third MOS transistor, a first end of the third MOS transistor is connected to a power supply, a gate of the third MOS transistor is electrically connected to a third output port of the oscillator; a fourth MOS transistor, a first end of the fourth MOS transistor is electrically connected to a second end of the third MOS transistor, a gate of the fourth MOS transistor is electrically connected to a fourth output port of the oscillator; a boost capacitor, a first end of the boost capacitor is electrically connected to a second end of the first MOS transistor, a second end of the boost capacitor is electrically connected to a second end of the third MOS transistor; a first capacitor, a first end of the first capacitor is electrically connected to a second end of the fourth MOS transistor, a second end of the first capacitor is grounded.

6. The low power consumption LCD liquid crystal display driving controller according to claim 5, wherein, The oscillator is a 4-step adjustable frequency ring oscillator.

7. The low power LCD liquid crystal display driver controller of claim 1, wherein, The voltage sampler comprises: a voltage dividing resistor string, one end of the voltage dividing resistor string is electrically connected to an LCD voltage source, the other end of the voltage dividing resistor string is grounded; a first switch, the first switch is used to control the on-off of the voltage dividing resistor string and the LCD voltage source; the first switch is controlled by the sampling enable signal; a second switch, the second switch is used to control the on-off of a second voltage output formed by voltage division of a plurality of resistors, the number of resistors is at least one less than the total number of the voltage dividing resistor string; the second switch is controlled by the sampling enable signal; a third switch, the third switch is used to control the on-off of a third voltage output formed by voltage division of one or more resistors; the third switch is controlled by the sampling enable signal; a selection switch group, comprising a plurality of switches, each switch is used to control the on-off of a fourth voltage formed by voltage division of a corresponding number of resistors, the fourth voltage can be changed by changing the on-off of the plurality of switches; a second capacitor, a first end of the second capacitor is connected to a second input interface of the voltage selection circuit, a second end of the second capacitor is grounded; a third capacitor, a first end of the third capacitor is connected to a third input interface of the voltage selection circuit, a second end of the third capacitor is grounded.

8. The low power consumption LCD liquid crystal display driving controller according to claim 1, wherein, The comparator comprises: an internal bandgap reference module, the internal bandgap reference module is used to generate a predetermined reference voltage and a predetermined bias current; the internal bandgap reference module is controlled by the reference enable signal; a comparison module, a positive input end of the comparison module is electrically connected to the reference voltage, the bias current is used to provide a bias condition for the comparison module; the comparison module is controlled by the comparison enable signal.

9. The low power consumption LCD liquid crystal display driving controller according to claim 1, wherein, The ratio of the fourth voltage to the LCD voltage is 0.1-0.9.

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