A multi-chip stacked vertical interconnection package structure and a packaging method

Abstract

The present application relates to the technical fields of semiconductor packaging, in particular to a multi-chip vertical interconnection packaging structure and a packaging method. The packaging structure comprises multi-layer stacked chips, the stacked chips are provided with pads, the pads of the stacked chips above the second layer stacked chip are provided with leakage holes, the leakage hole area of the pad of the upper layer stacked chip contains the leakage hole area of the pad of the lower layer stacked chip, a hole is arranged in the leakage hole of the pad and communicates with the pad of the next layer, and a conductive structure is arranged in the hole. The present application also provides a packaging method of the above multi-chip vertical interconnection packaging structure. Compared with the prior art, for the stacked structure of the rear through hole, the one-hole-to-bottom process implementation method can replace the separate processing procedures of each layer with the process procedure completed by the stacked structure, thereby greatly simplifying the process flow and reducing the packaging cost. Through the leakage hole area design of each layer chip, the effect that the signals transmitted through the conductive structure can be interconnected with each layer chip is realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, specifically to a packaging structure and method for multi-chip stacked vertical interconnection. Background Technology

[0002] In the field of advanced semiconductor packaging, for the Via-last technology, whether it is a face-up or face-down stack, the general practice is to punch a hole once for each layer of stacking. The main reason is that the method of punching a hole once after multiple layers of stacking cannot theoretically meet the requirement that the signals on each layer of chip can be interconnected through the via. Summary of the Invention

[0003] To overcome the shortcomings of the prior art, this invention provides a packaging structure for vertical interconnection of multi-chip stacking.

[0004] To achieve the above objectives, a multi-chip stacked vertical interconnect packaging structure is designed, including multiple stacked chips. The stacked chips are provided with pads. The pads of the stacked chips above the second stacked chip are provided with vias. The via area of ​​the pads of the upper stacked chip includes the via area of ​​the pads of the lower stacked chip. A hole is opened at the via of the pad to connect to the pad of the next layer. A conductive structure is provided in the hole.

[0005] The multilayer stacked chip includes four stacked chips. The first stacked chip has a first pad with no vias. The second stacked chip has a second pad with a 1 / 4 circular via. The third stacked chip has a third pad with a semi-circular via. The fourth stacked chip has a fourth pad with a 3 / 4 circular via.

[0006] The leakage holes are either concentric circles or rectangular structures.

[0007] One end of the conductive structure is exposed within the encapsulation structure and has bumps.

[0008] The present invention also provides a packaging method for the above-mentioned multi-chip stacked vertical interconnect packaging structure, comprising the following steps:

[0009] S1, bonding the substrate wafer to the first stacked wafer, with the pads of the substrate wafer corresponding to those of the first stacked wafer;

[0010] S2, thinning and stacking wafers;

[0011] S3, repeat bonding and thinning, and stack several layers of stacked wafers in sequence;

[0012] S4, a photomask is fabricated on top of the stacked wafers;

[0013] S5, through the vias, silicon etching and dielectric layer etching are performed on the stacked wafers in a cycle to form etching holes, and the portion of the pads of each stacked wafer that is smaller than the pads of the upper layer is exposed until the pads of the first stacked wafer are exposed, and then the photomask is removed.

[0014] S6, deposit dielectric layer in the etched hole, and then etch again to expose pad 1 and the pads of each stacked wafer.

[0015] S7, fill the etched holes with conductive structures and planarize the surface;

[0016] S8 thins the substrate wafer, creates bumps on the top, and dices to form individual modules.

[0017] In step S1, the substrate wafer and the first stacked wafer are polished before bonding.

[0018] In steps S2 and S3, the stacked wafers are thinned and then CMP polished to a thickness of 30-50 μm.

[0019] In step S6, megasonic cleaning is performed before dielectric layer deposition and after etching to expose the pads.

[0020] The conductive structure in step S7 is made of copper. The specific steps include first forming a PVD seed layer in the etched hole, and then performing an electroplating copper filling process. In the electroplating copper filling process, a strong inhibitor is used to adsorb on the wafer surface and the top of the etched hole to inhibit the deposition of copper on the wafer surface and the top of the hole, so as to achieve the deposition of copper from the bottom of the etched hole upwards.

[0021] Compared with the prior art, this invention can achieve a single-hole-to-the-end process for stacked structures with through-holes, replacing the separate processing of each layer with a process completed in one go, which greatly simplifies the process flow and reduces packaging costs. Through the design of the via areas of each chip layer, the signal transmitted through the conductive structure can be interconnected with each chip layer. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the packaging structure of the present invention.

[0023] Figure 2 This is a schematic diagram of the pads of the present invention.

[0024] Figure 3 This is a schematic diagram of the conductive structure of the present invention.

[0025] Figure 4 This is a cross-sectional view (AA) of the conductive structure of the present invention.

[0026] Figure 5 This is a BB cross-sectional view of the conductive structure of the present invention.

[0027] Figure 6 This is an exploded view of the conductive structure of the present invention.

[0028] Figure 7 This is a schematic diagram of the packaging method of the present invention.

[0029] See Figures 1-7 In this array, 1 is the stacked chip, 1-1 is the first stacked chip, 1-2 is the second stacked chip, 1-3 is the third stacked chip, 1-4 is the fourth stacked chip, 2 is the pad, 2-1 is the first pad, 2-2 is the second pad, 2-3 is the third pad, 2-4 is the fourth pad, 3 is the via, 4 is the conductive structure, 5 is the bump, 6 is the base wafer, 7 is the stacked wafer, 8 is the photomask, 9 is the etched hole, and 10 is the deposited dielectric layer. Detailed Implementation

[0030] The present invention will be further described below with reference to the embodiments and accompanying drawings. Example

[0031] like Figures 1-6 As shown, this embodiment provides a multi-chip stacked vertical interconnect packaging structure, including multiple stacked chips 1. The stacked chips 1 are provided with pads 2. The pads 2 of the stacked chips 1 above the second layer are provided with vias 3. The area of ​​the via 3 of the pads 2 of the upper layer of the stacked chips 1 includes the area of ​​the via 3 of the pads 2 of the lower layer of the stacked chips 1. A hole is opened at the via 3 of the pad 2 to connect to the pad 2 of the lower layer. A conductive structure 4 is provided in the hole. The area of ​​the via 3 of the pads 2 of the upper layer of the stacked chips 1 is larger than the area of ​​the via 3 of the pads 2 of the lower layer of the stacked chips 1. When through-holes are processed downward through the vias 3, the pads 2 of the lower layer are exposed. The conductive structure 4 contacts the exposed parts of each layer of pads 2, and the pads 2 of each layer of the stacked chips 1 are interconnected through the conductive structure 4.

[0032] One end of the conductive structure 4 exposes the encapsulation structure and has a bump 5. The bump 5 can be located at at least one end of the conductive structure 4, either at the top or bottom, such as... Figure 1 As shown, the bump 5 is set at the upper end and can be directly implanted after the conductive structure 4 is made, serving as the contact point for the flip-chip encapsulation structure.

[0033] This embodiment provides a structure for a circular notch-shaped leakage hole 3, such as... Figures 2-6As shown, the multilayer stacked chip 1 includes four stacked chip layers 1. The first stacked chip 1-1 has a pad 2-1, which has no via 3. The second stacked chip 1-2 has a pad 2-2, whose via 3 is a 1 / 4 circular hole. The third stacked chip 1-3 has a pad 3-3, whose via 3 is a semi-circular hole. The fourth stacked chip 1-4 has a pad 4-4, whose via 3 is a 3 / 4 circular hole. During stacking, the centers of the circular holes of each pad 2 are aligned vertically, as shown. Figures 4-5 Cross-sectional view of pad 2 and conductive structure 4 and Figure 6 As shown in the exploded view, a portion of the area above each pad 2 is exposed, and it can be interconnected with each layer of chip through the conductive structure 4.

[0034] The structure of the via 3 can also be a concentric circle structure or a rectangular structure, as long as the upper pad is smaller than the lower pad, so that the front of the lower pad has an exposed area to contact the conductive structure 4. The signal transmitted through the conductive structure 4 can be interconnected with the pads of each chip layer. Example

[0035] like Figure 7 As shown, this embodiment provides a packaging method for a multi-chip stacked vertical interconnect packaging structure, including the following steps:

[0036] S1, the substrate wafer 6 is bonded to the first stacked wafer 7, and the substrate wafer 6 corresponds to the pad 2 of the first stacked wafer 7;

[0037] Specifically, the substrate wafer 6 serves as a support and also has its own pads. These pads correspond one-to-one with the pads of the first stacked wafer 7 and are then mixed-bonded to form pad 2-1. Before bonding, the substrate wafer 6 and the first stacked wafer 7 are polished to ensure a smooth fit during bonding.

[0038] S2, Thinned stacked wafer 7;

[0039] Specifically, the substrate of wafer 7 can be thinned by grinding, and then CMP polished to a thickness of 30~50μm.

[0040] S3, repeat bonding and thinning, and stack several layers of stacked wafers 7 in sequence;

[0041] Specifically, during stacking, the pads of each stacked wafer 7 are arranged in a corresponding manner to form a stacked structure.

[0042] S4, a photomask 8 is fabricated on top of the stacked wafer 7;

[0043] Specifically, the photomask 8 covers the areas that do not need to be etched, protecting the stacked wafer 7, while exposing the positions of the pads 2 for subsequent etching.

[0044] S5, through the hole 3, the stacked wafer 7 is cyclically etched with silicon and dielectric layer to form etch hole 9, and the portion of the pad 2 of each stacked wafer 7 that is smaller than the upper pad 2 is exposed until the pad 2-1 of the first stacked wafer 7 is exposed, and then the photomask 8 is removed.

[0045] Specifically, the silicon via etching and dielectric layer etching of the stacked wafer 7 can be performed using a biased anisotropic dry etching technique, through the via 3 to expose the portion of each layer pad 2 smaller than the upper layer pad 2, and then the photomask 8 is removed.

[0046] S6, perform dielectric layer deposition in the etch hole 9 to form a deposited dielectric layer 10, and then perform etching again to expose pad 2-1 and pad 2 of each stacked wafer 7;

[0047] Specifically, PECVD can be used to deposit a dielectric layer 10 on the entire etched hole 9 and the top of the stacked wafer 7. The deposited dielectric layer 10 serves as the substrate for the subsequent filling of the conductive structure 4, making the conductive structure 4 insulated from the side of the wafer 7. After deposition, the deposited dielectric layer 10 on the surface of the pad 2 is removed by etching, exposing the pad 2. Megasonic cleaning is performed before dielectric layer deposition and after etching to expose the pad 2 to remove impurities.

[0048] S7, fill the etched hole 9 with conductive structure 4 and planarize the surface;

[0049] Specifically, a PVD seed layer is first created, followed by an electroplating copper-filling process to form the conductive structure 4. During the electroplating process, a strong inhibitor is adsorbed on the wafer surface and the top of the etched holes 9 to suppress copper deposition on the wafer surface and above the holes, allowing copper to be deposited upwards from the bottom of the etched holes 9. This bottom-up filling reduces the thickness of the plated copper and significantly shortens the plating time. More importantly, because the bottom-to-bottom structure is deep and the lower aperture is small, the use of a strong inhibitor prevents the top from depositing first, thus avoiding voids in the middle. After electroplating, the top is CMP-polished.

[0050] S8, thin the substrate wafer 6, create bumps 5 on the top, and dicing to form a single module;

[0051] Specifically, the substrate wafer 6 can be thinned by grinding, and then tin balls can be implanted as bumps 5 at the exposed position of the top conductive structure 4, and then a single module can be formed after dicing.

[0052] In this embodiment, the stacking of all stacked wafers 7 is completed first. After stacking, the vias 3 through the pads 2 are etched through to the bottom in one go. Then, the copper filling process is completed in one go within the etched vias, which greatly simplifies the process flow and reduces packaging costs. Through the design of the via regions of the pads of each stacked wafer 7, the interconnection between the conductive structure 4 and each layer of pads 2 is achieved.

Claims

1. A multi-chip stacked vertical interconnect packaging structure, characterized in that: The chip includes a multilayer stacked chip (1), which has pads (2). The pads (2) of the stacked chip (1) above the second layer stacked chip (1-2) have vias (3). The area of ​​the via (3) of the pad (2) of the upper layer stacked chip (1) includes the area of ​​the via (3) of the pad (2) of the lower layer stacked chip (1). A hole is opened at the via (3) of the pad (2) to connect to the pad (2) of the lower layer. A conductive structure (4) is provided in the hole. The multilayer stacked chip (1) includes four stacked layers. Chip (1), the first layer stacked chip (1-1) has a first pad (2-1), the first pad (2-1) has no hole (3), the second layer stacked chip (1-2) has a second pad (2-2), the hole (3) of the second pad (2-2) is a 1 / 4 round hole, the third layer stacked chip (1-3) has a third pad (2-3), the hole (3) of the third pad (2-3) is a semi-circular hole, the fourth layer stacked chip (1-4) has a fourth pad (2-4), the hole (3) of the fourth pad (2-4) is a 3 / 4 round hole.

2. The packaging structure for multi-chip stacked vertical interconnection according to claim 1, characterized in that: The leak (3) is a concentric circle structure or a rectangular structure.

3. The packaging structure for multi-chip stacked vertical interconnection according to claim 1, characterized in that: One end of the conductive structure (4) exposes the encapsulation structure and has bumps (5).

4. A packaging method for a multi-chip stacked vertical interconnect packaging structure according to any one of claims 1-3, characterized in that, Includes the following steps: S1, the base wafer (6) is bonded to the first stacked wafer (7), and the pads (2) of the base wafer (6) correspond to the pads (2) of the first stacked wafer (7); S2, thinning stacked wafers (7); S3, repeat bonding and thinning, and stack several layers of stacked wafers in sequence (7). S4, a photomask (8) is made on top of the stacked wafer (7). S5, through the hole (3), the stacked wafer (7) is cyclically etched with silicon and dielectric layer to form etch holes (9), and the portion of the pad (2) of each stacked wafer (7) smaller than the upper pad (2) is exposed until the pad 1 (2-1) of the first stacked wafer (7) is exposed, and then the photomask (8) is removed. S6, deposit a dielectric layer in the etch hole (9) to form a deposited dielectric layer (10), and then etch again to expose pad 1 (2-1) and the pads (2) of each stacked wafer (7). S7, fill the etched hole (9) with conductive structure (4) and planarize the surface; S8, the substrate wafer (6) is thinned, bumps (5) are made on the top, and dicing is performed to form a single module.

5. The packaging method for a multi-chip stacked vertical interconnect packaging structure according to claim 4, characterized in that: In step S1, the substrate wafer (6) and the first stacked wafer (7) are polished before bonding.

6. The packaging method for a multi-chip stacked vertical interconnection packaging structure according to claim 4, characterized in that: In steps S2 and S3, the stacked wafers (7) are thinned and then CMP polished to a thickness of 30 ~ 50 μm.

7. The packaging method for a multi-chip stacked vertical interconnection packaging structure according to claim 4, characterized in that: In step S6, megasonic cleaning is performed before dielectric layer deposition and after etching to expose pad 1 (2-1).

8. The packaging method for a multi-chip stacked vertical interconnection packaging structure according to claim 4, characterized in that: The conductive structure (4) in step S7 is made of copper. The specific steps include first forming a PVD seed layer in the etched hole (9), and then performing an electroplating copper filling process. In the electroplating copper filling process, a strong inhibitor is used to adsorb on the wafer surface and the top of the etched hole (9) to inhibit the deposition of copper on the wafer surface and the top of the hole, so as to achieve the deposition of copper from the bottom of the etched hole (9) upward.

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