Array substrate, display panel, display device and control method of array substrate

Abstract

The application discloses an array substrate, a display panel, a display device and a control method of the array substrate. The array substrate comprises a substrate, an array layer and a metal layer. The array layer comprises a transistor, and the transistor comprises an active layer and a first gate electrode. The first gate electrode is arranged on a side of the active layer away from the substrate. The active layer comprises a first channel region, a second channel region, a first source region and a first drain region. The metal layer is arranged on a side of the active layer close to the substrate and comprises a potential control part. The potential control part and the first channel region are overlapped. The potential control part is arranged in a position different from the second channel region in the orthographic projection of the substrate. Since the length of the second channel region is greater than that of the first channel region, when the first channel region is closed, the active layer exhibits the device characteristics of the second channel region, that is, the transistor has a larger subthreshold swing. When the first channel region is opened, the active layer exhibits the device characteristics of the first channel region, that is, the transistor has a larger on-state current.

Description

TECHNICAL FIELD

[0001] The present application relates to the display field, and in particular to an array substrate, a display panel, a display device and a control method of the array substrate. BACKGROUND

[0002] Organic light emitting diode (OLED) and flat display devices based on light emitting diode (LED) technology have been widely applied to mobile phones, televisions, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range, and have become the mainstream of display devices.

[0003] However, the use performance of the current OLED display product needs to be improved. SUMMARY

[0004] Embodiments of the present application provide an array substrate, a display panel, a display device and a control method of the array substrate, aiming to improve the use performance of the display panel.

[0005] The first aspect of the present application provides an array substrate, comprising: a substrate; an array layer located on one side of the substrate, the array layer comprising a transistor, the transistor comprising an active layer and a first gate electrode, the first gate electrode being located on a side of the active layer away from the substrate, the active layer comprising a first channel region, a second channel region, a first source region and a first drain region, the first channel region and the second channel region being connected between the first source region and the first drain region respectively, the length of the second channel region being greater than the length of the first channel region; and a metal layer located on a side of the active layer close to the substrate, the metal layer comprising a potential control portion, the potential control portion being at least partially overlapped with the projection of the first channel region on the substrate, the projection of the potential control portion on the substrate being located outside the projection of the second channel region on the substrate.

[0006] According to the first aspect of the present application, the first channel region comprises a main body portion and a connecting portion, the connecting portion being located at both ends of the main body portion close to the first source region and the first drain region, and the two ends of the second channel region being connected to the connecting portions at both ends of the main body portion respectively.

[0007] According to any one of the preceding embodiments of the first aspect of the present application, the projection of the main body portion on the substrate is at least partially overlapped with the projection of the potential control portion on the substrate.

[0008] According to any one of the preceding embodiments of the first aspect of the present application, the projection of the main body portion on the substrate is located within the projection of the potential control portion on the substrate; or the projection of the main body portion on the substrate is coincident with the projection of the potential control portion on the substrate.

[0009] According to any one of the foregoing embodiments of the first aspect of the present application, the potential control portion is located outside the orthographic projection of the connecting portion on the substrate.

[0010] According to any one of the foregoing embodiments of the first aspect of the present application, the active layer comprises a polycrystalline oxide semiconductor, and the potential control portion is configured to cause the turn-on voltage of the first channel region to be less than the turn-on voltage of the second channel region; or the active layer comprises an oxide semiconductor, and the potential control portion is configured to cause the turn-on voltage of the first channel region to be greater than the turn-on voltage of the second channel region.

[0011] According to any one of the foregoing embodiments of the first aspect of the present application, the orthographic projection of the second channel region on the substrate is in an arc shape or a polyline shape.

[0012] According to any one of the foregoing embodiments of the first aspect of the present application, the orthographic projections of the first channel region and the second channel region on the substrate are both located within the orthographic projection of the first gate on the substrate.

[0013] According to any one of the foregoing embodiments of the first aspect of the present application, the array layer further comprises: a first inorganic silicon layer located between the active layer and the first gate; and a second inorganic layer located between the metal layer and the active layer, the thickness of the first inorganic layer in the thickness direction of the array substrate being greater than the thickness of the second inorganic layer.

[0014] According to any one of the foregoing embodiments of the first aspect of the present application, the array layer further comprises a source-drain layer and an insulating layer, the insulating layer being located on the side of the first gate away from the substrate, and the source-drain layer being located on the side of the insulating layer away from the substrate, the source-drain layer comprising a source and a drain, the source being connected to the first source region via hole, and the drain being connected to the first drain region via hole.

[0015] According to any one of the foregoing embodiments of the first aspect of the present application, the array substrate further comprises a buffer layer located between the substrate and the metal layer.

[0016] According to any one of the foregoing embodiments of the first aspect of the present application, the array substrate further comprises an isolation structure located on the side of the array layer away from the substrate, the isolation structure enclosing a plurality of isolation openings, the isolation openings being configured to be provided with light-emitting units of the display panel.

[0017] According to any one of the foregoing embodiments of the first aspect of the present application, the isolation structure comprises a first layer and a second layer located on the side of the first layer away from the substrate, the orthographic projection of the first layer on the substrate being located within the orthographic projection of the second layer on the substrate.

[0018] According to any one of the foregoing embodiments of the first aspect of the present application, the first layer comprises a conductive material.

[0019] According to any one of the foregoing embodiments of the first aspect of the present application, the second layer comprises a conductive material or an insulating material.

[0020] According to any one of the foregoing embodiments of the first aspect of the present application, the second layer comprises a metal material, and the material of the first layer is different from that of the second layer.

[0021] According to any one of the foregoing embodiments of the first aspect of the present application, the isolation structure further comprises a third layer located on the side of the first layer facing the substrate, and the orthographic projection of the first layer on the substrate is located within the orthographic projection of the third layer on the substrate.

[0022] Embodiments of the second aspect of the present application provide a display panel comprising the array substrate of any one of the foregoing embodiments.

[0023] Embodiments of the third aspect of the present application provide a display device comprising the display panel of any one of the foregoing embodiments.

[0024] Embodiments of the fourth aspect of the present application provide a control method of an array substrate, the preparation method comprising:

[0025] adjusting the potential of the potential control portion so that the absolute value of the turn-on voltage of the first channel region is greater than that of the second channel region;

[0026] adjusting the potential of the first gate so that the first channel region is turned on or off.

[0027] According to the array substrate of the embodiments of the present application, the array substrate comprises a substrate, an array layer and a metal layer. The array layer comprises a transistor, and the transistor comprises an active layer and a first gate. The first gate is arranged on the side of the active layer facing away from the substrate, forming a top gate structure. The active layer comprises a first channel region, a second channel region, a first source region and a first drain region. The metal layer is located on the side of the active layer close to the substrate and comprises a potential control portion. The potential control portion is connected to a fixed potential. When the potential control portion and the first channel region overlap, the potential control portion can adjust the turn-on voltage of the first channel region. The orthographic projection of the potential control portion on the substrate is located outside the orthographic projection of the second channel region on the substrate, so that the potential control portion is difficult to affect the turn-on voltage of the second channel region, and the turn-on voltage of the second channel region is a normal turn-on voltage. Since the length of the second channel region is greater than that of the first channel region, when the first channel region is turned off, the active layer exhibits the device characteristics of the second channel region, i.e., the transistor has a large subthreshold swing. When the first channel region is turned on, since the first channel region is short, the current flows through the first channel region rather than the second channel region, and the active layer exhibits the device characteristics of the first channel region, i.e., the transistor has a large on-state current. Thus, the array substrate can simultaneously have a large subthreshold swing and a large on-state current, improving the use performance of the array substrate. BRIEF DESCRIPTION OF DRAWINGS

[0028] Other features, objects, and advantages of the application will become more apparent from the following detailed description when read in conjunction with the accompanying drawings, in which like reference numerals designate identical or corresponding parts throughout the several views, and wherein the drawings are not drawn to scale.

[0029] Figure 1 is a partial top view of an array substrate provided by a first embodiment of the present application;

[0030] Figure 2 is a partial schematic view of Figure 1 ;

[0031] Figure 3 is a sectional view of the array substrate at A-A in Figure 1 ;

[0032] Figure 4 is a sectional view of the array substrate at B-B in Figure 1 ;

[0033] Figure 5 is a partial top view of an array substrate in another embodiment;

[0034] Figure 6 is a sectional view of the array substrate at C-C in Figure 5 ;

[0035] Figure 7 is a partial sectional view of an array substrate in another embodiment;

[0036] Figure 8 is a partial sectional view of an array substrate in yet another embodiment;

[0037] Figure 9 is a partial sectional view of an array substrate in still another embodiment;

[0038] Figure 10 is a partial sectional view of a display panel provided by a second embodiment of the present application;

[0039] Figure 11 is a control method flowchart of an array substrate provided by a fourth embodiment of the present application.

[0040] Legend of reference numerals:

[0041] 10, array substrate;

[0042] 100, substrate;

[0043] 200, array layer; 210, transistor; 220, active layer; 221, first channel region; 222, second channel region; 223, first source region; 224, first drain region; 225, main body portion; 226, connection portion; 230, first gate electrode;

[0044] 300, metal layer; 310, potential control part;

[0045] 400, first silicon oxide layer;

[0046] 500, second silicon oxide layer;

[0047] 600, source-drain layer; 610, source electrode; 620, drain electrode;

[0048] 700, buffer layer;

[0049] 800, isolation structure; 810, first layer; 820, second layer; 830, third layer; 840, isolation opening;

[0050] 20, pixel definition layer; 21, pixel defining part; 22, pixel opening; 23, pixel electrode;

[0051] 30, light-emitting layer; 31, light-emitting unit;

[0052] 40, first electrode layer; 41, first electrode;

[0053] 50, functional layer;

[0054] 60, cover plate. DETAILED DESCRIPTION

[0055] The features and exemplary embodiments of various aspects of the present application will be described in detail below with reference to the drawings. The following detailed description is merely provided to explain the present application in the form of examples and is not configured to limit the present application. The present application can be implemented without some of the specific details by those skilled in the art. The following description of the embodiments is merely provided to provide a better understanding of the present application by showing examples of the present application.

[0056] It is to be understood that the terminology "first" and "second", etc. can be utilized herein simply to differentiate between two entities or operations, and does not necessarily imply a sequence or order between such entities or operations. Moreover, the terminology "comprises", "comprising", or any other variety thereof, is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by an "comprising" statement is also not excluded from a process, method, article, or apparatus that includes the element without the "comprising" statement.

[0057] It should be understood that when describing the structure of a component, when one layer, one region is referred to as being "on" or "above" another layer, another region, it can mean directly on or above the other layer, the other region, or other layers or regions are included between it and the other layer, the other region. And if the component is turned over, the layer, the region will be "under" or "below" the other layer, the other region.

[0058] Embodiments of the present application provide an array substrate, a display panel, a display device and a control method of the array substrate. Each embodiment of the array substrate, the display panel, the display device and the control method of the array substrate will be described below in conjunction with the accompanying drawings.

[0059] Please refer to Figures 1 to 4 , Figure 1 is a partial top view of an array substrate provided by a first aspect embodiment of the present application; Figure 2 is Figure 1 a partial schematic view of Figure 3 is Figure 1 a cross-sectional view of the array substrate at A-A in Figure 4 is Figure 1 a cross-sectional view of the array substrate at B-B in

[0060] As Figures 1 to 4As shown, the first aspect of the present application provides an array substrate 10, comprising a substrate 100, an array layer and a metal layer 300; the array layer is located on one side of the substrate 100, and the array layer comprises a transistor 210, the transistor 210 comprises an active layer 220 and a first gate 230, the first gate 230 is located on the side of the active layer 220 away from the substrate 100, the active layer 220 comprises a first channel region 221, a second channel region 222, a first source region 223 and a first drain region 224, the first channel region 221 and the second channel region 222 are respectively connected between the first source region 223 and the first drain region 224, and the length of the second channel region 222 is greater than the length of the first channel region 221; the metal layer 300 is located on the side of the active layer 220 close to the substrate 100, and the metal layer 300 comprises a potential control part 310, the orthogonal projection of the potential control part 310 on the substrate 100 at least partially overlaps with the orthogonal projection of the first channel region 221 on the substrate 100, and the orthogonal projection of the potential control part 310 on the substrate 100 is located outside the orthogonal projection of the second channel region 222 on the substrate 100.

[0061] The length of the second channel region 222 being greater than the length of the first channel region 221 means that the length of the second channel region 222 in its extension direction is greater than the length of the first channel region 221 in its extension direction, for example, the extension direction of the second channel region 222 is from the first source region 223 to the first drain region 224.

[0062] According to the array substrate 10 of the embodiment of the present application, the array substrate 10 comprises a substrate 100, an array layer and a metal layer 300. The array layer comprises a transistor 210, the transistor 210 comprising an active layer 220 and a first gate 230, the first gate 230 being disposed on a side of the active layer 220 away from the substrate 100, forming a top gate structure. The active layer 220 comprises a first channel region 221, a second channel region 222, a first source region 223 and a first drain region 224, and the metal layer 300 is located on a side of the active layer 220 close to the substrate 100 and comprises a potential control portion 310, the potential control portion 310 being connected with a fixed potential, and when the potential control portion 310 and the first channel region 221 overlap, the potential control portion 310 can adjust the turn-on voltage of the first channel region 221. The orthographic projection of the potential control portion 310 on the substrate 100 is located outside the orthographic projection of the second channel region 222 on the substrate 100, so that the potential control portion 310 is difficult to affect the turn-on voltage of the second channel region 222, and the turn-on voltage of the second channel region 222 is a normal turn-on voltage. Since the length of the second channel region 222 is greater than the length of the first channel region 221, when the first channel region 221 is turned off, the active layer 220 exhibits the device characteristics of the second channel region 222, i.e., the transistor 210 has a large subthreshold swing; when the first channel region 221 is turned on, since the first channel region 221 is short, the current will flow through the first channel region 221 rather than the second channel region 222, and the active layer 220 exhibits the device characteristics of the first channel region 221, i.e., the transistor 210 has a large on-state current, so that the array substrate 10 can simultaneously have a large subthreshold swing and a large on-state current, and the use performance of the array substrate 10 is improved.

[0063] As shown in Figure 1 and Figure 2 in some optional embodiments, the first channel region 221 comprises a main body portion 225 and a connecting portion 226, the connecting portion 226 being located at two ends of the main body portion 225 close to the first source region 223 and the first drain region 224, and the second channel region 222 is connected to the connecting portion 226 at two ends of the main body portion 225 respectively.

[0064] In these optional embodiments, the first channel region 221 includes a main body 225 and connecting portions 226 located at both ends of the main body 225. The second channel region 222 is connected to the connecting portions 226 to achieve parallel connection with the first channel region 221, and the second channel region 222 is electrically connected to the first source region 223 and the first drain region 224 through the connecting portions 226. Since the length of the second channel region 222 is greater than the length of the first channel region 221, after the first channel region 221 and the second channel region 222 are connected in parallel, when the first channel region 221 is turned off, the active layer 220 exhibits the device characteristics of the second channel region 222, that is, the transistor 210 has a large subthreshold swing; when the first channel region 221 is turned on, the active layer 220 exhibits the device characteristics of the first channel region 221, that is, the transistor 210 has a large on-state current, thereby enabling the array substrate 10 to simultaneously have a large subthreshold swing and a large on-state current, improving the performance of the array substrate 10.

[0065] In some alternative embodiments, the orthographic projection of the main body 225 onto the substrate 100 at least partially overlaps with the orthographic projection of the potential control unit 310 onto the substrate 100.

[0066] In these optional embodiments, the main body 225 overlaps with the potential control unit 310, enabling the potential control unit 310 to adjust the turn-on voltage of the main body 225 of the first channel region 221. When the voltage of the first gate 230 does not reach the turn-on voltage, the main body 225 of the first channel region 221 is turned off, and the active layer 220 exhibits the device characteristics of the second channel region 222, i.e., the transistor 210 has a large subthreshold swing; when the voltage of the first gate 230 reaches the turn-on voltage, the main body 225 of the first channel region 221 is turned on, and the active layer 220 exhibits the device characteristics of the first channel region 221, i.e., the transistor 210 has a large on-state current.

[0067] like Figure 2 As shown, optionally, the orthographic projection of the potential control unit 310 on the substrate 100 is located outside the orthographic projection of the connection portion 226 on the substrate 100, so that the turn-on voltage of the connection portion 226 is not affected by the potential control unit 310, and can be turned on synchronously with the second channel region 222, so that the second channel region 222 is electrically connected to the first source region 223 and the first drain region 224 through the connection portion 226.

[0068] Please see Figure 5 and Figure 6 , Figure 5 This is a partial top view of the array substrate in another embodiment; Figure 6 yes Figure 5 Cross-sectional view of the array substrate at the CC position.

[0069] like Figure 5 andFigure 6 As shown, optionally, the main body 225 is in the orthographic projection of the substrate 100 within the orthographic projection of the potential control portion 310 on the substrate 100, or the main body 225 is in the orthographic projection of the substrate 100 coinciding with the orthographic projection of the potential control portion 310 on the substrate 100, so that the main body 225 is completely controlled by the potential control portion 310, the whole turn-on voltage of the main body 225 is adjusted, and the accuracy and stability of the turn-on and turn-off of the main body 225 are improved.

[0070] In some optional embodiments, the active layer 220 includes a polycrystalline oxide semiconductor, for example, the active layer 220 includes low temperature poly-silicon (LTPS), and the potential control portion 310 is configured to make the turn-on voltage of the first channel region 221 smaller than the turn-on voltage of the second channel region 222.

[0071] In these optional embodiments, when the active layer 220 includes a polycrystalline oxide semiconductor, the first gate 230 voltage is adjusted, and the first gate 230 voltage is converted from a positive voltage to a negative voltage to make the active layer 220 change from an off state to an on state. And the turn-on voltage of the active layer 220 is a negative voltage, after the potential control portion 310 is connected to a fixed potential, the turn-on voltage of the first channel region 221 is smaller than the turn-on voltage of the second channel region 222, that is, the turn-on voltage of the first channel region 221 is more negative, when the first gate 230 voltage is converted from a positive voltage to a negative voltage, the second channel region 222 is preferentially turned on, and before the turn-on voltage of the first channel region 221 is reached, the active layer 220 exhibits the device characteristics of the second channel region 222, that is, the transistor 210 has a larger subthreshold swing; when the voltage of the first gate 230 reaches the turn-on voltage of the first channel region 221, the active layer 220 exhibits the device characteristics of the first channel region 221, and since the first channel region 221 is shorter than the second channel region 222, the transistor 210 has a larger on-state current.

[0072] In some optional embodiments, the active layer 220 includes an oxide semiconductor, for example, the active layer 220 includes indium gallium zinc oxide (IGZO), and the potential control portion 310 is configured to make the turn-on voltage of the first channel region 221 greater than the turn-on voltage of the second channel region 222.

[0073] In these alternative embodiments, when the active layer 220 comprises an oxide semiconductor, the voltage of the first gate 230 is adjusted from a negative voltage to a positive voltage to change the active layer 220 from an off state to an on state. Furthermore, the turn-on voltage of the active layer 220 is a positive voltage. After the potential control unit 310 is connected to a fixed potential, the turn-on voltage of the first channel region 221 is greater than the turn-on voltage of the second channel region 222. That is, the turn-on voltage of the first channel region 221 is more positive. When the voltage of the first gate 230 changes from a negative voltage to a positive voltage, the second channel region 222 turns on preferentially. Before reaching the turn-on voltage of the first channel region 221, the active layer 220 exhibits the device characteristics of the second channel region 222, that is, the transistor 210 has a large subthreshold swing. When the voltage of the first gate 230 reaches the turn-on voltage of the first channel region 221, the active layer 220 exhibits the device characteristics of the first channel region 221. Since the first channel region 221 is shorter than the second channel region 222, the transistor 210 has a large on-state current.

[0074] like Figure 1 As shown, in some optional embodiments, the orthographic projections of the first channel region 221 and the second channel region 222 onto the substrate 100 are both located within the orthographic projection of the first gate 230 onto the substrate 100.

[0075] In these optional embodiments, the first channel region 221 and the second channel region 222 are both configured corresponding to the first gate 230. When the voltage of the first gate 230 changes, the device states of the first channel region 221 and the second channel region 222 can be affected by the first gate 230 to control the off state and the on state of the first channel region 221 and the second channel region 222.

[0076] Please see Figure 7 , Figure 7 This is a partial cross-sectional view of the array substrate in another embodiment.

[0077] like Figure 7 As shown, in some optional embodiments, the array layer further includes a first inorganic layer 400 and a second inorganic layer 500. The first inorganic layer 400 is located between the active layer 220 and the first gate 230; the second inorganic layer 500 is located between the metal layer 300 and the active layer 220, and the thickness of the first inorganic layer 400 in the thickness direction of the array substrate 10 is greater than the thickness of the second inorganic layer 500.

[0078] In these alternative embodiments, the thickness of the first inorganic layer 400 between the first gate 230 and the active layer 220 is greater than that of the second inorganic layer 500 between the metal layer 300 and the active layer 220, that is, the thickness of the first inorganic layer 400 is larger. In this case, the inorganic layer between the first gate 230 and the active layer 220 is thicker, which can improve the subthreshold swing of the transistor 210.

[0079] Optionally, the first inorganic layer 400 and the second inorganic layer 500 each comprise silicon oxide.

[0080] Optionally, the array layer further comprises a source-drain layer 600 and an insulating layer, the insulating layer is located on the side of the first gate 230 away from the substrate 100, the source-drain layer 600 is located on the side of the insulating layer away from the substrate 100, the source-drain layer 600 comprises a source 610 and a drain 620, the source 610 is connected to the first source region 223 through a via, and the drain 620 is connected to the first drain region 224 through a via.

[0081] Please refer to Figure 2 and Figure 8 , Figure 8 is a partial sectional view of an array substrate in yet another embodiment.

[0082] As shown in Figure 2 and Figure 8 , optionally, the second channel region 222 has an arc shape or a polyline shape in the orthographic projection on the substrate 100, the arc shape or the polyline shape of the second channel region 222 can increase the extension length of the second channel region 222, when the length of the second channel region 222 is relatively long, in the case that the first channel region 221 is closed and the second channel region 222 is opened, the active layer 220 behaves as the device characteristics of the second channel region 222, that is, the transistor 210 can have a larger subthreshold swing.

[0083] Please refer to Figure 9 , Figure 9 is a partial sectional view of an array substrate in still another embodiment.

[0084] As shown in Figure 9 , optionally, the array substrate 10 further comprises a buffer layer 700, the buffer layer 700 is located between the substrate 100 and the metal layer 300, and has buffered external impact to protect the internal film layers of the array substrate 10 to realize stable function of the array substrate 10.

[0085] Please refer to Figure 10 , Figure 10 is a partial sectional view of a display panel provided in the second aspect of the present application.

[0086] As shown in Figure 10 , in some optional embodiments, the array substrate 10 further comprises an isolation structure 800, the isolation structure 800 is located on the side of the array layer away from the substrate 100, the isolation structure 800 encloses to form a plurality of isolation openings 840, and the isolation openings 840 are used to arrange light-emitting units 31 of the display panel.

[0087] In the alternative embodiments, the isolation structure 800 is disposed on the substrate 100 and encloses a plurality of isolation openings 840 for isolating the light-emitting layer 30 into a plurality of light-emitting units 31, thereby reducing the carrier crosstalk in the light-emitting layer 30 and improving the display effect of the display panel. In addition, the light-emitting units 31 can be prepared without using a precision mask plate, thereby reducing the development and use of the precision mask plate and lowering the manufacturing cost.

[0088] In some alternative embodiments, the isolation structure 800 includes a first layer 810 and a second layer 820 disposed on a side of the first layer 810 away from the substrate 100, and a projection of the first layer 810 on the substrate 100 is within a projection of the second layer 820 on the substrate 100.

[0089] In the alternative embodiments, the first layer 810 and the second layer 820 form the isolation structure 800, the first layer 810 disposed close to the substrate 100 has a projection on the substrate 100 within a projection of the second layer 820 on the substrate 100, the second layer 820 has an area greater than that of the first layer 810, the second layer 820 covers a surface of the first layer 810 close to the second layer 820, and the first layer 810 is recessed relative to the second layer 820 in a direction away from the isolation openings 840. When the light-emitting layer 30 is prepared, the light-emitting layer 30 has a large difference at the edge of the isolation structure 800, and the first layer 810 is recessed relative to the second layer 820, so that the light-emitting layer 30 is difficult to connect at the edge of the isolation structure 800, thereby being broken to form the light-emitting units 31.

[0090] Optionally, the first layer 810 includes a conductive material, so that the first electrode 41 of the display panel can be electrically connected to the first layer 810, and adjacent first electrodes 41 are conductive to each other through the first layer 810, thereby forming a full-area electrode.

[0091] In some alternative embodiments, the second layer 820 includes a conductive material or an insulating material.

[0092] In the alternative embodiments, the second layer 820 includes a conductive material, for example, the second layer 820 includes a non-metallic conductive material or a metallic conductive material. When the second layer 820 is a non-metallic conductive material or an insulating material, the second layer 820 is difficult to be etched in a wet etching process of the first layer 810 using an etching liquid, thereby making the first layer 810 more easily recessed relative to the second layer 820.

[0093] In some alternative embodiments, the second layer 820 includes a metallic material, and the first layer 810 and the second layer 820 are made of different materials.

[0094] In these optional embodiments, when the first layer 810 and the second layer 820 are both metal materials, the first layer 810 can be wet etched by using an etching liquid. By setting the etching liquid, the etching rate of the second layer 820 can be less than that of the first layer 810. Because the etching rate of the first layer 810 is greater, when the first layer 810 is wet etched by using the etching liquid, the second layer 820 will be etched to a certain extent, but the first layer 810 will be etched faster, so that the first layer 810 is arranged in a concave manner relative to the second layer 820.

[0095] In some optional embodiments, the isolation structure 800 further includes a third layer 830 located on the side of the first layer 810 facing the substrate 100, and the orthographic projection of the first layer 810 on the substrate 100 is located within the orthographic projection of the third layer 830 on the substrate 100. In these optional embodiments, because the first layer 810 is arranged in a concave manner, the first layer 810 has a faster etching rate than the second layer 820 and the third layer 830 during etching, so that the first layer 810 is formed in a concave manner. Because the etching rate of the first layer 810 is faster, more etching waste can easily enter other positions of the display panel, thereby causing adverse effects. After the third layer 830 is provided, the first layer 810 can be better attached to the third layer 830, and the etching waste generated can fall on the third layer 830, which is convenient for cleaning.

[0096] Embodiments of the second aspect of the present application also provide a display panel including the array substrate 10 of any of the above-mentioned embodiments of the first aspect. Because the display panel provided by the embodiments of the second aspect of the present application includes the array substrate 10 of any of the above-mentioned embodiments of the first aspect, the display panel provided by the embodiments of the second aspect of the present application has the beneficial effects of the array substrate 10 of any of the above-mentioned embodiments of the first aspect, which will not be described here again. Please continue to refer to Figure 10 In some optional embodiments, the display panel further includes a pixel definition layer 20, a light-emitting layer 30, a first electrode layer 40, a functional layer 50, and a cover plate 60. The pixel definition layer 20 is located on one side of the array substrate 10, and the pixel definition layer 20 includes a pixel defining portion 21 and a pixel opening 22 formed by the pixel defining portion 21; the light-emitting layer 30 is located on the side of the pixel definition layer 20 away from the array substrate 10, and the light-emitting layer 30 includes a light-emitting unit 31 located in the pixel opening 22; the first electrode layer 40 is located on the side of the pixel definition layer 20 away from the array substrate 10 and includes a first electrode 41; the functional layer 50 is located on the side of the first electrode layer 40 away from the array substrate 10; and the cover plate 60 is located on the side of the functional layer 50 away from the array substrate 10.

[0097] In the optional embodiments, the pixel defining portion 21 of the pixel definition layer 20 encloses the pixel opening 22 to set the light emitting unit 31 and realize normal light emission of the light emitting unit 31. The pixel defining portion 21 defines the setting area of each light emitting unit 31 to reduce the cross-color defect between the light emitting units 31. The cover plate 60 protects the display panel to improve the service life of the display panel.

[0098] Optionally, the functional layer 50 includes a touch layer to realize the touch function of the display panel.

[0099] Optionally, the display panel further includes a pixel electrode 23 exposed by the pixel opening 22. One of the pixel electrode 23 and the first electrode 41 serves as an anode of the light emitting unit 31, and the other serves as a cathode of the light emitting unit 31. The embodiments of the present application take the pixel electrode 23 as the anode of the light emitting unit 31 and the first electrode 41 as the cathode of the light emitting unit 31 as an example. The embodiments of the third aspect of the present application also provide a display device including the display panel of any one of the second aspect embodiments. Since the display device provided by the third aspect of the present application includes the display panel of any one of the second aspect embodiments, the display device provided by the third aspect of the present application has the beneficial effects of the display panel of any one of the second aspect embodiments, which will not be described here.

[0100] The display device in the embodiments of the present application includes but is not limited to a mobile phone, a personal digital assistant (PDA), a tablet computer, an electronic book, a television, an access control, a smart fixed phone, a console, and other display devices with display functions.

[0101] Please refer to Figure 11 , Figure 11 FIG. 1 is a flow diagram of a control method of an array substrate according to an embodiment of the fourth aspect of the present application.

[0102] As shown in Figure 11 , the fourth aspect of the present application provides a control method of an array substrate 10 for controlling any one of the array substrates 10. The control method of the array substrate 10 includes:

[0103] Step S01: Adjusting the potential of the potential control portion to make the absolute value of the opening voltage of the first channel region greater than the absolute value of the opening voltage of the second channel region.

[0104] Step S02: Adjusting the potential of the first gate to make the first channel region open or close.

[0105] According to the control method of the embodiment of the present application, the potential of the potential control unit 310 is adjusted through step S01, so as to adjust the turn-on voltage of the first channel region 221, and make the absolute value of the turn-on voltage of the first channel region 221 greater than the absolute value of the turn-on voltage of the second channel region 222. The potential of the first gate 230 is adjusted through step S02, so as to make the first channel region 221 turn on or off. Since the length of the second channel region 222 is greater than the length of the first channel region 221, when the first channel region 221 is off, the active layer 220 behaves as the device characteristics of the second channel region 222, that is, the transistor 210 has a larger subthreshold swing; when the first channel region 221 is on, since the first channel region 221 is shorter, the current will flow through the first channel region 221 rather than the second channel region 222, and the active layer 220 behaves as the device characteristics of the first channel region 221, that is, the transistor 210 has a larger on-state current, so as to realize that the array substrate 10 can have a larger subthreshold swing and a larger on-state current at the same time, and improve the use performance of the array substrate 10.

[0106] In accordance with the embodiments of the present application described above, these embodiments do not describe all the details, nor limit the present application to only the specific embodiments described. Obviously, according to the above description, many modifications and changes can be made. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that, include: Substrate; An array layer is located on one side of the substrate. The array layer includes transistors. Each transistor includes an active layer and a first gate. The first gate is located on the side of the active layer opposite to the substrate. The active layer includes a first channel region, a second channel region, a first source region, and a first drain region. The first channel region and the second channel region are respectively connected between the first source region and the first drain region. The length of the second channel region is greater than the length of the first channel region. The orthographic projections of the first channel region and the second channel region on the substrate are both located within the orthographic projection of the first gate on the substrate. A metal layer is located on the side of the active layer close to the substrate. The metal layer includes a potential control section. The orthographic projection of the potential control section on the substrate at least partially overlaps with the orthographic projection of the first channel region on the substrate. The orthographic projection of the potential control section on the substrate is located outside the orthographic projection of the second channel region on the substrate.

2. The array substrate according to claim 1, characterized in that, The first channel region includes a main body and a connecting part. The connecting part is located at both ends of the main body near the first source region and the first drain region. The two ends of the second channel region are respectively connected to the connecting parts at both ends of the main body.

3. The array substrate according to claim 2, characterized in that, The orthographic projection of the main body on the substrate and the orthographic projection of the potential control part on the substrate at least partially overlap.

4. The array substrate according to claim 2, characterized in that, The orthographic projection of the main body portion onto the substrate is located within the orthographic projection of the potential control portion onto the substrate; Alternatively, the orthographic projection of the main body on the substrate coincides with the orthographic projection of the potential control unit on the substrate.

5. The array substrate according to claim 2, characterized in that, The orthographic projection of the potential control unit onto the substrate is located outside the orthographic projection of the connection unit onto the substrate.

6. The array substrate according to claim 1, characterized in that, The active layer includes a polycrystalline oxide semiconductor, and the potential control unit is used to make the turn-on voltage of the first channel region less than the turn-on voltage of the second channel region; Alternatively, the active layer may include an oxide semiconductor, and the potential control unit may be configured to make the turn-on voltage of the first channel region greater than the turn-on voltage of the second channel region.

7. The array substrate according to claim 1, characterized in that, The orthographic projection of the second channel region onto the substrate is arc-shaped or zigzag-shaped.

8. The array substrate according to claim 1, characterized in that, The array layer further includes: A first inorganic layer is located between the active layer and the first gate. The second inorganic layer is located between the metal layer and the active layer, and the thickness of the first inorganic layer in the thickness direction of the array substrate is greater than the thickness of the second inorganic layer.

9. The array substrate according to claim 1, characterized in that, The array layer further includes a source-drain layer and an insulating layer. The insulating layer is located on the side of the first gate away from the substrate, and the source-drain layer is located on the side of the insulating layer away from the substrate. The source-drain layer includes a source and a drain. The source is connected to a via in the first source region, and the drain is connected to a via in the first drain region.

10. The array substrate according to claim 1, characterized in that, The array substrate further includes a buffer layer located between the substrate and the metal layer.

11. The array substrate according to claim 1, characterized in that, The array substrate further includes: An isolation structure is located on the side of the array layer away from the substrate. The isolation structure encloses and forms a plurality of isolation openings, which are used to house the light-emitting units of the display panel.

12. The array substrate according to claim 11, characterized in that, The isolation structure includes a first layer and a second layer located on the side of the first layer facing away from the substrate, wherein the orthographic projection of the first layer onto the substrate lies within the orthographic projection of the second layer onto the substrate.

13. The array substrate according to claim 12, characterized in that, The first layer comprises a conductive material.

14. The array substrate according to claim 12, characterized in that, The second layer comprises a conductive material or an insulating material.

15. The array substrate according to claim 12, characterized in that, The second layer comprises a metallic material, and the materials of the first layer and the second layer are different.

16. The array substrate according to claim 12, characterized in that, The isolation structure further includes a third layer located on the side of the first layer facing the substrate, wherein the orthographic projection of the first layer onto the substrate lies within the orthographic projection of the third layer onto the substrate.

17. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-16.

18. A display device, characterized in that, Includes the display panel as described in claim 17.

19. A method for controlling an array substrate, used to control the array substrate according to any one of claims 1-6, characterized in that, include: The potential of the potential control unit is adjusted so that the absolute value of the turn-on voltage of the first channel region is greater than the absolute value of the turn-on voltage of the second channel region. Adjust the potential of the first gate to turn the first channel region on or off.

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