A MOSFET structure and a method of fabricating the same

Abstract

The application discloses a MOSFET structure and a preparation method thereof, and belongs to the technical field of semiconductors; the MOSFET structure is composed of a plurality of mutually-parallel MOS cells, and a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source and a gate; the application sets a lightly-doped N layer in the middle of an N drift layer, and cooperates with the design of arc-shaped side-symmetrical P-layers on both sides, so that the electric field distribution in the device is effectively optimized; the lightly-doped N layer widens the depletion region between the channel and the drain, weakens the penetration of the drain electric field to the channel, the arc-shaped side-symmetrical P-layers are in direct contact with the N substrate layer to form a lateral field limiting ring, the electric field concentration is further dispersed, the drain-induced barrier lowering effect and the hot carrier effect are reduced, the control ability of the gate to the channel is enhanced, and thus the problems of the increase of subthreshold swing and the threshold voltage drift are inhibited, and the switch controllability of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a MOSFET structure and a preparation method thereof. BACKGROUND

[0002] Since the metal oxide semiconductor field effect transistor (MOSFET) was invented, it has played an irreplaceable core role in many electronic fields such as integrated circuits due to its unique advantages. In the early stage, the growth of a high-quality thermal oxide SiO2 thin layer on the silicon surface effectively neutralized the surface state, laying a key foundation for the birth of MOSFET. Since then, with the continuous evolution of technology, MOSFET has been widely used in various circuits from simple driving circuits to complex power rectifiers, inverters, etc., becoming the cornerstone of modern electronic systems.

[0003] The prior art (publication number: CN119947193A) discloses a Schottky thin film transistor structure based on a polycrystalline indium oxide active layer and a preparation method thereof. The technology includes a substrate, a gate electrode, a gate dielectric layer, an active layer, a barrier layer, an ohmic contact electrode, and a Schottky contact electrode which are sequentially stacked. The active layer covers the gate dielectric layer, and the active layer is polycrystalline indium oxide grown by metal organic chemical vapor deposition, with an optical band gap > 3.1eV. The barrier layer completely covers the active layer, and the barrier layer uses an insulating material with a high band gap. The thickness of the barrier layer is ≤ 5nm. The active layer uses polycrystalline indium oxide to improve the saturation current of the Schottky thin film transistor. The high band gap insulating material with a thickness not exceeding 5nm is used as the barrier layer to reduce the off-state current of the indium oxide Schottky transistor.

[0004] However, as integrated circuits develop towards higher integration and faster operation speed, the feature size of MOSFET is continuously reduced to achieve higher device density and faster switching speed. However, when the device size enters the nanometer scale range, the short channel effect becomes more and more significant, causing the drain-induced barrier lowering effect and the hot carrier effect to intensify. The short channel effect weakens the effective control of the gate on the channel, leading to an increase in the subthreshold swing, a decrease in the threshold voltage and difficulty in precise control, which in turn significantly increases the leakage current of the device, not only greatly increasing the power consumption, but also seriously affecting the switching speed and reliability of the device, greatly limiting the further improvement of the performance of integrated circuits. SUMMARY

[0005] The purpose of the present application is to provide a solution to the problems raised in the background art.

[0006] Technical solution: A MOSFET structure and a preparation method thereof, comprising a plurality of mutually juxtaposed MOS cells, a single MOS cell comprising a drain, a semiconductor epitaxial layer, a source and a gate; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, an N well layer and a P well layer, a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell;

[0007] A side-symmetrical P- layer is arranged inside a single MOS cell and on the left and right sides of the N drift layer, the cross-sectional profiles of the two side-symmetrical P- layers are arc-shaped, and the bottom ends of the two side-symmetrical P- layers are in contact with the upper surface of the N substrate layer.

[0008] Furthermore, a semicircular P- layer is formed inside the lightly doped N layer by ion implantation, and the bottom end of the semicircular P- layer is in contact with the upper surface of the N substrate layer.

[0009] Furthermore, a heavily doped N layer is formed outside the semicircular P- layer inside the lightly doped N layer by ion implantation, the cross-sectional profiles of the heavily doped N layer are semicircular, and the inside of the heavily doped N layer is in contact with the outside of the semicircular P- layer.

[0010] Furthermore, a semicircular P- layer is formed inside the lightly doped N layer by ion implantation, and the bottom end of the semicircular P- layer is in contact with the upper surface of the N substrate layer.

[0011] Furthermore, a trapezoidal heavily doped N-type half layer is formed outside the heavily doped N layer on the left and right sides of the lightly doped N layer by ion implantation.

[0012] Furthermore, a Y-shaped heavily doped N-type half layer is formed inside the lightly doped N layer by ion implantation, and the bottom end of the Y-shaped heavily doped N-type half layer is in contact with the upper surface of the N substrate layer.

[0013] Furthermore, a triangular heavily doped N-type half layer is formed inside the lightly doped N layer on the left and right sides by ion implantation, and the bottom ends of the two triangular heavily doped N-type half layers are in contact with the upper surface of the N substrate layer.

[0014] A MOSFET structure preparation method, comprising:

[0015] S1, the N substrate layer is sequentially cleaned with acetone, ethanol and deionized water by ultrasonic cleaning to remove surface organic matter and impurity particles, and then dried in an oven, and then treated by oxygen plasma to improve surface activity;

[0016] S2, depositing the N drift layer on the N substrate layer by low pressure chemical vapor deposition technology, the reaction gas being a mixture of silane and phosphine, and performing high temperature annealing in a nitrogen atmosphere after deposition to eliminate lattice defects generated in the deposition process;

[0017] S3, forming a rectangular mask pattern of the lightly doped N layer in the middle region of the N drift layer by photolithography, then implanting nitrogen ions into the rectangular mask pattern region by ion implantation to form the lightly doped N layer, removing the photoresist after implantation, then defining an arc-shaped region of the side-symmetrical P-layer by a new photolithography mask, implanting boron ions, and forming the arc-shaped cross section of the side-symmetrical P-layer by thermal diffusion process to ensure that the bottom end thereof is in contact with the upper surface of the N substrate layer, and placing it in an annealing furnace after implantation to repair lattice damage;

[0018] S4, defining a semicircular region one inside the lightly doped N layer by photolithography, then implanting boron ions into the semicircular region one by ion implantation to form the semicircular P-layer, ensuring that the bottom end thereof is in contact with the upper surface of the N substrate layer, then defining a semicircular region two outside the semicircular P-layer by photolithography, implanting phosphorus ions into the semicircular region two to form the heavily doped N layer, and making the inner side thereof in close contact with the outer side of the semicircular P-layer, and placing it in an annealing furnace after implantation to repair lattice damage;

[0019] S5, defining a semi-elliptical region at the top end of the heavily doped N layer by photolithography, implanting boron ions into the semi-elliptical region to form the semi-elliptical P-layer by ion implantation, and performing annealing after completion to activate the implanted impurity ions;

[0020] S6, then defining trapezoidal regions on the left and right sides of the lightly doped N layer by photolithography, implanting phosphorus ions into the trapezoidal regions to form the trapezoidal heavily doped N-type half layer by ion implantation, and then performing annealing to further activate impurities and repair lattice damage;

[0021] S7, implanting corresponding impurities in the specified regions in sequence to form the P+ layer, the N well layer and the P well layer by combining photolithography and ion implantation, wherein the P+ layer is implanted with boron ions, the N well layer is implanted with phosphorus ions, and the P well layer is implanted with boron ions, and performing annealing treatment after implantation to activate impurities and repair lattice damage;

[0022] S8, finally depositing and patterning metal layers in sequence by photolithography or sputtering process to form ohmic contact and Schottky contact of the drain, the source and the gate.

[0023] Advantages:

[0024] 1. The application effectively optimizes the electric field distribution inside the device by setting a lightly doped N layer in the middle of the N drift layer and designing arc-shaped symmetric P-layers on both sides, the lightly doped N layer widens the depletion region between the channel and the drain, weakening the penetration of the drain electric field to the channel, the arc-shaped symmetric P-layers directly contact with the N substrate layer to form a lateral field limiting ring, further dispersing the electric field concentration, reducing the drain-induced barrier lowering effect and hot carrier effect, and enhancing the control ability of the gate to the channel, thereby suppressing the problems of increased sub-threshold swing and threshold voltage drift, and improving the switch controllability of the device;

[0025] 2. The complementary doping structure is composed of the semicircular P-layer inside the lightly doped N layer, the heavily doped N layer and the semieliptical P-layer at the top, the gradient barrier design strengthens the constraint on carrier transport, the semicircular P-layer contacts with the N substrate layer to form a longitudinal PN junction, expands the space charge region to suppress the leakage current, the heavily doped N layer provides a low resistance conductive channel to reduce current transmission loss, and the semieliptical P-layer adjusts the electric field at the top of the heavily doped N layer to avoid abnormal aggregation of carriers, the synergistic effect of the three significantly reduces the device leakage current, reduces power consumption, and improves the switching speed;

[0026] 3. The symmetrical design of the trapezoidal heavily doped N-type half layer makes the carrier transport path in the nanochannel more uniform, avoiding thermal failure caused by excessive local current, in addition, the special morphology of the Y-shaped and triangular heavily doped N-type half layer further optimizes the carrier transport efficiency through multi-path conduction design and natural doping gradient, and enhances the electrical performance consistency of the device;

[0027] 4. The preparation process of the application adopts the combination of photolithography and ion implantation to realize precise doping and patterning of each functional layer, and cooperates with multi-step annealing treatment to effectively repair lattice damage and activate impurities, ensuring the stability and reliability of the device structure, the synergistic effect of the overall structure and process enables the device to maintain excellent electrical performance at the nanoscale, breaking through the bottleneck of traditional MOSFET in high-density integration and high-performance application, and providing strong support for the further development of integrated circuits. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a structure schematic diagram of embodiment 1 of the application;

[0029] Figure 2 is a structure schematic diagram of embodiment 2 of the application;

[0030] Figure 3 is a structure schematic diagram of embodiment 3 of the application;

[0031] Figure 4 is a structure schematic diagram of embodiment 4 of the application;

[0032] Figure 5 is a structural schematic diagram of embodiment 5 of the present application;

[0033] Figure 6 is a structural schematic diagram of embodiment 6 of the present application;

[0034] Figure 7 is a structural schematic diagram of embodiment 7 of the present application.

[0035] In the figure: 1, drain; 2, source; 3, gate; 4, N substrate layer; 5, N drift layer; 6, P+ layer; 7, N well layer; 8, P well layer; 9, lightly doped N layer; 10, side-symmetrical P- layer; 11, semicircular P- layer; 12, heavily doped N layer; 13, semieliptical P- layer; 14, trapezoidal heavily doped N half layer; 15, Y-shaped heavily doped N half layer; 16, triangular heavily doped N half layer. DETAILED DESCRIPTION

[0036] In order to make the technical scheme of the present application clearer, the present application is further described in detail below in combination with the drawings and specific embodiments.

[0037] As shown in Figures 1-7 , according to one aspect of the present application, a MOSFET structure preparation method is provided, which comprises:

[0038] Step one: the N substrate layer 4 is sequentially ultrasonically cleaned with acetone, ethanol and deionized water to remove surface organic matter and impurity particles, and then dried in an oven and treated by oxygen plasma to improve surface activity; the N substrate layer 4 is treated by acetone to dissolve surface grease organic matter, treated by ethanol to remove residual acetone and further degrease, and treated by deionized water to rinse residual chemical reagents and particle impurities, so as to avoid defects caused by impurities in subsequent thin film deposition, enhance the adhesion between the N substrate layer 4 and the subsequent N drift layer 4, and reduce the risk of interface peeling.

[0039] Step two: the N drift layer 5 is deposited on the N substrate layer 4 by using low-pressure chemical vapor deposition technology, and the reaction gas is a mixture of silane and phosphine; after deposition, high-temperature annealing is performed in a nitrogen atmosphere to eliminate lattice defects generated in the deposition process; silane provides a silicon skeleton, and phosphine serves as a donor impurity source; by adjusting the proportion of the two, the doping concentration of the N drift layer 5 is accurately controlled to ensure that it is an N-type semiconductor; and by high-temperature annealing in a nitrogen atmosphere, the lattice atoms are rearranged to eliminate vacancies, dislocations and other defects generated in the deposition process due to disordered atomic arrangement, thereby improving the carrier mobility.

[0040] Step three: Form a rectangular mask pattern of the lightly doped N layer 9 in the middle of the N drift layer 5 by photolithography technology, and then use ion implantation process to implant nitrogen ions into the rectangular mask pattern area to form the lightly doped N layer 9. After implantation, the photoresist is removed, and then the arc-shaped area of the side-symmetrical P-layer 10 is defined by a new photolithography mask, boron ions are implanted, and the side-symmetrical P-layer 10 is formed into an arc-shaped cross section by a thermal diffusion process to ensure that its bottom end is in contact with the upper surface of the N substrate layer 4. After implantation, it is placed in an annealing furnace to repair lattice damage; the lightly doped N layer 9 is located in the middle of the N drift layer 5 and serves as an auxiliary channel for carrier transport. Its low doping characteristic can reduce the on-resistance, and at the same time, a doping gradient is formed with the surrounding area to optimize the electric field distribution. The side-symmetrical P-layer 10 can disperse the electric field concentration at the corner through arc-shaped structure design to improve the device breakdown voltage. The bottom end is in contact with the N substrate layer 4 to form a "lateral PN junction", further optimizing the electric field distribution of the N drift layer 5 and suppressing avalanche breakdown on the side of the drain 1. The boron ions are diffused along the arc-shaped path by thermal diffusion to form a smooth doping profile. Annealing repairs the lattice damage caused by ion implantation, activates the impurity ions, and restores the semiconductor conductivity.

[0041] Step four: Define a semicircular area one inside the lightly doped N layer 9 by photolithography, and then use ion implantation process to implant boron ions into the semicircular area one to form a semicircular P-layer 11, ensuring that its bottom end is in contact with the upper surface of the N substrate layer 4. Then define a semicircular area two outside the semicircular P-layer 11 by photolithography, implant phosphorus ions into the semicircular area two to form a heavily doped N layer 12, and make its inside closely contact with the outside of the semicircular P-layer 11. After implantation, it is placed in an annealing furnace to repair lattice damage; the semicircular P-layer 11 is part of the "field limiting ring" and forms a PN junction with the N-type layer. Through the expansion of the space charge region, the electric field is further dispersed to improve the device's voltage resistance capability. The heavily doped N layer 12 forms a low-resistance channel by high phosphorus doping to connect the drain 1 and the N drift layer 5, reducing the contact resistance. At the same time, it forms a "complementary doping structure" with the semicircular P-layer 11 on the inside, optimizing the carrier transport path. The semicircular design makes the interface between the semicircular P-layer 11 and the heavily doped N layer 12 smooth, avoiding the electric field concentration caused by the right-angle structure. The close contact between the two ensures the continuous transition of carriers from the N layer to the P-layer, reducing interface scattering.

[0042] Step five: Define a semi-elliptical area at the top of the heavily doped N layer 12 by photolithography process, and use ion implantation process to implant boron ions into the semi-elliptical area to form a semi-elliptical P-layer 13. After completion, annealing is performed to activate the implanted impurity ions; the heavily doped N layer 12 makes the doping concentration smoothly transition from the center to the edge through the semi-elliptical profile, avoiding carrier traps caused by steep interfaces and improving the switching speed of the device.

[0043] Step six: Then define the trapezoidal area on the left and right side of the lightly doped N layer 9 by photoetching, and inject phosphorus ions into the trapezoidal area by ion implantation process to form trapezoidal heavily doped N type semi-layer 14, and then perform annealing to further activate impurities and repair lattice damage; The trapezoidal structure of the two trapezoidal heavily doped N type semi-layers 14 can increase the contact area with the source 2 metal, reduce the contact resistance, and ensure uniform current distribution on both sides of the device by symmetrical distribution on the left and right, avoiding thermal failure caused by excessive local current.

[0044] Step seven: Use photoetching and ion implantation to sequentially implant corresponding impurities in the specified area to form P+ layer 6, N well layer 7 and P well layer 8, wherein P+ layer 6 implants boron ions, N well layer 7 implants phosphorus ions, and P well layer 8 implants boron ions. After implantation, annealing is performed to activate impurities and repair lattice damage; The three-layer structure together forms the core conductive channel region of the device, P+ layer 6 provides a low-resistance carrier injection path, N well layer 7 and P well layer 8 form a conductive channel under the control of the gate voltage, and annealing activates impurities and repairs the lattice to ensure excellent performance of the channel region.

[0045] Step eight: Finally, through photoetching or sputtering process, metal layers are sequentially deposited and patterned to form ohmic contact and Schottky contact of drain 1, source 2 and gate 3; Good electrode contact is the guarantee of normal work of the device, ohmic contact ensures low-loss transmission of carriers, and Schottky contact ensures effective control of the gate on the channel, realizing high performance of the device.

[0046] Embodiment 1

[0047] As shown in Figure 1 , a MOSFET structure is provided, which is composed of a plurality of mutually juxtaposed MOS cells, and a single MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2 and a gate 3; The semiconductor epitaxial layer includes an N substrate layer 4, an N drift layer 5, a P+ layer 6, an N well layer 7 and a P well layer 8, and the N drift layer 5 of a single MOS cell is provided with a lightly doped N layer 9 in the middle;

[0048] The lightly doped N layer 9 in the middle of the N drift layer 5 can optimize the electric field distribution between the channel and the drain 1, reduce the abnormal transport of carriers, thereby inhibiting the increase of leakage current, and the N substrate layer 4 provides stable support, reduces the structural defects caused by unstable substrate, and cooperates with the synergistic effect of P+ layer 6, N well layer 7, P well layer 8 and other layers to make the carrier transport more orderly, improve the switching speed of the device, at the same time, the reasonable layout of each layer reduces the aging speed of the device caused by excessive leakage current, enhances the stability during work, improves the reliability, and finally breaks the limitation of leakage current problem on the performance improvement of integrated circuit, creating conditions for the realization of higher performance integrated circuit.

[0049] Embodiment 2

[0050] As shown in Figure 2 , the inside of the single MOS cell and the left and right sides of the N drift layer 5 are provided with side-symmetrical P-layers 10, the cross-sectional profiles of the two side-symmetrical P-layers 10 are arc-shaped, and the bottom ends of the two side-symmetrical P-layers 10 are in contact with the upper surface of the N substrate layer 4;

[0051] The arc-shaped profiles of the side-symmetrical P-layers 10 provided inside the single MOS cell and on the left and right sides of the N drift layer 5 can make the electric field uniformly distributed at the interface between the side-symmetrical P-layers 10 and the surrounding N-type region, avoiding the concentration of electric field caused by the right-angle or acute-angle structure, thereby reducing the abnormal multiplication and injection of carriers, and the layout of the two side-symmetrical P-layers 10 can balance the electrical properties of the left and right sides of the device, ensuring the symmetry and stability of the carrier transport path, while the design that the bottom ends are in direct contact with the N substrate layer 4 can expand the space charge region through the lateral PN junction formed by the side-symmetrical P-layers 10 and the N substrate layer 4, further optimize the electric field distribution of the entire drift region, enhance the inhibition of the penetration of the drain electric field to the channel region, and at the same time, improve the withstand voltage capability of the device under reverse bias, reduce the risk of leakage and breakdown caused by excessive local electric field, and finally improve the overall stability and working reliability of the device.

[0052] Embodiment 3

[0053] As shown in Figure 3 , the inside of the lightly doped N layer 9 is formed with a semicircular P-layer 11 by ion implantation, and the bottom end of the semicircular P-layer 11 is in contact with the upper surface of the N substrate layer 4;

[0054] The semicircular P-layer 11 formed inside the lightly doped N layer 9 by ion implantation has a semicircular profile that makes the interface between the P-layer 11 and the surrounding lightly doped N layer 9 smoothly transition, avoiding the concentration of electric field caused by steep boundaries, which helps to optimize the local electric field distribution, and the bottom end is in direct contact with the N substrate layer 4, which can expand the space charge region through the longitudinal PN junction formed by the P-layer 11 and the N substrate layer 4, enhance the constraint on the movement of carriers near the channel, reduce the uncontrolled current between the drain and the source, and at the same time, cooperate with the side-symmetrical P-layer 10 to further improve the control ability of the gate 3 on the channel, inhibit abnormal leakage caused by structural defects or electric field disorder, thereby enhancing the stability and reliability of the device in operation.

[0055] Embodiment 4

[0056] As shown in Figure 4 , the inside of the lightly doped N layer 9 and outside of the semicircular P-layer 11 are formed with a heavily doped N layer 12 by ion implantation, the cross-sectional profiles of the heavily doped N layer 12 are semicircular, and the inside of the heavily doped N layer 12 is in contact with the outside of the semicircular P-layer 11;

[0057] The semicircular P-layer 11 outside and the semicircular heavy-doped N-layer 12 inside the lightly-doped N-layer 9 are formed by ion implantation. The semicircular profile of the semicircular heavy-doped N-layer 12 forms a smooth arc-shaped interface with the outside of the semicircular P-layer 11, ensuring close contact and smooth transition between the two, avoiding stress concentration and charge accumulation at the interface, and facilitating smooth transport of carriers between adjacent regions. The heavy-doped characteristic makes the region have low resistance characteristics, which can serve as an efficient conduction channel for carriers, reducing energy loss during current transmission. At the same time, it forms a complementary doping structure with the semicircular P-layer 11 on the inside, further optimizing the electric field distribution inside the lightly-doped N-layer 9 through the synergistic effect of the two, enhancing the potential control ability of the channel region, suppressing unnecessary leakage current paths, and improving the switching response speed and working stability of the device in cooperation with other layered structures.

[0058] Example 5

[0059] As shown in Figure 5 , the top end of the heavy-doped N-layer 12 is formed with a semi-elliptical P-layer 13 by ion implantation, and the left and right sides of the lightly-doped N-layer 9 and outside the heavy-doped N-layer 12 are formed with trapezoidal heavy-doped N-type half-layers 14 by ion implantation.

[0060] The semi-elliptical P-layer 13 formed at the top end of the heavy-doped N-layer 12 by ion implantation, and the trapezoidal heavy-doped N-type half-layers 14 formed on the left and right sides of the lightly-doped N-layer 9 and outside the heavy-doped N-layer 12 by ion implantation, the arc profile of the semi-elliptical P-layer 13 can smoothly connect with the top end of the heavy-doped N-layer 12, and can adjust the electric field distribution at the top end of the heavy-doped N-layer 12 through its P-type characteristics during device operation, suppress abnormal aggregation of carriers in this region, and reduce leakage caused by excessive local electric field. The trapezoidal structure of the trapezoidal heavy-doped N-type half-layers 14 can expand the contact area with adjacent layers, and its heavy-doped characteristics ensure a low-resistance path for carrier transport. At the same time, the symmetrical layout on the left and right can balance the current distribution on both sides of the lightly-doped N-layer 9, avoiding local overheating caused by excessive current on one side. The semi-elliptical P-layer 13 and the trapezoidal heavy-doped N-type half-layers 14 cooperate with each other to further optimize the potential gradient inside the entire lightly-doped N-layer 9, enhance the control accuracy of the gate on the channel, and improve the switching consistency and working reliability of the device.

[0061] Example 6

[0062] As shown in Figure 6 , the inside of the lightly-doped N-layer 9 is formed with a Y-shaped heavy-doped N-type half-layer 15 by ion implantation, and the bottom end of the Y-shaped heavy-doped N-type half-layer 15 is in contact with the upper surface of the N-substrate layer 4.

[0063] The Y-shaped branch structure can form multiple low-resistance conductive channels within the lightly doped N-layer 9, improving carrier transport efficiency. At the same time, the junction of the main branch and the branch can disperse the current density, avoiding overheating caused by local current concentration. The bottom end is in direct contact with the N-substrate layer 4, which can establish a stable conductive connection from the substrate to the interior of the lightly doped N-layer 9, enhancing the electrical synergy between different regions. The interface formed by the Y-shaped profile and the surrounding lightly doped N-layer 9 can optimize the local electric field distribution, reduce scattering and loss during carrier transport, and further enhance the gate's ability to control the channel in conjunction with other doped layers, thereby enhancing the device's switching response speed and operating stability.

[0064] Example 7

[0065] like Figure 7 As shown, triangular heavily doped N-type half-layers 16 are formed on the left and right sides of the interior of the lightly doped N-layer 9 by ion implantation, and the bottom ends of the two triangular heavily doped N-type half-layers 16 are in contact with the upper surface of the N substrate layer 4.

[0066] The triangular heavily doped N-type half-layer 16 has its vertices facing inwards towards the device and its base connected to the N-substrate layer 4. This shape allows the heavily doped region to gradually narrow upwards from the substrate, forming a natural doping concentration gradient. This helps to smoothly transport charge carriers from the substrate to the channel region, reducing abrupt changes in resistance at the interface. The symmetrically distributed triangular structures on both sides can balance the current path inside the lightly doped N-layer 9, avoiding the accumulation of charge carriers on one side. At the same time, the sides of the triangle can disperse the local electric field, preventing abnormal movement of charge carriers caused by electric field concentration. The contact between the bottom end and the N-substrate layer 4 strengthens the electrical connection between the substrate and the active region. Together with other doped layers, it optimizes the conductivity and gate control efficiency of the device, improving the overall operational stability.

[0067] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A MOSFET structure comprising a plurality of parallel MOS cells, each MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (2), and a gate (3); the semiconductor epitaxial layer comprising an N-substrate layer (4), an N-drift layer (5), a P+ layer (6), an N-well layer (7), and a P-well layer (8), characterized in that: A lightly doped N layer (9) is provided in the middle of the N drift layer (5) of a single MOS cell; A laterally symmetrical P-layer (10) is provided inside a single MOS cell and on the left and right sides of the N drift layer (5). The cross-sectional profiles of the two laterally symmetrical P-layers (10) are both arc-shaped, and the bottom ends of the two laterally symmetrical P-layers (10) are in contact with the upper surface of the N substrate layer (4). The interior of the lightly doped N layer (9) is formed by ion implantation of a semi-circular P-layer (11), the bottom end of which is in contact with the upper surface of the N substrate layer (4). A heavily doped N layer (12) is formed by ion implantation inside the lightly doped N layer (9) and outside the semi-circular P-layer (11). The cross-sectional profile of the heavily doped N layer (12) is semi-circular, and the inner side of the heavily doped N layer (12) is in contact with the outer side of the semi-circular P-layer (11). The top of the heavily doped N layer (12) is formed with a semi-elliptical P-layer (13) by ion implantation.

2. The MOSFET structure according to claim 1, characterized in that: The left and right sides of the lightly doped N layer (9) and the outer side of the heavily doped N layer (12) are both formed by ion implantation to form trapezoidal heavily doped N-type half-layers (14). The opposite sides of the two trapezoidal heavily doped N-type half-layers (14) are in contact with the opposite sides of the two N drift layers (5).

3. A MOSFET structure comprising a plurality of parallel MOS cells, each MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (2), and a gate (3); the semiconductor epitaxial layer comprising an N-substrate layer (4), an N-drift layer (5), a P+ layer (6), an N-well layer (7), and a P-well layer (8), characterized in that: A lightly doped N layer (9) is provided in the middle of the N drift layer (5) of a single MOS cell; A laterally symmetrical P-layer (10) is provided inside a single MOS cell and on the left and right sides of the N drift layer (5). The cross-sectional profiles of the two laterally symmetrical P-layers (10) are both arc-shaped, and the bottom ends of the two laterally symmetrical P-layers (10) are in contact with the upper surface of the N substrate layer (4). The interior of the lightly doped N layer (9) is formed by ion implantation of a Y-shaped heavily doped N-type half-layer (15), and the bottom end of the Y-shaped heavily doped N-type half-layer (15) is in contact with the upper surface of the N substrate layer (4).

4. A MOSFET structure comprising a plurality of parallel MOS cells, each MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (2), and a gate (3); the semiconductor epitaxial layer comprising an N-substrate layer (4), an N-drift layer (5), a P+ layer (6), an N-well layer (7), and a P-well layer (8), characterized in that: A lightly doped N layer (9) is provided in the middle of the N drift layer (5) of a single MOS cell; A laterally symmetrical P-layer (10) is provided inside a single MOS cell and on the left and right sides of the N drift layer (5). The cross-sectional profiles of the two laterally symmetrical P-layers (10) are both arc-shaped, and the bottom ends of the two laterally symmetrical P-layers (10) are in contact with the upper surface of the N substrate layer (4). The lightly doped N layer (9) has triangular heavily doped N-type half-layers (16) formed on its left and right sides by ion implantation. The bottom ends of the two triangular heavily doped N-type half-layers (16) are in contact with the upper surface of the N substrate layer (4).

5. A method for fabricating a MOSFET structure, characterized in that, The fabrication method, applied to the MOSFET structure of claim 2, comprises the following steps: S1. Select N substrate layer (4), and clean the N substrate layer (4) sequentially with acetone, ethanol and deionized water by ultrasonic cleaning to remove surface organic matter and impurity particles. Then dry it in an oven and then treat it with oxygen plasma to improve surface activity. S2. The N drift layer (5) is deposited on the N substrate layer (4) using low-pressure chemical vapor deposition technology. The reaction gas is a mixture of silane and phosphine. After deposition, high-temperature annealing is performed in a nitrogen atmosphere to eliminate lattice defects generated during the deposition process. S3. A rectangular mask pattern of the lightly doped N layer (9) is formed in the middle region of the N drift layer (5) by photolithography. Then, nitrogen ions are implanted into the rectangular mask pattern area by ion implantation process to form the lightly doped N layer (9). After implantation, the photoresist is removed. Then, the arc-shaped region of the side-symmetric P-layer (10) is formed by defining a new photolithography mask. Boron ions are implanted, and the side-symmetric P-layer (10) is made into an arc-shaped cross-section by thermal diffusion process to ensure that its bottom end is in contact with the upper surface of the N substrate layer (4). After implantation, it is placed in an annealing furnace to repair lattice damage. S4. A semi-circular region one is defined inside the lightly doped N layer (9) by photolithography. Then, boron ions are implanted into the semi-circular region one to form the semi-circular P-layer (11) by ion implantation process, ensuring that its bottom end is in contact with the upper surface of the N substrate layer (4). Then, a semi-circular region two is defined outside the semi-circular P-layer (11) by photolithography. Phosphorus ions are implanted into the semi-circular region two to form the heavily doped N layer (12), so that its inner side is in close contact with the outer side of the semi-circular P-layer (11). After implantation, it is placed in an annealing furnace to repair lattice damage. S5. A semi-elliptical region is defined at the top of the heavily doped N layer (12) by photolithography. Boron ions are implanted into the semi-elliptical region to form the semi-elliptical P-layer (13) by ion implantation. After completion, annealing is performed to activate the implanted impurity ions. S6. Next, the trapezoidal regions are defined on the left and right sides of the lightly doped N layer (9) by photolithography. Phosphorus ions are implanted into the trapezoidal regions to form the trapezoidal heavily doped N-type half-layer (14) by ion implantation process. Then, annealing is performed to further activate impurities and repair lattice damage. S7. Using a combination of photolithography and ion implantation, corresponding impurities are sequentially implanted in the designated area to form the P+ layer (6), the N-well layer (7), and the P-well layer (8). Boron ions are implanted in the P+ layer (6), phosphorus ions are implanted in the N-well layer (7), and boron ions are implanted in the P-well layer (8). After implantation, annealing is performed to activate the impurities and repair lattice damage. S8. Finally, through photolithography or sputtering processes, metal layers are deposited and patterned sequentially to form ohmic and Schottky contacts for the drain (1), source (2) and gate (3).

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