Semiconductor structure and its fabrication method

Abstract

This disclosure relates to a semiconductor structure and its fabrication method. The semiconductor structure includes: a driving substrate, a first epitaxial structure connected to the driving substrate, and a second epitaxial structure connected to the first epitaxial structure. The driving substrate is selectively connected to a first semiconductor layer and a second semiconductor layer of the first epitaxial structure, and a third semiconductor layer and a fourth semiconductor layer of the second epitaxial structure via metal electrodes, so as to independently control the first epitaxial structure and the second epitaxial structure. On the one hand, it enables the simultaneous realization of two light-emitting units with two main emission wavelengths on the same driving substrate, thereby achieving high color rendering index LED white backlight; on the other hand, it enables independent control of the two light-emitting units, thereby achieving full-color LED display.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] With the development of technology, semiconductor devices have attracted increasing attention. Among them, light-emitting diodes, or LEDs for short, emit visible light by utilizing the recombination of electrons and holes. LEDs are widely used in lighting, backlighting, and displays.

[0003] In the field of LED backlighting, blue LEDs are usually combined with phosphors to form white LEDs, which are then used as backlights for display applications. However, the LED backlight chips prepared by this method have a low color gamut because the light-emitting units are only monochromatic, resulting in low color fidelity of the display.

[0004] In the field of LED displays, the light-emitting layer of LEDs is usually achieved by using phosphors or quantum dots for wavelength conversion, such as blue LEDs with red and green phosphors. However, the efficiency of blue light excitation of green phosphors in LED full-color chips prepared by this method is low, and the production cost of green phosphors is high. In other existing technologies, LED full-color chips can also integrate red, green and blue light-emitting units onto the same substrate by peel bonding, but this preparation method is complicated and costly.

[0005] To address these issues, LEDs that emit two wavelengths simultaneously can be used, along with red phosphors, to achieve high color rendering index LED white backlighting or full-color LED chips. However, current technology makes it difficult to create a light-emitting unit with two main emission wavelengths simultaneously on the same driving substrate. Summary of the Invention

[0006] This disclosure provides a semiconductor structure and its fabrication method. On the one hand, it enables two light-emitting units with two main emission wavelengths to be simultaneously located on the same driving substrate, thereby achieving a high color rendering index LED white backlight. On the other hand, it enables independent control of the two light-emitting units, thereby achieving full-color LED display.

[0007] According to a first aspect of this disclosure, a semiconductor structure is provided, comprising: a driving substrate; a first epitaxial structure connected to the driving substrate, the first epitaxial structure including a first semiconductor layer, a second semiconductor layer, and a first light-emitting layer located between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer and the second semiconductor layer having opposite conductivity types, and the first semiconductor layer being located on the side of the first epitaxial structure closer to the driving substrate; and a second epitaxial structure connected to the first epitaxial structure, the second epitaxial structure including a third semiconductor layer, a fourth semiconductor layer, and a second light-emitting layer located between the third semiconductor layer and the fourth semiconductor layer, the third semiconductor layer and the fourth semiconductor layer having opposite conductivity types, the second semiconductor layer and the fourth semiconductor layer having the same conductivity type, and the fourth semiconductor layer being located on the side of the second epitaxial structure closer to the first epitaxial structure, such that the fourth semiconductor layer is connected to the second semiconductor layer; wherein the driving substrate is connected to the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer respectively via metal electrodes to independently control the first epitaxial structure and the second epitaxial structure.

[0008] Optionally, the semiconductor structure further includes a transparent conductive layer located between the first epitaxial structure and the second epitaxial structure.

[0009] Optionally, the driving substrate is connected to one of the second and fourth semiconductor layers, the first semiconductor layer, and the third semiconductor layer via metal electrodes.

[0010] Optionally, the semiconductor structure further includes a first channel and a second channel; the first channel extends from the surface of the first semiconductor layer into the second semiconductor layer or the fourth semiconductor layer, so that the driving substrate is connected to the second semiconductor layer or the fourth semiconductor layer via a first electrode in the first channel; the second channel extends from the surface of the first semiconductor layer into the third semiconductor layer, so that the driving substrate is connected to the third semiconductor layer via a second electrode in the second channel; and the driving substrate is directly connected to the first semiconductor layer via a third electrode.

[0011] Optionally, an insulating layer is provided on the surface of the first semiconductor layer and on the inner sidewall surfaces of the first channel and the second channel.

[0012] Optionally, a reflective layer is disposed between the first semiconductor layer and the insulating layer.

[0013] Optionally, the material of the transparent conductive layer includes indium tin oxide.

[0014] Optionally, the first epitaxial structure has a first patterned structure, and the second epitaxial structure has a second patterned structure corresponding to the first patterned structure. The first epitaxial structure and the second epitaxial structure are connected by the interlocking of the first patterned structure and the second patterned structure.

[0015] Optionally, the second semiconductor layer and the fourth semiconductor layer are at the same horizontal position, and the adjacent second semiconductor layer and the fourth semiconductor layer are exposed simultaneously through the third channel, so that the adjacent second semiconductor layer and the fourth semiconductor layer are connected to the driving substrate through the fourth electrode, and the first semiconductor layer and the third semiconductor layer are connected to the driving substrate through the fifth electrode and the sixth electrode, respectively.

[0016] Optionally, the second semiconductor layer and the fourth semiconductor layer are not at the same horizontal position, the first semiconductor layer is connected to the driving substrate through the seventh electrode, the second semiconductor layer is connected to the driving substrate through the eighth electrode, the third semiconductor layer is connected to the driving substrate through the ninth electrode, and the fourth semiconductor layer is connected to the driving substrate through the tenth electrode.

[0017] Optionally, a passivation layer is provided between the first epitaxial structure and the second epitaxial structure.

[0018] Optionally, a protective layer is provided between the overall structure formed by the connection of the first epitaxial structure and the second epitaxial structure and the driving substrate.

[0019] Optionally, the materials of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride materials.

[0020] Optionally, the semiconductor structure also includes

[0021] The third extensional structure has a third graphical structure corresponding to the second graphical structure, and the third extensional structure and the second extensional structure are connected by the interlocking of the second graphical structure and the third graphical structure.

[0022] Optionally, the third epitaxial structure is connected to the driving substrate. The third epitaxial structure includes a fifth semiconductor layer, a third light-emitting layer, and a sixth semiconductor layer stacked together. The fifth semiconductor layer is located on the side of the third epitaxial structure closer to the driving substrate. The fifth semiconductor layer and the sixth semiconductor layer have opposite conductivity types. The first light-emitting layer, the second light-emitting layer, and the third light-emitting layer all emit different wavelengths.

[0023] According to a second aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0024] A first epitaxial structure is provided, wherein the first epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and a first light-emitting layer located between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have opposite conductivity types;

[0025] A second epitaxial structure is provided, which is connected to a first epitaxial structure. The second epitaxial structure includes a third semiconductor layer, a fourth semiconductor layer, and a second light-emitting layer located between the third semiconductor layer and the fourth semiconductor layer. The third semiconductor layer and the fourth semiconductor layer have opposite conductivity types, and the fourth semiconductor layer has the same conductivity type as the second semiconductor layer. The fourth semiconductor layer is located on the side of the second epitaxial structure closer to the first epitaxial structure, so that the fourth semiconductor layer is connected to the second semiconductor layer.

[0026] The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are selectively exposed by etching;

[0027] A driving substrate is provided, and the driving substrate is bonded to the side of the first epitaxial structure away from the second epitaxial structure; and

[0028] The driving substrate is selectively connected to the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer via metal electrodes, thereby independently controlling the first epitaxial structure and the second epitaxial structure.

[0029] Optionally, connecting the second epitaxial structure to the first epitaxial structure includes:

[0030] The first epitaxial structure and the second epitaxial structure are connected by direct bonding between the second semiconductor layer and the fourth semiconductor layer; or...

[0031] The first epitaxial structure and the second epitaxial structure are connected by a transparent conductive layer disposed between the second semiconductor layer and the fourth semiconductor layer.

[0032] Optionally, before connecting the second epitaxial structure to the first epitaxial structure, the method further includes:

[0033] The first epitaxial structure and the second epitaxial structure are graphically represented such that the first epitaxial structure has a first graphical structure and the second epitaxial structure has a second graphical structure corresponding to the first graphical structure. The first epitaxial structure and the second epitaxial structure are connected by the interlocking of the first graphical structure and the second graphical structure.

[0034] Optionally, providing the first epitaxial structure includes: providing a first substrate, and sequentially forming the first semiconductor layer and the second semiconductor layer on the first substrate;

[0035] Providing a second epitaxial structure includes: providing a second substrate, and sequentially forming the third semiconductor layer and the fourth semiconductor layer on the second substrate;

[0036] After connecting the second epitaxial structure to the first epitaxial structure, the method further includes: removing the first substrate and the second substrate.

[0037] After connecting the first epitaxial structure and the second epitaxial structure through the interlocking of the first patterned structure and the second patterned structure, the method further includes:

[0038] Provide a third extensional structure;

[0039] The third extensional structure is graphically represented such that the third extensional structure has a third graphical structure corresponding to the second graphical structure;

[0040] The third epitaxial structure is bonded to the second epitaxial structure through the intercalation and bonding of the third patterned structure and the second patterned structure.

[0041] The semiconductor structure and fabrication method disclosed herein have at least the following advantages:

[0042] By connecting a first epitaxial structure on a driving substrate and a second epitaxial structure on the first epitaxial structure, two light-emitting units (the first epitaxial structure and the second epitaxial structure) with two main emission wavelengths are realized on the same driving substrate, thereby realizing a high color rendering index LED white backlight. Furthermore, the two light-emitting units are processed simultaneously, simplifying the processing steps and saving manufacturing costs.

[0043] By selectively connecting the driving substrate to the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, the first epitaxial structure and the second epitaxial structure (two light-emitting units) can be independently controlled, enabling independent light emission from the two light-emitting units and thus achieving full-color LED display. Attached Figure Description

[0044] Figure 1This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0045] Figure 2A and Figure 2B for Figure 1 The schematic diagrams of the first epitaxial structure and the second epitaxial structure provided in the manufacturing method are shown.

[0046] Figure 3 This is a schematic diagram of a semiconductor structure according to a first embodiment of the present disclosure.

[0047] Figure 4 To make Figure 3 The diagram shows the intermediate structure corresponding to the connection step between the first epitaxial structure and the second epitaxial structure in the semiconductor structure process.

[0048] Figure 5 This is a schematic diagram of a semiconductor structure according to a second embodiment of the present disclosure.

[0049] Figure 6 To make Figure 5 The diagram shows the intermediate structure corresponding to the connection step between the first epitaxial structure and the second epitaxial structure in the semiconductor structure process.

[0050] Figure 7 To make Figure 5 The diagram shows the intermediate structure corresponding to the etching step in the semiconductor structure process.

[0051] Figure 8 This is a schematic diagram of a semiconductor structure according to a third embodiment of the present disclosure.

[0052] Figure 9 This is a schematic diagram of a semiconductor structure according to a fourth embodiment of the present disclosure.

[0053] Figures 10A to 10C To make Figure 9 A schematic diagram of the intermediate structure of the first epitaxial structure and the second epitaxial structure provided in the process of the semiconductor structure shown.

[0054] Figure 11 This is a schematic diagram of a semiconductor structure according to the fifth embodiment of the present disclosure.

[0055] Figure 12 To make Figure 11 The diagram shows the intermediate structure corresponding to the etching step in the semiconductor structure process.

[0056] Figures 13A to 13F Exemplary examples illustrate three forms of the first protrusion of the first extensional structure and the groove of the second extensional structure according to embodiments of the present disclosure.

[0057] Figure 14A schematic diagram of the semiconductor structure provided in the sixth embodiment.

[0058] Figure 15 for Figure 14 A schematic diagram of the intermediate structure of the third epitaxial structure provided in the process of the semiconductor structure shown.

[0059] The following is a list of all reference numerals appearing in this disclosure:

[0060] First epitaxial structure 1; First semiconductor layer 101; Second semiconductor layer 102; First light-emitting layer 103; Second epitaxial structure 2; Third semiconductor layer 201; Fourth semiconductor layer 202; Second light-emitting layer 203; Driving substrate 3; First electrode 401; Second electrode 402; Third electrode 403; Fourth electrode 404; Fifth electrode 405; Sixth electrode 406; Seventh electrode 407; Eighth electrode 408; Ninth electrode 409; Tenth electrode 410; Eleventh electrode 411; Twelfth electrode 412; Insulating layer 5; Protective layer 6; Transparent conductive layer 7; First substrate 9; Second substrate 10; First channel 11; Second channel 12; Mirror layer 13; First protrusion 14; Groove 15; Passivation layer 16; Third channel 17; Third epitaxial structure 18; Fifth semiconductor layer 181; Sixth semiconductor layer 182; Third light-emitting layer 182; Third substrate 19. Detailed Implementation

[0061] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.

[0062] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. Unless otherwise defined, the technical or scientific terms used in this disclosure should be understood in their ordinary sense by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “a” or “one,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. “A plurality” or “several” indicates two or more. Unless otherwise stated, the terms “front,” “rear,” “lower,” and / or “upper,” and similar terms are for ease of description only and are not limited to a location or spatial orientation. The terms “comprising,” “including,” and similar terms mean that the elements or objects preceding “comprising,” encompass the elements or objects listed following “comprising,” and their equivalents, and do not exclude other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this disclosure and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0063] First Embodiment

[0064] like Figures 1 to 4 As shown, a semiconductor structure and its fabrication method are provided according to the first embodiment of this disclosure.

[0065] like Figure 3As shown, the semiconductor structure includes: a driving substrate 3; a first epitaxial structure 1 connected to the driving substrate 3; the first epitaxial structure 1 including a first semiconductor layer 101, a second semiconductor layer 102, and a first light-emitting layer 103 located between the first semiconductor layer 101 and the second semiconductor layer 102; the first semiconductor layer 101 and the second semiconductor layer 102 having opposite conductivity types; and the first semiconductor layer 101 located on the side of the first epitaxial structure 1 closer to the driving substrate 3; and a second epitaxial structure 2 connected to the first epitaxial structure 1; the second epitaxial structure 2 including a third semiconductor layer 201, a fourth semiconductor layer 202, and a first light-emitting layer 103 located between the third semiconductor layer 201 and the second semiconductor layer 102. The second light-emitting layer 203 is located between the first epitaxial structure 101 and the fourth semiconductor layer 202. The third semiconductor layer 201 and the fourth semiconductor layer 202 have opposite conductivity types, while the second semiconductor layer 102 and the fourth semiconductor layer 202 have the same conductivity type. The fourth semiconductor layer 202 is located on the side of the second epitaxial structure 2 closest to the first epitaxial structure 1, so that the fourth semiconductor layer 202 is connected to the second semiconductor layer 102. The driving substrate 3 is connected to the first semiconductor layer 101, the second semiconductor layer 102, the third semiconductor layer 201, and the fourth semiconductor layer 202 respectively via metal electrodes to independently control the first epitaxial structure 1 and the second epitaxial structure 2. The driving substrate 3 can refer to a driving circuit.

[0066] According to the first embodiment of this disclosure, on one hand, by connecting a first epitaxial structure 1 to a driving substrate 3 and a second epitaxial structure 2 to the first epitaxial structure 1, two light-emitting units (the first epitaxial structure 1 and the second epitaxial structure 2) with two main emission wavelengths are realized on the same driving substrate 3, thereby achieving a high color rendering index LED white backlight. Furthermore, the synchronous processing of the two light-emitting units simplifies the processing steps and saves manufacturing costs. On the other hand, by connecting the driving substrate 3 to the first semiconductor layer 101, the second semiconductor layer 102, the third semiconductor layer 201, and the fourth semiconductor layer 202 respectively, the first epitaxial structure 1 and the second epitaxial structure 2 (the two light-emitting units) can be independently controlled, enabling independent emission of the two light-emitting units and thus achieving full-color LED display.

[0067] The first epitaxial structure 1 and the second epitaxial structure 2 serve as two light-emitting units with two different emission wavelengths. By using these two different primary emission wavelengths, the color gamut of the LED backlight chip can be significantly improved. In this embodiment, the emission wavelength of the first epitaxial structure 1, which is closer to the driving substrate 3, is greater than that of the second epitaxial structure 2, allowing it to emit white light or display full color. For example, to achieve white backlighting for the LED, the first epitaxial structure 1 can be a green light unit, and the second epitaxial structure 2 can be a blue light unit. In specific applications, the appropriate unit can be selected as needed, and this embodiment is not limited to this specific example.

[0068] According to the first embodiment of this disclosure, both the first semiconductor layer 101 and the third semiconductor layer 201 can be N-type semiconductor layers, and both the second semiconductor layer 102 and the fourth semiconductor layer 202 can be P-type semiconductor layers; or, both the first semiconductor layer 101 and the third semiconductor layer 201 can be P-type semiconductor layers, and both the second semiconductor layer 102 and the fourth semiconductor layer 202 can be N-type semiconductor layers. The materials of the first semiconductor layer 101, the second semiconductor layer 102, the three semiconductor layers, and the fourth semiconductor layer 202 can be group III nitride materials.

[0069] For example, the first semiconductor layer 101 and the third semiconductor layer 201 are both N-type semiconductor layers, and the second semiconductor layer 102 and the fourth semiconductor layer 202 are both P-type semiconductor layers.

[0070] The materials of the first semiconductor layer 101 and the third semiconductor layer 201 can be, for example, N-type group III nitride materials. The N-type doping element can include at least one of Si, Ge, Sn, Se, or Te. The group III nitride material can include any one or a combination of GaN, AlGaN, InGaN, and AlInGaN.

[0071] The formation process of an N-type semiconductor layer may include: atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or combinations thereof.

[0072] The materials of the second semiconductor layer 102 and the fourth semiconductor layer 202 can be, for example, p-type group III nitride materials. The p-type doping element can include at least one of Mg, Zn, Ca, Sr or Ba. The group III nitride material can include any one or a combination of GaN, AlGaN, InGaN, and AlInGaN.

[0073] The formation process of the P-type semiconductor layer can be referenced from the formation process of the N-type semiconductor layer.

[0074] The first light-emitting layer 103 and the second light-emitting layer 203 may include at least one of a single quantum well structure, a multiple quantum well (MQW) structure, a quantum wire structure, and a quantum dot structure. The first light-emitting layer 103 and the second light-emitting layer 203 may include a well layer and a barrier layer formed of a group III nitride material. The group III nitride material may include any one or a combination of GaN, AlGaN, InGaN, and AlInGaN.

[0075] For example, the well layer may include Al x Ga 1-x N layers, where x is the percentage of Al mass relative to the sum of Al and Ga masses, 1 ≥ x ≥ 0; and / or the barrier layer may include Al y Ga 1-y N layers, where y is the percentage of Al mass relative to the sum of Al and Ga masses, 1 ≥ y ≥ 0. The bandgap of the well layer is smaller than that of the barrier layer.

[0076] In this embodiment, the first light-emitting layer 103 and the second light-emitting layer 203 may include an In component, and the In component in the first light-emitting layer 103 is greater than the In component in the second light-emitting layer 203. In specific applications, the specific selection can be made as needed, for example, the In component in the first light-emitting layer 103 may be less than or equal to the In component in the second light-emitting layer 203, and is not limited to this embodiment.

[0077] The formation process of the well layer and / or barrier layer can refer to the formation process of the N-type semiconductor layer.

[0078] The well layer and / or barrier layer may or may not be doped with Al. Not doping with Al can improve the crystal quality, but doping with Al can reduce the resistivity.

[0079] Alternating layers of wells and barriers can form a multi-quantum-well structure, further improving luminescence efficiency.

[0080] According to the first embodiment of this disclosure, as Figures 3 to 4 As shown, the first epitaxial structure 1 and the second epitaxial structure 2 are connected by direct bonding between the second semiconductor layer 102 and the fourth semiconductor layer 202.

[0081] According to the first embodiment of this disclosure, the driving substrate 3 is a conductive substrate connected to one of the second semiconductor layer 102 and the fourth semiconductor layer 202, the first semiconductor layer 101 and the third semiconductor layer 201 via metal electrodes.

[0082] The first semiconductor layer 101, the third semiconductor layer 201, and the second semiconductor layer 102 or the fourth semiconductor layer 202 are independently connected to the driving substrate 3 through their respective metal electrodes. Therefore, the two light-emitting units can be controlled independently, that is, the first epitaxial structure 1 and the second epitaxial structure 2 can be controlled independently, thereby realizing full-color display of the LED backlight chip.

[0083] For example, the semiconductor structure also includes a first channel 11 and a second channel 12; the first channel 11 extends from the surface of the first semiconductor layer 101 into the second semiconductor layer 102 or the fourth semiconductor layer 202, so that the driving substrate 3 is connected to the second semiconductor layer 102 or the fourth semiconductor layer 202 via the first electrode 401 in the first channel 11; the second channel 12 extends from the surface of the first semiconductor layer 101 into the third semiconductor layer 201, so that the driving substrate 3 is connected to the third semiconductor layer 201 via the second electrode 402 in the second channel 12; and the driving substrate 3 is directly connected to the first semiconductor layer 101 via the third electrode 403.

[0084] like Figure 3 As shown, in the first embodiment of this disclosure, the first channel 11 extends from the surface of the first semiconductor layer 101 to the second semiconductor layer 102. Since the fourth semiconductor layer 202 is directly bonded to the second semiconductor layer 102, the fourth semiconductor layer 202 can share the first electrode 401 with the second semiconductor layer to be connected to the driving substrate 3.

[0085] An insulating layer 5 is provided on the surface of the first semiconductor layer 101 and the inner sidewall surfaces of the first channel 11 and the second channel 12. The insulating layer 5 may include materials such as silicon dioxide and silicon nitride.

[0086] like Figure 1 As shown, according to the first embodiment of this disclosure, the method for fabricating the semiconductor layer includes:

[0087] S10: Provides the first extensional structure 1;

[0088] S20: Provide a second epitaxial structure 2, and bond the second epitaxial structure 2 to the first epitaxial structure 1;

[0089] S30: Etch the first epitaxial structure 1 and the second epitaxial structure 2 to selectively expose the first semiconductor layer 101, the second semiconductor layer 102, the third semiconductor layer 201 and the fourth semiconductor layer 202;

[0090] S40: Provide a driving substrate 3, bond the driving substrate 3 to the side of the first epitaxial structure 1 away from the second epitaxial structure 2, so that the driving substrate 3 is connected to the first semiconductor layer 101, the second semiconductor layer 102, the third semiconductor layer 201 and the fourth semiconductor layer 202 through metal electrodes, thereby independently controlling the first epitaxial structure 1 and the second epitaxial structure 2.

[0091] In step S10, providing the first epitaxial structure 1 includes: providing a first substrate 9, and sequentially forming a first semiconductor layer 101, a first light-emitting layer 103, and a second semiconductor layer 102 (e.g., ...) on the first substrate 9. Figure 2A (As shown).

[0092] In step S20, providing the second epitaxial structure 2 includes: providing a second substrate 10, and sequentially forming a third semiconductor layer 201, a second light-emitting layer 203, and a fourth semiconductor layer 202 (e.g., ...) on the second substrate 10. Figure 2B (As shown).

[0093] After connecting the second epitaxial structure 2 to the first epitaxial structure 1, the method further includes removing the first substrate 9.

[0094] The materials of the first substrate 9 and the second substrate 10 can be one or more of sapphire, silicon carbide, silicon, diamond or GaN.

[0095] According to the first embodiment of this disclosure, in step S30, etching the first epitaxial structure 1 and the second epitaxial structure 2 to expose the first semiconductor layer 101, the second semiconductor layer 102, the third semiconductor layer 201 and the fourth semiconductor layer 202 specifically includes: after removing the first substrate 9, performing photolithography on the first epitaxial structure 1 to form a first channel 11 and a second channel 12, so that the first channel 11 extends to the second semiconductor layer 102 and the second channel 12 extends to the third semiconductor layer 201.

[0096] After the first channel 11 and the second channel 12 are formed, an insulating layer 5 can be deposited on the surface of the first semiconductor layer 101 and on the bottom and inner sidewall surfaces of the first channel 11 and the second channel 12 for isolation and protection. Before fabricating the first electrode 401, the second electrode 402 and the third electrode 403, the insulating layer 5 located at the bottom of the first channel 11 and the second channel 12 and part of the insulating layer 5 located on the surface of the first semiconductor layer 101 are removed to reserve the fabrication area of ​​the first electrode 401, the second electrode 402 and the third electrode 403.

[0097] Next, a protective layer 6 can be deposited on the upper surface of the insulating layer 5 for further deposition of the first electrode 401, the second electrode 402, and the third electrode 403, such that the second semiconductor layer 102 and the fourth semiconductor layer 202 are connected to the driving substrate 3 through the first electrode 401, the third semiconductor layer 201 is connected to the driving substrate 3 through the second electrode 402, and the first semiconductor layer 101 is connected to the driving substrate 3 through the third electrode 403. The material of the protective layer 6 includes materials such as SiO2 or SiN.

[0098] After step S40, the method further includes removing the second substrate 10.

[0099] Second Embodiment

[0100] like Figures 5 to 7 As shown, the second embodiment of this disclosure provides a semiconductor structure that is substantially the same as the semiconductor structure of the first embodiment. The difference lies in that, in the second embodiment, the first epitaxial structure 1 and the second epitaxial structure 2 are connected by a transparent conductive layer 7 disposed between the second semiconductor layer 102 and the fourth semiconductor layer 202; the first channel 11 extends from the surface of the first semiconductor layer 101 into the transparent conductive layer 7. In this embodiment, the first channel 11 extends from the surface of the first semiconductor layer 101 into the transparent conductive layer 7, and the first electrode 401 is connected to the second semiconductor layer 102 and the fourth semiconductor layer 202 through the transparent conductive layer 7 to improve conductivity and reduce resistance.

[0101] The transparent conductive layer 7 is made of indium tin oxide.

[0102] The method for fabricating the semiconductor structure in the second embodiment is largely the same as that in the first embodiment. The only difference is that in the second embodiment, the fabrication method further includes forming transparent conductive layers 7 on the second semiconductor layer 102 and the fourth semiconductor layer 202, respectively, so that the first epitaxial structure 1 and the second epitaxial structure 2 are connected by bonding the two transparent conductive layers 7.

[0103] Third Embodiment

[0104] like Figure 8 As shown, the third embodiment of this disclosure provides a semiconductor structure that is substantially the same as the semiconductor structure of the second embodiment. The difference is that in the third embodiment, a reflective layer 13 is disposed between the first semiconductor layer 101 and the insulating layer 5.

[0105] The method for fabricating the semiconductor structure in the third embodiment is largely the same as that in the second embodiment. The only difference is that in the third embodiment, the fabrication method further includes: before forming the insulating layer 5, forming a reflective layer 13 on the surface of the first semiconductor layer 101. The reflective layer 13 includes an oxide multilayer material structure or a group III nitride multilayer material structure. The oxide multilayer material structure includes SiO2 / TiO2 and other multilayer materials, and the group III nitride multilayer material structure includes AlGaN / GaN and other multilayer materials. Optionally, the group III nitride multilayer material structure... The group III nitride stacked material can be a porous structure to increase the reflectivity of the group III nitride stacked material structure; or, when providing the first epitaxial structure 1, a reflector layer 13, a first semiconductor layer 101, a first light-emitting layer 103 and a second semiconductor layer 102 are sequentially formed on the first substrate 9. Optionally, the reflector layer 13 includes a group III nitride stacked material structure, wherein the group III nitride stacked material structure includes stacked materials such as AlGaN / GaN. Optionally, the group III nitride stacked material can be a porous structure to increase the reflectivity of the group III nitride stacked material structure.

[0106] Fourth and Fifth Embodiments

[0107] like Figure 9 and Figures 10A to 10C As shown, the fourth embodiment of this disclosure provides a semiconductor structure. Figures 11 to 12 As shown, the fifth embodiment of this disclosure provides a semiconductor structure.

[0108] The semiconductor structures of the fourth and fifth embodiments are generally the same as those of the first embodiment, except that in the fourth and fifth embodiments, the first epitaxial structure 1 and the second epitaxial structure 2 are bonded together by complementary structures.

[0109] Specifically, according to the fourth and fifth embodiments of this disclosure, the first extensional structure 1 has a first patterned structure, the second extensional structure 2 has a second patterned structure corresponding to the first patterned structure, and the first extensional structure 1 and the second extensional structure 2 are connected by the interlocking of the first patterned structure and the second patterned structure.

[0110] For example, one of the first extensional structure 1 and the second extensional structure 2 is provided with one or more first protrusions 14, and the other of the first extensional structure 1 and the second extensional structure 2 is provided with one or more grooves 15 corresponding to one or more first protrusions 14. The first extensional structure 1 and the second extensional structure 2 are connected by the engagement of one or more first protrusions 14 with one or more grooves 15. Figures 13A to 13FExemplary examples show three forms of the first protrusion 14 of the first epitaxial structure 1 and the groove 15 of the second epitaxial structure 2 according to embodiments of the present disclosure. Optionally, the cross-sectional shape of the first protrusion 14 and the groove 15 can be a triangle, square, strip, polygon, circle or ellipse, etc., and the cross-section is parallel to the first substrate 9 or parallel to the second substrate 10.

[0111] In this embodiment, the depth of the groove 15 at least penetrates the second light-emitting layer 203. As an optional implementation, the depth of the groove 15 may penetrate the third semiconductor layer 201 or not penetrate the third semiconductor layer 201. Wherein, the depth of the groove 15 not penetrating the third semiconductor layer 201 includes the bottom of the groove 15 stopping at the surface of the third semiconductor layer 201 or the groove 15 partially penetrating the third semiconductor layer 201. With this configuration, the third semiconductor layer 201 is not completely etched, and the third semiconductor layer 201 of the second epitaxial structure 2 connects each of the second light-emitting layers 203 so that each of the second light-emitting layers 203 shares a common electrode, simplifying electrode fabrication. Figure 10A and Figure 10B This illustrates a scenario where the depth of the groove 15 does not penetrate the third semiconductor layer 201. Figure 10C This diagram shows a structure after the first epitaxial structure 1 and the second epitaxial structure 2 are bonded together, with the depth of the groove 15 penetrating through the third semiconductor layer 201.

[0112] The semiconductor structures of the fourth and fifth embodiments are largely the same, the only difference being the relative positional relationship between the second semiconductor layer 102 and the fourth semiconductor layer 202.

[0113] like Figure 9 As shown, in the fourth embodiment, after the first epitaxial structure 1 and the second epitaxial structure 2 are fitted together, the second semiconductor layer 102 and the fourth semiconductor layer 202 are not at the same horizontal position. The first semiconductor layer 101 is connected to the driving substrate 3 through the seventh electrode 407, the second semiconductor layer 102 is connected to the driving substrate 3 through the eighth electrode 408, the third semiconductor layer 201 is connected to the driving substrate 3 through the ninth electrode 409, and the fourth semiconductor layer 202 is connected to the driving substrate 3 through the tenth electrode 410. The first semiconductor layer 101, the second semiconductor layer 102, the third semiconductor layer 201 and the fourth semiconductor layer 202 are respectively connected to the driving substrate 3 through different electrodes to achieve independent control of the first light-emitting layer 103 and the second light-emitting layer 203.

[0114] like Figure 11 and Figure 12As shown, in the fifth embodiment, the second semiconductor layer 102 and the fourth semiconductor layer 202 are at the same horizontal position. The adjacent second semiconductor layer 102 and fourth semiconductor layer 202 are simultaneously exposed through the third channel 17, so that the adjacent second semiconductor layer 102 and fourth semiconductor layer 202 are jointly connected to the driving substrate 3 through the fourth electrode 404. The first semiconductor layer 101 and the third semiconductor layer 201 are connected to the driving substrate 3 through the fifth electrode 405 and the sixth electrode 406, respectively. The first epitaxial structure 1 is located on the side of the second light-emitting layer 203 closest to the driving substrate 3, and the emission wavelength of the first light-emitting layer 103 is greater than that of the second light-emitting layer 203. This avoids the second light-emitting layer 203 absorbing the light emitted by the first light-emitting layer 103, thereby preventing crosstalk between the second light-emitting layer 203 and the light emitted by the first light-emitting layer 103. This ensures the uniformity of the wavelength of the light emitted by the first epitaxial structure 1 after passing through the first light-emitting layer 103, facilitating the subsequent fabrication of the full-color LED structure.

[0115] In the fourth and fifth embodiments, a passivation layer 16 is disposed between the first epitaxial structure 1 and the second epitaxial structure 2. The passivation layer 16 can be made of SiO2 or SiN, etc.

[0116] In the fourth and fifth embodiments, a protective layer 6 is provided between the overall structure formed by the connection of the first epitaxial structure 1 and the second epitaxial structure 2 and the driving substrate 3.

[0117] The methods for fabricating the semiconductor structure in the fourth and fifth embodiments are largely the same as those in the first embodiment, except that in the fourth and fifth embodiments, before connecting the second epitaxial structure 2 to the first epitaxial structure 1, the following steps are further included:

[0118] The first epitaxial structure 1 and the second epitaxial structure 2 are graphically represented such that the first epitaxial structure 1 has a first graphical structure and the second epitaxial structure 2 has a second graphical structure corresponding to the first graphical structure, thereby bonding the first epitaxial structure 1 and the second epitaxial structure 2 together through the first graphical structure and the second graphical structure in a chimera manner.

[0119] In this embodiment, before the first epitaxial structure 1 and the second epitaxial structure 2 are bonded, a passivation layer 16 is prepared on the surface of both the first epitaxial structure 1 and the second epitaxial structure 2. The material of the passivation layer 16 is a dielectric material such as SiO2 or SiN.

[0120] Sixth Embodiment

[0121] The semiconductor structure provided in the sixth embodiment is substantially the same as that in the fourth and fifth embodiments, except that, for example... Figure 14 As shown, Figure 14This is a schematic diagram of the semiconductor structure provided in the sixth embodiment. The semiconductor structure provided in the sixth embodiment further includes a third epitaxial structure 18. The third epitaxial structure 18 has a third patterned structure corresponding to the second epitaxial structure 2. The third epitaxial structure 18 and the second epitaxial structure 2 are connected by the interlocking of the second patterned structure and the third patterned structure. The third epitaxial structure 18 is connected to the driving substrate 3. The third epitaxial structure 18 includes a fifth semiconductor layer 181, a third light-emitting layer 183, and a sixth semiconductor layer 182 stacked together. The fifth semiconductor layer 181 and the sixth semiconductor layer 182 have opposite conductivity types, and the fifth semiconductor layer 181 and the first semiconductor layer 101 have the same conductivity type. Specifically, the second epitaxial structure 2 has a second patterned structure, and the first epitaxial structure 1 and the third epitaxial structure 18 have a first patterned structure and a third patterned structure corresponding to the second patterned structure. The first epitaxial structure 1 and the third epitaxial structure 18 are respectively interlocked with the second patterned structure through the first patterned structure and the third patterned structure. In this embodiment, the second epitaxial structure 2 is provided with a plurality of grooves 15, the first epitaxial structure 1 is provided with one or more first protrusions 14, and the third epitaxial structure 18 is provided with one or more second protrusions 184. The number of grooves 15 is equal to the sum of the number of first protrusions 14 and second protrusions 184, and the first protrusions 14 and second protrusions 184 are staggered within the grooves 15. Optionally, in this embodiment, the first epitaxial structure 1, the second epitaxial structure 2, and the third epitaxial structure 18 emit different wavelengths. Optionally, the emission colors of the first epitaxial structure 1, the second epitaxial structure 2, and the third epitaxial structure 18 are red, green, and blue, respectively, to achieve full-color display of the semiconductor structure.

[0122] In the third epitaxial structure 18, the fifth semiconductor layer 181 is located on the side of the third epitaxial structure 18 closer to the driving substrate 3. The fifth semiconductor layer 181 is connected to the driving substrate 3 through the eleventh electrode 411, and the sixth semiconductor layer 182 is connected to the driving substrate 3 through the twelfth electrode 412. The eleventh electrode 411 and the twelfth electrode 412 can be prepared simultaneously with the eighth electrode 408 and the ninth electrode 409 to simplify the preparation process.

[0123] The method for fabricating the semiconductor structure in the sixth embodiment is largely the same as that in the fourth and fifth embodiments, except that after bonding the first epitaxial structure 1 and the second epitaxial structure 2, a third epitaxial structure 18 is provided and patterned, so that the third epitaxial structure 18 has a third patterned structure corresponding to the second patterned structure, and the third epitaxial structure 18 is bonded to the second epitaxial structure 2 through the interlocking bonding of the third patterned structure and the second patterned structure.

[0124] Among them, such as Figure 15 As shown, Figure 15 for Figure 14 The schematic diagram of the intermediate structure of the third epitaxial structure provided in the semiconductor structure process shown illustrates that providing the third epitaxial structure 18 includes providing a third substrate 19, on which a fifth semiconductor layer 181, a third light-emitting layer 183, and a sixth semiconductor layer 182 are sequentially formed. After patterning the third epitaxial structure 18 and before bonding it to the second epitaxial structure 2, a passivation layer 16 is also prepared on the third epitaxial structure 18. The third epitaxial structure 18 is then bonded to the second epitaxial structure 2 through a third patterned structure and a second patterned structure, and the third substrate 19 is removed.

[0125] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Driving substrate (3). A first epitaxial structure (1) is connected to the driving substrate (3). The first epitaxial structure (1) includes a first semiconductor layer (101), a second semiconductor layer (102), and a first light-emitting layer (103) located between the first semiconductor layer (101) and the second semiconductor layer (102). The first semiconductor layer (101) and the second semiconductor layer (102) have opposite conductivity types. The first semiconductor layer (101) is located on the side of the first epitaxial structure (1) closer to the driving substrate (3). as well as The second epitaxial structure (2) is connected to the first epitaxial structure (1). The second epitaxial structure (2) includes a third semiconductor layer (201), a fourth semiconductor layer (202), and a second light-emitting layer (203) located between the third semiconductor layer (201) and the fourth semiconductor layer (202). The third semiconductor layer (201) and the fourth semiconductor layer (202) have opposite conductivity types, and the second semiconductor layer (102) and the fourth semiconductor layer (202) have the same conductivity type. The fourth semiconductor layer (202) is located on the side of the second epitaxial structure (2) closer to the driving substrate (3) so that the fourth semiconductor layer (202) is connected to the second semiconductor layer (102). The driving substrate (3) is connected to the first semiconductor layer (101), the second semiconductor layer (102), the third semiconductor layer (201) and the fourth semiconductor layer (202) respectively through metal electrodes, so as to independently control the first epitaxial structure (1) and the second epitaxial structure (2). The first extensional structure (1) has a first graphical structure, and the second extensional structure (2) has a second graphical structure corresponding to the first graphical structure. The first extensional structure (1) and the second extensional structure (2) are connected by the interlocking of the first graphical structure and the second graphical structure.

2. The semiconductor structure according to claim 1, characterized in that, The second semiconductor layer (102) and the fourth semiconductor layer (202) are at the same horizontal position. The second semiconductor layer (102) and the fourth semiconductor layer (202) are exposed simultaneously through the third channel (17) so that the adjacent second semiconductor layer (102) and the fourth semiconductor layer (202) are connected to the driving substrate (3) through the fourth electrode (404). The first semiconductor layer (101) and the third semiconductor layer (201) are connected to the driving substrate (3) through the fifth electrode (405) and the sixth electrode (406), respectively.

3. The semiconductor structure according to claim 1, characterized in that, The second semiconductor layer (102) and the fourth semiconductor layer (202) are not at the same horizontal position. The first semiconductor layer (101) is connected to the driving substrate (3) through the seventh electrode (407), the second semiconductor layer (102) is connected to the driving substrate (3) through the eighth electrode (408), the third semiconductor layer (201) is connected to the driving substrate (3) through the ninth electrode (409), and the fourth semiconductor layer (202) is connected to the driving substrate (3) through the tenth electrode (410).

4. The semiconductor structure according to claim 1, characterized in that, A passivation layer (16) is provided between the first epitaxial structure (1) and the second epitaxial structure (2).

5. The semiconductor structure according to claim 1, characterized in that, A protective layer (6) is provided between the overall structure formed by the connection of the first epitaxial structure (1) and the second epitaxial structure (2) and the driving substrate (3).

6. The semiconductor structure according to claim 1, characterized in that, The materials of the first semiconductor layer (101), the second semiconductor layer (102), the third semiconductor layer (201), and the fourth semiconductor layer (202) are group III nitride materials.

7. The semiconductor structure according to claim 1, characterized in that, Also includes: The third extensional structure (18) has a third graphical structure corresponding to the second graphical structure, and the third extensional structure (18) and the second extensional structure (2) are connected by the interlocking of the second graphical structure and the third graphical structure.

8. The semiconductor structure according to claim 7, characterized in that, The third epitaxial structure (18) is connected to the driving substrate (3). The third epitaxial structure (18) includes a fifth semiconductor layer (181), a third light-emitting layer (183), and a sixth semiconductor layer (182) stacked together. The fifth semiconductor layer (181) is located on the side of the third epitaxial structure (18) closer to the driving substrate (3). The fifth semiconductor layer (181) and the sixth semiconductor layer (182) have opposite conductivity types. The first light-emitting layer (103), the second light-emitting layer (203), and the third light-emitting layer (183) all have different emission wavelengths.

9. A method for fabricating a semiconductor structure, characterized in that, include: A first epitaxial structure (1) is provided, wherein the first epitaxial structure (1) includes a first semiconductor layer (101), a second semiconductor layer (102) and a first light-emitting layer (103) located between the first semiconductor layer (101) and the second semiconductor layer (102), wherein the first semiconductor layer (101) and the second semiconductor layer (102) have opposite conductivity types; A second epitaxial structure (2) is provided, which is connected to the first epitaxial structure (1). The second epitaxial structure (2) includes a third semiconductor layer (201), a fourth semiconductor layer (202), and a second light-emitting layer (203) located between the third semiconductor layer (201) and the fourth semiconductor layer (202). The third semiconductor layer (201) and the fourth semiconductor layer (202) have opposite conductivity types, and the fourth semiconductor layer (202) has the same conductivity type as the second semiconductor layer (102). The fourth semiconductor layer (202) is located on the side of the second epitaxial structure (2) closer to the driving substrate (3) so that the fourth semiconductor layer (202) is connected to the second semiconductor layer (102). The first semiconductor layer (101), the second semiconductor layer (102), the third semiconductor layer (201) and the fourth semiconductor layer (202) are selectively exposed by etching. Provide a driving substrate (3), and bond the driving substrate (3) to the side of the first epitaxial structure (1) away from the second epitaxial structure (2); and The driving substrate (3) is selectively connected to the first semiconductor layer (101), the second semiconductor layer (102), the third semiconductor layer (201) and the fourth semiconductor layer (202) through metal electrodes, thereby independently controlling the first epitaxial structure (1) and the second epitaxial structure (2). Before connecting the second epitaxial structure (2) to the first epitaxial structure (1), the method further includes: The first extensional structure (1) and the second extensional structure (2) are graphically represented such that the first extensional structure (1) has a first graphical structure and the second extensional structure (2) has a second graphical structure corresponding to the first graphical structure. The first extensional structure (1) and the second extensional structure (2) are connected by the interlocking of the first graphical structure and the second graphical structure.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, Providing a first epitaxial structure (1) includes: providing a first substrate (9), and sequentially forming a first semiconductor layer (101) and a second semiconductor layer (102) on the first substrate (9); Providing a second epitaxial structure (2) includes: providing a second substrate (10), and sequentially forming the third semiconductor layer (201) and the fourth semiconductor layer (202) on the second substrate (10). After connecting the second epitaxial structure (2) to the first epitaxial structure (1), the method further includes removing the first substrate (9) and the second substrate (10).

11. The method for fabricating a semiconductor structure according to claim 9, characterized in that, After the first epitaxial structure (1) and the second epitaxial structure (2) are connected by the interlocking of the first patterned structure and the second patterned structure, the method further includes: Provide a third extensional structure (18); The third extensional structure (18) is graphically represented such that the third extensional structure (18) has a third graphical structure corresponding to the second graphical structure; The third epitaxial structure (18) is bonded to the second epitaxial structure (2) through the intercalation and bonding of the third patterned structure and the second patterned structure.

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