Devices for generating high frequency clocks

Abstract

The present invention relates to a device for generating a high frequency clock 303, which comprises a controller 311, a first FLL or PLL control loop 323, a fixed frequency reference clock oscillator 1101, an input signal 308, a divider ratio calculator 1110 and a measuring device 509. The first FLL or PLL control loop 323 has a first divider 520. The fixed frequency reference clock oscillator 1101 generates a reference clock 306. The measuring device 509 measures the reference signal occasionally present in the input signal 308 and determines the associated effective measurement value 517. The divider 520 divides the high frequency clock 303 into the frequency of the divided high frequency clock 521 by a frequency division ratio and divides it into the auxiliary clock 1112 by a second frequency division ratio. The divider ratio calculator 1110 determines the measurement value of the auxiliary clock 1112 and compares the effective measurement value 517 with the measurement value of the auxiliary clock 1112, and thereby determines a ratio value reflecting the ratio and / or difference between the measurement value 517 and the measurement value of the auxiliary clock 1112. The frequency divider ratio calculator 1110 changes the target frequency dividing ratio 1111 of the first frequency divider 520 according to the deviation.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 202310782797.4, whose application date is June 29, 2023 and invention name is “Device and method for generating high-frequency clock”. Technical Field

[0002] The present invention relates to a device and a method for generating a high frequency clock according to an input signal, which is preferably a LIN data signal on a LIN data bus. Background Art

[0003] The precise synchronization of the high-frequency clock of a high-frequency oscillator and of a continuous low-frequency reference clock in frequency, cycle duration or phase with a reference signal which is always present at sporadic time intervals has long been known, in particular in the analog transmission of signals (radio, television).

[0004] For example, in VHF transmissions a so-called pilot tone is always transmitted, which the receiver uses as a reference for mixing down the frequency difference signal for stereo transmission.

[0005] With the invention of analog color television, the technology was developed in which a reference signal which is not permanent but is present periodically is transmitted by means of so-called color burst signals, to which the receiver can be synchronized. Figure 1 A portion of a color burst signal and other signal curves before and after are shown. As examples, reference is made to WO 1999 055088 A1, WO 1993 010605 A1, US 4 115 811 A and DE 19 619 509 C1.

[0006] For this purpose, a phase-locked loop (PLL) is preferably used, which has a holding mode and a readjustment mode.

[0007] Here, Wikipedia defines PLL as follows: "A phase-locked loop (PLL) is a control loop with a controlled oscillator whose phase tracks the phase of an external signal. In a phase-locked loop, the dependence of the manipulated variable on the control deviation (phase shift) is periodic. As a result, the control can be "locked" to various relative phases that differ by integer multiples of 2π (360°). In the locked state, the frequency of the oscillator is the frequency of the reference signal." (Source: https: / / de.wikipedia.org / wiki / Phasenregelschleif e#:~:text=Eine%20Phasenregelschleife%20%28PLL%2C%20nach%20englisch%20phaselocked%20loop%29%20ist,von%2 0der%20Regelabweichung%20%E2%80%93%20der%20Phasenverschiebung%20%E2%80%93%20periodisch, Download: 06.06.2022).

[0008] The PLL control loop generally includes an oscillator that generates a clock signal having a clock frequency. The clock frequency depends on the value of the control input signal of the oscillator. If necessary, the clock divider converts the clock signal into a comparison clock having a lower comparison clock frequency by frequency division. The phase detector compares the time position of the clock edge of the comparison clock with the time position of the edge of the input clock signal of the PLL. Therefore, the phase detector compares the phase of the clock edge of the comparison clock with the phase of the clock edge of the input clock signal of the PLL, and generates a phase signal that preferably can have negative and positive values. Then, the PI controller or another suitable controller preferably forms the control input signal of the oscillator according to the phase signal. Preferably, in combination with the sign of the phase detector, the sign of the transfer function of the controller is selected so that the device establishes PLL phase synchronization.

[0009] For example, an input signal (e.g. a CVBS signal) may not permanently have a synchronization signal for the clock. For example, it is known that a CVBS signal for teletext data may have different clock run-ins between CVBS lines. Reference is made herein to the standard "Enhanced Teletext Specification", European Telecommunication Standard ETS 300 706, May 1997, EBU / CENELEC / ETSI JTC, DE / JTC-TTEXT-EACEM, in particular " Figure 4: Clock preamble, framing code and timing reference" and document DE 19 619 509 C1 and Infineon Technologies AG "Preliminary User Manual TVTEXT PRO SDA 55xx", version 1, July 21, 1999, Chapter 5, with particular emphasis on Chapter 5.2.2 "Data Separation". The number of periods of the clock preamble of the teletext signal may vary between CVBS lines and may deviate from the ideal standard. Therefore, it is useful for the PLL a) detect the start of the clock preamble, and b) then readjust the clock very quickly within a few cycles during the clock preamble, and c) determine the end of the clock preamble. The subsequent teletext data is RTZ (return to zero) data. That is, each data bit has at least one edge. Preferably, d) the data field control characteristics of the PLL's PI regulator are different from the clock preamble control characteristics, because the distance between the edges may be twice as large. In addition, the edge direction may change depending on the data. Preferably, the PLL determines or detects the end of the data field. Preferably, e) from then on, the PLL's PI regulator ignores the value of the phase signal until the next clock preamble starts, thereby subsequently freezing the frequency of the oscillator. Thereby, the speed of regulating the phase and frequency of the clock preamble of the next line is increased.

[0010] Here, the color burst signal for the color burst for setting the color angle is always transmitted periodically exactly after the line sync pulse. This transmission form has the following properties in conjunction with the field of color television application:

[0011] Due to the fixed, predetermined timing regime, the start and end of the color angle synchronization phase can be determined very easily and immediately by a simple external detector which switches the PLL used to generate the color signal between hold mode and re-regulation mode.

[0012] Initial synchronization of the PLL used to generate the color signal occurs during power-up and at each switch to a different transmitter. Here, for analog color angle signals, it is usually not important if information is lost during the synchronization process. Even if synchronization requires 300 color bursts, only one field is lost, which is not noticeable to a human.

[0013] Interferences of the color burst signal of the color burst for setting the color angle only cause minimal disruptions to the transmission, since the transient time of the PLL for generating the color signal is preferably significantly longer than the duration of the color burst signal. The PLL for generating the color signal therefore integrates between these temporary errors.

[0014] In the CVBS signal, the clock preamble of the teletext signal is also always transmitted periodically within a well-defined time interval after the end of the line synchronization pulse of the line signal of the CVBS signal.

[0015] This form of data transmission in the CVBS line has the following characteristics together with the application field of teletext transmission:

[0016] Due to the fixed, predefined timing regime, at least in the case of an ideal CVBS signal, the start and end of the synchronization phase can again be determined by an external detector which switches the teletext PLL (PLL: Phase Locked Loop) for teletext clock recovery between a hold mode, in which the teletext PLL control loop of the teletext PLL is frozen, and a readjustment mode, in which the teletext PLL control loop of the teletext PLL is readjusted in phase by readjusting the frequency of the teletext PLL oscillator.

[0017] • The initial synchronization of the teletext PLL occurs during power-up and at each switch to a different transmitter, and here preferably synchronizes with each new scan line.

[0018] • A disturbance of the clock preamble results in a complete data loss of the data transmitted in the scan line, since the transient time of the PLL is preferably significantly shorter than the duration of the teletext clock preamble. Therefore, the teletext PLL does not integrate between these temporary errors.

[0019] This also applies analogously to the transmission of digital messages in which such data losses are likewise unacceptable and in particular data transmissions and thus synchronizations are only carried out sporadically. Figure 2 A synchronization signal for data transmission on a LIN bus is shown. The requirement here is that the transient oscillation has completely completed after the first synchronization field, so that the subsequent data can be received without errors. Here, since the quality of the synchronization signal must be evaluated before the transmission can start, the evaluation of the synchronization signal and any frequency correction of the transmission reference frequency can only be carried out at the end of the synchronization signal but before the start of data transmission when there is no longer a synchronization signal. Therefore, the above-mentioned methods for synchronously generating a high-frequency clock for a reference signal that only appears occasionally for a short time and serves as a synchronization signal, and the related devices, are not suitable, because they actually require the synchronization signal as a reference signal to be parallel to the entire execution duration of the re-regulation of the high-frequency clock.

[0020] There are already some solutions that meet this requirement, such as US 6,097,754, US 2002 / 0101 884A1 and US 2005 / 0024 111A1, which operate with a fixed high-frequency reference clock and thus use a low-frequency clock regulated according to the reference clock to decode the input signal or clock the processor. However, the fixed high-frequency reference clock is not corrected here.

[0021] Some slave systems require a precise (<1%) high-frequency reference clock while also requiring low system cost. Here, the system cost prohibits the use of a corresponding oscillator with the desired inherent accuracy. However, this frequency accuracy is usually present in the master device and can therefore also be transmitted via the synchronization signal. Therefore, a solution is sought in a system that is able to provide a highly precise high-frequency reference clock using the synchronization signal and is able to reach the target accuracy after receiving at most two synchronization signals.

[0022] With the above solution, this would be possible if the high frequency clock is a high multiple (>100) of the processor frequency. This feature is sometimes difficult to implement in typical semiconductor processes if one wants to use the maximum speed of the processor, especially for small processors. Therefore, there is no solution where the high frequency reference clock can also be used as the processor clock and the accuracy requirements can be met by the high frequency reference clock itself.

[0023] To this end, EP 1 971 069 A1 determines a correction signal for re-regulating the high-frequency reference clock based on the count duration of the synchronization signal. This correction signal is then supplied to the high-frequency oscillator. The problem with this solution is that the transfer function from the correction signal to the frequency of the high-frequency oscillator is usually nonlinear and subject to strong scattering between the components. Therefore, the target accuracy can only be achieved after many synchronization signals. This does not meet the requirements. Summary of the invention

[0024] Purpose

[0025] The purpose of this article is to provide a structure and method by which a high-precision high-frequency clock of a high-frequency oscillator can be provided in a short time using an accurate external reference signal that may only appear occasionally within the input signal, wherein the high-frequency clock can preferably be used as the system clock of the device.

[0026] In this case, the reference signal in the input signal does not have to be permanently present, but should also be present only intermittently, if necessary only rarely. In special cases, this reference signal in the input signal can be, for example, a synchronization field of a LIN communication of a LIN master. In this case, infrequent communications are sufficient for synchronizing the high-precision high-frequency clock of the high-frequency oscillator with the reference signal in the input signal.

[0027] Solution to the task

[0028] The present invention relates to an apparatus 300 and a related method for generating a high frequency clock 303. The apparatus 300 comprises a controller 311, a first FLL or PLL control loop 323, a second FLL or PLL control loop 324 and an input signal 308, which occasionally comprises a reference signal as a synchronization signal.

[0029] The invention is particular in that, in the method of the invention, the presence of a reference signal in the input signal 308 is detected, then the parameters of the detected reference signal (e.g., frequency and / or period duration and / or phase) are determined as valid measured values ​​of these parameters of the reference signal of the input signal 308, and preferably they are temporarily stored in one or more first memories of the measuring device 509 or the like. In the method of the invention, the parameters stored in the one or more first memories of the measuring device 509 are subjected to a plausibility check before further use in order to minimize interference. In the sense of the invention, the measured values ​​of the parameters of the reference signal temporarily stored in the one or more first memories should be plausible if they are within a generally predetermined expected value interval of the corresponding relevant parameter. In the method of the invention, preferably, only such plausibility-checked measured values ​​of the detected reference signal are transferred from the respective first memories of the measuring device 509 associated with the respective measured values ​​of the respective parameters to the second memories of the measuring device 509 associated with the corresponding valid measured values ​​of the parameter, and are stored in the second memories. In the method according to the invention, a reference clock 306 is then generated from these stored, plausibility-checked and thus verified valid measured values. The values ​​of the parameters of the reference clock 306 generated in this way then correspond accordingly to the valid measured values ​​517 of the parameters of one or more valid and usually no longer present reference signals in the input signal 308, according to a relationship that is preferably predefined or set by the controller 311 of the device 300 according to the invention. Since the valid values ​​of the detected parameters are preferably temporarily stored in the second memory of the measuring device 509, the reference clock 306 can also be generated when one or more reference signals are no longer present in the input signal 308. As a result, it is possible to process reference signals that occur very rarely. The high-frequency clock 303 is then synthesized from the reference clock 306, and the method is now complete.

[0030] The detection of the reference signal can be performed by time control related to a start signal such as a synchronization pulse, a start bit, etc., which time control stipulates that the reference signal is detected after a predetermined or set time period has passed after the start signal is received. The detection of the reference signal can also be performed by a matched filter (optimal filter), or for example, by continuous wavelet analysis of the input signal with a wavelet of a predetermined prototype reference signal (e.g., a clock preamble). They determine that a predetermined signal curve can be observed on the input signal 308 and interpret the signal curve as a reference signal.

[0031] If a start signal is used which precedes the reference signal in time by, for example, a predefined time interval, the device according to the invention can also identify the start signal, for example by a continuous wavelet analysis of the input signal by means of a suitable matched filter (optimal filter) or, for example, a wavelet with a predetermined prototype reference signal (for example, a synchronization pulse or a start code in the form of a predetermined bit sequence or pulse sequence). They determine that a predetermined signal curve can be observed on the input signal 308 and, if necessary, interpret this signal curve as a start signal.

[0032] The device 300 of the present invention corresponds to the method: the second FLL or PLL control loop 324 of the device 300 of the present invention converts the sporadic reference signal into a continuous reference clock 306 having at least the same frequency, cycle duration and phase. In many preferred applications, the frequency of the continuous reference clock 306 can also be a multiple of the frequency of the reference signal in the input signal 308. In such preferred applications, the cycle duration of the continuous reference clock 306 can also be only a fraction of the cycle duration of the reference signal in the input signal 308. The reference clock 306 is the input signal of the first FLL or PLL control loop 323, which boosts the low-frequency but continuous reference clock 306 to a high-frequency clock 303 with an even significantly higher frequency. As long as the second FLL or PLL control loop 324 is re-regulated by the deviation signal 518 of the target value calculator 510, the first FLL or PLL control loop 323 is preferably frozen. The second FLL or PLL control loop 324 is only enabled when the reference clock 306 is re-regulated by the sporadic reference signal in the input signal 308. Otherwise, the second FLL or PLL regulation loop 324 is preferably frozen and thus provides a constant reference clock 306 .

[0033] The device 300 of the present invention may operate the first FLL or PLL control loop 323 as a PLL (Phase Locked Loop) or a FLL (Frequency Locked Loop).

[0034] The device 300 of the present invention may operate the second FLL or PLL control loop 324 as a PLL (Phase Locked Loop) or a FLL (Frequency Locked Loop).

[0035] A phase-locked loop, commonly referred to as a PLL, is a regulation loop with a controlled oscillator whose phase tracks the phase of an external signal.

[0036] A frequency locked loop, often called an FLL, is a control loop with a controlled oscillator whose frequency tracks the frequency of an external signal. Since frequency is the time derivative of phase, the two control loops can usually be converted to each other.

[0037] The input signal at least intermittently or occasionally comprises a low-frequency reference signal which, as a synchronization signal, is intended to synchronize the high-frequency signal of the high-frequency oscillator in terms of phase and / or frequency and / or period duration.

[0038] According to the basic idea, the synchronization is performed in two phases.

[0039] In a first synchronization phase, the high-frequency clock of the high-frequency oscillator of the first FLL or PLL control loop is synchronized to the permanently available low-frequency reference clock of the reference oscillator. In a second synchronization phase, the low-frequency reference clock of the reference oscillator of the second FLL or PLL control loop is synchronized to a reference signal that is only available occasionally and is a temporary part of the input signal as a synchronization signal.

[0040] The second FLL or PLL control loop 324 is special in that the second FLL or PLL control loop 324 measures the occasionally present reference signal of the input signal 308 in the first phase via the high-frequency clock 303. Therefore, as long as the high-frequency clock 303 remains constant, the device 303 according to the invention can perform the following operations after the second FLL or PLL control loop 324 or its device components have measured and evaluated the reference signal in the input signal 308, in particular even when the reference signal is no longer present in the input signal 308:

[0041] 1. Using the frozen high-frequency clock 303 of the first FLL or PLL control loop 323 and by using the measured parameters of the reference signal of the input signal 308 that has disappeared, the second FLL or PLL control loop 324 can reconstruct the reference signal as the reference clock 306 .

[0042] 2. The second FLL or PLL control loop 324 can determine the deviation of the parameters of the reconstructed reference clock 306 relative to the corresponding detected parameters of the reference signal, and re-adjust the various parameters of the reference clock 306, such as re-adjusting the frequency of the reference clock 306 relative to the detected frequency of the reference signal.

[0043] Ultimately, this leads to 3 possible solutions:

[0044] 1. After the second FLL or PLL control loop 324 evaluates the received reference signal of the input signal 308, the second FLL or PLL control loop 324 can reconstruct the sporadic reference signal of the input signal 308 as long as no reference signal is present in the input signal 308 and re-regulate the low-frequency reference clock 306 according to the determined parameters of one or more received valid reference signals of the input signal 308, wherein for the reconstruction, the second FLL or PLL control loop 324 preferably uses the high-frequency clock 303 of the first FLL or PLL control loop 323 that was frozen when re-regulating the second FLL or PLL control loop 324. Then, the second FLL or PLL control loop 324 regulates itself to the detected parameters of one or more valid reference signals of the input signal 308 using the reference clock 306.

[0045] 2. After determining the deviation in frequency, cycle duration or phase between the reference clock 306 and one or more valid reference signals in the input signal 308, the second FLL or PLL control loop 324 can generate a reconstructed reference signal 806, for example, by dividing the high frequency clock 303 by the frequency division ratio in the reconstruction oscillator 810. Then, even if the reference signal only occasionally appears in the input signal 308, the second FLL or PLL control loop 324 can adjust itself to the reconstructed reference signal 806. Preferably, the controller 311 freezes the first FLL or PLL control loop 323 during the adjustment of the second FLL or PLL control loop 324, so that the parameters of the high frequency clock 303, such as the frequency, cycle duration and phase, remain unchanged during the freezing period. After adjusting the second FLL or PLL control loop 324, the controller 311 preferably freezes the second FLL or PLL control loop 324, so that the parameters of the reference clock 306, such as the frequency, cycle duration and phase, remain unchanged during the freezing period. At the same time, the controller 311 preferably unfreezes the first FLL or PLL control loop 323 so that the first FLL or PLL control loop 323 can now re-control the high-frequency clock 303 so that the frequency or cycle duration or phase of the high-frequency clock 303 is in desired proportion in magnitude to the frequency or cycle duration or phase of the reference clock 306 and therefore to the frequency or cycle duration or phase of one or more valid reference signals in the input signal 308.

[0046] 3. The first FLL or PLL control loop 323 generating the high frequency clock 303 may include a clock divider 520, which divides the high frequency clock 303 into a divided high frequency clock 521 according to the division ratio of the clock divider 520. The controller 311 or another applicable device of the device 300 of the present invention may determine the deviation between the frequency or cycle duration or phase of one or more valid reference signals in the input signal 308 and the corresponding parameters in the frequency or cycle duration or phase of the auxiliary clock 1112, for example, by means of a division ratio calculator 1110. The auxiliary clock 1112 may be the same as the divided high frequency clock 521. The auxiliary clock 1112 is usually at a predetermined division ratio with the high frequency clock 303. Preferably, the first divider 520 also generates the auxiliary clock 1112 according to the high frequency clock 303. According to the determined deviation, the division ratio calculator 1110 preferably generates a new value of the future division ratio 1111, and the first divider 520 uses the new value to divide the high frequency clock 303 into the divided high frequency clock 521 in the future. In this case, the first FLL or PLL control loop 323 then usually controls the frequency or the cycle duration or the phase of the high-frequency clock 303 in this way. Since the clock divider 520 represents a purely mathematical relationship and does not have any manufacturing tolerances with respect to other setting options of the oscillator, corrections can be made immediately here without freezing the first FLL or PLL control loop 323.

[0047] In order to keep the reference clock as undisturbed as possible during the absence of the synchronization signal, the second FLL or PLL control loop preferably freezes the controller of the device of the invention that performs the method of the invention during the period when the input signal does not include the synchronization signal as the reference signal of the reference oscillator. Therefore, when the input signal does not include the synchronization signal as the reference signal of the reference oscillator, the reference oscillator of the second FLL or PLL control loop operates as a non-regulated reference oscillator with a constant frequency or cycle duration or phase. The first FLL or PLL control loop regulates the frequency and / or cycle duration and / or phase of the high-frequency clock of the high-frequency oscillator to the reference clock of the reference oscillator as the pilot signal of the first FLL or PLL controller.

[0048] If the reference signal is now present in the input signal in the form of a synchronization signal, then in variant A of the invention, when executing the method of the invention, the controller of the device of the invention freezes the first FLL or PLL control loop and then operates the high-frequency oscillator as a non-regulated oscillator. The high-frequency oscillator then continues to provide a high-frequency clock with a constant frequency, cycle duration and phase, which does not differ from the frequency, cycle duration and phase that the high-frequency clock of the high-frequency oscillator had before freezing.

[0049] The controller of the device according to the invention can thereby determine or ascertain the presence of a reference signal in the form of a synchronization signal in the input signal in various ways.

[0050] Firstly, the application using the device of the invention can have a predeterminable time scheme in which the reference signal always appears in the input signal at a predetermined time. Then, the controller of the device of the invention can determine by means of a timer that the reference signal should now appear in the input signal at the corresponding point in time and start the synchronization process if it is determined that the reference signal is detected.

[0051] Secondly, the controller can observe the input signal by suitable means and determine the foreshadowing of the reference signal by a suitable start signal in the input signal. Here, the application using the device of the present invention can also have a predeterminable time scheme related to the reference signal in time, in which the reference signal always appears in the input signal at a predetermined time with a known time interval starting from the start signal after the start signal appears in the input signal.

[0052] Thirdly, the controller may observe the input signal by suitable means and determine the start of the reference signal by a suitable start of the reference signal in the input signal. Here, applications using the apparatus of the present invention may also have a predeterminable time scheme temporally related to the reference signal, in which after the start of the reference signal appears in the input signal, the remainder of the reference signal is still present in the input signal for a sufficient time to be used for synchronization at a predetermined time with a known time interval from the start of the reference signal.

[0053] Now, the device of the present invention that performs the method of the present invention uses a high-frequency clock with a constant frequency to measure a reference signal present in the input signal, in particular to measure the frequency and / or cycle duration and / or phase of the reference signal. Here, if necessary, the device of the present invention preferably generates a suitable low-frequency auxiliary clock based on the high-frequency clock for measuring the reference signal.

[0054] Preferably, the controller of the device according to the invention or another auxiliary device of the device according to the invention evaluates the reference signal measurement value as the measurement result. For example, if the detected frequency and / or cycle duration and / or phase is outside the corresponding expected value interval, it is meaningless to use this reference signal for synchronization. The controller of the device according to the invention then interrupts the synchronization process and unfreezes the first FLL or PLL control loop with the high-frequency oscillator again.

[0055] However, if the reference signal in the input signal is valid, the controller of the device of the invention executing the method of the invention then unfreezes the second FLL or PLL control loop which is in a normal operating state. Thus, the high frequency oscillator of the first FLL or PLL control loop then provides a constant high frequency clock, and the low frequency reference oscillator provides a regulated low frequency reference clock.

[0056] Using a high-frequency clock, the device of the present invention determines the value of the reference clock of the reference oscillator corresponding to the detected value of the reference signal, and compares these values. To this end, if necessary, the device of the present invention preferably generates a suitable low-frequency auxiliary clock for the comparison based on the high-frequency clock. Preferably, the device of the present invention stores the measured value of the reference signal so that the second FLL or PLL control loop can have a control constant that is longer than the duration of occurrence of the reference signal used as the synchronization signal in the input signal. Subsequent comparisons may involve comparisons of the frequency and / or cycle duration and / or phase of the reference clock with the reference signal of the input signal. Based on the comparison result, the second FLL or PLL control loop re-regulates the frequency and / or cycle duration and / or phase of the reference oscillator until the reference oscillator provides a reference clock that corresponds to the corresponding previous measurement of the frequency or cycle duration or phase of the device of the present invention in the reference signal in terms of frequency and / or cycle duration and / or phase.

[0057] Once the controller of the device of the present invention determines that the deviation of the frequency and / or cycle duration and / or phase of the reference clock from the corresponding previous measurement of the frequency or cycle duration or phase determined in the reference signal by the device of the present invention is numerically less than a predetermined maximum deviation value, the controller determines that the regulation enters a steady state. Alternatively, after the controller determines that the reference signal is a valid reference signal that may be suitable for a synchronized reference oscillator, the controller may also re-regulate through the second FLL or PLL regulation loop within the following specific time, during which the controller may determine that the second FLL or PLL regulation loop is very likely to enter a steady state after this period of time. In the sense of this article, this time-controlled termination method is functionally equivalent to a measurement value-controlled termination method under the control performed by the second FLL or PLL regulation loop.

[0058] As soon as the termination condition is reached in a time-controlled manner / measurement-value-controlled manner, the controller of the device according to the invention terminates the control of the reference oscillator and freezes the second FLL or PLL control loop, so that the reference oscillator now again provides a constant and non-regulated reference clock, at least until the next occurrence of the reference signal as a synchronization signal in the input signal. The controller then re-enables the control of the high-frequency oscillator by the first FLL or PLL control loop, so that the high-frequency oscillator then again provides a high-frequency clock, the frequency and / or the period duration and / or the phase of which are again set by the first FLL or PLL control loop in accordance with the reference clock.

[0059] In a variant, the controller freezes the first FLL or PLL control loop during the measurement of the reference signal in the input signal, so that the high frequency clock used as a measuring means is constant during the measurement time of the reference signal and does not change due to the control.

[0060] A device for generating a high frequency clock 303 is described herein, which includes a controller 311, a first FLL or PLL control loop 323, a second FLL or PLL control loop 324, and an input signal 308. As a part of the input signal 308, a reference signal used as a synchronization signal of the high frequency clock 303 appears intermittently and / or occasionally. When the second FLL or PLL control loop 324 is enabled, the second FLL or PLL control loop 324 generates a reference clock 306 according to the reference signal. Here, the reference signal is used as a target signal of the second FLL or PLL control loop 324. When the second FLL or PLL control loop 324 is deactivated, the second FLL or PLL control loop 324 generates the reference clock 306 in a manner that is independent of the reference signal of the input signal 308, wherein, in this case, the second FLL or PLL control loop 324 continues to generate the reference clock 306, and the frequency, cycle duration and phase of the reference clock 306 at this time are the same as the frequency, cycle duration and phase of the reference clock 306 generated by the second FLL or PLL control loop 324 in the most recent period when the second FLL or PLL control loop 324 was most recently enabled. Therefore, when the second FLL or PLL control loop 324 is deactivated, the parameters of the reference clock 306 are actually frozen. Therefore, the second FLL or PLL control loop 324 is preferably configured to: when the second FLL or PLL control loop 324 is deactivated, the reference clock 306 as the target signal of the second FLL or PLL control loop 324 is generated according to the state of the reference signal in the most recently enabled state of the second FLL or PLL control loop 324. When the first FLL or PLL control loop 323 is enabled, the first FLL or PLL control loop 323 generates a high frequency clock 303 according to the reference clock 306 used as the target signal of the first FLL or PLL control loop 323. When the first FLL or PLL control loop 323 is disabled, the first FLL or PLL control loop 323 generates a high frequency clock 303 as the target signal of the first FLL or PLL control loop according to the state of the reference clock 306 in the last enabled state of the first FLL or PLL control loop 323. This state is also referred to as frozen herein. Preferably, the frequency of the high frequency clock 303 is numerically greater than the frequency of the reference clock 306. Preferably, the cycle duration of the high frequency clock 303 is numerically less than the cycle duration of the reference clock 306. The controller 311 can enable and disable the second FLL or PLL control loop 324 through the second enable / disable signal 325 of the controller 311. The device 300 of the present invention can be in a normal state 400. In particular, in the normal state 400 of the device 300 of the present invention, the controller 311 preferably disables the second FLL or PLL control loop 324 via the second enable / disable signal 325 of the controller 311. The controller 311 may enable or disable the first FLL or PLL control loop 323 via the first enable / disable signal 313 of the controller 311.In the normal state 400 of the device 300 of the present invention, the controller 311 enables the first FLL or PLL control loop 323, preferably by the first enable / disable signal 313 of the controller 311. In the normal state 400, the controller 311 detects the arrival of the reference signal of the input signal 308. Alternatively, in the normal state 400, the controller 311 may anticipate or be notified by the device components of the second control loop 324 of the arrival of the reference signal of the input signal at a predetermined time relative to the start time (e.g., which is characterized by the start signal of the input signal 308). In the state 403 of measuring the synchronization signal of the input signal 308, the controller 311 and / or the device components of the second FLL or PLL control loop 324 measure the reference signal in the input signal 308 used as the synchronization signal, and determine the value of the parameter of the reference signal in the input signal 308 used as the synchronization signal. The controller 311 enables the second FLL or PLL control loop 324 and, for example, after such detection, brings the second FLL or PLL control loop 324 into a state 406 for correcting the frequency or cycle duration or phase of the reference clock 306, so that the second FLL or PLL control loop 324 regulates the corresponding parameters of the reference clock 306 until these parameters of the reference clock 306 substantially correspond to the determined value of the parameter of the reference signal used as a synchronization signal in the input signal 308 or a value derived therefrom. Here, "substantially" means that the remaining control deviation is numerically smaller than the maximum value allowed by the intended application. Then, the controller 311 deactivates the second FLL or PLL control loop 324 and returns the second FLL or PLL control loop 324 to the normal state 400 of the device 300 of the present invention as soon as the value of the corresponding parameter of the reference clock 306 substantially corresponds to the determined value of the parameter of the reference signal used as a synchronization signal in the input signal 308 or a value derived therefrom. Here, "substantially" again means that the remaining control deviation is numerically smaller than the maximum value allowed by the intended application.

[0061] In a first possible improvement of the invention, the controller 311 or the device component of the second control loop 324 evaluates the measured value of the reference signal in the input signal 308 and determines the evaluation result. This makes it possible to prevent the reference clock 306 and therefore the high-frequency clock 303 from being disturbed. For whether the reference signal is actually a reference signal, this depends on, for example, the time when the presence of the reference signal in the input signal 308 is detected and the measured values ​​of the reference signal such as frequency, cycle duration and phase, which must be within a predetermined value interval. The device 300 of the present invention only processes the values ​​of the measured values ​​of the parameters of the reference signal that are within these value intervals and the correct period (for example, relative to the time after the time when the start signal is identified).

[0062] In a second possible improvement of the present invention, when the evaluation result includes one or more values ​​that are not located in the predetermined value interval or do not correspond to the predetermined value, the controller 311 causes the device 300 of the present invention to stay in the normal state 400, wherein the second FLL or PLL control loop 324 is deactivated. This prevents the reference clock 306 and therefore the high-frequency clock 303 from being disturbed.

[0063] In a third possible improvement of the present invention, a reference signal used as a synchronization signal in input signal 308 is measured using high frequency clock 303 and / or a signal derived from high frequency clock 303 and / or a signal related to high frequency clock 303. This has the advantage that no external time reference is required.

[0064] In a fourth possible improvement of the invention, the reference clock 306 in the enabled second FLL or PLL control loop 324 is measured using the high frequency clock 303 and / or a signal derived from and / or related to the high frequency clock 303. This also has the advantage that no external time reference is required.

[0065] In a fifth possible improvement of the present invention, in the state 403 of measuring the synchronization signal of the input signal 308, the value of the parameter used as the reference signal of the synchronization signal in the input signal 308, which is determined by the device component of the device, includes at least one or more values ​​of one or more of the following parameters:

[0066] The number of cycles of the reference signal in the input signal 308 within a predetermined period of time, and / or

[0067] The frequency of the reference signal in the input signal 308, and / or

[0068] the duration of a complete cycle (cycle duration) of the reference signal in the input signal 308, and / or

[0069] The phase of the reference signal in the input signal 308 relative to the divided high frequency clock 521, and / or

[0070] The phase of the reference signal in the input signal 308 relative to the reference clock 306, and / or

[0071] the duration of the low phase and / or high phase of a cycle of the reference signal in the input signal 308, and / or

[0072] a duration of a certain number of cycles of the reference signal in the input signal 308, and / or

[0073] • A certain number of durations of low phases and / or high phases of the reference signal in the input signal 308 .

[0074] In a sixth possible improvement of the present invention, the controller 311 disables the first FLL or PLL control loop 323 before enabling the second FLL or PLL control loop 324, and disables the second FLL or PLL control loop 324 before enabling the first FLL or PLL control loop 323. This prevents the reference clock 306 and the high frequency clock 303 from being disturbed.

[0075] In a seventh possible modification of the present invention, if the device 300 of the present invention is in a state 402 to 405 which is not the normal state 400 of the device 300 of the present invention, the controller 311 disables the first FLL or PLL regulation loop 323. Therefore, the device 300 of the present invention can use a reference signal which only occasionally appears in the input signal 308 as a synchronization signal of the reference clock 306.

[0076] In an eighth possible improvement of the present invention, the second FLL or PLL control loop 324 includes a low-frequency reference oscillator 505, which generates a reference clock 306 having a reference clock frequency, a reference clock cycle duration, and a reference clock phase. In an eighth possible improvement of the present invention, the controller 311 and / or the device components of the second FLL or PLL control loop 324 determine the deviation value of the frequency and / or cycle duration and / or phase of the reference signal of the input signal 308 relative to the reference clock frequency and / or reference clock cycle duration and / or reference clock phase of the reference clock 306 of the low-frequency reference oscillator 505. Therefore, the device 300 of the present invention has an actual value that allows the reference clock 306 to be readjusted first.

[0077] In a ninth possible improvement of the invention, the second FLL or PLL control loop 324 comprises a measuring device 509 for measuring the input signal 308. This firstly allows detecting a reference signal in the input signal 308 and determining parameters of the input signal. For example, the measuring device 509 can store sampled values ​​of a time portion of the input signal 308 in a memory and extract the parameter of interest of the reference signal from the sampled time curve.

[0078] In a tenth possible improvement of the present invention, the measuring device 509 as a device component of the second FLL or PLL control loop 324 detects the arrival of the reference signal of the input signal 308 in the normal state 400 of the device 300 of the present invention, and then notifies the controller 311 of the arrival of the reference signal of the input signal 308 in the normal state 400 of the device 300 of the present invention. This enables the method of the present invention to start.

[0079] In the eleventh possible improvement of the present invention, in particular in the state 403 of measuring the synchronization signal of the input signal 308, the measuring device 509 as a device component of the second FLL or PLL control loop 324 measures the reference signal used as the synchronization signal in the input signal 308. Therefore, the device 300 of the present invention obtains access to the parameters of the reference signal required when it readjusts the reference clock 306.

[0080] In a twelfth possible improvement of the invention, a measuring device 509 as a device component of the second FLL or PLL control loop 324 determines effective values ​​517 of parameters of one or more reference signals which occur occasionally and are used as synchronization signals in the input signal 308. By providing these values, the device 300 of the invention then has target values ​​for controlling the reference clock 306, even if the reference signal is no longer present in the input signal 308 after the reference signal has ended. Thus, the time available for controlling the reference clock 306 is longer than the reference signal.

[0081] In a thirteenth possible improvement of the present invention, the effective values ​​of the parameters of the reference signal used as the synchronization signal in the input signal 308 determined by the measuring device 509 as a device component of the second FLL or PLL control loop 324 include at least one or more effective values ​​517 of one or more of the following parameters:

[0082] The number of cycles of the reference signal used as the synchronization signal in the input signal 308, and / or

[0083] The frequency of the reference signal in the input signal 308, and / or

[0084] the duration of a complete cycle (cycle duration) of the reference signal in the input signal 308, and / or

[0085] The phase of the reference signal in the input signal 308 relative to the divided high frequency clock 521, and / or

[0086] The phase of the reference signal in the input signal 308 relative to the reference clock 306, and / or

[0087] the duration of the low phase and / or high phase of a cycle of the reference signal in the input signal 308, and / or

[0088] a duration of a certain number of cycles of the reference signal in the input signal 308, and / or

[0089] • A certain number of durations of low phases and / or high phases of the reference signal in the input signal 308 .

[0090] In a fourteenth possible improvement of the present invention, the reference signal used as a synchronization signal in the input signal 308 has at least two reference signal features (in particular, a rising edge and / or a falling edge), and the measuring device 509 counts the number of cycles of the high-frequency clock 303 and / or a signal derived from the high-frequency clock 303 and / or a signal related to the high-frequency clock 303 between a first time when the first reference signal feature in the input signal 308 appears and a second time when the second reference signal feature in the input signal 308 appears. In a fourteenth possible improvement of the present invention, the measuring device 509 determines a second count value in this way. Preferably, the measuring device evaluates the second count value and outputs the second count value or a value derived therefrom as an effective measured value 517 of a parameter of one or more reference signals in the input signal 308. Therefore, the device of the present invention then has a target value for regulating the reference clock 306.

[0091] In a fifteenth possible improvement of the present invention, the controller 311 and / or the second FLL or PLL control loop 324 uses the second count value as an effective measurement value 517 of the frequency and / or cycle duration and / or phase of the reference signal of the input signal 308. Therefore, the second FLL or PLL control loop 324 of the device 300 of the present invention then has a target value for controlling the reference clock 306.

[0092] In a sixteenth possible improvement of the present invention, the second FLL or PLL control loop 324 has a reference measuring device 507 for measuring the low frequency reference clock 306. This enables the device 300 of the present invention to detect the actual value of the reference clock 306 for controlling it.

[0093] In a seventeenth possible improvement of the invention, a reference measuring device 507 as a device component of the second FLL or PLL control loop 324 determines the values ​​of parameters of the low-frequency reference clock 306, in particular the frequency and / or the period duration and / or the phase of the low-frequency reference clock 306. Thus, the device 300 of the invention detects the actual value for controlling the reference clock 306.

[0094] In an eighteenth possible improvement of the present invention, the low-frequency reference clock 306 has at least two reference clock features (particularly a rising edge and / or a falling edge), and the reference measurement device 507 counts the number of cycles of the high-frequency clock 303 and / or a signal derived from the high-frequency clock 303 and / or a signal related to the high-frequency clock 303 between a first time when the first reference clock feature in the low-frequency reference clock 306 appears and a second time when the second reference clock feature in the low-frequency reference clock 306 appears. In the eighteenth possible improvement of the present invention, the reference measurement device 507 determines the third count value in this way. Therefore, the device 300 of the present invention has the actual value of the reference clock 306 for regulating it.

[0095] In a nineteenth possible improvement of the present invention, the controller 311 and / or the second FLL or PLL control loop 324 uses the third count value or a value derived therefrom as a reference clock frequency measurement value signal 516 of a reference measuring device 507 for a measurement value 516 of the low-frequency reference clock 306, in particular as a measurement value 516 of the frequency and / or cycle duration of the reference clock 306. Therefore, the device 300 of the present invention uses the actual value of the reference clock 306 to control it.

[0096] In the twentieth possible improvement of the present invention, the low-frequency reference clock 306 has at least one reference clock feature (particularly a rising edge and / or a falling edge), and the reference signal in the input signal 308 has at least one reference signal feature (particularly a rising edge and / or a falling edge). In the twentieth possible improvement of the present invention, the reference measurement device 507 counts the number of cycles of the high-frequency clock 303 and / or a signal derived from the high-frequency clock 303 and / or a signal related to the high-frequency clock 303 between the time when the reference clock feature in the low-frequency reference clock 306 appears and the time when the reference signal feature in the reference signal of the input signal 308 appears. In this twentieth possible improvement of the present invention, the reference measurement device 507 determines the third count value in this way.

[0097] In a twenty-first possible improvement example of the present invention, the controller 311 and / or the second FLL or PLL control loop 324 are configured to use the third count value or a value derived therefrom as a reference clock phase measurement value signal 516 of a reference measurement device 507 for a measurement value 516 of a low-frequency reference clock 306, in particular for the phase measurement value 516 serving as the reference clock 306.

[0098] In the twenty-second possible improvement example of the present invention, the low-frequency reference clock 306 has at least one reference clock characteristic (especially the rising edge and / or the falling edge), and the divided high-frequency clock 521 has at least one reference high-frequency clock characteristic (especially the rising edge and / or the falling edge).

[0099] In the twenty-third possible improvement example of the present invention, the reference measurement device 507 counts the number of cycles of the high-frequency clock 303 and / or a signal derived from the high-frequency clock 303 and / or a signal related to the high-frequency clock 303 between the time when the reference clock feature in the low-frequency reference clock 306 appears and the time when the reference high-frequency clock feature in the divided high-frequency clock 521 appears. In this twenty-third possible improvement example of the present invention, the reference measurement device 507 determines the third count value in this way.

[0100] In a twenty-fourth possible improvement example of the present invention, the controller 311 and / or the second FLL or PLL control loop 324 uses the third count value or a value derived therefrom as a reference clock phase measurement value signal 516 of a reference measurement device 507 for a measurement value 516 of the low-frequency reference clock 306, in particular as a phase measurement value 516 of the reference clock 306.

[0101] In the twenty-fifth possible improvement example of the present invention, the reference signal in the input signal 308 has at least one reference signal characteristic (especially a rising edge and / or a falling edge), and the divided high-frequency clock 521 has at least one reference high-frequency clock characteristic (especially a rising edge and / or a falling edge).

[0102] In the twenty-sixth possible improvement example of the present invention, the phase detector 519 counts the number of cycles of the high-frequency clock 303 and / or a signal derived from the high-frequency clock 303 and / or a signal related to the high-frequency clock 303 between the time when the reference signal feature in the reference signal of the input signal 308 appears and the time when the reference high-frequency clock feature in the divided high-frequency clock 521 appears. In the twenty-sixth possible improvement example of the present invention, the phase detector 519 determines the fourth count value in this way.

[0103] In the twenty-seventh possible improvement example of the present invention, the controller 311 and / or the first FLL or PLL control loop 323 uses the fourth count value or a value derived therefrom as the high-frequency clock phase measurement value signal 516 of the phase detector 519, in particular as the phase measurement value 516 of the high-frequency clock 303.

[0104] In the twenty-eighth possible improvement example of the present invention, the reference clock 306 has at least one reference clock characteristic (especially the rising edge and / or the falling edge), and the divided high-frequency clock 521 has at least one reference high-frequency clock characteristic (especially the rising edge and / or the falling edge).

[0105] In a twenty-ninth possible improvement example of the present invention, the phase detector 519 counts the number of cycles of the high-frequency clock 303 and / or a signal derived from the high-frequency clock 303 and / or a signal related to the high-frequency clock 303 between the time when the reference clock feature of the reference clock 306 appears and the time when the reference high-frequency clock feature in the divided high-frequency clock 521 appears. In the twenty-ninth possible improvement example of the present invention, the phase detector 519 determines the fifth count value in this way.

[0106] In a thirtieth possible improvement example of the present invention, the controller 311 and / or the first FLL or PLL control loop 323 uses the fifth count value or a value derived therefrom as the high-frequency clock phase measurement value signal 516 of the phase detector 519, in particular as the phase measurement value 519 of the high-frequency clock 303.

[0107] In a thirty-first possible improvement of the present invention, the second FLL or PLL control loop 324 has a target value calculator 510. This enables the device 300 of the present invention to determine the control deviation when the reference clock 306 is controlled.

[0108] In a thirty-second possible improvement of the present invention, the target value calculator 510 determines a deviation 518, in particular a deviation 518 in the form of a difference, between a measured value 516 of the low-frequency reference clock 306 or a value derived therefrom or related thereto and a determined effective value 517 of a parameter of one or more reference signals used as synchronization signals of the input signal 308. Thus, the device 300 of the present invention has a measured value for the control deviation of the control reference clock 306.

[0109] In a thirty-third possible improvement of the invention, the frequency and / or cycle duration and / or phase of reference clock 306 depends on deviation 518 and / or a value derived therefrom or related thereto. This closes the control loop for controlling reference clock 306 of device 300 of the invention.

[0110] In the thirty-fourth possible improvement of the present invention, the second FLL or PLL control loop 324 has a second controller II 504. The second controller II 504 of the device 300 of the present invention is preferably a PI controller, etc. It ensures that the control error is substantially zero except for a small residual error when the reference clock 306 is controlled.

[0111] In a thirty-fifth possible improvement of the present invention, the second FLL or PLL control loop 324 has a reference oscillator 505, and the second controller II 504 forms a second control signal II 514 of the second controller II 504 according to the deviation 518 and / or in a manner proportional to the deviation and / or a value derived therefrom or a value related thereto. Therefore, the device 300 of the present invention has a manipulated variable for controlling the reference oscillator 306. In a thirty-fifth possible improvement of the present invention, the reference oscillator 505 forms the reference clock 306 according to the second control signal II 514.

[0112] In a thirty-sixth possible improvement of the present invention, the second controller II 504 forms the second control signal II 514 of the second controller II 504 according to a correction value depending on a) the deviation 518 or b) a value derived therefrom or c) a value related thereto, taking into account the trimming curve and / or the trimming step size during a) to c). This has the advantage that non-ideal conditions can be taken into account and the device 300 of the present invention can be improved by a calibration step.

[0113] In a thirty-seventh possible improvement of the present invention, the second FLL or PLL control loop 324 has a reconstruction oscillator 810, which simulates the control signal of the input signal 308 at least when the control signal is not available, so that the time reference of similar parameters of the device 300 of the present invention is also available at these times. For example, the parameters can be the values ​​of frequency, cycle duration and phase.

[0114] In a thirty-eighth possible improvement example of the present invention, the reconstruction oscillator 810 generates a reconstructed reference signal 806 based on the effective value 517 of the parameters of one or more reference signals of the input signal 308 detected by the measuring device 509 .

[0115] In the thirty-ninth possible improvement of the present invention, the reconstruction oscillator 810 also preferably generates a reconstruction reference signal 806 from the high-frequency clock 303 based on the effective value 517 of the parameters of one or more reference signals of the input signal 308 detected by the measuring device 509. For example, the parameters may be the values ​​of frequency, cycle duration and phase.

[0116] In the fortieth possible improvement of the present invention, the reconstruction oscillator 810 has an additional clock divider. Preferably, the additional clock divider generates the reconstruction reference signal 806 from the high-frequency clock 303 by clock-dividing the high-frequency clock 303 according to the division ratio using a division ratio associated with the clock divider. Preferably, the division ratio depends on the effective value 517 detected by the measuring device 509 and / or the value derived therefrom of the parameters of one or more reference signals of the input signal 308. In particular, the division ratio can be proportional or inversely proportional to the values ​​of these parameters, or, for example, can be the time integral of these values ​​or their inverse or other values ​​derived from these parameters. For example, the parameters can be the values ​​of frequency, cycle duration and phase.

[0117] In the forty-first possible improvement of the present invention, the reconstruction oscillator 810 generates a frequency correction reference signal 906. Preferably, the reconstruction oscillator 810 generates the frequency correction reference signal 906 according to the effective value 517 of the parameter of one or more reference signals of the input signal 308 detected by the measuring device 509 and the parameter 516 of the reference clock 306 determined by the reference measuring device 507. For example, the parameter may be the value of the frequency, cycle duration and phase.

[0118] In the 42nd possible improvement of the present invention, the reconstruction oscillator 810 generates a frequency correction reference signal 906 from the high frequency clock 303 according to the effective value 517 of the parameter of one or more reference signals of the input signal 308 detected by the measuring device 509 and according to the parameter 516 of the reference clock 306 determined by the reference measuring device 507. For example, the parameters can be the values ​​of frequency, cycle duration and phase, respectively.

[0119] In the 43rd possible improvement of the present invention, the reconstruction oscillator 810 has an additional clock divider. In the 43rd possible improvement of the present invention, the additional clock divider generates a frequency correction reference signal 906 from the high-frequency clock 303 by clock-dividing the high-frequency clock 303 according to the division ratio of the clock divider using a division ratio, the division ratio depending on the effective value 517 of the parameter of one or more reference signals of the input signal 308 detected by the measuring device 509 and the parameter 516 determined by the reference measuring device 507 of the reference clock 306. For example, the parameters can be the values ​​of frequency, cycle duration and phase, respectively.

[0120] Thus, by means of the reconstruction oscillator 810, a frequency-corrected reference signal 906 can actually be generated based on the detected effective values ​​of the parameters 517 of one or more reference signals of the input signal 308, which have been detected by the measuring device 509, and the determined parameters 516 of the reference clock 306, which have been detected by the reference measuring device 507, to which the second FLL or PLL control loop 324 can subsequently be regulated. In the simplest case, this generation is performed by dividing the clock 303 in an additional clock divider of the reconstruction oscillator 810 with a division ratio, which is, for example, calculated and set in the clock divider by the controller 311 based on the detected effective values ​​517 of the parameters of one or more reference signals of the input signal 308 and / or the determined parameters 516 of the reference clock 306, or the clock divider itself is determined and set based on the detected effective values ​​517 of the parameters of one or more reference signals of the input signal 308 and / or the determined parameters 516 of the reference clock 306.

[0121] In the forty-fourth possible improvement of the present invention, the second FLL or PLL control loop 324 has a second phase detector 819 and / or a second frequency difference detector 819 and / or a second cycle duration difference detector 819. Therefore, the device 300 of the present invention can determine the deviation between the frequency or cycle duration or phase of the reference clock 306 and the frequency or cycle duration or phase of the reconstructed reference signal 806 or the frequency correction reference signal 906.

[0122] Therefore, in the forty-fifth possible improvement example of the present invention, the second phase detector 819 compares the reconstructed reference signal 806 or the frequency-corrected reference signal 906 with the reference clock 306, and / or the second frequency difference detector 819 compares the reconstructed reference signal 806 or the frequency-corrected reference signal 906 with the reference clock 306, and / or the second cycle duration difference detector 819 compares the reconstructed reference signal 806 or the frequency-corrected reference signal 906 with the reference clock 306. In the forty-fifth possible improvement example of the present invention, the second phase detector 819 generates a deviation signal of the phase detector 819 for the phase deviation between the reconstructed reference signal 806 or the frequency-corrected reference signal 906 and the reference clock 306 according to the result of the comparison. Alternatively, in the forty-fifth possible improvement example of the present invention, the second frequency difference detector 819 generates a deviation signal of the frequency difference detector 819 for the frequency deviation between the reconstructed reference signal 806 or the frequency-corrected reference signal 906 and the reference clock 306 according to the result of the comparison. Alternatively, in the forty-fifth possible improvement example of the present invention, the second cycle duration difference detector 819 generates a deviation signal of the cycle duration difference detector 819 for reconstructing the cycle duration deviation between the reference signal 806 or the frequency correction reference signal 906 and the reference clock 306 based on the result of the comparison.

[0123] Then, in a forty-sixth possible improvement of the present invention, the frequency and / or cycle duration and / or phase of the reference clock 306 depends on the value of the deviation signal 818 and / or a value derived therefrom or related thereto.

[0124] In the forty-seventh possible improvement example of the present invention, the second regulator II 504 generates a second control signal II 514 based on the value of the deviation signal 818 and / or in a manner proportional to the value of the deviation signal 818 and / or a value derived therefrom or related thereto, and forms a reference clock 306 based on the second control signal II 514.

[0125] In the forty-eighth possible improvement example of the present invention, the second regulator II 504 forms a second control signal II 514 based on a correction value depending on a) the value of the deviation signal 818 or b) a value derived therefrom or c) a value related thereto, taking into account the trimming curve and / or the trimming step size from a) to c).

[0126] In the forty-ninth possible improvement of the present invention, as long as the controller 311 notifies the second regulator II 504 that the second FLL or PLL regulation loop 324 should be in a disabled state through the second enable / disable signal 325, the second regulator II 504 maintains the second control signal II 514 at an unchanged value. Therefore, this enables the second FLL or PLL regulation loop 324 to be disabled.

[0127] In the fiftieth possible improved example of the present invention, the first FLL or PLL control loop 323 has a high-frequency oscillator 502 that generates a high-frequency clock 303.

[0128] In the fifty-first possible improvement example of the present invention, the first FLL or PLL control loop 323 has a first clock divider 520. In the fifty-first possible improvement example of the present invention, the first clock divider 520 divides the high frequency clock 303 of the high frequency oscillator 502 into a divided high frequency clock 521 according to a first division ratio of the first clock divider 520. Therefore, the first FLL or PLL control loop 323 has an actual signal that can be used to compare with the reference clock 306 used to control the high frequency clock 303.

[0129] In the fifty-second possible improvement example of the present invention, the first FLL or PLL control loop 323 has a phase detector 519 and / or a frequency difference detector 519 and / or a cycle time difference detector 519 of the first FLL or PLL control loop 323, so that the device 300 of the present invention can detect the phase and / or frequency deviation of the high-frequency clock 303, and use it to control the high-frequency clock 303. For ease of explanation, the phase detector 519, the frequency difference detector 519 and the cycle time difference detector 519 are generally referred to as the phase detector 519 as a general term.

[0130] In the fifty-third possible improvement example of the present invention, the phase detector 519 of the first FLL or PLL control loop 323 detects the phase difference and / or frequency difference and / or cycle duration difference between the reference clock 306 and the divided high-frequency clock 521 as a measurement value, and forms a high-frequency clock frequency measurement value signal 522 representing the measurement value or a value derived therefrom. Therefore, the device 300 of the present invention is able to determine the current deviation of the current frequency and / or cycle duration and / or phase of the high-frequency clock 303 from the target value specification of the reference clock 306, and use it to control the high-frequency clock 303.

[0131] In a fifty-fourth possible improved example of the present invention, the first FLL or PLL control loop 323 has a first regulator I 502 of the first FLL or PLL control loop 323.

[0132] In the fifty-fifth possible improvement example of the present invention, the first regulator I 501 forms the first control signal I 515 of the first regulator I 501 according to the high-frequency clock frequency measurement value signal 522. In the fifty-fifth possible improvement example of the present invention, the high-frequency oscillator 502 forms the high-frequency clock 303 at least temporarily according to the first control signal I 515 of the first regulator I 501.

[0133] In the fifty-sixth possible improvement example of the present invention, the first regulator I 501 is configured to maintain the first control signal I 515 at a constant value as long as the controller 311 notifies the first regulator I 501 through the first enable / disable signal 313 that the first FLL or PLL control loop 323 should be in a disabled state.

[0134] In the fifty-seventh possible improvement example of the present invention, if the controller 311 notifies the first regulator I 501 through the first enable / disable signal 313 that the first FLL or PLL control loop 323 should be in the enabled state, the first regulator I 501 no longer maintains the first control signal I 515 as a constant value, and controls the high-frequency clock 303 through the first control signal I 515. Since each measurement substantially uses the high-frequency clock 303 having the same parameters (e.g., frequency and / or cycle duration length and / or phase) even when measurements are made at different times within the calibration phase, the device 300 of the present invention can minimize interference in the measurement of the second FLL or PLL control loop 324 that uses the high-frequency clock 303 for measurement.

[0135] In the fifty-eighth possible improvement example of the present invention, the first regulator I 501 keeps the first control signal I 515 at a constant value until a reference clock feature, in particular a rising edge or a falling edge, appears in the reference clock 306. In the fifty-eighth possible improvement example of the present invention, when a reference clock feature (in particular, a rising edge or a falling edge) appears in the reference clock 306, the first regulator I 501 sets the first frequency divider 520 and / or the first control signal I 515 to a predetermined value, and from then on, the first control signal I 515 is no longer forced to be a constant value. Therefore, if the first FLL or PLL control loop 323 was previously disabled, the device 300 of the present invention can re-enable the control of the high-frequency clock 303 by the first FLL or PLL control loop 323.

[0136] In a fifty-ninth possible improvement example of the present invention, the controller 311 detects the duration of a specific number of cycles of the reference clock 306 of the reference oscillator 505 through the high-frequency clock 303 and through the component 507 for measuring the reference clock 306. In this fifty-ninth possible improvement example of the present invention, the controller 311 corrects the frequency and / or cycle duration and / or phase of the reference clock 306 of the reference oscillator 505 according to the determined deviation, in particular in a manner proportional to the determined deviation, and detects the duration of the specific number of cycles of the reference clock 306 of the reference oscillator 505 again until the frequency and / or cycle duration and / or phase of the reference clock 306 of the reference oscillator 505 reaches the target value of the frequency or cycle duration or phase of the reference clock 306 of the reference oscillator 505.

[0137] In the sixtieth possible improvement example of the present invention, the controller 311 freezes the first FLL or PLL control loop 323 when the reference signal of the input signal 308 arrives, thereby deactivating the first FLL or PLL control loop 323, so that the high-frequency clock 303 of the controllable high-frequency oscillator 502 or the first FLL or PLL control loop 323 does not change its frequency and / or cycle duration and / or phase, especially during the duration of the presence of the reference signal of the input signal 308.

[0138] In the sixty-first possible improvement of the present invention, after deactivating the first FLL or PLL control loop 323 immediately after the end of the appearance of the reference signal as a synchronization signal in the input signal 308, the device 300 of the present invention does not re-enable the first FLL or PLL control loop 323. In the sixty-first possible improvement of the present invention, the device 300 of the present invention re-enables the first FLL or PLL control loop 323 only at the end of the remaining data frame of the data communication after the reference signal in the input signal 308, or only at the end of the relevant data message (i.e., the data communication transmitted by the input signal 308) after the reference signal in the input signal 308. Therefore, in the sixty-first possible improvement of the present invention, the device 300 of the present invention delays the re-enabling of the first FLL or PLL control loop 323 until the end of the communication. Therefore, the control process can only interfere with the data communication with a lower probability.

[0139] In the sixty-second possible improvement of the present invention, if the device 300 of the present invention is not in the normal state 400 and if the controller 311 subsequently detects the arrival of another additional reference signal in the input signal 308, the device 300 of the present invention returns to the normal state 400, because the most recent reference signal may not be a reference signal, but the device 300 of the present invention simply erroneously interprets the signal as such a reference signal. This avoids interference with the regulation of the high-frequency clock 303.

[0140] In the sixty-third possible improvement of the present invention, the device 300 of the present invention has a component 510 for detecting the successful completion of the correction 406 of the frequency and / or phase and / or cycle duration of the reference clock 306. In the sixty-third possible improvement of the present invention, the device 300 of the present invention, in particular, its controller 311, notifies the superior system that the frequency and / or phase and / or cycle duration of the reference clock 306 has been reached. This enables the superior system to recognize that data communication can be performed in terms of timely sampling of the data signal appearing at least on the input signal 308.

[0141] In the sixty-fourth possible improvement example of the present invention, after successfully completing the correction 406 of the frequency and / or cycle duration and / or phase of the reference clock 306 and after reaching the frequency and / or cycle duration and / or phase of the reference clock 306, the device 300 of the present invention switches to "fine correction mode". The fine correction mode of the device 300 of the present invention is different from the normal mode (the normal mode is the mode in which the device is in, for example, during the first synchronization after the system of the device 300 of the present invention is started) in that the device corrects the second FLL or PLL control loop 324 or the reference oscillator 505 only through a specific number of trimming steps or through a specific frequency change or cycle duration change or phase change of the reference clock 306 of the second FLL or PLL control loop 324 and / or the reference oscillator 504, or the correction is limited to the trimming step or the specific frequency change or cycle duration change or phase change, in particular, limited to a fine-tuning step or the minimum possible change in frequency change or cycle duration change or phase change of the reference clock 306 of the second FLL or PLL control loop 324 and / or the reference oscillator 504. Furthermore, when leaving the normal state 400, the device can subsequently omit deactivation of the first FLL or PLL control loop 324, since the transient process of the first FLL or PLL control loop 324 and the limitation of frequency change and / or cycle duration change and / or phase change have been previously completed.

[0142] In the sixty-fifth possible improvement example of the present invention, the device 300 of the present invention has a non-volatile memory. Particularly preferably, the controller 311 of the device 300 of the present invention has the non-volatile memory. Preferably, after the correction 406 of the frequency, cycle duration or phase of the reference clock 306 is completed or directly before the device 300 of the present invention stops running, the device 300 of the present invention and / or the controller 311 of the device 300 of the present invention and / or another suitable sub-device of the device 300 of the present invention stores the determined values ​​for frequency correction and / or cycle duration correction and / or phase correction in the non-volatile memory.

[0143] In the sixty-sixth possible improvement example of the present invention, the device 300 of the present invention and / or the controller 311 of the device 300 of the present invention and / or another suitable sub-device of the device 300 of the present invention reads the values ​​for frequency correction and / or cycle duration correction and / or phase correction of the reference clock 306 determined during debugging from the non-volatile memory, and uses these values ​​for frequency correction and / or cycle duration correction and / or phase correction of the reference clock 306.

[0144] In the sixty-seventh possible improvement example of the present invention, the second FLL or PLL control loop 324 has a phase detector 819 and / or a frequency difference detector 819 and / or a cycle time difference detector 819. In the following paragraphs, for the sake of simplicity, the phase detector 519, the frequency difference detector 519 and the cycle time difference detector 519 are sometimes referred to as only the phase detector 519 in the same way to improve the comprehensibility of the text. In the sixty-seventh possible improvement example of the present invention, the second FLL or PLL control loop 324 has a clock divider 1024, a reference clock 306, a reconstruction oscillator 810 and a measuring device 509. In the sixty-seventh possible improvement example of the present invention, the measuring device 509 detects a measured value 517 of a parameter of one or more occasionally occurring reference signals in the input signal 308, wherein these parameters are typically the frequency and / or cycle duration and / or phase of one or more occasionally occurring reference signals in the input signal 308. In the sixty-seventh possible improvement of the present invention, the reconstruction oscillator 810 generates a reconstructed reference signal 806 based on the detected measurement value 517 of the frequency and / or cycle duration and / or phase of one or more reference signals in the input signal 308. Preferably, this dependence of the reconstructed reference signal 806 makes the value of the basic parameter of the reference clock 306 consistent with the corresponding value of the corresponding basic parameter of the one or more reference signals in the input signal 308, or has a fixed numerical relationship with them. These parameters are preferably also the corresponding frequency and / or phase and / or cycle duration. In the sixty-seventh possible improvement of the present invention, the clock divider 1024 of the second FLL or PLL control loop 324 divides the reference clock 306 into a divided reference clock 1025 according to the division ratio of the clock divider 1024 of the second FLL or PLL control loop 324. Here, the phase detector 819 compares the value of the parameter of the frequency or phase or cycle duration of the reconstructed reference signal 806 with the value of the corresponding parameter of the frequency or phase or cycle duration of the divided reference clock 1025, and forms the value of the deviation signal 1018 of the phase detector 819 according to the value of the comparison result. In the sixty-seventh possible improvement example of the present invention, the second regulator II 504 forms the value of the second control signal II 514 according to the value of the deviation signal 1018. Then, the reference oscillator 505 preferably forms the reference clock 306 according to the value of the second control signal II 514.

[0145] In the sixty-seventh possible improvement of the present invention, the measuring device 509 detects the measured values ​​of the parameters of one or more reference signals that occur occasionally in the input signal 308, evaluates their rationality, and transmits them as valid measured values ​​517 of the parameters of one or more valid reference signals that occur occasionally in the input signal 308. Then, the reconstruction oscillator 810 generates the reconstructed reference signal 806 based on these detected valid measured values ​​517 of the frequency and / or cycle duration and / or phase of the one or more valid reference signals of the input signal 308.

[0146] In the sixty-eighth possible improvement of the device for generating a high-frequency clock 303 of the present invention, the device includes a controller 311, a first FLL or PLL control loop 323, a fixed-frequency reference clock oscillator 1101, an input signal 308, a frequency division ratio calculator 1110 and a measuring device 509. The first FLL or PLL control loop 323 has a first frequency divider 520. In the sixty-eighth possible improvement of the present invention, the reference signal appears temporarily and / or occasionally as a part of the input signal 308. In the sixty-eighth possible improvement of the present invention, the fixed-frequency reference clock oscillator 1101 usually generates a reference clock 306. In the sixty-eighth possible improvement of the present invention, the frequency of the high-frequency clock 303 is usually greater than the frequency of the reference clock 306 in value. In the sixty-eighth possible improvement of the present invention, the cycle duration of the high-frequency clock 303 is usually less than the cycle duration of the reference clock 306 in value. In the sixty-eighth possible improvement example of the present invention, in the state 403 of measuring the parameters of the reference signal of the input signal 308, the measuring device 509 measures one or more reference signals that occasionally appear in the input signal 308, and preferably determines the corresponding measured values ​​of the frequency and / or cycle duration and / or phase of the one or more reference signals in the input signal 308. If necessary, in the sixty-eighth possible improvement example of the present invention, the measuring device 509 evaluates the determined measured value. In this case, the device of the present invention preferably checks whether the measured value is located in a previously known and / or predetermined and / or stored measured value interval. If these determined measured values ​​are located in a previously known and / or predetermined and / or stored measured value interval, these measured values ​​are valid measured values, and the one or more reference signals from which these measured values ​​are derived are valid reference signals. In the sixty-eighth possible improvement example of the present invention, the first frequency divider 520 divides the high-frequency clock 303 into the frequency of the divided high-frequency clock 521 at a frequency division ratio. In parallel, the first frequency divider 520 preferably divides the high frequency clock 303 into the auxiliary clock 1112 of the first frequency divider 520 at a second frequency division ratio. If necessary, the auxiliary clock 1112 can be the same as the divided high frequency clock 521. In the sixty-eighth possible improvement example of the present invention, the frequency division ratio calculator 1110 preferably determines the measured value of the frequency and / or cycle duration and / or phase of the auxiliary clock 1112 through the auxiliary clock 1112. In the sixty-eighth possible improvement example of the present invention, the frequency division ratio calculator 1110 preferably receives the measured value 517 of the frequency and / or cycle duration and / or phase of one or more reference signals in the input signal 308 from the measuring device 509. In the sixty-eighth possible improvement example of the present invention, the frequency division ratio calculator 1110 compares the measured value 517 of the frequency or cycle duration of one or more reference signals of the input signal 308 with the measured value of the frequency and / or cycle duration of the auxiliary clock 1112, and thereby determines the ratio value.The ratio value preferably reflects the ratio and / or difference between the measured value 517 of the frequency or cycle duration or phase of one or more effective reference signals of the input signal 308 and the measured value of the frequency and / or cycle duration and / or phase of the auxiliary clock 1112, or a value derived therefrom. In a sixty-eighth possible improvement of the present invention, the frequency division ratio calculator 1110 changes the target frequency division ratio 1111 of the first frequency divider 520 according to the deviation value between the predetermined ratio value 1113 and the ratio value.

[0147] In the sixty-ninth possible improvement example of the present invention regarding the device for generating the high-frequency clock 303, in the state 403 of measuring the parameters of the reference signal of the input signal 308, the measuring device 509 measures one or more reference signals that occasionally appear in the input signal 308 and evaluates them as "valid" or "invalid" reference signals. In the sixty-ninth possible improvement example of the present invention regarding the device for generating the high-frequency clock 303, in the case of excluding invalid reference signals, the measuring device 509 determines the valid measurement value 517 according to the measurement value of the valid reference signal. These valid measurements 517 are usually the measurement values ​​of the parameters of one or more reference signals in the input signal 308. These parameters are usually the frequency and / or cycle duration and / or phase of one or more reference signals of the input signal and the values ​​determined by these valid measurement values. In the sixty-ninth possible improvement example of the present invention, the frequency division ratio calculator 1110 usually receives the current valid measurement value 517 of the frequency and / or cycle duration and / or phase of one or more reference signals in the input signal 308 from the measuring device 509. In the sixty-ninth possible improvement example of the present invention, the frequency division ratio calculator 1110 compares the effective measurement values ​​517 of the frequency and / or cycle duration and / or phase of one or more reference signals of the input signal 308 with the corresponding measurement values ​​of the frequency and / or cycle duration and / or phase of the auxiliary clock 1112. In the sixty-ninth possible improvement example of the present invention, the frequency division ratio calculator 1110 determines a ratio value based on the effective measurement value, which reflects the ratio and / or difference between the measurement values ​​517 of the frequency or cycle duration or phase of one or more effective reference signals of the input signal 308 and the measurement values ​​of the frequency and / or cycle duration and / or phase of the auxiliary clock 1112, or a value derived therefrom.

[0148] In the seventieth possible improvement of the present invention, the corresponding method comprises generating a reconstructed reference signal 806, in particular by means of a reconstruction oscillator 810 according to the detected valid measured values ​​517 of the frequency and / or cycle duration and / or phase of one or more reference signals of the input signal 308. Preferably, the reconstruction oscillator 810 generates the reconstructed reference signal 806 from the high frequency clock 303 by dividing the high frequency clock 303 into the reconstructed reference signal 806 according to the detected valid measured values ​​517. In parallel, the method of the present invention comprises dividing the reference clock 306 into a divided reference clock 1025 according to the division ratio by means of a clock divider 1024 of a second FLL or PLL control loop 324. In addition, the method of the present invention comprises comparing the value of the parameter of the frequency or phase or cycle duration of the reconstructed reference signal 806 with the value of the corresponding parameter of the frequency or phase or cycle duration of the divided reference clock 1025 by means of a phase detector 819 or a frequency difference detector 819 or a cycle duration difference detector 819, and forming the value of the deviation signal 1018 according to the value of the comparison result. The method of the invention further comprises, for example, forming the value of the second control signal II 514 by means of the second controller II 504 as a function of the value of the deviation signal 1018 and in particular forming the reference clock 306 by means of the reference oscillator 505 as a function of the value of the second control signal II 514 .

[0149] In the seventy-first possible improvement example of the present invention, differently from the above description, the method includes generating a reconstructed reference signal 806 by reconstructing the oscillator 810 only based on the detected effective measurement value 517 of the frequency and / or period duration and / or phase of one or more reference signals of the input signal 308.

[0150] In the seventy-second possible improvement of the present invention, the method for generating the high-frequency clock 303 includes generating a substantially fixed-frequency reference clock 306, in particular by means of a fixed-frequency reference clock oscillator 1101. Here, the frequency of the high-frequency clock 303 is usually greater than the frequency of the reference clock 306, or the cycle duration of the high-frequency clock 303 is usually less than the cycle duration of the reference clock 306.

[0151] In the seventy-third possible improvement example of the present invention, the method includes in the state 403 of measuring the parameters of the reference signal of the input signal 308, in particular detecting the values ​​of parameters of one or more reference signals that occasionally appear in the input signal 308 by means of the measuring device 509, wherein the parameters may include frequency and / or period duration and / or phase.

[0152] In a seventy-fourth possible improvement of the invention, the method comprises in a state 403 of measuring parameters of a reference signal of the input signal 308 , in particular by means of a measuring device 509 , evaluating detection values ​​of one or more parameters of the reference signal which occur occasionally in the input signal 308 .

[0153] In the seventy-fifth possible improvement of the present invention, the method includes determining the measured value 517 of the parameter of one or more reference signals in the input signal 308 based on the determined / evaluated value of the parameter of one or more reference signals that occasionally appear in the input signal 308, in particular by the measuring device 509, wherein the parameter may include the frequency and / or the cycle duration and / or the phase. In the seventy-fifth possible improvement of the present invention, the method includes dividing the high-frequency clock 303 into the frequency and / or cycle duration of the divided high-frequency clock 521 by the frequency division ratio, in particular by the first frequency divider 520. In the seventy-fifth possible improvement of the present invention, the method includes dividing the high-frequency clock 303 into the auxiliary clock 1112 according to the second frequency division ratio, in particular by the first frequency divider 520. In the seventy-fifth possible improvement of the present invention, the method includes determining the measured value of the frequency and / or cycle duration and / or phase of the auxiliary clock 1112, in particular by the frequency division ratio calculator 1110. In the seventy-second possible improvement of the present invention, the method comprises comparing the determined measured values ​​517 of the frequency and / or cycle duration and / or phase of one or more reference signals of the input signal 308 with the corresponding measured values ​​of the frequency and / or cycle duration and / or phase of the auxiliary clock 1112, in particular by means of a frequency division ratio calculator 1110. In the seventy-fifth possible improvement of the present invention, the method comprises determining a ratio value, in particular by means of a frequency division ratio calculator 1110, which reflects the ratio and / or difference between the measured values ​​517 of the frequency or cycle duration or phase of one or more valid reference signals of the input signal 308 and the corresponding measured values ​​of the frequency and / or cycle duration and / or phase of the auxiliary clock 1112, or a value derived therefrom. In the seventy-fifth possible improvement of the present invention, in particular by means of a frequency division ratio calculator 1110, the target frequency division ratio 1111 of the first frequency divider (520) is changed according to a predetermined ratio value 1113 and a deviation value between the ratio value, thereby exemplarily completing the method.

[0154] In the seventy-sixth possible improvement of the device for generating a high-frequency clock 303 of the present invention, in the state 403 of measuring the parameters of the reference signal of the input signal 308, the measuring device 509 measures and, if necessary, evaluates one or more valid reference signals that occasionally appear in the input signal 308. Preferably, the measuring device 509 determines the valid measured value 517 of the parameter of the one or more reference signals in the input signal 308. In parallel with this, the frequency division ratio calculator 1110 preferably receives the valid measured value 517 of the frequency and / or period duration and / or phase of the one or more reference signals in the input signal 308 from the measuring device 509. In the seventy-sixth possible improvement example of the present invention, the division ratio calculator 1110 generally compares the effective measured values ​​517 of the frequency and / or cycle duration and / or phase shift of one or more reference signals of the input signal 308 with the corresponding measured values ​​of the frequency and / or cycle duration and / or phase shift of the auxiliary clock 1112, and thereby determines a ratio value, which reflects the ratio and / or difference between the effective measured values ​​517 of the frequency or cycle duration or phase of one or more effective reference signals of the input signal 308 and the measured values ​​of the frequency and / or cycle duration and / or phase of the auxiliary clock 1112, or a value derived therefrom. BRIEF DESCRIPTION OF THE DRAWINGS

[0155] Figure 1 The following PAL color burst signal from the prior art is shown: https: / / de.wikipedia.org / wiki / Phasenregelschleife#:~:text=Eine%20Phasenre gelschleife%20%28PLL%2C%20nach%20englisch%20phaselocked%20loop%29%20ist,von%20der%20Regelabweichung%20%E2%80%93%20der%20Phasenverschiebung%20%E2%80%93%20periodisch.

[0156] Figure 2 The LIN sync field from https: / / www.eetimes.com / design-flexibility-key-to-simplifying-the-implementation-of-lin is shown. Figure 1 and Figure 2 This article refers to Figure 1 and Figure 2 The content of the prior art cited in.

[0157] Figure 3The basic structure of the device 300 of the present invention is shown in a schematic and simplified manner.

[0158] Figure 4 The sequence of the method according to the first variant of the invention is shown in a simplified and schematic manner.

[0159] Figure 5 The device 300 of the present invention is shown in a schematic and simplified manner, wherein the design of the first FLL or PLL control loop 323 and the second FLL or PLL control loop 324 is similar to that of the first FLL or PLL control loop 323. Figure 3 More details.

[0160] Figure 6 Corresponds to Figure 4 , but the difference is that the first FLL or PLL control loop 323 has a different enable.

[0161] Figure 7 To a large extent corresponds to Figure 5 , where Figure 5 In comparison, Figure 7 Lieutenant General Figure 5 The reference oscillator 505 is divided into an adjustable second clock divider 702 and a non-adjustable reference oscillator 701 .

[0162] Figure 8 To a large extent corresponds to Figure 5 , where Figure 5 In comparison, the reconstruction oscillator 810 and the second phase detector 819 or the second frequency difference detector 819 or the second period duration difference detector 819 replace Figure 5 The reference measuring equipment 507 and Figure 5 The target value calculator 510 is used.

[0163] Fig. 9 To a large extent corresponds to Figure 5 ,in Fig. 9 The device 300 of the present invention now alternatively includes a comparator 910, which preferably determines the deviation value between the measured value of the frequency and / or cycle duration and / or phase of the reference clock frequency measurement value signal 516 or the reference clock cycle duration measurement value signal 516 or the reference clock phase measurement value signal 516 and the valid measured value 517 of the frequency or cycle duration or phase of one or more of the most recent valid reference signals in the input signal 308, and generates a comparison result in the form of a comparison result signal 918.

[0164] Fig.10 express Figure 8 The simplification of the technical enlightenment, as in Figure 8In the embodiment, the reconstruction oscillator 810 generates a reference signal as the continuous reconstructed reference signal 806 based on the detected valid measurements of the frequency and / or cycle duration and / or phase of one or more valid reference signals of the input signal 308 .

[0165] Fig.11 A particularly simple version of the device 300 of the present invention is shown, in which a fixed frequency reference clock oscillator 1101 generates the reference clock 306 . DETAILED DESCRIPTION

[0166] Figure 1

[0167] Figure 1 The following prior art PAL color burst signal is shown: https: / / de.wikipedia.org / wiki / Phasenregelschleife#:~:text=Eine%20Phasenre gelschleife%20%28PLL%2C%20nach%20englisch%20phaselocked%20loop%29%20ist,von%20der%20Regelabweichung%20%E2%80%93%20der%20Phasenverschiebung%20%E2%80%93%20periodisch. Figure 1 This article refers to Figure 1 The content of the prior art cited in.

[0168] Figure 2

[0169] Figure 2 The LIN sync field is shown from https: / / www.eetimes.com / design-flexibility-key-to-simplifying-the-implementation-of-lin. Figure 2 This article refers to Figure 2 The content of the prior art cited in.

[0170] Figure 3

[0171] Figure 3 The basic structure of the device 300 of the present invention is shown in a schematic and simplified manner.

[0172] The input signal 308 at least intermittently includes a reference signal which is used as a synchronization signal for the high-frequency clock 303. Therefore, the reference signal is usually present in the input signal 308 only occasionally. Therefore, the input signal 308 usually includes the reference signal only occasionally. Therefore, the synchronization of the high-frequency clock 303 to the reference signal is not easy. Therefore, the basic idea of ​​the method of the present invention and the device of the present invention is to first obtain a continuous reference clock 306 from the sporadic reference signal through the second FLL and PLL control loop 324, and the frequency, cycle duration and phase of the reference clock are as consistent as possible with the frequency, cycle duration and phase of the reference signal of the input signal 308. Only in the second step, the first FLL and PLL control loop 323 is synchronized to the reference clock 306 and generates the high-frequency clock 303. Here, the first FLL or PLL control loop 323 is designed so that the frequency of the high-frequency clock 303 is numerically greater than the frequency of the reference clock 306 according to the first frequency division ratio, or so that the cycle duration of the high-frequency clock 303 is numerically smaller than the cycle duration of the reference clock 306 according to the first frequency division ratio. Therefore, the second FLL or PLL control loop 324 generates a low-frequency continuous reference clock 306 based on a low-frequency and only occasionally occurring reference signal of the input signal 308. Therefore, the first FLL or PLL control loop 323 generates a continuous high-frequency clock 303 based on the low-frequency continuous reference clock 306. Since the reference signal in the input signal 308 usually only appears occasionally, the second FLL or PLL control loop 324 is usually frozen when there is no reference signal in the input signal 308. If there is no reference signal in the input signal 308, the device component of the second FLL or PLL control loop 324 preferably notifies the controller 311 via the reference signal signaling 326 whether the reference signal is detected in the input signal 308. The controller 311 enables or disables the second FLL or PLL control loop 324 accordingly through the corresponding second enable / disable signal 325 according to the reference signal signal 326 and the other states in which the device components of the device 300 of the present invention are currently located, or enables or disables the first FLL or PLL control loop 323 accordingly through the corresponding first enable / disable signal 313 in a manner independent of the reference signal signal 326 and the other states in which the device components of the device 300 of the present invention are currently located. In this case, the disabled or frozen second control loop 324 should be understood as the disabled second FLL or PLL control loop 324 not changing the most recently regulated frequency, cycle duration and phase of the reference clock 306, that is, preferably keeping them constant.If the second FLL or PLL control loop 324 detects the presence of a reference signal in the input signal 308, or if the second FLL or PLL control loop 324 or the controller 311 determines the presence of a reference signal due to the time position relative to the start signal previously detected in the input signal 308, the controller 311 or the second FLL or PLL control loop 324 enables the control of the reference clock 306 by the second FLL or PLL control loop 324. Now, the second FLL or PLL control loop preferably uses the high frequency clock 303 as a time reference for measuring the reference signal in the input signal 308. It has been shown to be optimal that the control of the high frequency clock 303 by the first FLL and PLL control loop 323 is stopped during the activation of the control of the reference clock 306 by the second FLL or PLL control loop 324, and that the frequency, cycle duration and phase of the high frequency clock 303 remain constant and unchanged during the deactivation of the control of the high frequency clock 303 by the first FLL or PLL control loop 323. As soon as the second FLL or PLL control loop 324 determines that the frequency and / or cycle duration and / or phase of the reference clock 306 again corresponds to the most recently detected frequency and / or cycle duration and / or phase of the reference signal of the input signal 308, the controller 311 preferably freezes the second control loop 324 again and thus deactivates its control of the reference clock 306. As a result, the frequency, cycle duration and phase of the reference clock 306 are constant again. The controller 311 then enables the first FLL or PLL control loop 323 again, so that the first FLL or PLL control loop 323 again uses the new frequency and phase of the reference clock 306 to control the frequency, cycle duration and phase of the high-frequency clock 303. The device 300 of the present invention remains in this state until the next reference signal appears in the input signal 308.

[0173] If the reference signal appears too early or appears at an unexpected position, the controller 311 determines that an error exists. Typically, the device 300 of the present invention ignores the reference signal. If necessary, the device 300 of the present invention also interrupts (if possible) the ongoing re-regulation of the reference clock 306 to prevent a worse situation from occurring.

[0174] Depending on the progress of the re-regulation of the reference clock, the device 300 of the present invention waits to re-enable the first FLL or PLL regulation loop 323 as necessary until the second FLL or PLL regulation loop successfully re-regulates the reference clock 306 based on the subsequent new valid reference signal in the input signal 308. So far, the controller 311 of the device 300 of the present invention generally keeps the frequency, cycle duration and phase of the high-frequency clock 303 constant. Therefore, by evaluating the validity of the reference signal detected by the second FLL or PLL regulation loop 324 in the input signal 308, the device of the present invention can minimize the impact of the disturbed reference signal in the input signal 308 and maintain emergency operation.

[0175] This stability in turn allows the high frequency clock 303 to be used in the controllers and measurement devices of the first FLL or PLL control loop 323 and the second FLL or PLL control loop 324, and can be used to provide timing for the digital circuits of these device components of the device 300 of the present invention.

[0176] Figure 4

[0177] Figure 4 The process of the method according to the first variant of the invention is shown in a simplified and schematic manner.

[0178] In the normal state and normal operation 400 of the device 300 of the present invention, the first FLL or PLL control loop 323 is preferably enabled. This means that the first regulator I 501 is preferably enabled and the first FLL or PLL control loop 323 re-regulates the high frequency clock 303 according to the reference clock 306. In the normal state and normal operation 400 of the device 300 of the present invention, the second FLL or PLL control loop 324 is preferably disabled. This means that the second regulator II 504 is preferably disabled and the second FLL or PLL control loop 324 does not re-regulate the reference clock 306, but keeps it at the most recently regulated frequency of the reference clock 306 and / or the most recently regulated cycle duration of the reference clock 306 and / or the most recently regulated phase of the reference clock 306.

[0179] In the check state 401 , the device 300 of the invention repeatedly checks whether a reference signal in the form of a synchronization signal of the input signal 308 is detected, for example by device components of the device of the invention, in particular by device components of the second FLL or PLL control loop 324 .

[0180] If the device of the invention does not find that a reference signal has been detected in the input signal 308 , the device of the invention 300 typically returns to the normal state 400 of the device of the invention 300 again.

[0181] If the device 300 of the present invention detects something in the input signal 308 that may be a reference signal or detects something that may indicate a reference signal, the device 300 of the present invention typically switches to a state 402 of measuring a reference signal in the input signal 308 that is used as a synchronization signal. For example, the device 300 of the present invention may detect a start signal in the input signal that indicates a reference signal. If the time interval between the start signal and the synchronization signal that should be used as a reference signal for the reference clock 306 is known with sufficient accuracy, the device 300 of the present invention typically enters the state 402 of measuring a reference signal in the input signal 308 that is used as a synchronization signal only with a predetermined time delay.

[0182] Differently, the device 300 of the present invention can also track the signal waveform of the input signal 308, and draw a conclusion that a synchronization signal exists in the input signal 308 based on the characteristic signal waveform. In the state 402 of measuring the reference signal used as the synchronization signal in the input signal 308, the device 300 of the present invention and / or its device components (for example, the device components of the second control loop 324) generally preferably use the high-frequency clock 303 to detect one or more important parameters of the reference signal in the input signal 308. The values ​​of the parameters of the reference signal used as the synchronization signal in the input signal 308 determined by the device components of the device 300 of the present invention in the state 402 of measuring the synchronization signal of the input signal 308 preferably include at least one or more values ​​of one or more of the following parameters:

[0183] The number of cycles of the reference signal in the input signal 308 within a predetermined period of time, wherein the device 300 of the present invention preferably determines the predetermined period of time by counting a predetermined number of cycles of the high frequency clock 303 .

[0184] The frequency and / or cycle duration of a reference signal in the input signal 308, wherein the device 300 of the present invention preferably determines the cycle duration of the reference signal by counting the number of cycles of the high-frequency clock 303 during the duration of half a cycle or one cycle or a predetermined number of cycles of the reference signal in the input signal 308, and, if necessary, forms a reciprocal or performs a similar calculation to determine the frequency.

[0185] The phase of the reference signal in the input signal 308 compared to the reference clock 303, wherein the device 300 of the present invention preferably determines the phase of the reference signal by counting the number of cycles of the high-frequency clock 303 during a period starting from an edge of the reference signal in the input signal 308 and ending with a corresponding edge of the reference clock 306, using its controller 311 or counter.

[0186] ·The phase of the reference signal in the input signal 308 relative to the divided high-frequency clock 521, wherein the device 300 of the present invention preferably uses its controller 311 or counter to determine the phase of the reference signal by counting the number of cycles of the high-frequency clock 303 in a period starting from an edge of the reference signal in the input signal 308 and ending with a corresponding edge of the divided high-frequency clock 521.

[0187] ·The duration of a complete cycle of the reference signal in the input signal 308 (cycle duration), wherein the device 300 of the present invention preferably determines the duration of a complete cycle of the reference signal in the input signal 308 (cycle duration) by counting the number of cycles of the high-frequency clock 303 during the duration of a complete cycle of the reference signal in the input signal 308.

[0188] ·The duration of the low phase and / or high phase of a period of the reference signal in the input signal 308, wherein the device 300 of the present invention preferably determines the duration of the low phase and / or high phase of the period of the reference signal in the input signal 308 by counting the number of periods of the high-frequency clock 303 during the duration of the low phase and / or high phase of the period of the reference signal in the input signal 308.

[0189] ·The duration of a specific number of cycles of the reference signal in the input signal 308, wherein the device 300 of the present invention preferably determines the duration of the specific number of cycles of the reference signal in the input signal 308 by counting the number of cycles of the high-frequency clock 303 during the duration of the specific number of cycles of the reference signal in the input signal 308.

[0190] · Duration of a specific number of low phases and / or high phases of a reference signal in the input signal 308, wherein the device 300 of the present invention preferably determines the duration of the specific number of low phases and / or high phases of the reference signal in the input signal 308 by counting the number of cycles of the high-frequency clock 303 during the duration of the specific number of low phases and / or high phases of the reference signal in the input signal 308.

[0191] Preferably, in this state 402 of measuring the synchronization signal of the input signal 308, the device 300 of the present invention keeps the first FLL and PLL control loop 324 deactivated, so that the frequency and / or cycle duration and / or phase of the high-frequency clock 303 are constantly frozen. Therefore, the remaining device components of the device 300 of the present invention can use the high-frequency clock 303 as a time reference in this state 402, which is the basic idea according to the present invention.

[0192] After the device 300 according to the invention has processed the state 402 in which the synchronization signal of the input signal 308 is measured and all basic measurements have been performed, the device 300 preferably switches to the state 403 in which the synchronization signal of the input signal 308 is evaluated. The processing of this state 403 serves to prevent the supposed reference signal (which is neither a reference signal nor a disturbed reference signal) from possibly influencing and thus disturbing the reference clock 306 and thus the high-frequency clock 303. Very particularly preferably, the device 300 according to the invention or a device component of the device 300 according to the invention (e.g. the controller 311) checks the plausibility of the measured value of the reference signal of the input signal 308 determined in the previous state 402. For example, the reference signal in the input signal 308 should have a frequency and / or a period with a period duration that lies within the corresponding expected value intervals of these parameters, respectively.

[0193] Based on this evaluation in the previous state 403, the device 300 of the present invention or a corresponding sub-device of the device 300 of the present invention (e.g., the controller 311) determines in a decision process 404 whether the synchronization signal of the input signal 308 is valid and whether the synchronization signal of the input signal 308 and the parameters extracted therefrom are suitable for re-regulation of the reference clock 306. If this is not the case, the device 300 of the present invention preferably returns to the normal state, so that the reference clock 306 is not re-regulated, and the first FLL or PLL regulation loop 323 is enabled again when entering the normal state. In this case, since possibly erroneous parameters may generally cause the reference clock 306 and therefore the high-frequency clock 303 to be disturbed, the device 300 of the present invention or one of the sub-devices of the device 300 (e.g., its controller 311) preferably deactivates the second FLL or PLL regulation loop 324.

[0194] However, if the synchronization signal of the input signal 308 is valid and the synchronization signal of the input signal 308 and the parameters extracted therefrom are suitable for re-regulation of the reference clock 306, the device 300 of the present invention generally switches to a state 405 of calculating a target value of frequency and measuring the frequency of the reference clock 306 or calculating a target value of cycle duration and measuring the cycle duration of the reference clock 306 or calculating a target value of phase and measuring the phase of the reference clock 306. In the state 405 of calculating the target value of frequency, cycle duration and / or phase and measuring the frequency, cycle duration and / or phase of the reference clock 306, the device 300 of the present invention preferably detects one of the following parameters of the reference clock 306:

[0195] The number of cycles of the reference clock 306 within a predetermined period, wherein the device 300 of the present invention preferably determines the predetermined period by counting a predetermined number of cycles of the high frequency clock 303 .

[0196] The frequency and / or cycle duration of the reference clock 306, wherein the device 300 of the present invention preferably determines the cycle duration of the reference clock 306 by counting the number of cycles of the high-frequency clock 303 during the duration of half a cycle or one cycle or a predetermined number of cycles of the reference clock 306, and if necessary forms a reciprocal or performs a similar calculation to determine the frequency.

[0197] The phase of the reference clock 306 relative to the divided high-frequency clock 521, wherein the device 300 of the present invention preferably determines the phase of the reference clock 306 by counting the number of cycles of the high-frequency clock 303 within a period starting from an edge of the divided high-frequency clock 521 to an end of a corresponding edge of the reference clock 306 or from an edge of the reference clock 306 to an end of a corresponding edge of the divided high-frequency clock 521.

[0198] The phase of the reference clock 306 compared to the reference signal in the input signal 308, wherein the apparatus 300 of the present invention preferably determines the phase of the reference clock 306 by counting the number of cycles of the high-frequency clock 303 within a period starting from an edge of the reference signal in the input signal 308 to an end of a corresponding edge of the reference clock 306 or from an edge of the reference clock 306 to an end of a corresponding edge of the reference signal in the input signal 308.

[0199] The duration of a complete cycle of the reference clock 306 , wherein the inventive device 300 preferably determines the duration of a complete cycle of the reference clock 306 by counting the number of cycles of the high-frequency clock 303 during the duration of a complete cycle of the reference clock 306 .

[0200] · The duration of the low phase and / or the high phase of the cycle of the reference clock 306, wherein the device 300 of the present invention preferably determines the duration of the low phase and / or the high phase of the cycle of the reference clock 306 by counting the number of cycles of the high-frequency clock 303 during the duration of the low phase and / or the high phase of the cycle of the reference clock 306.

[0201] The duration of a specific number of cycles of the reference clock 306 , wherein the device 300 of the present invention preferably determines the duration of the specific number of cycles of the reference clock 306 by counting the number of cycles of the high-frequency clock 303 during the duration of the specific number of cycles of the reference clock 306 .

[0202] a duration of a specific number of low phases and / or high phases of the reference clock 306, wherein the device 300 of the present invention preferably determines the duration of the specific number of low phases and / or high phases of the reference clock 306 by counting the number of cycles of the high-frequency clock 303 during the duration of the specific number of low phases and / or high phases of the reference clock 306.

[0203] Thus, the device 300 according to the invention then has the measured value 317 of the reference signal in the input signal 308 and the measured value of the reference clock 306. The device 300 according to the invention then switches to a state 406 in which the frequency and / or the period duration and / or the phase of the reference clock 306 are corrected. Preferably, in this state 406, the device 300 according to the invention determines the deviation between the measured value 317 of the reference signal in the input signal 308 and the measured value of the reference clock 306. To this end, in this state 406, for example, the device 300 according to the invention preferably forms the difference between the measured value 317 of the reference signal in the input signal 308 and the measured value of the reference clock 306. It is also possible to form the difference in the reverse direction. Then, in this state 406 of the device 300 according to the invention, the device 300 according to the invention preferably corrects the reference clock 306 according to the determined deviation.

[0204] For example, the device 300 of the present invention can determine the deviation of the frequency and / or cycle duration and / or phase of the reference signal of the input signal 308 relative to the frequency and / or cycle duration and / or phase of the reference clock 306, and then correct the frequency or cycle duration or phase of the reference clock 306 according to the determined deviation. Preferably, the correction is proportional to the deviation. For example, if the trend of the trimming curve of the frequency or cycle duration or phase of the reference oscillator 305 that generates the reference clock 306 is known, the device 300 of the present invention can perform the correction of the frequency or cycle duration or phase of the reference clock 306 by means of a calculator directly taking into account the trimming curve or the trimming step size. Preferably, the device 300 of the present invention does not perform the correction of the frequency or cycle duration or phase of the reference clock 306 in one step but step by step. After each calibration, the device 300 of the present invention checks in a checking step 407 whether the value of the frequency, cycle duration or phase of the reference clock 306 is within an allowed frequency value interval around a frequency target value of the frequency of the reference clock 306, or within an allowed cycle duration value interval around a cycle duration target value of the cycle duration of the reference clock 306, or within an allowed phase value interval around a phase target value of the phase of the reference clock 306. The frequency target value usually corresponds to the frequency of the reference signal of the input signal 308 or a value derived therefrom. The cycle duration target value usually corresponds to the cycle duration of the reference signal of the input signal 308 or a value derived therefrom. The phase target value usually corresponds to the phase of the reference signal of the input signal 308 or a value derived therefrom. If the frequency of the reference clock 306 is not within the allowed frequency value interval around the frequency target value of the frequency of the reference clock 306, or if the cycle duration of the reference clock 306 is not within the allowed cycle duration value interval around the cycle duration target value of the cycle duration of the reference clock 306, or if the phase of the reference clock 306 is not within the allowed phase value interval around the phase target value of the phase of the reference clock 306, the device of the present invention repeats the state 406 of correcting the frequency, cycle duration or phase of the reference clock 306 and then checking and measuring the frequency, cycle duration or phase of the reference clock 306. However, if the frequency of the reference clock 306 is within the allowed frequency value interval around the frequency target value of the frequency of the reference clock 306, or if the cycle duration of the reference clock 306 is within the allowed cycle duration value interval around the cycle duration target value of the cycle duration of the reference clock 306, or if the phase of the reference clock 306 is within the allowed phase value interval around the phase target value of the phase of the reference clock 306, the device 300 of the present invention deactivates the second FLL or PLL control loop 324, and then preferably subsequently enables the first FLL or PLL control loop 323, so that the reference clock 306 is then frozen at a specific frequency, a specific cycle duration, and a specific phase, and the high-frequency clock 303 is regulated by the first FLL or PLL control loop according to the reference clock 306.The device 300 of the invention then preferably switches to the normal state 400 again.

[0205] Figure 5

[0206] Figure 5 The device of the invention is shown in a schematic and simplified manner.

[0207] This article uses Figure 3 The device is further explained.

[0208] Input signal 308 at least intermittently or occasionally includes a reference signal which serves as a synchronization signal for synchronizing high-frequency signal 303 of high-frequency oscillator 502 in terms of phase and / or cycle duration and / or frequency.

[0209] The device 300 of the present invention comprises a first FLL or PLL control loop 323 (502, 303, 520, 521, 519, 522, 501, 515, 502), which generates a high frequency clock 303 according to a low frequency reference clock 306. The device 300 of the present invention can operate the first FLL or PLL control loop 323 as a PLL (phase locked loop) or as a FLL (frequency locked loop).

[0210] The device 300 of the present invention includes a second FLL or PLL control loop 324 (505, 306, 507, 516, 518, 504, 514, 505) that generates a reference clock 306 based on a reference signal in the input signal 308. The device 300 of the present invention can operate the second FLL or PLL control loop as a PLL (phase locked loop) or as a FLL (frequency locked loop).

[0211] The device 300 of the present invention is provided with a high frequency oscillator 502 in the first FLL or PLL control loop 323 and a low frequency reference oscillator 505 in the second FLL or PLL control loop 324 .

[0212] In the first FLL or PLL control loop 323, the high frequency oscillator 502 generates a high frequency clock 303, the frequency of which depends on the value of the first control signal I 515 of the first controller I 501. Therefore, the first controller I 501 controls the high frequency oscillator 502 through the first control signal I 515. The first controller I 501 is preferably a PI controller or a PID controller, etc. Therefore, the first controller I 501 preferably controls the frequency and / or cycle duration and / or phase of the high frequency clock 303 of the high frequency oscillator 502 through the first control signal I 515. The first clock divider 520 divides the high frequency clock 303 of the high frequency oscillator 502 into a divided high frequency clock 521 according to a first frequency division ratio (which may also be 1). Therefore, the frequency of the divided high frequency clock 521 is usually lower than the frequency of the high frequency clock 303 of the high frequency oscillator 502. Therefore, the cycle duration of the divided high frequency clock 521 is usually greater than the cycle duration of the high frequency clock 303 of the high frequency oscillator 502. The frequency division ratio may also be a non-integer. However, a non-integer frequency division ratio is not preferred. In a steady state, the frequency of the divided high-frequency clock 521 preferably substantially corresponds to the frequency of the reference clock 306. In a steady state, the cycle duration of the divided high-frequency clock 521 preferably substantially corresponds to the cycle duration of the reference clock 306. The phase detector 519 of the first control loop compares the frequency and / or cycle duration and / or phase of the reference clock 306 with the frequency or cycle duration or phase of the divided high-frequency clock 521, and forms a high-frequency clock frequency measurement value signal 522 of the phase detector 519 of the first control loop based on the result of the comparison. The first regulator I 501 uses the value of the high-frequency clock frequency measurement value signal 522 of the phase detector 519 of the first control loop as the measurement value of the high-frequency clock 303 to form the first control signal I515 of the first regulator I 501 based on the measurement value. The first regulator 1501 controls the high frequency oscillator 502 by using the first control signal 1515 of the first regulator 1501, and controls the frequency and / or cycle duration and / or phase of the high frequency clock 303 of the high frequency oscillator 502 in this way, for example. The value of the high frequency clock frequency measurement value signal 522 of the phase detector 519 may be the difference between the frequency of the reference clock 306 and the frequency of the divided high frequency clock 521. The value of the high frequency clock frequency measurement value signal 522 of the phase detector 519 may be the difference between the cycle duration of the reference clock 306 and the cycle duration of the divided high frequency clock 521. The value of the high frequency clock frequency measurement value signal 522 of the phase detector 519 may be the difference between the phase shift of the reference clock 306 and the corresponding phase shift of the divided high frequency clock 521. It may also be the difference of the number of cycles of the reference clock 306 measured by the phase detector 519 of the first control loop in a period in which the divided high frequency clock 521 has a predetermined first number of cycles minus the first number of cycles.It may also be a difference value obtained by subtracting the first number of cycles of the divided high-frequency clock 521 from the number of cycles measured by the phase detector 519 of the first control loop in a period in which the reference clock 306 has a predetermined first number of cycles. Based on the value of the high-frequency clock frequency measurement value signal 522 of the phase detector 519 and / or a signal related thereto or a signal derived therefrom, the first controller 1501 generates a first control signal 1515 of the first controller 1501, and the first controller 1501 uses the first control signal 1515 to control the high-frequency oscillator 502, and for example, controls the frequency and / or cycle duration and / or phase of the high-frequency clock 303 of the high-frequency oscillator 502. In the normal state 400, the first FLL or PLL control loop 323 is enabled and maintains the high-frequency clock 303 of the high-frequency oscillator 502 at a constant frequency and / or cycle duration and / or a constant phase if necessary, so that the frequency and cycle duration of the high-frequency clock 303 are constant and only depend on the frequency or cycle duration or phase of the reference clock 306.

[0213] The reference measuring device 507 of the second FLL or PLL control loop 324 measures the frequency and / or cycle duration of the low-frequency reference clock 306 of the reference oscillator 505, and determines a reference clock frequency measurement value signal 516 of the reference measuring device 507. Preferably, the reference measuring device 507 of the second FLL or PLL control loop 324 measures the frequency and / or cycle duration of the low-frequency reference clock 306 of the reference oscillator 505, and determines the reference clock frequency measurement value signal 516 of the reference measuring device 507 by using the high-frequency clock 303. Preferably, the reference measuring device 507 of the second FLL or PLL control loop 324 is a counter that counts the cycles of the high-frequency clock 303 according to the reference clock 306 as a start / stop signal for counting. The target value calculator 510 for the measured value of the low-frequency reference clock 306 (in the form of the reference clock frequency measured value signal 516) compares the measured value of the frequency and / or the period duration of the low-frequency reference clock 306 (in the form of the reference clock frequency measured value signal 516) with the effective value 517 of the parameter of the frequency or period duration or phase of one or more sporadically occurring reference signals of the input signal 308 provided by the measuring device 509 for measuring the input signal 308 and determines the deviation. Very particularly preferably, the measuring device 509 detects the respective period duration of one or more reference signals in the input signal 308 and the reference measuring device 507 detects the period duration of the reference clock 306, since these measurements only require the measuring device 509 designed as a counter of the high-frequency clock 303 and the reference measuring device 507 designed as a counter of the high-frequency clock 303. In this case, the measuring device 509 preferably has a counter which counts the periods of the high-frequency clock 303 as a function of the reference signal of the input signal 308 as a start / stop signal.

[0214] Preferably, the measuring device 509 has one or more first measured value memories in which the measuring device 509 temporarily stores the measured values ​​of the frequency and / or the period duration and / or the phase of the reference signal of the input signal 308 after the measuring device 509 detects them and before the measuring device 509 transmits them to the target value calculator 510. The purpose of this is that these measured values ​​will continue to be available even if the reference signal is not present in the input signal 308. The target value calculator 510 is used to compare the measured values ​​of the low-frequency reference clock 306 with the corresponding valid measured values ​​of the reference signal in the input signal 508. Preferably, the measuring device 509 evaluates these detected measured values ​​of the frequency and / or the period duration and / or the phase of the reference signal of the input signal 308 stored in the one or more first measured value memories.

[0215] If the reference signal has ended (ie the input signal 308 no longer has a reference signal), the measuring device 509 and / or the controller 311 may evaluate whether the reference signal detected by the measuring device 509 is actually a reference signal. This is the problem to be solved by the present invention.

[0216] Preferably, the detected frequency value of the reference signal in the second memory of the measuring device 509, for example, should be within the allowed frequency value interval. The measuring device 509 preferably checks this requirement. Preferably, the detected cycle duration value of the reference signal in the second memory of the measuring device 509, for example, should be within the allowed cycle duration value interval. The measuring device 509 preferably checks this requirement. Preferably, the detected phase value of the reference signal in the second memory of the measuring device 509, for example, should be within the allowed phase value interval. The measuring device 509 preferably checks this requirement. If necessary, the controller 311 can take over this task instead of the measuring device 509. In this regard, the controller 311 itself can also be used and regarded as part of the measuring device 509 in this sense, and if necessary, it can also be used and regarded as part of other device components of the device 300 of the present invention. If this is the case in each case, the measuring device 509 is more likely to detect the original reference signal. Therefore, the measuring device 509 then uses these values ​​that may be derived from the original reference signal to regulate the second FLL or PLL regulation loop 324, because the measured values ​​of the measuring device meet one or more of these conditions. On the contrary, if one or more of these conditions are not met, the measuring device 509 can determine that the detected measurement value is not derived from the original reference signal. The measuring device 509 preferably no longer uses the detected measurement value identified as a possible non-original reference signal. Preferably, the measuring device 509 only transmits the measurement value that is evaluated as the most likely original reference signal or the value derived by the measuring device 509 from the input signal 308 that is evaluated as the most likely one or more original reference signals as the effective measurement value 517 to the target value calculator 510. Target value calculator 510 Deviation signal 518 of the target value calculator 510, which corresponds to the deviation of the effective measurement value 517 of the measurement value of the low-frequency reference clock 306 relative to the frequency or other suitable parameters (e.g., cycle duration and / or phase) of one or more effective reference signals of the input signal 308. The deviation signal 518 from the target value calculator 510 of the measuring device 509 informs the second controller II 504 of the effective value of the deviation between the measured values ​​of the frequency and / or the cycle duration and / or the phase of the reference clock frequency measurement value signal 516 or the reference clock cycle duration measurement value signal 516 or the reference clock phase measurement value signal 516 and the effective measured values ​​517 of the frequency or the cycle duration or the phase of one or more effective reference signals of the input signal 308. Based on these effective measured values, the second controller II 504 generates a second control signal II 514 of the second controller II 504, with which the freezable controller II 504 controls the reference oscillator 505 with an adjustable frequency, and for example controls the frequency and / or the phase of the reference clock 306 of the reference oscillator 505 with an adjustable frequency.Preferably, the measuring device 509 temporarily stores these valid measurement values ​​in one or more memories until the measuring device 509 detects a new valid measurement value of the subsequent reference signal of the input signal 308 again. Before the measuring device 509 detects a new valid measurement value of the subsequent reference signal of the input signal 308 again, the measuring device 509 preferably outputs the measurement values ​​stored in the one or more second memories as, for example, valid measurement values ​​517 of the frequency or cycle duration or phase of one or more valid reference signals of the input signal 308 to the target value calculator 510, which generates a deviation signal 518 of the target value calculator 510, which corresponds to the deviation of the measurement value of the low-frequency reference clock 306 relative to the valid measurement value 517 of the frequency or other suitable parameters (e.g., cycle duration and / or phase) of one or more valid reference signals of the input signal 308.

[0217] Therefore, in Figure 5 In the exemplary case of Figure 5The second FLL or PLL control loop 324 of the embodiment represents an FLL with a frequency control loop, wherein the target value calculator 510 determines the frequency deviation in the form of the value of the deviation signal 518. For the measured value of the low-frequency reference clock 306 (in the form of the reference clock frequency measurement value signal 516), the target value calculator 510 can also compare the phase measurement value of the low-frequency reference clock 306 (in the form of the reference clock phase measurement value signal 516) with the phase effective measurement value 517 of one or more occasionally occurring effective reference signals of the input signal 308 provided by the measuring device 509 for measuring the input signal 308, and determine the deviation. Preferably, the target value calculator 510 transmits the deviation to the second controller II 504 of the second FLL or PLL control loop 324 using the deviation signal 518 of the target value calculator 510. Preferably, the deviation signal 518 informs the second controller II 504 of the second FLL or PLL control loop 324 of the deviation value between the reference clock frequency measurement value of the reference clock frequency measurement value signal 516 and the effective measurement value 517 of, for example, the frequency or cycle duration or phase of one or more effective reference signals of the input signal 308, or the deviation value between the reference clock phase measurement value of the reference clock frequency measurement value signal 516 and the effective measurement value 517 of, for example, the frequency or cycle duration or phase of one or more effective reference signals of the input signal 308, or a value derived therefrom or a value related thereto. The second controller II 504 of the second FLL or PLL control loop 324 generates a second control signal II 514 of the second controller II 504 of the second FLL or PLL control loop 324, and the second controller II 504 of the second FLL or PLL control loop 324 controls the reference oscillator 505 with an adjustable frequency or an adjustable cycle duration or an adjustable phase using the second control signal II 514. Therefore, the second controller II 504 of the second FLL or PLL control loop 324 controls, for example, the frequency and / or the cycle duration and / or the phase of the reference clock 306 of the reference oscillator 505 according to the value received by it via the deviation signal 518. Therefore, the frequency and / or the cycle duration and / or the phase of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324 preferably depends on the value received by it via the deviation signal 518. Therefore, the frequency and / or the cycle duration and / or the phase of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324 preferably depends on the deviation transmitted by the target value calculator 510 to the second controller II 504 of the second FLL or PLL control loop 324 via the deviation signal 518.

[0218] The basic idea of ​​the invention is that the controller 311 of the device 300 of the invention freezes the second regulator II 504 of the reference oscillator 505 of the second FLL or PLL control loop 324 for generating the reference clock 306 during normal operation 400. Therefore, the second regulator II 504 of the reference oscillator 505 is deactivated in normal operation 400. Therefore, in this normal operating state 400, the frequency, cycle duration and phase of the high-frequency clock 303 depend only on the frozen frequency, cycle duration and phase of the reference clock 306.

[0219] Preferably, the controller 311 monitors the input signal 308 by measuring the input signal 308 using the measuring device 509 of the second FLL or PLL control loop 324. As long as the measuring device 509 for measuring the input signal 308 does not report to the controller 311 that a synchronization signal as a reference signal in the input signal 308 is detected in the state 401, the device 300 of the present invention preferably remains in the normal state 400. In this normal state 400, the second regulator II 504 of the second FLL or PLL control loop 324 is frozen and is therefore deactivated, while the first regulator I 501 of the first FLL or PLL control loop 323 is enabled and therefore readjusts the frequency and the cycle duration and, if necessary, the phase of the high-frequency clock 303 of the high-frequency oscillator 502 according to the frequency and the cycle duration and, if necessary, the phase of the reference clock 306 of the reference oscillator 505. Therefore, the frequency, cycle duration and phase of reference clock 306 of reference oscillator 505 and thus of high-frequency clock 303 of high-frequency oscillator 502 are fixedly set in this normal state.

[0220] However, once the measuring device 509 for measuring the input signal 308 reports to the controller 311 that the synchronization signal as an occasional reference signal in the input signal 308 is detected in the state 401, the device 300 of the present invention preferably usually leaves the normal state 400 under the instruction of the controller 311 and switches to the state 402 of measuring the detected synchronization signal in the input signal 308. In this state 402, the device 300 of the present invention measures the reference signal as a synchronization signal of the input signal 308 through the measuring device 509 for measuring the input signal 308, and the reference signal appears as the content of the input signal 308. During the duration of measuring the reference signal in the input signal 308, the controller 311 of the device 300 of the present invention usually continues to keep the control of the frequency and cycle duration and, if necessary, the phase of the reference clock 306 generated by the second FLL or PLL control loop 323 disabled, and preferably continues to freeze the frequency, cycle duration and phase of the reference clock 306. Therefore, the controller 311 of the device 300 of the present invention preferably continues to keep the frequency, cycle duration and phase of the reference clock 306 constant in this state 402. During the deactivation of the second regulator II 504, the controller 311 can then correct the reference oscillator 505 and therefore the reference clock 306 as described below, which correction depends on the deviation between the detection parameters of the detected reference signal in the input signal 308 and the corresponding parameters of the reference clock 306 (for example, the corresponding frequency or cycle duration or phase).

[0221] As described above, the reference measuring device 507 for measuring the frequency and / or cycle duration of the low-frequency reference clock 306 detects the reference clock frequency of the reference clock 306. Preferably, the reference measuring device 507 is a counting circuit, which detects, for example, the number of cycles of the high-frequency clock 303 within the duration of the second predetermined number of cycles of the reference clock 306, or the number of cycles of the reference clock 306 within the period corresponding to the second predetermined number of cycles of the high-frequency clock 303. If necessary, the reference measuring device 507 forms the inverse of the counting result. Therefore, here, the high-frequency clock 303 preferably forms a time reference for measuring the reference signal and the reference clock 306 in the input signal 308. If the high-frequency clock 303 is relatively constant, the reference measuring device 507 can therefore determine the value of the reference clock 306 that depends on the average frequency or the average cycle duration of the high-frequency clock 303. Then, in this state 402 of measuring the synchronization signal of the input signal 308, the controller 311 of the device 300 of the present invention uses the high-frequency oscillator 502 and the high-frequency clock 303 generated thereby as a reference.

[0222] Therefore, in the state 402 of measuring the synchronization signal of the input signal 308, the second FLL or PLL control loop 324 with the second controller II 504 is frozen, and the frequency, cycle duration and phase of the reference clock 306 of the reference oscillator 505 are frozen. Figure 5 In a variation of the embodiment, in the state 402 of the synchronization signal of the measuring input signal 308, the first FLL or PLL control loop 323 having the first regulator I 501 is enabled, and the first FLL or PLL control loop 323 controls the high-frequency oscillator 502 according to the reference clock 306 and thus controls the frequency, cycle duration and phase of the high-frequency clock 303.

[0223] After the state 402 of measuring the synchronization signal of the input signal 308 and thus obtaining the deviation 518 from the target value calculator 510 after the measurement state 402, in order to achieve the desired target accuracy, the device 300 of the present invention can enter the state 403 of evaluating the synchronization signal of the input signal 308, and determine whether the synchronization signal of the input signal 308 is valid in the state 404. Preferably, the controller 311 determines whether the synchronization signal of the input signal 308 is valid in the state 404 based on the data received by the controller 311 from other device components of the device 300 of the present invention, but preferably from the target value calculator 510.

[0224] Therefore, in the state 402 of evaluating the synchronization signal of the input signal 308 and during the state 404 of determining whether the synchronization signal of the input signal 308 is valid, the second FLL or PLL control loop 324 with the second regulator II 504 preferably continues to be frozen, and the frequency, cycle duration and phase of the reference clock 306 of the reference oscillator 505 preferably continue to be frozen. Therefore, in the state 402 of evaluating the synchronization signal of the input signal 308 and during the state 404 of determining whether the synchronization signal of the input signal 308 is valid, the first FLL or PLL control loop 323 with the first regulator I 501 preferably continues to be enabled, and the first FLL or PLL control loop 323 preferably continues to regulate the frequency, cycle duration and phase of the high-frequency oscillator 502 and therefore the high-frequency clock 303 according to the reference clock 306.

[0225] If the synchronization signal of the input signal 308 is invalid, the device 300 of the present invention preferably switches back to the normal state 400. If the synchronization signal of the input signal 308 is invalid, the controller 311 preferably causes the device 300 of the present invention to preferably switch back to the normal state 400.

[0226] However, if the synchronization signal of the input signal 308 is valid, the device 300 of the present invention preferably switches to the state 405 of calculating the target value of the frequency and / or the cycle duration and / or the phase of the reference clock 506. In the state 405 of calculating the target value of the frequency and / or the cycle duration and / or the phase of the reference clock 506, the measuring device 509 for measuring the input signal 308 preferably detects the relevant parameters of the valid synchronization signal of the input signal 308. If necessary, the device 300 of the present invention can also use the parameters that the measuring device 509 for measuring the input signal 308 has determined in one of the previous states or in the previous measurement and / or in the synchronization process (400 to 407). Preferably, the values ​​of these parameters are present in the memory of the device 300 of the present invention, for example, in the memory of the controller 311, after the device 300 of the present invention and / or the controller 311 have determined the values ​​of these parameters and then temporarily stored these parameter values. Preferably, the measuring device 509 for measuring the input signal 308 determines valid measured values ​​517 of the frequency and / or period duration and / or phase of one or more synchronization signals of the input signal 308 which occur occasionally as valid reference signals.

[0227] In the state 405 of measuring the frequency and / or cycle duration and / or phase of the reference clock 306 and calculating the target value of the frequency and / or cycle duration and / or phase of the reference clock 306, the reference measuring device 507 detects the value of the frequency and / or cycle duration and / or phase of the low-frequency reference clock 306 and generates a reference clock frequency measurement value signal 516 of the reference measuring device 507 as a measured value of the low-frequency reference clock 306 according to the value. The target value calculator 510 uses this value of the reference clock frequency measurement value signal 516 to determine the deviation. To this end, the target value calculator 510 now compares the measured value of the low-frequency reference clock 306 (in the form of the value of the reference clock frequency measurement value signal 516) with the valid measured value 517 of the frequency or cycle duration or phase of one or more occasionally occurring reference signals of the input signal 308 provided by the measuring device 509. To this end, the measuring device 509 transmits the valid measured value 517 of the frequency or cycle duration or phase of one or more occasionally occurring valid reference signals of the input signal 308 to the target value calculator 510 via the relevant measured value signal 517. Preferably, the target value calculator 510 determines the deviation between the effective measurement value of the measurement value signal 517 and the value of the reference clock frequency measurement value signal 516. The technical revelation of this article particularly emphasizes that even if the reference signal of the input signal 308 no longer exists in the input signal 308, the measuring device 509 preferably maintains the effective measurement value (the measurement value is based on the measurement of the reference signal) of the measurement value signal 517 of the frequency or period duration or phase of one or more occasionally occurring effective reference signals of the input signal 308 and maintains it constant. Preferably, when the device of the present invention is again in state 402 and when a new measurement value of the frequency or cycle duration or phase of a previously unconsidered reference signal of the input signal 308 is successfully evaluated as a new valid measurement value in states 403 and 404, the measuring device 509 then replaces the valid measurement value 517 of the frequency or cycle duration or phase of one or more occasionally occurring valid reference signals of the input signal 308 with only this new measurement value of the frequency or cycle duration or phase of one or more occasionally occurring valid reference signals of the input signal 308, which new measurement value is based on the previously unconsidered new measurement value of the previously unconsidered new reference signal of the input signal 308. In this case, the device 300 of the present invention evaluates the obtained new measurement value of the frequency or cycle duration or phase of one or more occasionally occurring valid reference signals of the input signal 308 as the new valid measurement value 517 of the frequency or cycle duration or phase of one or more occasionally occurring valid reference signals of the input signal 308, which the device 300 of the present invention forms under consideration of the detected measurement value of the previously unconsidered reference signal of the input signal 308. This makes the attenuation correction and tracking of the reference clock 306 independent of the duration of the reference signal in the input signal 308 .Therefore, the target value calculator 510 can compare the most recent valid reference clock phase measurement of the low-frequency reference clock 306 (in the form of a reference clock phase measurement signal 516) with a valid measurement 517 of the frequency or period duration or phase of one or more occasionally occurring valid reference signals of the input signal 308 and determine the deviation therebetween.

[0228] In the state 405 of calculating the target value of the frequency or cycle duration or phase, the second FLL or PLL control loop 324 having the second regulator II 504 preferably continues to be frozen, and the frequency, cycle duration and phase of the reference clock 306 of the reference oscillator 505 preferably continue to be frozen. Therefore, in the state 405 of calculating the target value of the frequency or cycle duration or phase, the first FLL or PLL control loop 323 having the first regulator I 501 preferably continues to be enabled, and the first FLL or PLL control loop 323 preferably continues to regulate the frequency or cycle duration or phase of the high-frequency oscillator 502 and thus the high-frequency clock 303 according to the reference clock 306.

[0229] Preferably, under the instruction of the controller 311, the device 300 of the present invention switches from the state 405 of calculating the target value of the frequency, cycle duration or phase of the reference clock 306 to the state 406 of correcting the frequency, cycle duration or phase of the reference clock 306 of the reference oscillator 505.

[0230] In the state 406 for correcting the frequency or cycle duration or phase of the reference clock 306 of the reference oscillator 505, the second FLL or PLL control loop 324 with the second controller II 504 is now preferably enabled in order to perform the correction according to the value of the deviation signal 518 of the target value calculator 510 or based on this value. The deviation signal 518 of the target value calculator 510 generally informs the value of the deviation between the reference clock frequency measurement value signal 516 of the reference measuring device 507 and the measurement value signal 517 of the frequency or cycle duration or phase of one or more valid reference signals of the input signal 308, or a value proportional to the deviation, or a value dependent on the deviation, or a value derived from the deviation, or a value related to the deviation. In the case of phase-related regulation of the reference clock 306, the deviation signal 518 of the target value calculator 510 generally informs the value of the deviation between the reference clock phase measurement value signal 516 of the reference measurement device 507 and the valid measurement value of the phase measurement value signal 517 of one or more valid reference signals of the input signal 308, or a value proportional to the deviation, or a value dependent on the deviation, or a value derived from the deviation, or a value related to the deviation. Regulation using other parameters such as cycle duration length, time length of high phase, time length of low phase, duration of a predetermined number of cycles, etc. can also be performed in a similar manner and are considered disclosed and claimed here.

[0231] Now, the frequency, cycle duration and phase of the reference clock 306 of the reference oscillator 505 are no longer frozen. In the case of frequency regulation, the second regulator II 504 now corrects the frequency of the reference oscillator 505 until the reference clock frequency measurement value signal 516 of the reference measuring device 507 as the measurement value of the low-frequency reference clock 306 coincides with the valid measurement value 517 of the frequency of one or more reference signals of the input signal 308 provided by the measuring device 509 within predetermined limits. In the case of cycle duration regulation, the second regulator II 504 now corrects the cycle duration of the reference oscillator 505 until the reference clock cycle duration measurement value signal 516 of the reference measuring device 507 as the measurement value of the low-frequency reference clock 306 coincides with the valid measurement value 517 of the cycle duration of one or more reference signals of the input signal 308 provided by the measuring device 509 within predetermined limits. In the case of phase regulation, the second regulator II 504 now corrects the phase of the reference oscillator 505 until the reference clock phase measurement value signal 516 of the reference measuring device 507 as the measurement value of the low-frequency reference clock 306 is consistent with the effective measurement value 517 of the phase of one or more reference signals of the input signal 308 provided by the measuring device 509 within predetermined limits. Since these two signals are usually quantized digital signals, it is necessary that they can also be required to be completely consistent here. Therefore, in the state 406 of correcting the frequency or cycle duration or phase of the reference clock 306 of the reference oscillator 505, the high-frequency oscillator 502 now operates as an "alternative reference oscillator" for synchronizing the reference oscillator 505. Therefore, preferably, as long as the digital device components and the controller 311 of the second FLL or PLL control loop 324 need a clock, the high-frequency clock 303 provides them with a clock as a system clock.

[0232] Since the reference oscillator 505 and therefore the reference clock 306 are no longer a reliable time reference before correction, the controller 311 freezes the first FLL or PLL control loop 323 and thus deactivates the first FLL or PLL control loop 323 before enabling the second FLL or PLL control loop 324. Therefore, in the state 406 in which the frequency or cycle duration or phase of the reference clock 306 of the reference oscillator 505 is corrected, the second FLL or PLL control loop 324 with the second regulator II 504 is now preferably enabled, and the second FLL or PLL control loop 324 also continues to regulate the reference oscillator 505 and therefore the frequency, cycle duration and phase of the reference clock 306 according to the synchronization signal in the input signal 308. In state 406 for correcting the frequency or cycle duration or phase of the reference clock 306 of the reference oscillator 505, the first FLL or PLL control loop 323 having the first regulator I 501 is now preferably frozen, and the frequency, cycle duration and phase of the high-frequency clock 303 of the high-frequency oscillator 502 are preferably frozen.

[0233] Therefore, the core idea of ​​the technical teaching of this article is that the reference oscillator 505 and the high frequency oscillator 502 briefly exchange roles during the duration of the synchronization signal that synchronizes the reference oscillator 505 with the input signal 308.

[0234] This has the advantageous effect that the correction of the frequency or the cycle duration or the phase of the high-frequency clock 303 of the high-frequency oscillator 201 takes place in a single correction step.

[0235] The device 300 of the invention that performs the method of the invention is particularly suitable for devices that communicate with the outside world, for example, via a data bus and must have a high-precision high-frequency clock 303, for example, as a system clock of the device 300 of the invention, so as to always scan the data on the data bus at the center of the eye of the data transmitted via the data bus (for example, a LIN data bus). In the proposal herein, in the application of the device 300 of the invention, a reference signal of a special synchronization data field external to the device 300 of the invention, for example, as a transmission of the LIN data bus (which is a synchronization signal as part of the input signal 308) is occasionally available, and the device 300 of the invention can use this special synchronization data field as a reference signal of the input signal 308 during the execution of the method of the invention, so as to synchronize the reference oscillator 505, and then also synchronize the high-frequency oscillator 502 on this basis. In the case of a single-wire data bus such as a LIN data bus, the input signal 308 is preferably a data bus line or a signal obtained directly from the data bus signal. However, the data bus can also be, for example, a unidirectional or bidirectional differential data bus with two data lines. Exemplary representatives of such a data bus are a CAN data bus, a CAN-FD data bus, a LVDS data bus or an ISLED data bus, etc. Therefore, the input signal 308 may also be a differential data signal between two or more data lines.

[0236] Therefore, in a method for generating a high-frequency clock 303 of a high-frequency oscillator 502 of the above type, this object is achieved according to the invention by the following steps:

[0237] Generate the reference clock 306 by means of a controllable low-frequency reference oscillator 505 , wherein the reference oscillator 505 is part of the second FLL or PLL control loop 324 and generates the reference clock 306 ;

[0238] The high frequency clock 303 is generated by an adjustable high frequency oscillator 502, wherein the adjustable high frequency oscillator 502 is part of a first FLL or PLL control loop 323, and wherein the frequency of the high frequency clock 303 is numerically greater than the frequency of a reference clock 306 of a reference oscillator 505, and wherein the period duration of the high frequency clock 303 is numerically less than the period duration of the reference clock 306 of the reference oscillator 505, and wherein the first FLL or PLL control loop 323 uses the reference clock 306 of a second FLL or PLL control loop 324 as a target value for the first FLL or PLL control loop 323 in a state 400 of normal operation;

[0239] Detecting the onset of a reference signal (in the form of a synchronization signal) of the external input signal 308, preferably by means of a measuring device 509 for measuring the input signal 308 in a first step;

[0240] If necessary, preferably at the time of or shortly after the external input signal, but at least in states 406 and 407, preferably by the controller 311 of the device 300 of the present invention, freeze and thus deactivate the first FLL or PLL control loop 324 including the high-frequency oscillator 502, so that the high-frequency clock 303 does not change its frequency and cycle duration and / or phase during the duration that the second FLL or PLL control loop 324 re-controls the reference clock 306. Depending on the variant of the design of the device of the present invention or the implementation of the method of the present invention, the step of freezing the first FLL or PLL control loop 324 can also be omitted in this process.

[0241] The reference signal in the input signal 308 is detected, preferably by means of a measuring device 509 for measuring the input signal 308 , and in a second step various parameters are determined, preferably by means of the measuring device 509 for measuring the input signal 308 .

[0242] Preferably, the device 300 of the present invention uses the high-frequency clock 303 to measure the reference signal in the input signal 308. Here, if necessary, the device 300 of the present invention can also measure multiple parameters simultaneously, so that the device 300 can, for example, better evaluate the signal quality and validity of the reference signal later. Here, these determined parameters of the reference signal of the input signal 308 include at least one or more of the following parameters:

[0243] a. a first number of cycles of the reference signal of the input signal 308 within a time interval that depends on a second number of cycles of the high frequency clock 303 of the high frequency oscillator 502, and / or

[0244] b. The frequency of the reference signal of the input signal 308, and / or

[0245] c. the duration of a complete cycle of the reference signal of the input signal 308 (cycle duration), which is measured in particular in the form of the number of cycles of the high-frequency clock 303 of the high-frequency oscillator 502, and / or

[0246] d. the phase of the reference signal of the input signal 308 relative to the reference clock 306, which is measured in particular as the number of cycles of the high-frequency clock 303 of the high-frequency oscillator 502 in the period starting from an edge of the reference signal of the input signal 308 and ending with a corresponding edge of the reference clock 306 or starting from an edge of the reference clock 306 and ending with a corresponding edge of the reference signal of the input signal 308, and / or

[0247] e. the phase of the reference signal of the input signal 308 relative to the divided high-frequency clock 521, which is measured in particular in the form of the number of cycles of the high-frequency clock 303 of the high-frequency oscillator 502 in the time period starting from an edge of the reference signal of the input signal 308 and ending with a corresponding edge of the divided high-frequency clock 521 or starting from an edge of the divided high-frequency clock 521 and ending with a corresponding edge of the reference signal of the input signal 308, and / or

[0248] f. the duration of the low phase and / or high phase of a period of the reference signal of the input signal 308, which is measured in particular in the form of the number of periods of the high-frequency clock 303 of the high-frequency oscillator 502, and / or

[0249] g. the duration of a certain number of periods of the reference signal of the input signal 308, which is measured in particular in the form of a number of periods of the high-frequency clock 303 of the high-frequency oscillator 502, and / or

[0250] the duration of a certain number of low phases and / or high phases of a reference signal of the input signal 308 , which is measured in particular in the form of a number of periods of the high-frequency clock 303 of the high-frequency oscillator 502 ;

[0251] The reference signal of the input signal 308 detected as a synchronization signal in this way and / or the parameters of the reference signal of the input signal 308 detected as a synchronization signal in this way are evaluated by the controller 311 of the device 300 of the present invention or another sub-device, and the controller 311 of the device 300 of the present invention or another sub-device determines whether the reference signal of the input signal 308 is a valid reference signal. This step of the method performed by the device 300 of the present invention is usually performed after the device 300 of the present invention completes the measurement of the reference signal of the input signal 308. Here, the device 300 of the present invention can, for example, evaluate whether the reference signal of the input signal 308 has a specific number of cycles within a predetermined period of time, and therefore whether it is a valid (i.e., effective) reference signal. In addition, taking into account the generally existing knowledge of the basic accuracy of the high-frequency clock 303 of the high-frequency oscillator 302, the device 300 of the present invention can evaluate whether the frequency or period duration or phase of the reference signal of the input signal 308 is within the expected and allowed value range based on the duration of the measurement. Furthermore, the device 300 of the present invention may use the durations of the low and high phases it measures to assess the input signal quality, for example to determine whether a reference signal of the input signal 308 is severely interfered with, or whether the signal quality is sufficient;

[0252] If the detection parameters and the detection measurement values ​​of the reference signal of the input signal 308 are not within one or more of these predetermined expected value intervals and therefore the reference signal of the input signal 308 is invalid (i.e., failed), the detection reference signal and / or the detection parameters of the input signal 308 are discarded by the controller 311 of the device 300 of the present invention or another sub-device of the device 300 of the present invention, and a possible freezing of the first FLL or PLL control loop 324 including the high-frequency oscillator 502 is terminated, and in a fourth step, the device 300 of the present invention is returned to the normal state 400;

[0253] If the detection parameters and the detection measured values ​​of the reference signal of the input signal 308 are within the predetermined expected value interval and the input signal is therefore valid (i.e., effective), then in a fourth step, the high-frequency clock 303 of the high-frequency oscillator 502 is preferably kept at a fixed frequency and cycle duration and phase by the controller 311 or another sub-device of the device 300 of the present invention, and the first FLL or PLL control loop 324 is kept deactivated, wherein this step can also be performed directly before the reference clock 306 is corrected;

[0254] In a fourth step, the frequency and / or cycle duration and / or phase of the reference clock 306 of the low-frequency reference oscillator 505 is detected, and the deviation of the determined frequency and / or cycle duration and / or phase of the reference signal of the input signal 308 from the detected frequency and / or cycle duration and / or phase of the reference clock 306 of the low-frequency reference oscillator 505 and / or the deviation of the determined parameter of the reference signal of the input signal 308 from the corresponding value of the corresponding parameter of the reference clock 306 of the low-frequency reference oscillator 505 is determined. For this fourth step, the apparatus of the invention must know the frequency or cycle duration of the reference signal of the input signal 308. However, this does not necessarily limit the method to a single valid frequency interval of the frequency of the reference signal of the input signal 308 or a single valid cycle duration interval of the cycle duration of the reference signal of the input signal 308. A plurality of different, previously known, allowed frequency intervals or cycle duration intervals (e.g. defined by the baud rate) are conceivable. These different, previously known, allowed frequency intervals or cycle duration intervals must only be distinguishable within the range of the basic accuracy of the frequency or cycle duration of the high-frequency clock 303 of the high-frequency oscillator 502 of the device 300 of the present invention, i.e., they need to be spaced relative to each other within the frequency range or cycle duration range and must not overlap. For example, in the absence of an external reference signal of the input signal 308, if the frequency or cycle duration of the high-frequency clock 303 of the high-frequency oscillator 502 of the device of the present invention has a basic accuracy of ±5%, this results in a very fine granularity of distinguishable possible reference signals of the input signal 308 that can be used as a reference signal by the device 300 of the present invention. In this step, the device 300 of the present invention determines the deviation of the frequency and / or cycle duration and / or phase of the reference signal of the input signal 308 from the frequency and / or cycle duration and / or phase of the reference clock 306 of the low-frequency reference oscillator 505. Preferably, the device 300 of the present invention can use the high frequency clock 303 of the high frequency oscillator 502 to measure the duration of a specific number of cycles of the reference clock 306 of the reference oscillator 505, for example by counting the cycles of the high frequency clock 303 during the period.

[0255] In a fourth step, the frequency and / or the period duration and / or the phase of the reference clock 306 of the low-frequency reference oscillator 505 is corrected for the specific deviation and / or a value related to or dependent on the deviation by enabling the second FLL or PLL control loop 324 including the reference oscillator 505. Thus, the device 300 of the invention now corrects the frequency and / or the period duration and / or the phase of the reference clock 306 of the low-frequency reference oscillator 505 for the previously determined deviation or a value derived therefrom. For example, if the course of the trimming curve of the frequency or the period duration or the phase of the reference oscillator 505 is known, the frequency and / or the period duration and / or the phase of the reference clock 306 can be corrected directly by calculation, for example by the controller 311, taking into account the trimming curve or the trimming step size;

[0256] in a fifth step, determining a sufficient correction of the frequency and / or cycle duration and / or phase of the reference clock 306 of the low-frequency reference oscillator 505 by means of a reference measuring device 507 for measuring the frequency or cycle duration or phase of the low-frequency reference clock 306 and a target value calculator 510 for the measured value of the low-frequency reference clock 306, deactivating the second FLL or PLL control loop 324 by means of the controller 311 of the device 300 of the present invention or another sub-device of the device 300 of the present invention, and finally re-enabling the first FLL or PLL control loop 324 to complete the correction; and

[0257] In this fifth step, in the normal state 400 , the frequency and / or the cycle duration and / or the phase of the high-frequency clock 303 of the high-frequency oscillator 502 are corrected and regulated by the first FLL or PLL control loop 324 .

[0258] The advantage of the method proposed herein is that, for example, in the case of data communication via a LIN data bus, the frequency, cycle duration and phase of the high-frequency clock 303 can be made to correspond to a target frequency or a target cycle duration or a target phase with very good target accuracy after a single LIN synchronization field as a synchronization signal of the input signal 308 of the data communication via the LIN data bus. It is particularly useful to use the high-frequency clock 303 as a system clock of a computer system that evaluates data from the input signal 308 (preferably a data bus signal), for example, of a controller 311 of the device 300 of the present invention, other digital parts or data from the input signal 308 (preferably a data bus signal). For this purpose, the device 300 of the present invention does not require a high-precision reference signal that frequently recurs in the input signal 308. A reference signal that rarely occurs is sufficient for the device 300 of the present invention. Instead of a complete synchronization field, a previously known single signal or previously known data content with a duration that is known to the device 300 of the present invention can also be used.

[0259] For example, the method can also be combined with known automatic baud rate determination for serial communications such as LIN. It should be noted here that the fourth step requires a certain time to be completed. Depending on the specific design, this time may be longer than the duration between, for example, the end of the LIN synchronization field as a reference signal and the start of the actual data transmission in the LIN data frame. If this is expected, at least the fifth step and, if necessary, the fourth step will not be executed immediately after the end of the synchronization field (i.e., the reference signal), but the start of the execution of these steps will be delayed until the end of the communication (here, the LIN data communication). Even if there is a deviation in the high-frequency clock 303, the communication itself can be protected by the automatic baud rate generation. After the end of the communication, there is still enough time to execute the fourth and fifth steps (states 405, 406 and 407).

[0260] If during the execution of the fourth and fifth steps (states 405, 406 and 407) a new synchronization field (i.e. a new reference signal in the input signal 308) unexpectedly comes as the start of a new data transmission, the method can jump back to the first step (normal state 400) from one of these steps at any time. The communication itself is then protected again by the known automatic baud rate detection. In this special case, the high-frequency clock 303 gradually approaches the desired target accuracy of the high-frequency clock 303.

[0261] The system of the device 300 of the present invention may include means (e.g., 310, 311) for recognizing the completion of the fifth step (states 406 and 407). The recognition of the completion of the fifth step (states 406 and 407) by the means (e.g., 310, 311) for recognizing the completion of the fifth step (states 406 and 407) preferably notifies the superior system that the target accuracy of the high-frequency clock 303 of the high-frequency oscillator 502 has been achieved.

[0262] This embodiment requires a low-frequency reference oscillator 505 for generating a low-frequency reference clock 306 and a high-frequency adjustable oscillator 502 for generating a high-frequency clock 303. Here, the low-frequency reference oscillator 505 is used as a reference for generating the high-frequency clock 303, for example in the form of the first FLL or PLL control loop 323 (FLL: frequency locked loop; PLL: phase locked loop). Without an additional high-precision external reference signal of the input signal 308, this already has a certain basic accuracy g1, which should be improved according to the invention by an external reference signal of the input signal 308. The order of the method for improving the accuracy, which is preferably performed by the device 300 of the invention, is generally the order described above.

[0263] Alternatively, in the case of a non-regulatory reference oscillator 701, the device of the invention can correct the frequency division ratio of the control loop according to the determined deviation. However, for this purpose, a correspondingly fine-tunable frequency division ratio is required. For example, this frequency division ratio can be generated by using a non-integer frequency divider in the device of the invention.

[0264] The method can also switch to "fine calibration mode" after completing step 5 and reaching the target accuracy. The fine calibration mode is different from the above sequence in that:

[0265] In the fourth step (states 406 and 407 ), the correction is performed only for a certain number of trimming steps or is limited thereto, in particular to one fine-tuning step.

[0266] The stopping of the first FLL or PLL control loop 322 (states 402 to 407) in the first step and the limiting of the frequency change or cycle duration change or phase change in the fourth step can be omitted due to the previously completed transient process of the second FLL or PLL control loop 324. Then, the fifth step becomes a part of the fourth step.

[0267] The task of the fine correction mode is to correct only frequency changes and / or period duration changes and / or phase changes which occur, for example, due to temperature dependencies or aging during operation.

[0268] The method can also be extended to store the determined values ​​for the frequency correction or cycle duration correction or phase correction of the second FLL or PLL control loop 324 in the non-volatile memory of the device 300 and / or its controller 311 after the fifth step or when the device 300 of the present invention is turned off. This has the advantage that the device 300 of the present invention can then immediately start with a higher basic accuracy of the reference clock 306 at the next startup.

[0269] However, the core of the invention is the sequence of the first to fifth steps listed above, which allows the target accuracy of the high-frequency clock 303 to be reached already after the presence of an accurate reference signal once in the input signal 308 .

[0270] Figure 6

[0271] Figure 6 Corresponds to Figure 4 , but the difference lies in the different activation of the first FLL or PLL control loop 323. Figure 4 In the example, the first FLL or PLL control loop 323 is enabled in states 402, 403, 404, 405, while in this example, the first FLL or PLL control loop 323 is disabled in states 402, 403, 404, 405. Figure 4In the states 402, 403, 404, 405 of detecting, evaluating and processing the value of the reference signal in the input signal 308, the high-frequency clock 303 is regulated and therefore not constant, while in Figure 6 In the states 402, 403, 404, 405 of detecting, evaluating and processing the value of the reference signal in the input signal 308, the high-frequency clock 303 is not regulated and is therefore constant. Therefore, the measured values ​​detected at different times using the high-frequency clock 303 can be used for comparison.

[0272] Figure 7

[0273] Figure 7 To a large extent corresponds to Figure 5 In this regard, this paper refers to Figure 5 . Figure 5 compared to, Figure 5 The reference oscillator 505 is Figure 7 504 is divided into an adjustable second clock divider 701 and an unadjustable reference oscillator 701. The unadjustable reference oscillator 701 provides a reference pre-clock 703 that is fixedly set in a constructive manner or fixedly set in other ways. The adjustable second clock divider 702 divides the reference pre-clock 703 into a reference clock 306 according to a second division ratio. Preferably, the second regulator II 504 provides a clock divider signal 714 of the second regulator II 504 instead of the second control signal II 514 of the second regulator II 504. Preferably, the second division ratio of the second clock divider 702 depends on the value of the clock divider signal 714 of the second regulator II 504. Therefore, the second regulator II 504 can adjust the frequency and / or cycle duration and / or phase of the reference clock 306 generated by the second clock divider 702 through the clock divider signal 714.

[0274] Figure 8

[0275] Figure 8 To a large extent corresponds to Figure 5 In this regard, this paper refers to Figure 5 . Figure 5 In comparison, the reconstruction oscillator 810 and the second phase detector 819 or the second frequency difference detector 819 or the second period duration difference detector 819 replace Figure 5 The reference measuring device 507 and Figure 5 In particular, when the reference variable of the second FLL or PLL control loop 324 is the phase of the reference clock 306, the phase detector 819 is used instead of Figure 5In particular, when the reference variable of the second FLL or PLL control loop 324 is the frequency of the reference clock 306, the frequency difference detector 819 is used instead of Figure 5 In particular, when the reference variable of the second FLL or PLL control loop 324 is the cycle duration of the reference clock 306, the cycle duration difference detector 819 is used instead of Figure 5 The target value calculator 510 in .

[0276] The reconstruction oscillator 810 reconstructs the reference signal which only occurs occasionally in the input signal 308, so that the reconstructed reference signal 806 is used continuously and not only occasionally as a target value signal for regulating the reference clock 306 for the device 300 of the present invention, in particular for the second FLL or PLL control loop 324. Therefore, the reconstruction oscillator 810 generates the reconstructed reference signal 806 from the reference signal of the input signal 308 according to the valid measured values ​​517 of the frequency and / or cycle duration and / or phase of one or more occasionally occurring reference signals of the input signal 308 detected by the measuring device 509. Here, if the measuring device 509 detects the valid measured values ​​517 of the frequency and / or cycle duration and / or phase of one or more occasionally occurring reference signals of the input signal 308, the frequency and / or cycle duration and / or phase of the reconstructed reference signal 806 preferably respectively corresponds to the corresponding measured values ​​of the detected valid measured values ​​517 of the frequency and / or cycle duration and / or phase of one or more occasionally occurring reference signals of the input signal 308. For example, the reconstruction oscillator 810 may be implemented as a clock divider that divides the high-frequency clock 303 into the reconstruction clock 806. In this case, preferably, the division ratio used by the reconstruction oscillator 810 when dividing the high-frequency clock 303 into the reconstruction clock 806 depends on one or more of these detected valid measurement values ​​517 of the frequency and / or cycle duration and / or phase of one or more occasionally occurring reference signals of the input signal 308.

[0277] Preferably, the measuring device 509 comprises one or more first measured value memories, in which the measuring device 509 temporarily stores the measured values ​​of the frequency and / or cycle duration and / or phase of the reference signal of the input signal 308 after the measurement device 509 detects them and before they are transmitted to the reconstruction oscillator 810 by the measuring device 509. The purpose of this is that these detection measured values ​​will continue to be available even if the reference signal that only appears occasionally and usually for a short time is no longer present on the input signal 308. Preferably, the measuring device 509 evaluates these detection measured values, which are preferably measured values ​​of the frequency and / or cycle duration and / or phase of the reference signal of the input signal 308 and are then usually located in one or more first measured value memories. For example, the value of the detection frequency of the reference signal then located in the first memory of the measuring device 509 should preferably be within the allowed frequency value interval. The measuring device 509 preferably checks this requirement. For example, the value of the detection cycle duration of the reference signal then located in the first memory of the measuring device 509 should preferably be within the allowed cycle duration value interval. The measuring device 509 preferably checks this requirement. For example, the value of the detected phase of the reference signal then located in the first memory of the measuring device 509 should preferably be located within the allowed phase value interval. The measuring device 509 preferably checks this requirement. If necessary, the controller 311 can perform this task instead of the measuring device 509. In this regard, the controller 311 itself can also be part of the measuring device 509 in this sense, and if necessary, it can also be used as and regarded as a device component of other device components of the device 300 of the present invention. If the inspection of these requirements shows that the detection measurement value meets these requirements in each case, the measuring device 509 is more likely to detect the original reference signal in the input signal 308. Since the measurement values ​​of the measuring device 509 meet one or more of the above conditions, the measuring device 509 then uses these measurement values ​​that are likely to be derived from the original reference signal to regulate the second FLL or PLL regulation loop 324. Then, these measurement values ​​are effective measurement values ​​517. Then, when multiple measurement values ​​of different reference signals are used to form effective measurement values ​​517, the measuring device can also use these measurement values ​​to form such effective measurement values ​​517. On the contrary, if one or more of the above conditions are not met, the measuring device 509 may determine that the detected measurement value is not derived from the original reference signal. The measuring device 509 preferably no longer uses the detected measurement value identified as a possible non-original reference signal, but discards the measurement value. Preferably, the device 300 of the present invention then increases the error counter by a first error counter increment, which is preferably a positive integer greater than 0. In the case where the reference signal is identified as a possible non-original reference signal, the device 300 of the present invention decreases the error counter by a second error counter increment, which is preferably a positive integer greater than 0.The first error counter increment may be equal to the second error counter increment. If the counter reading of the error counter exceeds a predetermined error counter reading threshold, the device 300 of the present invention may, for example, notify the information to the superior system via a data bus, or keep the information for the superior system to read via the data bus. Preferably, in the case where the reference signal is identified as a possible non-original reference signal, the controller 311 increases the error counter in the memory or register of the controller 311 and / or the device 300 of the present invention by a first error counter increment, and the first error counter increment is preferably a positive integer greater than 0. In the case where the reference signal is identified as a possible original reference signal, the controller 311 reduces the error counter in the memory or register of the controller 311 and / or the device 300 of the present invention by a second error counter increment, and the second error counter increment is preferably a positive integer greater than 0. The first error counter increment may be equal to the second error counter increment. If the counter reading of the error counter exceeds a predetermined error counter reading threshold, the device 300 of the present invention and / or the controller 311 may, for example, notify the information to the superior system via a data bus, or keep the information for the superior system to read via the data bus. If the measured values ​​in the first memory of the measuring device 509 meet the above conditions, the measuring device 509 regards these measured values ​​as valid measured values, and stores these measured values ​​in the first memory of the measuring device 509 as valid measured values ​​of the frequency and / or cycle duration and / or phase of the reference signal in the input signal 308, for example, in the second memory of the measuring device 509, and overwrites the measured values ​​that may already exist here. After the system of the device 300 of the present invention is started, the valid starting value is preferably present in the second memory of the measuring device 509, and the valid starting value ensures that the system of the device 300 of the present invention is started with a possible reasonable starting value. Preferably, the measuring device 509 only transmits the valid measured values ​​of the reference signal that is evaluated as the most likely to be the original and located in its second memory as the valid measured values ​​517 of the frequency or cycle duration or phase of one or more occasionally occurring valid reference signals of the input signal 308 to the reconstruction oscillator 810, and the reconstruction oscillator 810 generates the reconstruction reference signal 806 from the high-frequency clock 303 according to these transmitted valid measured values. Preferably, the measuring device 509 temporarily stores these valid measurement values ​​in the one or more second memories until the measuring device 509 detects new valid measurement values ​​of the subsequent, newly occurring reference signal of the input signal 308 again and evaluates them as valid. Before the measuring device 509 detects new valid measurement values ​​of the subsequent reference signal of the input signal 308 again, the measuring device 509 preferably continuously outputs the measurement values ​​stored in the one or more second memories as valid measurement values ​​to the reconstruction oscillator 810.Thus, as described above, valid measurements stored in the one or more second memories preferably influence the generation of the reconstructed reference signal 806 by the reconstruction oscillator 810 .

[0278] The second phase detector 819 or the second frequency difference detector 819 or the second cycle duration difference detector 819 generates the deviation signal 818 according to the difference between the frequency value or the cycle duration value or the phase value of the reconstructed reference signal 806 and the corresponding value of the frequency or the cycle duration or the phase of the reference clock 306. Preferably, the value of the deviation signal 818 represents a) the phase difference value between the phase of the reconstructed reference signal 806 and the phase of the reference clock 306, and / or b) the frequency difference value between the frequency of the reconstructed reference signal 806 and the frequency of the reference clock 306, and / or c) the cycle duration value between the cycle duration of the reconstructed reference signal 806 and the cycle duration of the reference clock 306, and / or values ​​derived from these values ​​that can realize similar or analogous functions in the second FLL-PLL control loop 324. For example, the value of the deviation signal 818 may represent a value proportional to: a) a phase difference between the phase of the reconstructed reference signal 806 and the phase of the reference clock 306, and / or b) a frequency difference between the frequency of the reconstructed reference signal 806 and the frequency of the reference clock 306, and / or c) a cycle duration difference between the cycle duration of the reconstructed reference signal 806 and the cycle duration of the reference clock 306. Figure 8In the example of , the second controller II 504 of the second FLL or PLL control loop 324 also generates a second control signal II 514 of the second controller II 504 of the second FLL or PLL control loop 324. The second controller II 504 of the second FLL or PLL control loop 324 uses the second control signal II 514 to control the reference oscillator 505 with an adjustable frequency or an adjustable cycle duration or an adjustable phase. Therefore, the second controller II 504 of the second FLL or PLL control loop 324 controls the frequency and / or cycle duration and / or phase of the reference clock 306 of the reference oscillator 505 according to the reconstructed reference signal 806, for example. Therefore, the value of the frequency and / or cycle duration and / or phase of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324 preferably depends on the corresponding value of the frequency and / or cycle duration and / or phase of the reconstructed reference signal 806. Very particularly preferably, the FLL or PLL control loop 324 controls the phase. Therefore, very particularly preferably, the phase detector 819 detects the phase difference (phase difference) between these signals 806 and 306. Therefore, the frequency and / or the period duration and / or the phase of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324 preferably depends on a deviation value of the corresponding values ​​of the reconstructed reference signal 806 and the reference clock 306, which the second phase detector 819 or the second frequency difference detector 819 or the second period duration difference detector 819 determines and notifies the second controller II 504 of the deviation value via a deviation signal 818. Therefore, the deviation signal 818 of the phase detector 818 or the frequency difference detector 819 or the period duration difference detector 819 for reconstructing the deviation of the frequency or the period duration or the phase between the reference signal 806 and the reference clock 306 controls the reference oscillator 505 and thus the frequency and / or the period duration and / or the phase of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324. Therefore, in Figure 8In the example of the invention, the second FLL or PLL control loop 324 includes a reconstruction oscillator 810, which continues to generate the occasional reference signal in the input signal 308 while maintaining the most important parameters of the one or more valid reference signals that have recently appeared, at least when the reference signal in the input signal 308 is not available or is no longer available, so that the time reference of similar parameters of the device 300 of the present invention is also available during these times. For example, these most important parameters can be the values ​​of frequency, cycle duration and phase. To this end, the reconstruction oscillator 810 preferably generates a preferably continuous reconstruction reference signal 806 based on the effective measurement values ​​517 of the frequency or cycle duration or phase of one or more occasional valid reference signals of the input signal 308 detected by the measuring device 509, and the reconstruction reference signal 806 substantially corresponds to the continuous continuation of the occurring reference signal in time. Therefore, the parameter values ​​of the reconstruction reference signal 806 preferably substantially correspond to the effective measurement values ​​of the parameters 517 of the one or more occasional valid reference signals of the input signal 308. Therefore, the reconstruction oscillator 810 preferably generates the reconstructed reference signal 806 from the high-frequency clock 303 according to the effective measured values ​​of the parameters 517 of one or more effective reference signals of the input signal 308 detected by the measuring device 509. For example, the reconstruction oscillator 810 can be another frequency divider, which divides the high-frequency clock into the reconstructed reference signal 806 according to the effective measured values ​​of the parameters 517 of one or more effective reference signals that occasionally appear in the input signal 308 detected by the measuring device 509, so that the reconstructed reference signal 806 has the most important effective parameters of the effective reference signals that occasionally appear in the input signal 308. For example, these most important parameters can also be the values ​​of frequency, cycle duration and phase. Therefore, the reconstruction oscillator 810 preferably has the additional clock divider. Preferably, the additional clock divider generates the reconstructed reference signal 806 from the high-frequency clock 303 by clock dividing the high-frequency clock 303 according to the frequency division ratio using the clock divider with the relevant frequency division ratio. As described above, the frequency division ratio preferably depends on the effective measured values ​​of the parameters 517 of one or more effective reference signals of the input signal 308 detected by the measuring device 509 and / or the most important parameters derived therefrom. In particular, the frequency division ratio can be proportional or inversely proportional to the values ​​of these effective parameters, or can be, for example, the time integral of these values ​​or their inverse or other values ​​derived from these effective parameters. For example, the effective parameters can be the values ​​of frequency, cycle duration and phase, respectively.

[0279] Preferably, the second FLL or PLL control loop 324 has a second phase detector 819 and / or a second frequency difference detector 819 and / or a second cycle duration difference detector 819. Thus, the device 300 of the present invention can determine the deviation between the frequency or cycle duration or phase of the reference clock 306 and the frequency or cycle duration or phase of the reconstructed reference signal 806. In this sense, Figure 8 The second FLL or PLL control loop 324 is particularly preferably a real PLL (phase locked loop) with a phase detector 819. The second phase detector 819 compares the reconstructed reference signal 806 with the reference clock 306, and / or the second frequency difference detector 819 compares the reconstructed reference signal 806 with the reference clock 306, and / or the second cycle duration difference detector 819 compares the reconstructed reference signal 806 with the reference clock 306. The second phase detector 819 generates a deviation signal of the phase detector 819 for reconstructing the phase deviation between the reference signal 806 and the reference clock 306 according to the result of the comparison. Alternatively, the second frequency difference detector 819 generates a deviation signal of the frequency difference detector 819 for reconstructing the frequency deviation between the reference signal 806 and the reference clock 306 according to the result of the comparison. Alternatively, the second cycle duration difference detector 819 generates a deviation signal of the cycle duration difference detector 819 for reconstructing the cycle duration deviation between the reference signal 806 and the reference clock 306 according to the result of the comparison.

[0280] The controller 311 preferably deactivates the first FLL or PLL control loop 323 during the measurement, evaluation and reconstruction of the reference signal of the input signal 308 by the reference oscillator 810. Therefore, the high-frequency clock 303 is generally substantially constant in frequency and / or cycle duration and / or phase during the measurement, evaluation and reconstruction of the reference signal of the input signal 308 by the measuring device 509. The second FLL or PLL control loop 324 re-regulates the phase of the reference clock 306 until the values ​​of the parameters (frequency, cycle duration, phase) of the reference clock 306 are consistent with the corresponding valid measured values ​​of the parameters 517 of one or more reference signals of the input signal 308, except for the regulation error.

[0281] Fig. 9

[0282] Fig. 9 To a large extent corresponds to Figure 5 In this regard, this paper refers to Figure 5 In Figure 5 In the example, the second FLL or PLL control loop 324 uses the target value calculator 510. Figure 5In the example, the target value calculator 510 calculates the value of the deviation signal 518 and transmits the deviation value to the second controller II 504 of the second FLL or PLL control loop 324 through the deviation signal 518. Figure 5 In the figure, the value of the deviation signal 518 of the target value calculator 510 generally represents the deviation value between the measured value of the frequency and / or cycle duration and / or phase of the reference clock frequency measurement value signal 516 or the reference clock cycle duration measurement value signal 516 or the reference clock phase measurement value signal 516 and the valid measured value 517 of the frequency or cycle duration or phase of one or more of the most recent valid reference signals in the input signal 308.

[0283] Alternatively, Fig. 9 The device 300 of the present invention in the embodiment comprises a comparator 910. Preferably, the comparator 910 determines the deviation between the measured value of the frequency and / or the cycle duration and / or the phase of the reference clock frequency measurement value signal 516 or the reference clock cycle duration measurement value signal 516 or the reference clock phase measurement value signal 516 and the valid measured value 517 of the frequency or the cycle duration or the phase of one or more of the most recent valid reference signals in the input signal 308, and forms a comparison result in the form of a comparison result signal 918. To this end, the comparator 910 preferably determines the difference between the measured value of the frequency and / or the cycle duration and / or the phase of the reference clock frequency measurement value signal 516 or the reference clock cycle duration measurement value signal 516 or the reference clock phase measurement value signal 516 and the respectively corresponding valid measured value 517 of the frequency or the cycle duration or the phase of one or more of the most recent valid reference signals in the input signal 308. Preferably, the comparator 910 forms the comparison result signal 918 according to the difference. Typically, the value of the comparison result signal 918 is proportional to the difference. If necessary, the value of the comparison result signal 918 can be equal to the difference. The frequency correction oscillator 920 generates the frequency correction reference signal 906 using the high frequency clock 303. Preferably, the frequency correction reference signal 906 is continuous and does not appear only occasionally in the input signal 308 like the reference signal. Preferably, the parameter value of the frequency correction reference signal 906 corresponds to the corresponding valid measured value of the parameter 517 of one or more of the most recent valid reference signals in the input signal 308. Therefore, the frequency correction reference signal 918 is obviously more suitable for regulation than the reference signal of the input signal 308. As shown in Figure 8 in Fig. 9 In the example of , the second FLL or PLL control loop 324 also includes a second phase detector 819 or a second frequency difference detector 819 or a second cycle duration difference detector 819. Fig. 9 In the case of , if the reference variable of the second FLL or PLL control loop 324 is the phase of the reference clock 306 relative to the frequency correction reference signal 906, the second phase difference detector 819 is particularly preferably used here. Fig. 9 In the case of , if the reference variable of the second FLL or PLL control loop 324 is the frequency of the reference clock 306, then the second frequency difference detector 819 is particularly preferably used here. Fig. 9 In the case where the reference variable of the second FLL or PLL control loop 324 is the period duration of the reference clock 306 , the second period duration difference detector 819 is particularly preferably used here.

[0284] The frequency correction oscillator 920 reconstructs the reference signal that only occurs occasionally in the input signal 308 based on the comparison result 918 and thus generates the frequency correction reference signal 906, so that the frequency correction reference signal 906 is continuously and not just occasionally available for the device 300 of the present invention, in particular for the second FLL or PLL control loop 324, as a target value signal for regulating the reference clock 306. Therefore, the frequency correction oscillator 920 generates this frequency correction reference signal 906 from one or more valid reference signals of the input signal 308 based on the valid measured values ​​517 of the frequency and / or period duration and / or phase of one or more occasionally occurring valid reference signals of the input signal 308 detected by the measuring device 509. Here, if the measuring device 509 detects valid measured values ​​517 of the frequency and / or cycle duration and / or phase of one or more occasionally occurring valid reference signals of the input signal 308, the frequency and / or cycle duration and / or phase of the frequency correction reference signal 906 preferably corresponds to the corresponding valid measured values ​​of the detected valid measured values ​​517 of the frequency and / or cycle duration and / or phase of one or more occasionally occurring valid reference signals of the input signal 308. For example, the frequency correction oscillator 920 can be implemented as a clock divider, which divides the high-frequency clock 303 into the frequency correction reference signal 906. In this case, the division ratio used by the frequency correction oscillator 920 when dividing the high-frequency clock 303 into the frequency correction reference signal 906 preferably depends on one or more of these detected valid measured values ​​517 of the frequency and / or cycle duration and / or phase of one or more valid reference signals of the input signal 308.

[0285] Preferably, the measuring device 509 comprises one or more first measured value memories, in which the measuring device 509 temporarily stores the measured values ​​of the frequency and / or cycle duration and / or phase of the reference signal of the input signal 308 after they have been detected by the measuring device 509 and before they are transmitted to the comparator 910 by the measuring device 509. The purpose of this is that these detected measured values ​​will continue to be available even if the reference signal, which only occurs occasionally and usually for a short time, is no longer present on the input signal 308. Preferably, the measuring device 509 evaluates these detected measured values, which are preferably measured values ​​of the frequency and / or cycle duration and / or phase of the reference signal of the input signal 308 and are then usually located in one or more first measured value memories of the measuring device 509. For example, the value of the detected frequency of the reference signal then located in the first memory of the measuring device 509 should preferably be within the allowed frequency value interval. The measuring device 509 preferably checks this requirement. For example, the value of the detected cycle duration of the reference signal then located in the first memory of the measuring device 509 should preferably be within the allowed cycle duration value interval. The measuring device 509 preferably checks this requirement. For example, the value of the detected phase of the reference signal then located in the first memory of the measuring device 509 should preferably be located within the allowed phase value interval. The measuring device 509 preferably checks this requirement. If necessary, the controller 311 can perform this task instead of the measuring device 509. In this respect, the controller 311 itself can also be part of the measuring device 509 in this sense, and if necessary, can also be used and regarded as a device component of other device components of the device 300 of the present invention. If the check of these requirements shows that the detected effective values ​​517 of the parameters of one or more reference signals of the input signal 308 meet these requirements in each case, then the measuring device 509 is more likely to detect the original reference signal in the input signal 308. Since the measured values ​​of the measuring device 509 meet one or more of the above conditions, the measuring device 509 then uses these measured values ​​that are likely to be derived from the original reference signal or the values ​​derived therefrom as the effective measured values ​​517 for regulating the second FLL or PLL control loop 324. On the contrary, if one or more of the above conditions are not met, the measuring device 509 can determine that the detected measured values ​​are not derived from the original reference signal. The measuring device 509 preferably no longer uses the detected measurement value of the reference signal that is identified as possibly not being the original reference signal, but discards the measurement value. Preferably, the device 300 of the present invention then increases the error counter by a first error counter increment, which is preferably a positive integer greater than 0. In the case where the reference signal is identified as possibly being the original reference signal, the device 300 of the present invention decreases the error counter by a second error counter increment, which is preferably a positive integer greater than 0. The first error counter increment may be equal to the second error counter increment.If the counter reading of the error counter exceeds a predetermined error counter reading threshold, the device 300 of the present invention may, for example, notify the superior system of the information via a data bus, or keep the information for the superior system to read via the data bus. If the count reading of the error counter is lower than another predetermined error counter reading threshold that may be the same or different, the device 300 of the present invention may also, for example, notify the superior system of the other information via a data bus, or keep the other information for the superior system to read via the data bus. Preferably, in the case where the reference signal is identified as possibly not being the original reference signal, the controller 311 increases the error counter in the memory or register of the controller 311 and / or the device 300 of the present invention by a first error counter increment, and the first error counter increment is preferably a positive integer greater than 0. In the case where the reference signal is identified as possibly being the original reference signal, the controller 311 reduces the error counter in the memory or register of the controller 311 and / or the device 300 of the present invention by a second error counter increment, and the second error counter increment is preferably a positive integer greater than 0. The first error counter increment may be equal to the second error counter increment. If the counter reading of the error counter exceeds a predetermined error counter reading threshold, the device 300 of the present invention and / or the controller 311 can, for example, notify the information to the superior system via the data bus, or keep the information for the superior system to read via the data bus. If the count reading of the error counter is lower than another predetermined error counter reading threshold that may be the same or different, the device 300 of the present invention can also, for example, notify the superior system of the other information via the data bus, or keep the other information for the superior system to read via the data bus. If the measured values ​​in the first memory of the measuring device 509 meet the above conditions, the measuring device 509 regards these measured values ​​as valid measured values, and stores these measured values ​​in the second memory of the measuring device 509 as valid measured values ​​of the frequency and / or cycle duration and / or phase of one or more valid reference signals in the input signal 308, and overwrites the measured values ​​that may already exist here. After the system of the device 300 of the present invention is started, the valid starting value as the valid measured value is preferably present in the second memory of the measuring device 509, which ensures that the system of the device 300 of the present invention is started with a possible reasonable starting value. Preferably, the measuring device 509 transmits only one or more measured values ​​which are evaluated as being most likely to be the original reference signal as valid measured values ​​517 to the comparator 910, wherein the measured values ​​are located in a second memory of the measuring device 509. When high-frequency clock 303 is used as necessary, the comparator 910 determines the difference between the valid measured values ​​of one or more reference signals of the input signal 308 and the corresponding measured values ​​of the reference clock frequency measured value signal 516 or the reference clock period duration measured value signal 516 or the reference clock phase measured value signal 516 of the reference clock 306.Preferably, the measuring device 509 temporarily stores these valid measured values ​​in the one or more second memories until the measuring device 509 detects new valid measured values ​​of a subsequent, newly occurring reference signal of the input signal 308 again and evaluates them as valid. Before the measuring device 509 detects new valid measured values ​​of a subsequent reference signal of the input signal 308 again, the measuring device 509 preferably continues to output the measured values ​​stored in the one or more second memories as valid measured values ​​to the comparator 910, preferably continuously. Therefore, as described above, the valid measured values ​​stored in the one or more second memories preferably influence the generation of the frequency-corrected reference signal 906 by the frequency-corrected oscillator 920.

[0286] The second phase detector 819 or the second frequency difference detector 819 or the second cycle duration difference detector 819 generates the deviation signal 818 according to the difference between the frequency value or the cycle duration value or the phase value of the frequency correction reference signal 906 and the corresponding value of the frequency or the cycle duration or the phase of the reference clock 306. Preferably, the value of the deviation signal 818 represents a) the phase difference value between the phase of the frequency correction reference signal 906 and the phase of the reference clock 306, and / or b) the frequency difference value between the frequency of the frequency correction reference signal 906 and the frequency of the reference clock 306, and / or c) the cycle duration value between the cycle duration of the frequency correction reference signal 906 and the cycle duration of the reference clock 306, and / or values ​​derived from these values ​​that can realize similar or similar functions in the second FLL-PLL control loop 324. For example, the value of the deviation signal 818 may represent a value proportional to: a) the phase difference between the phase of the frequency-corrected reference signal 906 and the phase of the reference clock 306, and / or b) the frequency difference between the frequency of the frequency-corrected reference signal 906 and the frequency of the reference clock 306, and / or c) the cycle duration difference between the cycle duration of the frequency-corrected reference signal 906 and the cycle duration of the reference clock 306. Fig. 9In the example of , the second controller II 504 of the second FLL or PLL control loop 324 also generates a second control signal II 514 of the second controller II 504 of the second FLL or PLL control loop 324. The second controller II 504 of the second FLL or PLL control loop 324 uses the second control signal II 514 to control the reference oscillator 505 with an adjustable frequency or an adjustable cycle duration or an adjustable phase. Therefore, the second controller II 504 of the second FLL or PLL control loop 324 controls the frequency and / or cycle duration and / or phase of the reference clock 306 of the reference oscillator 505 according to the frequency correction reference signal 906, for example. Therefore, the value of the frequency and / or cycle duration and / or phase of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324 preferably depends on the corresponding value of the frequency and / or cycle duration and / or phase of the frequency correction reference signal 906. Very particularly preferably, the FLL or PLL control loop 324 controls the phase. Therefore, very particularly preferably, the phase detector 819 detects the phase difference (phase difference) between these signals, namely the frequency-corrected reference signal 906 and the reference clock 306. Therefore, the frequency and / or the cycle duration and / or the phase of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324 preferably depends on the deviation value of the corresponding values ​​of the frequency-corrected reference signal 906 and the reference clock 306, which the second phase detector 819 or the second frequency difference detector 819 or the second cycle duration difference detector 819 determines and notifies the second controller II 504 of the deviation value via the deviation signal 818. Therefore, the deviation signal 818 of the phase detector 818 or the frequency difference detector 819 or the cycle duration difference detector 819 for reconstructing the deviation of the frequency or the cycle duration or the phase between the reference signal 906 and the reference clock 306 controls the reference oscillator 505 and thus controls the frequency and / or the cycle duration and / or the phase of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324. Therefore, in Fig. 9In the example of , the second FLL or PLL control loop 324 includes a frequency correction oscillator 920, which, while maintaining the most important parameters of the most recently occurring one or more valid reference signals, continues to generate occasionally occurring valid reference signals in the input signal 308, at least when the valid reference signals in the input signal 308 are not available or are no longer available, i.e., during the interval between the occurrence of valid reference signals in the input signal 308, so that the time reference of the parameters of the device 300 of the present invention similar to these valid reference signals is also available during these times. For example, these most important parameters can be the values ​​of frequency, cycle duration and phase. To this end, the frequency correction oscillator 920 preferably generates a preferably continuous frequency correction reference signal 906 based on the valid measurement values ​​of the parameters 517 of the occasionally occurring one or more reference signals in the input signal 308 detected by the measuring device 509, which frequency correction reference signal 906 substantially corresponds to the temporally continuous continuation of the occurring reference signals. Therefore, the frequency correction oscillator 920 preferably generates the reconstructed reference signal 906 from the high frequency clock 303 according to the valid parameters 517 of one or more reference signals of the input signal 308 detected by the measuring device 509. For example, the error correction oscillator 920 can be another frequency divider, which divides the high frequency clock 303 into the frequency correction reference signal 906 according to the effective measured values ​​of the parameters 517 of one or more valid reference signals that occasionally appear in the input signal 308 detected by the measuring device 509, so that the frequency correction reference signal 906 has the most important valid parameters of the one or more valid reference signals that occasionally appear in the input signal 308. For example, these most important parameters can be the values ​​of frequency, cycle duration and phase. Therefore, the frequency correction oscillator 920 preferably has the additional clock divider. Preferably, the additional clock divider uses the clock divider with the relevant frequency division ratio to generate the frequency correction reference signal 906 from the high frequency clock 303 by clock dividing the high frequency clock 303 according to the frequency division ratio. As described above, the frequency division ratio preferably depends on the values ​​of the parameters 517 of one or more reference signals of the input signal 308 and the effective values ​​detected by the measuring device 509 and / or the values ​​of the most important parameters derived therefrom. In particular, the frequency division ratio may be proportional or inversely proportional to the effective values ​​of these effective parameters, or may be, for example, the time integral of these effective values ​​or their inverse or other values ​​derived from these effective values ​​of the parameters of one or more reference signals of the input signal 308. For example, the effective parameters may be the values ​​of frequency, period duration and phase, respectively.

[0287] Preferably, the second FLL or PLL control loop 324 has a second phase detector 819 and / or a second frequency difference detector 819 and / or a second cycle duration difference detector 819. Thus, the device 300 of the present invention can determine the deviation between the frequency or cycle duration or phase of the reference clock 306 and the frequency or cycle duration or phase of the frequency correction reference signal 906. In this sense, Fig. 9 The second FLL or PLL control loop 324 is particularly preferably a real PLL (phase locked loop) with a phase detector 819. If necessary, the second phase detector 819 compares the frequency correction reference signal 906 with the reference clock 306. If necessary, the second frequency difference detector 819 compares the frequency correction reference signal 906 with the reference clock 306. If necessary, the second cycle duration difference detector 819 compares the frequency correction reference signal 906 with the reference clock 306. If necessary, the second phase detector 819 compares the frequency correction reference signal 906 with the reference clock 306. The second phase detector 819 generates a deviation signal of the phase detector 819 as a phase deviation between the frequency correction reference signal 906 and the reference clock 306 based on the result of the comparison. Alternatively, the second frequency difference detector 819 generates a deviation signal of the frequency difference detector 819 as a frequency deviation between the frequency correction reference signal 906 and the reference clock 306 based on the result of the comparison. Alternatively, the second cycle duration difference detector 819 generates a deviation signal of the cycle duration difference detector 819 as a cycle duration deviation between the frequency correction reference signal 906 and the reference clock 306 based on the result of the comparison.

[0288] The controller 311 preferably deactivates the first FLL or PLL control loop 323 during the measurement, evaluation and reconstruction of the reference signal of the input signal 308 by the frequency correction oscillator 920. Therefore, the high-frequency clock 303 is generally substantially constant in frequency and / or cycle duration and / or phase during the measurement, evaluation and reconstruction of the reference signal of the input signal 308 by the measuring device 509. The second FLL or PLL control loop 324 re-regulates the phase of the reference clock 306 until the values ​​of the parameters (frequency, cycle duration, phase) of the reference clock 306 coincide with the corresponding effective values ​​of the effective parameters 517 of the reference signal, except for the regulation error.

[0289] Fig.10

[0290] Fig.10 express Figure 8 Simplification of technical implications. Figure 8As shown, the reconstruction oscillator 810 generates a reference signal as the continuous reconstruction reference signal 806 based on the detected valid measurement values ​​of the frequency and / or cycle duration and / or phase of one or more valid reference signals of the input signal 308. However, the phase detector 819 now does not use the reference clock 306 for comparison with the reconstruction reference signal 806. Instead, the clock divider 1024 divides the reference clock 306 into the divided reference clock 1025. Therefore, the frequency range of the frequency of the reference clock 306 can be more freely selected in the design according to the application. The phase detector 819 or the frequency difference detector 819 or the cycle duration difference detector 819 compares the divided reference clock 1025 with the reconstructed reference signal 806, and forms a deviation signal 1018 of the phase detector 819 or the frequency difference detector 819 or the cycle duration difference detector 819 for the deviation of the frequency or cycle duration or phase between the reconstructed reference signal 806 and the divided reference clock 1025, and then the phase detector 819 or the frequency difference detector 819 or the cycle duration difference detector 819 notifies the second regulator II 504 of the deviation signal.

[0291] For example, the frequency difference detector 819 may compare the frequency value of the reconstructed reference signal 806 with the frequency value of the divided reference clock 1025, and determine a deviation value between the frequency value of the reconstructed reference signal 806 and the frequency value of the divided reference clock 1025 as a comparison result. Preferably, the frequency difference detector 819 transmits the determined deviation value as the value of the deviation signal 1018 or a value derived therefrom to the second regulator II 504.

[0292] For example, the phase detector 819 may compare the phase value of the reconstructed reference signal 806 with the phase value of the divided reference clock 1025, and determine a deviation value between the phase value of the reconstructed reference signal 806 and the phase value of the divided reference clock 1025 as a comparison result. Preferably, the phase detector 819 transmits the determined deviation value as the value of the deviation signal 1018 or a value derived therefrom to the second regulator II 504.

[0293] For example, the cycle duration difference detector 819 may compare the cycle duration value of the reconstructed reference signal 806 with the cycle duration value of the divided reference clock 1025, and determine the deviation value between the cycle duration value of the reconstructed reference signal 806 and the cycle duration value of the divided reference clock 1025 as the comparison result. Preferably, the cycle duration difference detector 819 transmits the determined deviation value as the value of the deviation signal 1018 or a value derived therefrom to the second regulator II 504.

[0294] As described above, the second controller II 504 preferably forms a control signal II 514 of the second controller II 504 according to the deviation signal 1018. As described in other parts of this document, the second controller II 504 is preferably a PI controller, etc. The adjustable reference oscillator 505 generates a reference clock 306 according to the control signal II 514 of the second controller II 504, and uses the reference clock 306 to close the control loop of the second FLL or PLL control loop 324. Fig.10 Other aspects of Figure 8 .

[0295] Fig.11

[0296] Fig.11 A particularly simple version of the inventive device 300 is shown. A fixed frequency reference clock oscillator 1101 generates a reference clock 306. The frequency and / or period duration and / or phase of the fixed frequency reference clock oscillator 1101 and thus of the reference clock 306 typically drifts. Fig.11 Technical Inspiration Now assume that the drift is so slow that the first FLL or PLL control loop 323 can compensate for it when generating the high-frequency clock 303. The first frequency divider 520 divides the high-frequency clock 303 to the frequency of the divided high-frequency clock 521 at a frequency division ratio. Fig.11 In the example, the first frequency divider preferably divides the high frequency clock 303 into the auxiliary clock 1112 of the frequency divider 520 according to the second frequency division ratio. The frequency division ratio calculator 1110 uses the auxiliary clock 1112 to detect the measured value of the frequency and / or cycle duration of the auxiliary clock 1112. The frequency division ratio calculator 1110 compares the effective measured value 517 of the frequency or cycle duration of one or more effective reference signals of the input signal 308 with the measured value of the frequency and / or cycle duration of the auxiliary clock 1112. Thus, the ratio between the effective measured value 517 of the frequency or cycle duration of one or more effective reference signals of the input signal 308 and the measured value of the frequency and / or cycle duration of the auxiliary clock 1112 is generated. According to the ratio of deviation relative to the predetermined ratio 1113, the frequency division ratio calculator 1110 changes the target frequency division ratio 1111 of the frequency divider 520. Preferably, the frequency division ratio calculator 1110 behaves similarly to a PI controller, so that the target frequency division ratio 1111 changes only slowly and gradually. However, the variation is still faster than the drift of the fixed frequency reference clock oscillator 1101 and, therefore, the reference clock 306. Therefore, the division ratio calculator 1110 compensates for the drift of the fixed frequency reference clock oscillator 1101. If desired, the controller 311 may specify a factor 1113 by which the frequency and / or cycle duration of the auxiliary clock 1112 deviates in proportion to the effective measured value 517 of the frequency or cycle duration of one or more effective reference signals of the input signal 308 in the steady state.

[0297] advantage

[0298] The method of the invention and the device of the invention have the advantage that, after a single LIN synchronization field of a data communication carried out by a LIN data bus, a CPU frequency can be brought to a CPU frequency that corresponds to a target frequency with very good target accuracy. For this purpose, the device of the invention does not require a frequently recurring high-precision reference signal. A rarely occurring reference signal is sufficient for the device of the invention. However, the advantages are not limited to this.

[0299] By using the method of the present invention, the device of the present invention can have a reduced inherent accuracy compared to the necessary target accuracy. When the device of the present invention is implemented as a micro integrated circuit, the test and calibration workload can be reduced. This saves costs. However, the necessary target accuracy can also be within the range that will be achieved due to temperature changes and aging in the semiconductor process for producing the device of the present invention without using the method of the present invention in the device of the present invention. By applying the method of the present invention, the device of the present invention can achieve the desired target accuracy of the frequency after the first occasional reference signal (for example, after receiving a LIN synchronization field (LIN-Synchronisationsfeld)). Therefore, the device of the present invention generally does not require any transient process that spans multiple reference signals (that is, for example, multiple LIN synchronization fields) for a longer time. Another advantage is that the method proposed in this article is compatible with the automatic baud rate detection method known in the prior art. Therefore, the idea of ​​the present invention according to the present invention is to combine the method proposed in this article with the known automatic baud rate detection method.

[0300] Conclusion

[0301] The above description is not exhaustive and does not limit the present disclosure to the examples shown. Other variations of the disclosed examples can be understood and implemented by those skilled in the art based on the drawings, the disclosure and the claims. The indefinite article "one" or "an" and its variations do not exclude a plurality, and the reference to a specific number of elements does not exclude the possibility of more or fewer elements. A single unit can implement the functions of a plurality of elements described in the present disclosure, and conversely, a plurality of elements can implement the functions of a unit. A large number of alternatives, equivalents, variations and combinations are possible without departing from the scope of use of the present disclosure.

[0302] Unless otherwise stated, all features of the present invention can be freely combined with each other. This applies to the entire document presented here. Unless otherwise stated, the features described in the description of the figures can also be freely combined with other features as features of the present invention. Here, it is not explicitly stipulated that individual features of the exemplary embodiment are restricted to combinations with other features of the exemplary embodiment. In addition, object features of the device can also be transformed into method features for use, and method features can also be transformed into object features of the device for use. Therefore, such transformation is automatically disclosed.

[0303] In the above detailed description, reference is made to the drawings. The examples in the description and drawings should be considered illustrative and should not be considered as limiting the specific examples or elements described. Multiple examples can be derived from the above description and / or drawings and / or claims by modifying, combining or changing specific elements. In addition, those skilled in the art can deduce examples or elements not literally described from the description and / or drawings.

[0304] Reference numerals list

[0305] 300 The device of the present invention;

[0306] 303 High frequency clock (fast system clock). Preferably, the high frequency clock also serves as a system clock to drive the controller 311 and other digital circuits of the device 300;

[0307] 306 a low frequency reference clock having a reference clock frequency;

[0308] 308 input signal, for example, it has a synchronization signal, for example, it has a synchronization field;

[0309] 311 controller;

[0310] 313 a first enable / disable signal for the controller 311 of the freezable regulator I 501;

[0311] 323 first FLL or PLL control loop;

[0312] 324 second FLL or PLL control loop;

[0313] 325 a second enable / disable signal for the controller 311 of the second regulator II 504;

[0314] 326 Reference signal signaling;

[0315] 400 Normal state and normal operation of the device 300 of the present invention;

[0316] 401 Detecting a synchronization signal in the form of a reference signal in the input signal 308;

[0317] 402 Measure the state of the reference signal in the input signal 308;

[0318] 403 evaluates the state of the reference signal of the input signal 308;

[0319] 404 determines whether the reference signal of the input signal 308 is valid;

[0320] 405 is a state of measuring the frequency and / or cycle duration and / or phase of the reference clock 306 and calculating a target value of the frequency and / or cycle duration and / or phase of the reference clock 306;

[0321] 406 calibrates the frequency and / or cycle duration and / or phase of the reference clock 306 and verifies the state of measuring the frequency and / or cycle duration and / or phase of the reference clock 306;

[0322] 407 is a step of checking whether the target values ​​of frequency and / or cycle duration and / or phase have been reached;

[0323] 501 Freezable Regulator I;

[0324] 502 a high frequency oscillator for generating a high frequency clock (system clock) 303;

[0325] 504 Freezable second regulator II;

[0326] 505 is a controllable reference oscillator for generating a reference clock 306;

[0327] 507 A reference measurement device for measuring the frequency and / or cycle duration and / or phase shift of the low-frequency reference clock 306;

[0328] 509 is a measuring device for measuring the input signal 308. The measuring device is particularly used for measuring a reference signal in the input signal 308;

[0329] 510 a target value calculator for the measured value of the low frequency reference clock 306;

[0330] 514 control signal II of the second controller II 504 , with which the freezable controller II 504 controls the reference oscillator 505 with an adjustable frequency and, for example, controls the frequency and / or phase of the reference clock 306 of the reference oscillator 505 with an adjustable frequency;

[0331] 515 a first control signal I of the first controller I 501, with which the first controller I 501 controls the high-frequency oscillator 502 and, for example, controls the frequency and / or cycle duration and / or phase of the high-frequency clock 303 of the high-frequency oscillator 502;

[0332] 516 a reference clock frequency measurement value signal or a reference clock cycle duration measurement value signal or a reference clock phase measurement value signal of the reference measurement device 507, for use by the target value calculator 510 in the measurement value of the frequency, cycle duration or phase of the low-frequency reference clock 306;

[0333] 517 valid measured values ​​of the frequency or other suitable parameters (e.g., cycle duration and / or phase) of one or more valid reference signals of the input signal 308 provided by the measurement device 509 for measuring the input signal 308;

[0334] 518 a deviation signal provided by the target value calculator 510 for the measured values ​​of the low-frequency reference clock 306, which deviation signal notifies the second controller II 504 of the deviation value between the measured value of the frequency and / or the cycle duration and / or the phase of the reference clock frequency measured value signal 516 or the reference clock cycle duration measured value signal 516 or the reference clock phase measured value signal 516 and the valid measured value 517 of the frequency or the cycle duration or the phase of one or more valid reference signals of the input signal 308;

[0335] 519 a phase detector 519 and / or a frequency difference detector 519 and / or a cycle duration difference detector 519 of the first FLL or PLL control loop 323;

[0336] 520 first clock divider;

[0337] 521 The first clock divider 520 divides the high frequency clock 303 by the first frequency division to form a divided high frequency clock;

[0338] 522 a high-frequency clock frequency measurement value signal of the phase detector 519 of the first control loop, for use by the first controller I501 in the measurement value of the high-frequency clock 303;

[0339] 701 Uncontrolled reference oscillator;

[0340] 702 second clock divider;

[0341] 703 reference pre-clock;

[0342] 714 clock divider signal;

[0343] 806 reconstructs a reference signal;

[0344] 810 a reconstruction oscillator, which generates a reference signal as a reconstructed reference signal 806 based on the detected measured values ​​of the frequency and / or cycle duration and / or phase of the reference signal of the input signal 308;

[0345] 818 The phase detector 819 or the frequency difference detector 819 or the cycle time difference detector 819 is used to reconstruct the deviation of the frequency, cycle time or phase between the reference signal 806 and the reference clock 306. The phase detector 819 or the frequency difference detector 819 or the cycle time difference detector 819 sends a deviation signal to the second controller II.

[0346] 504 notifies the deviation signal;

[0347] 819 a second phase detector 819 and / or a second frequency difference detector 819 and / or a second cycle duration difference detector 819, which generates a deviation signal 818 according to the difference in frequency and / or cycle duration and / or phase between the reconstructed reference signal 806 and the reference clock 306;

[0348] 906 frequency correction reference signal;

[0349] 910 Comparator;

[0350] 918 comparison result signal;

[0351] 920 Frequency Correction Oscillator;

[0352] 1018 A deviation signal of the phase detector 819 or the frequency difference detector 819 or the cycle duration difference detector 819 for reconstructing the deviation of the frequency, cycle duration or phase between the reference signal 806 and the divided reference clock 1025, the phase detector 819 or the frequency difference detector 819 or the cycle duration difference detector 819 notifying the second controller II 504 of the deviation signal;

[0353] 1024 a clock divider for the reference clock 306;

[0354] 1025 divided reference clock 1025;

[0355] 1101 Fixed frequency reference clock oscillator;

[0356] 1110 Division Ratio Calculator;

[0357] 1111 frequency division ratio of the frequency divider 520;

[0358] 1112 Auxiliary clock;

[0359] 1113 Factor (signaling of factor).

[0360] Citation list

[0361] DE 19 619 509 C1;

[0362] EP 1 971 069 A1;

[0363] US 4 115 811;

[0364] US 6 097 754;

[0365] US2002 / 0 101 884A1;

[0366] US2005 / 0 024 111A1;

[0367] WO 1993 010 605A1;

[0368] WO 1999 055 088A1;

[0369] https: / / de.wikipedia.org / wiki / Phasenregelschleife#:~:text=Eine%20Phas enregelschleife%20%28PLL%2C%20nach%20englisch%20phase-locked%20loop%29%20ist,von%20der%20Regelabweichung%20%E2%80%93%20der%20Phasenverschiebung%20%E2%80%93%20periodisch;

[0370] https: / / www.eetimes.com / design-flexibility-key-to-simplifying-the-implementation-of-lin;

[0371] Infineon Technologies "Preliminary User's Manual TVTEXT PRO SDA 55xx", Version 1, July 21, 1999, Chapter 5, with special emphasis on Chapter 5.2.2 "Data Separation";

[0372] Standard "Enhanced Teletext specification" European Telecommunication Standard ETS 300 706, May 1997, EBU / CENELEC / ETSI JTC, DE / JTC-TTEXT-EACEM, in particular " Figure 4 : Clock preamble, framing code, and timing reference".

Claims

1. A device for generating a high frequency clock (303), in, The device comprises a controller (311), and The device comprises a first FLL or PLL control loop (323), and The device comprises a second FLL or PLL control loop (324), and wherein the apparatus comprises an input signal (308), and wherein the reference signal appears intermittently as part of the input signal (308), and wherein the second FLL or PLL control loop (324) is configured to generate a reference clock (306) based on one or more of the reference signals of the input signal (308) as a target signal of the second FLL or PLL control loop (324) when the second FLL or PLL control loop (324) is enabled, and wherein the second FLL or PLL control loop (324) is configured to generate the reference clock (306) as a target signal of the second FLL or PLL control loop (324) according to a state depending on measured values ​​of one or more valid reference signals when the second FLL or PLL control loop (324) is disabled, and wherein the first FLL or PLL control loop (323) is configured to generate a high frequency clock (303) based on the reference clock (306) used as a target signal of the first FLL or PLL control loop (323) when the first FLL or PLL control loop (323) is enabled, and wherein the first FLL or PLL control loop (323) is configured to, when the first FLL or PLL control loop (323) is disabled, continue to generate the high frequency clock (303) as a target signal of the first FLL or PLL control loop (323) according to the state of the reference clock (306) in the last enabled state of the first FLL or PLL control loop (323), and wherein the frequency of the high-frequency clock (303) is numerically greater than the frequency of the reference clock (306), or wherein the cycle duration of the high-frequency clock (303) is numerically less than the cycle duration of the reference clock (306), and wherein the controller (311) is configured to, in a normal state (400) of the device (300), disable the second FLL or PLL control loop (324) via a second enable / disable signal (325) of the controller (311), and wherein the controller (311) is configured to enable the first FLL or PLL control loop (323) via a first enable / disable signal (313) of the controller (311) in the normal state (400) of the device (300), and wherein the controller (311) is configured to detect the arrival of one or more of the reference signals of the input signal (308) in the normal state (400), or anticipate the arrival of one or more of the reference signals of the input signal (308) at a predetermined time or be notified of the arrival of one or more of the reference signals of the input signal (308) by a device component of the second FLL or PLL control loop (324), and wherein the controller (311) and / or the device component of the second FLL or PLL control loop (324) are configured to measure the reference signal used as the synchronization signal in the input signal (308) and evaluate the reference signal in the input signal (308), and determine the value of a parameter of the reference signal used as the synchronization signal in the input signal (308), and wherein the controller (311) is configured to subsequently enable the second FLL or PLL control loop (324) and cause the second FLL or PLL control loop (324) to enter a state (406) of correcting the frequency, cycle duration or phase of the reference clock (306), so that the second FLL or PLL control loop (324) regulates the corresponding parameter of the reference clock (306) until the corresponding parameter of the reference clock (306) corresponds to a determined value of the parameter of one or more of the reference signals used as the synchronization signal in the input signal (308) or a value derived therefrom, and The controller (311) is configured to subsequently deactivate the second FLL or PLL control loop (324) and thereby return the second FLL or PLL control loop (324) to the normal state (400) once the value of the corresponding parameter of the reference clock (306) corresponds to a determined value of the parameter of the reference signal in the input signal (308) used as the synchronization signal or a value derived therefrom.

2. The device according to claim 1, wherein: The controller (311) and / or device components of the second FLL or PLL regulation loop (324) are configured to evaluate the measured value of the reference signal in the input signal (308) and determine an evaluation result.

3. The device according to claim 2, wherein: The controller (311) is configured to keep the device in the normal state (400) when the evaluation result includes one or more values ​​that are not within a predetermined value interval or do not correspond to a predetermined value, wherein the second FLL or PLL control loop (324) is disabled.

4. The device according to any one of claims 1 to 3, wherein: The device is configured to measure the reference signal used as the synchronization signal in the input signal (308) using the high-frequency clock (303) and / or a signal derived from the high-frequency clock (303) and / or a signal related to the high-frequency clock (303).

5. The device according to any one of claims 1 to 3, wherein: The device is configured to measure the reference clock (306) within the enabled second FLL or PLL regulation loop (324) using the high frequency clock (303) and / or a signal derived from and / or related to the high frequency clock (303).

6. The device according to any one of claims 1 to 3, wherein: In measuring the state (403) of the synchronization signal of the input signal (308), the device component of the device determines the value of the parameter of the reference signal in the input signal (308) used as the synchronization signal, and the value of the parameter of the reference signal at least includes one or more values ​​of one or more of the following parameters: - the number of cycles of the reference signal in the input signal (308) within a predetermined period of time, and / or - the frequency and / or cycle duration of the reference signal in the input signal (308), and / or - the duration of a complete period of the reference signal in the input signal (308) and / or its inverse, and / or - the phase of the reference signal in the input signal (308) relative to the divided high frequency clock (521), and / or, - the phase of the reference signal in the input signal (308) relative to the reference clock (306), and / or - the duration of the low phase and / or high phase of a period of the reference signal in the input signal (308), and / or - the duration of a specific number of periods of the reference signal in the input signal (308), and / or - a duration of a specific number of low phases and / or high phases of the reference signal in the input signal (308).

7. The device according to any one of claims 1 to 3, in, The controller (311) is configured to disable the first FLL or PLL control loop (323) before enabling the second FLL or PLL control loop (324), and The controller (311) is configured to disable the second FLL or PLL control loop (324) before enabling the first FLL or PLL control loop (323).

8. The device according to claim 7, wherein: The controller (311) is configured to deactivate the first FLL or PLL regulation loop (323) when the device is in a state (402-405) different from the normal state (400).

9. The device according to any one of claims 1 to 3, in, The second FLL or PLL control loop (324) includes a reference oscillator (505) that generates the reference clock (306) having a reference clock frequency and a reference clock phase, and Wherein, the controller (311) and / or the device components of the second FLL or PLL control loop (324) are configured to determine the value of the deviation of the frequency and / or phase of one or more of the reference signals of the input signal (308) relative to the reference clock frequency and / or reference clock phase of the reference clock (306) of the reference oscillator (505).

10. The device according to any one of claims 1 to 3, wherein: The second FLL or PLL control loop (324) comprises a measuring device (509) for measuring the input signal (308).

11. The device according to claim 10, wherein: The measuring device (509) is used to measure one or more of the reference signals present in the input signal (308).

12. The device according to claim 10, wherein: The measuring device (509) as a device component of the second FLL or PLL control loop (324) is configured to detect the arrival of one or more reference signals of the input signal (308) in the normal state (400), or to notify the controller (311) of the arrival of one or more reference signals of the input signal (308).

13. The apparatus according to claim 10, wherein: The measuring device (509) as a device component of the second FLL or PLL control loop (324) is configured to measure the reference signal in the input signal (308) which serves as the synchronization signal.

14. The device according to claim 13, wherein: The measuring device (509) as a device component of the second FLL or PLL control loop (324) is configured to measure the reference signal in the input signal (308) used as the synchronization signal in the state (403) of measuring the synchronization signal of the input signal (308).

15. The apparatus according to claim 13, wherein: The measuring device (509) as a device component of the second FLL or PLL control loop (324) is configured to determine the value of the parameter of the reference signal in the input signal (308) used as the synchronization signal.

16. The device according to claim 15, wherein: The values ​​of the parameters of the reference signal used as the synchronization signal in the input signal (308) determined by the measuring device (509) as a device component of the second FLL or PLL control loop (324) include at least one or more values ​​of one or more of the following parameters: - the number of cycles of the reference signal in the input signal (308) used as the synchronization signal, and / or - the frequency and / or period duration of one or more of the reference signals of the input signal (308), and / or - the duration of a complete period of one or more of said reference signals of said input signal (308) and / or the inverse thereof, and / or - the phase of the reference signal in the input signal (308) relative to the divided high frequency clock (521), and / or, - the phase of the reference signal in the input signal (308) relative to the reference clock (306), and / or - the duration of the low phase and / or high phase of a period of the reference signal in the input signal (308), and / or - the duration of a specific number of periods of one or more of said reference signals of said input signal (308), and / or - a duration of a specific number of low phases and / or high phases of one or more of said reference signals of said input signal (308).

17. The device according to claim 10, in, The reference signal used as the synchronization signal in the input signal (308) has at least two reference signal characteristics, and The measuring device (509) is configured to count the number of cycles of the high-frequency clock (303) and / or a signal derived from the high-frequency clock (303) and / or a signal related to the high-frequency clock (303) between a first time when a first reference signal feature in the input signal (308) appears and a second time when a second reference signal feature in the input signal (308) appears, and thereby determine a second count value.

18. The apparatus according to claim 17, wherein: The reference signal feature is a rising edge and / or a falling edge.

19. The apparatus according to claim 17, wherein: The controller (311) and / or the second FLL or PLL control loop (324) is configured to use the second count value as a measure of the frequency and / or cycle duration and / or phase of one or more of the reference signals of the input signal (308).

20. The apparatus according to any one of claims 1 to 3, wherein: The second FLL or PLL control loop (324) has a reference measurement device (507) for measuring the reference clock (306).

21. The apparatus according to claim 20, wherein: The reference measurement device (507), being a device component of the second FLL or PLL regulation loop (324), is configured to determine the value of the parameter of the reference clock (306).

22. The apparatus according to claim 21, wherein The parameters are the frequency and / or cycle duration and / or phase of the reference clock (306).

23. The apparatus of claim 21, wherein: The values ​​of the parameters of the reference clock (306) determined by the reference measurement device (507) as a device component of the second FLL or PLL control loop (324) include at least one or more values ​​of one or more of the following parameters: - the number of cycles of the reference clock (306), and / or - the frequency and / or cycle duration of the reference clock (306), and / or - the duration of a complete cycle of the reference clock (306) and / or its inverse, and / or - the phase of the reference clock (306) relative to the divided high frequency clock (521), and / or, - the phase of the reference clock (306) relative to the reference signal in the input signal (308), and / or - the duration of the low phase and / or high phase of a cycle of the reference clock (306), and / or - a duration of a certain number of cycles of the reference clock (306), and / or - a duration of a specific number of low phases and / or high phases of the reference clock (306).

24. The apparatus according to claim 20, in, The reference clock (306) has at least two reference clock characteristics, and The reference measurement device (507) is configured to count the number of cycles of the high-frequency clock (303) and / or a signal derived from the high-frequency clock (303) and / or a signal related to the high-frequency clock (303) between a first time when a first reference clock feature in the reference clock (306) appears and a second time when a second reference clock feature in the reference clock (306) appears, and thereby determine a third count value.

25. The apparatus of claim 24, wherein: The reference clock feature is a rising edge and / or a falling edge.

26. The apparatus of claim 24, wherein: The controller (311) and / or the second FLL or PLL control loop (324) is configured to use the third count value or a value derived therefrom as a reference clock frequency measurement value signal of the reference measurement device (507) for the measurement value of the reference clock (306).

27. The apparatus of claim 26, wherein: The controller (311) and / or the second FLL or PLL control loop (324) is configured to use the third count value or a value derived therefrom as a measure of the frequency and / or cycle duration of the reference clock (306).

28. The apparatus according to claim 21, in, The reference clock (306) has at least one reference clock characteristic, and wherein the reference signal in the input signal (308) has at least one reference signal characteristic, and Wherein, the reference measurement device (507) is configured to count the number of cycles of the high-frequency clock (303) and / or a signal derived from the high-frequency clock (303) and / or a signal related to the high-frequency clock (303) between the time when a first reference clock feature in the reference clock (306) appears and the time when a second reference signal feature in the reference signal of the input signal (308) appears, and thereby determine a third count value.

29. The apparatus of claim 28, wherein: The reference clock feature is a rising edge and / or a falling edge.

30. The apparatus of claim 28, wherein: The reference signal feature is a rising edge and / or a falling edge.

31. The apparatus of claim 28, wherein: The controller (311) and / or the second FLL or PLL control loop (324) is configured to use the third count value or a value derived therefrom as a reference clock phase measurement value signal of the reference measurement device (507) for the measurement value of the reference clock (306).

32. The apparatus of claim 31, wherein: The controller (311) and / or the second FLL or PLL control loop (324) is configured to use the third count value, or a value derived therefrom, as a measure of the phase of the reference clock (306).

33. The apparatus according to claim 23, in, The reference clock (306) has at least one reference clock characteristic, and The divided high frequency clock (521) has at least one reference high frequency clock feature, and Wherein, the reference measurement device (507) is configured to count the number of cycles of the high-frequency clock (303) and / or a signal derived from the high-frequency clock (303) and / or a signal related to the high-frequency clock (303) between the time when a first reference clock feature in the reference clock (306) appears and the time when a second reference high-frequency clock feature in the divided high-frequency clock (521) appears, and thereby determine a third count value.

34. The apparatus of claim 33, wherein: The reference clock feature is a rising edge and / or a falling edge.

35. The apparatus of claim 33, wherein: The reference high frequency clock feature is a rising edge and / or a falling edge.

36. The apparatus of claim 33, wherein: The controller (311) and / or the second FLL or PLL control loop (324) is configured to use the third count value or a value derived therefrom as a reference clock phase measurement value signal of the reference measurement device (507) for the measurement value of the reference clock (306).

37. The apparatus of claim 36, wherein: The controller (311) and / or the second FLL or PLL control loop (324) is configured to use the third count value, or a value derived therefrom, as a measure of the phase of the reference clock (306).

38. The apparatus according to any one of claims 1 to 3, wherein: The second FLL or PLL control loop (324) has a target value calculator (510).

39. The apparatus of claim 38, wherein: The target value calculator (510) is configured to determine a deviation (518) between a measured value of the reference clock (306) or a value derived therefrom or related thereto and a determined value of the parameter of the reference signal in the input signal (308) used as the synchronization signal.

40. The apparatus of claim 39, wherein: The deviation (518) is a deviation in the form of a difference.

41. The apparatus of claim 39, wherein: The frequency and / or cycle duration and / or phase of the reference clock (306) depends on the deviation (518) and / or a value derived therefrom or related thereto.

42. The apparatus of claim 39, wherein: The second FLL or PLL control loop (324) has a second controller II (504).

43. The apparatus according to claim 42, in, The second FLL or PLL control loop (324) has a reference oscillator (505), and wherein the second regulator II (504) is configured to form a second control signal II (514) of the second regulator II (504) as a function of the deviation (518) and / or in a manner proportional to the deviation and / or as a function of a value derived therefrom or related thereto, and The reference oscillator (505) is configured to form the reference clock (306) according to the second control signal II (514).

44. The apparatus of claim 43, wherein: The second regulator II (504) is configured to form the second control signal II (514) of the second regulator II (504) based on a correction value that depends on a) the deviation (518) or b) a value derived therefrom or c) a value related thereto, taking into account the trimming curve and / or the trimming step size from a) to c).

45. The apparatus according to any one of claims 1 to 3, in, The second FLL or PLL control loop (324) comprises a measuring device (509) for measuring the input signal (308), wherein the second FLL or PLL control loop (324) comprises a reference measurement device (507) for measuring the reference clock (306), and The second FLL or PLL control loop (324) has a reconstructed oscillator (810).

46. ​​The apparatus of claim 45, wherein: The reconstruction oscillator (810) is configured to generate a reconstructed reference signal (806) based on parameters of one or more of the reference signals of the input signal (308) detected by the measurement device (509).

47. The apparatus of claim 46, wherein: The reconstruction oscillator (810) is configured to generate a reconstructed reference signal (806) from the high frequency clock (303) based on the parameters of one or more of the reference signals of the input signal (308) detected by the measuring device (509).

48. The apparatus of claim 47, wherein: The reconstruction oscillator (810) has a clock divider, which is configured to generate the reconstructed reference signal (806) from the high-frequency clock (303) by clock division corresponding to the division ratio, wherein the division ratio depends on the parameters of one or more of the reference signals of the input signal (308) detected by the measuring device (509) or parameters derived from these parameters.

49. The apparatus according to claim 46, in, The reconstruction oscillator (810) is configured to generate a frequency correction reference signal (906) according to the following parameters: said parameter of one or more of said reference signals of said input signal (308) detected by said measuring device (509), and The parameters of the reference clock (306) are determined by the reference measurement device (507).

50. The apparatus according to claim 49, in, The reconstruction oscillator (810) is configured to generate the frequency correction reference signal (906) from the high frequency clock (303) according to the following parameters: said parameter of one or more of said reference signals of said input signal (308) detected by said measuring device (509), and The parameters of the reference clock (306) are determined by the reference measurement device (507).

51. The apparatus according to claim 50, in, The reconstruction oscillator (810) has a clock divider, and the clock divider is configured to generate a frequency correction reference signal (906) from the high-frequency clock (303) by clock division corresponding to the division ratio of the clock divider, wherein the division ratio depends on the following parameters: - said parameter of one or more of said reference signals of said input signal (308) detected by said measuring device (509), and - said parameters of said reference clock (306) determined by said reference measurement device (507).

52. The apparatus of claim 49, wherein: The second FLL or PLL control loop (324) has a second phase detector and / or a second frequency difference detector and / or a second cycle duration difference detector.

53. The apparatus according to claim 52, in, The second phase detector and / or the second frequency difference detector and / or the second cycle duration difference detector are configured to compare the reconstructed reference signal (806) or the frequency corrected reference signal (906) with the reference clock (306), and The second phase detector and / or the second frequency difference detector and / or the second cycle duration difference detector are configured to generate the following deviation signal according to the comparison result: a deviation signal of the second phase detector for a phase deviation between the reconstructed reference signal (806) or the frequency corrected reference signal (906) and the reference clock (306), or a deviation signal of the second frequency difference detector for the frequency deviation between the reconstructed reference signal (806) or the frequency corrected reference signal (906) and the reference clock (306), or - a deviation signal of the second cycle duration difference detector for a cycle duration deviation between the reconstructed reference signal (806) or the frequency-corrected reference signal (906) and the reference clock (306).

54. The apparatus of claim 53, wherein: The frequency and / or cycle duration and / or phase of the reference clock (306) depends on the value of the deviation signal and / or a value derived therefrom or related thereto.

55. The apparatus according to claim 54, in, The second FLL or PLL control loop (324) has a second controller II (504), The second regulator II (504) is configured to generate a second control signal II (514) according to the value of the deviation signal and / or in a manner proportional to the value of the deviation signal and / or a value derived therefrom or related thereto, and to form the reference clock (306) according to the second control signal II (514).

56. The apparatus of claim 55, wherein: The second regulator II (504) is configured to form the second control signal II (514) based on a correction value that depends on a) the value of the deviation signal or b) a value derived therefrom or c) a value related thereto, taking into account the trimming curve and / or the trimming step size from a) to c).

57. The apparatus of claim 55, wherein: The second regulator II (504) is configured to maintain the second control signal II (514) at a constant value as long as the controller (311) notifies the second regulator II (504) through a second enable / disable signal (325) that the second FLL or PLL control loop (324) should be in a disabled state.

58. Apparatus according to any one of claims 1 to 3, wherein: The first FLL or PLL control loop (323) has a high-frequency oscillator (502), and wherein the high-frequency oscillator (502) generates the high-frequency clock (303).

59. The apparatus according to claim 58, in, The first FLL or PLL control loop (323) has a first clock divider (520), and The first clock divider (520) is configured to divide the high-frequency clock (303) of the high-frequency oscillator (502) into a divided high-frequency clock (521) according to a first division ratio of the first clock divider (520).

60. The apparatus of claim 59, wherein: The first FLL or PLL control loop (323) has a phase detector and / or a frequency difference detector and / or a periodic time difference detector of the first FLL or PLL control loop (323), wherein the phase detector, the frequency difference detector and the periodic time difference detector are collectively referred to as a phase detector.

61. The apparatus of claim 60, wherein: The phase detector of the first FLL or PLL control loop (323) is configured to detect the phase difference and / or frequency difference and / or cycle duration difference between the reference clock (306) and the divided high-frequency clock (521) as a measurement value, and to form a high-frequency clock frequency measurement value signal (522) based on the measurement value.

62. The apparatus of claim 61, wherein: The first FLL or PLL control loop (323) has a first controller I (501) of the first FLL or PLL control loop (323).

63. The apparatus according to claim 62, in, The first regulator I (501) is configured to form a first control signal I (515) of the first regulator I (501) according to the high-frequency clock frequency measurement value signal (522), and The high-frequency oscillator (502) at least temporarily forms the high-frequency clock (303) according to the first control signal I (515) of the first controller I (501).

64. The apparatus of claim 63, wherein: The first regulator I (501) is configured to maintain the first control signal I (515) at a constant value as long as the controller (311) notifies the first regulator I (501) through a first enable / disable signal (313) that the first FLL or PLL control loop (323) should be in a disabled state.

65. The apparatus of claim 63, wherein: The first regulator I (501) is configured to no longer maintain the first control signal I (515) at a constant value when the controller (311) notifies the first regulator I (501) through a first enable / disable signal (313) that the first FLL or PLL control loop (323) should be in an enabled state.

66. The apparatus according to claim 65, in, The first regulator I (501) is configured to maintain the first control signal I (515) at a constant value until a reference clock feature appears in the reference clock (306), and when the reference clock feature appears in the reference clock (306), the first clock divider (520) and / or the first control signal I (515) are set to a predetermined value, and from then on the first control signal I (515) is no longer forced to a constant value.

67. The apparatus of claim 66, wherein: The reference clock feature is a rising edge or a falling edge.

68. The apparatus according to claim 9, in, The controller (311) and / or the reference measuring device (507) of the device (300) for measuring the reference clock (306) is configured to detect the duration of a specific number of cycles of the reference clock (306) of the reference oscillator (505) via the high frequency clock (303) and via the reference measuring device (507) for measuring the reference clock (306), and wherein the target value calculator (510) for determining the deviation of the controller (311) and / or the device (300) is configured to determine the deviation between the detected duration and / or a value derived therefrom and a measured value of the frequency and / or period duration of one or more of the reference signals of the input signal (308), and Wherein, the controller (311) and / or the second FLL or PLL control loop (324) are configured to correct the frequency and / or cycle duration and / or phase of the reference clock (306) of the reference oscillator (505) according to the determined deviation, and to detect the duration of a specific number of cycles of the reference clock (306) of the reference oscillator (505) again until the target value of the frequency and / or cycle duration and / or phase of the reference clock (306) of the reference oscillator (505) is reached.

69. The apparatus of claim 68, wherein: The controller (311) and / or the second FLL or PLL control loop (324) is configured to correct the frequency and / or cycle duration and / or phase of the reference clock (306) of the reference oscillator (505) in proportion to the determined deviation.

70. The apparatus of claim 58, wherein: The controller (311) is configured to temporarily freeze and thereby deactivate the first FLL or PLL control loop (323) when one or more of the reference signals of the input signal (308) are present, so that the high-frequency clock (303) of the controllable high-frequency oscillator (502) or the first FLL or PLL control loop (323) does not change its frequency and / or cycle duration and / or phase during the duration of the presence of the reference signal of the input signal (308).

71. The apparatus according to any one of claims 1 to 3, in, The device is configured to not re-enable the first FLL or PLL regulation loop (323) after deactivating the first FLL or PLL regulation loop (323) immediately after the occurrence of a reference signal as a synchronization signal in the input signal (308) ends, and The device is configured to re-enable the first FLL or PLL control loop (323) only at the end of the remaining data frame after the reference signal in the input signal (308), or only at the end of the related data message after the reference signal in the input signal (308), and thus delay the re-enabling of the first FLL or PLL control loop (323) until the end of the related data message, wherein the related data message is the data communication transmitted via the input signal (308).

72. The apparatus of any one of claims 1 to 3, wherein: The device is configured to return to the normal state (400) when the device is not in the normal state (400) and when the controller subsequently detects the arrival of another additional reference signal in the input signal (308).

73. The apparatus according to any one of claims 1 to 3, The device has a target value calculator (510) for detecting successful completion of the correction of the frequency and / or cycle duration and / or phase of the reference clock (306), and in, The device is configured to notify a superordinate system that the frequency and / or cycle duration and / or phase of the reference clock (306) has been reached.

74. The apparatus of claim 73, wherein: The controller (311) is configured to notify a superior system that the frequency and / or cycle duration and / or phase of the reference clock (306) has been reached.

75. The apparatus according to claim 9, in, The device is configured to switch to a "fine correction mode" after successfully completing the correction of the frequency and / or cycle duration and / or phase of the reference clock (306) and after reaching a target frequency and / or target cycle duration and / or target phase of the reference clock (306), The difference of the fine correction mode of the device is that: the device is configured to perform or limit the correction of the second FLL or PLL control loop (324) or the reference oscillator (505) only by a specific number of trimming steps or by a specific frequency change or cycle duration change or phase change of the reference clock (306) of the second FLL or PLL control loop (324) and / or the reference oscillator (505), and The device is configured so that when leaving the normal state (400), the deactivation of the first FLL or PLL control loop (324) is omitted due to the previously completed transient process of the first FLL or PLL control loop (324) and the limitation of frequency change or cycle duration change or phase change.

76. The apparatus of claim 75, wherein: The device is configured to limit the correction of the second FLL or PLL control loop (324) or the reference oscillator (505) to one trimming step or the smallest possible change in frequency or cycle duration or phase of the reference clock (306) of the second FLL or PLL control loop (324) and / or the reference oscillator (505).

77. The apparatus according to any one of claims 1 to 3, in, The device (300) has a non-volatile memory, and The device (300) is configured to store the determined values ​​for frequency correction, cycle duration correction and / or phase correction of the reference clock (306) in the non-volatile memory after the correction of the frequency, cycle duration and / or phase of the reference clock (306) is completed or when the device stops running.

78. The apparatus of claim 77, wherein: The controller (311) and / or another sub-device of the device (300) has the non-volatile memory.

79. The apparatus according to claim 78, in, The device is configured to read values ​​for frequency correction, cycle duration correction and / or phase correction of the reference clock (306) determined during debugging from the non-volatile memory and use the values ​​for frequency correction, cycle duration correction and / or phase correction of the reference clock (306).

80. The apparatus of claim 79, wherein: The controller (311) and / or another sub-device of the device (300) is configured to read from the non-volatile memory the values ​​for frequency correction and / or cycle duration correction and / or phase correction of the reference clock (306) determined during debugging.

81. The apparatus according to any one of claims 1 to 3, in, The second FLL or PLL control loop (324) has a second phase detector and / or a second frequency difference detector and / or a second cycle time difference detector. For simplicity, the second phase detector and / or the second frequency difference detector and / or the second cycle time difference detector are referred to as the second phase detector in the same manner below, and The second FLL or PLL control loop (324) has a clock divider (1024), and The second FLL or PLL control loop (324) has a reference clock (306), and The second FLL or PLL control loop (324) has a reconfiguration oscillator (810), and wherein the second FLL or PLL control loop (324) has a measuring device (509), and The second FLL or PLL control loop (324) has a second controller II (504), and The second FLL or PLL control loop (324) includes a reference oscillator (505), and wherein the measuring device (509) detects measured values ​​of parameters of one or more reference signals in the input signal (308), and wherein the parameter is the frequency and / or cycle duration and / or phase of one or more of the reference signals in the input signal (308), and wherein the reconstruction oscillator (810) generates a reconstructed reference signal (806) based on the measured values ​​of the frequency and / or cycle duration and / or phase of one or more of the reference signals of the input signal (308), and wherein the clock divider (1024) of the second FLL or PLL control loop (324) divides the reference clock (306) into a divided reference clock (1025) according to a division ratio of the clock divider (1024) of the second FLL or PLL control loop (324), and wherein the second phase detector compares the value of the parameter of the frequency, phase or cycle duration of the reconstructed reference signal (806) with the value of the corresponding parameter of the frequency, phase or cycle duration of the divided reference clock (1025), and forms the value of the deviation signal of the second phase detector according to the value of the comparison result, and The second regulator II (504) forms a value of a second control signal II (514) according to the value of the deviation signal, and The reference oscillator (505) forms the reference clock (306) according to the value of the second control signal II (514).

82. The apparatus according to claim 81, in, The measuring device (509) detects a valid measured value of the parameter of one or more valid reference signals in the input signal (308), and The reconstruction oscillator (810) generates a reconstructed reference signal (806) based on the detected valid measurement values ​​of the frequency and / or cycle duration and / or phase of one or more valid reference signals of the input signal (308).

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