Active display pixel circuit and pulse width modulation driving method thereof

Abstract

The present application relates to a pulse width modulation driving method for a pixel circuit, comprising receiving initial display data, wherein for a display pixel circuit, the initial display data for each frame comprises an X-bit binary number; converting the initial display data into first display data, wherein the first display data comprises a K-ary number having Y bits; each frame is divided into Y subframes, wherein each subframe comprises a write time and a maximum light-emitting time, wherein the maximum light-emitting time in each subframe is at least a function of K and the subframe sequence number y, where y is an integer greater than 0 and less than or equal to Y; writing the corresponding bit of the first display data into the display pixel circuit during the write time of each subframe; and driving the light-emitting element in the display pixel circuit to emit light based on the first display data. The present application also relates to an active display pixel circuit and an electronic device comprising the aforementioned display pixel circuit.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an active display pixel circuit, a display device including an active display pixel array, and a pulse width modulation driving method for the display pixel circuit. Background Art

[0002] In recent years, research on micro-light-emitting diode (Micro-LED) display technology has attracted widespread attention. Compared with traditional displays such as liquid crystal displays (LCDs) or organic light-emitting diodes (OLEDs), Micro-LED displays offer advantages such as ultra-high brightness, high contrast, fast switching response speeds, and potentially better stability.

[0003] However, due to the unique optoelectronic properties of Micro-LEDs, the Pulse Amplitude Modulation (PAM) method used in traditional displays is not suitable for Micro-LED displays. The reasons include that the current-voltage characteristic curve of Micro-LEDs is steep, much steeper than that of traditional OLED displays, making it difficult to accurately control the display grayscale by controlling the amplitude of current or voltage. The external quantum efficiency (EQE) of Micro-LEDs varies with the driving current, especially at low driving currents, where the EQE decreases significantly. In addition, the emission wavelength of Micro-LEDs varies with the driving current, and a more obvious color shift occurs at low driving currents.

[0004] Existing Micro-LED displays use a pulse width modulation (PWM) drive method, which can maintain high luminous efficiency and a constant wavelength for Micro-LEDs. This solves the problems of low luminous efficiency and wavelength shift associated with PAM (Pulse Width Modulation) drive. However, the existing PWM drive method is also unsuitable for display devices with high frame rates and high display resolutions.

[0005] Furthermore, active displays in applications such as mobile phones and televisions are large or medium in size, and thin-film transistors (TFTs) are often used to fabricate pixel circuits and driver circuits for these active displays. However, TFTs commonly used to fabricate pixel circuits suffer from low mobility and long write times, making them unable to meet the high frame rate and high display resolution requirements of display devices.

[0006] Active displays in applications like AR and VR are miniature in size, and single-crystal silicon CMOS processes are commonly used to fabricate pixel and driver circuits. However, CMOS processes suffer from issues such as device mismatch and high leakage current, and require higher-frequency drive schemes, which translates to higher mobility, compared to TFT processes. CMOS processes also suffer from issues such as insufficient mobility and long write times, making them unable to meet the high frame rate and resolution requirements of display devices.

[0007] Therefore, a new driving method is needed to address the shortcomings of the aforementioned LED pixel circuits in terms of display accuracy, resolution, frame rate, and other aspects, and to improve the performance of active-light-emitting displays. The PWM driving method is not limited to Micro-LEDs but can also be applied to LED, OLED, QLED, and other displays. Summary of the Invention

[0008] In response to the technical problems existing in the prior art, the present application proposes a pulse width modulation driving method for a display pixel circuit, comprising receiving initial display data, wherein for a display pixel circuit, the initial display data of each frame includes an X-bit binary number, where X is an integer greater than or equal to 2; converting the initial display data into first display data, wherein the first display data includes a K-ary number having Y bits, where Y is an integer greater than 0, X is greater than Y, and K is an integer greater than or equal to 3; wherein each frame is divided into Y subframes, each subframe includes a write time and a maximum light-emitting time, and the maximum light-emitting time in each subframe is at least a function of K and a sequence number y of the subframe, where y is an integer greater than 0 and less than or equal to Y; writing a corresponding bit of the first display data into the pixel circuit during the write time of each subframe; and driving a light-emitting element in the pixel circuit to emit light based on the first display data; wherein the actual light-emitting time of the light-emitting element in each subframe is at least a function of a value of a corresponding bit of the first display data, K, and the sequence number y of the subframe, and the actual light-emitting time is less than or equal to the maximum light-emitting time of the subframe.

[0009] In particular, driving the pixel to emit light based on the first display data includes comparing the first display signal with a reference signal in each subframe, and when the relative relationship between the first display signal and the reference signal changes, the light-emitting state of the light-emitting element changes, wherein the first display signal includes a voltage corresponding to the value of each bit of the first display data.

[0010] In particular, when the reference signal is a step signal, the reference signal includes (K-1) steps of equal height, each step has the same duration, and the longest luminous time of each subframe is evenly divided into (K-1) parts.

[0011] The present application proposes an active display pixel circuit, comprising a light-emitting element; a PWM signal generating module, configured to receive a scanning signal, a reference signal and a first display signal, and output a PWM signal; wherein the PWM signal generating module includes a comparing unit, the comparing unit being configured to compare the first display signal with the reference signal, and causing the PWM signal to jump when the comparison result changes; a constant current module being configured to provide a light-emitting current to the light-emitting element; a switch module being coupled between the constant current module and the light-emitting element; the PWM signal generating module being configured to control the on or off state of the switch module using the PWM signal; wherein the first display data comprises a K-ary number having Y bits, where Y is an integer greater than 0. wherein K is an integer greater than or equal to 3, the first display signal includes a voltage corresponding to each value of each bit of the first display data; for each display pixel circuit, one frame includes Y subframes, each subframe includes a write time and a maximum light-emitting time, the write time in each subframe is the same, and the maximum light-emitting time in each subframe is at least a function of K and the serial number y of the subframe, wherein y is an integer greater than 0 and less than or equal to Y; during the write time of each subframe, the PWM signal generating module is configured to receive the first display signal; the actual light-emitting time of the light-emitting element in each subframe is at least a function of the first display signal, K, and the serial number y of the subframe, and the actual light-emitting time is less than or equal to the maximum light-emitting time of the subframe.

[0012] In particular, when the reference signal is a step signal, the reference signal includes (K-1) steps of equal height, each step has the same duration, and the longest luminous time of each subframe is evenly divided into (K-1) parts.

[0013] In particular, the switching module includes a switching transistor (204, 304, 404, 504 or 604), the control electrode of the switching transistor (204, 304, 404, 504 or 604) is coupled to the PWM signal generating module to receive the PWM signal, the first electrode is coupled to the constant current module, and the second electrode is coupled to the anode of the light-emitting element; and the constant current module includes a first transistor (T24, T34, T44, T54 or T64), the control electrode of the first transistor (T24, T34, T44, T54 or T64) receives an enable signal, the first electrode is configured to receive a high level, and the second electrode is coupled to the first electrode of the switching transistor (204, 304, 404, 504 or 604).

[0014] In particular, the comparison unit in the PWM signal generating module includes a second transistor (T41, T51 or T61) and a first capacitor (C41, C51 or C61); the first end of the first capacitor (C41, C51 or C61) is configured to receive the reference signal; the control electrode of the second transistor (T41, T51 or T61) is coupled to the second end of the first capacitor (C41, C51 or C61), and the first electrode is coupled to the control electrode of the first transistor (T44, T54 or T64).

[0015] In particular, the comparison unit further includes a third transistor (T43), the control electrode of the third transistor (T43) receiving the scanning signal, the first electrode receiving the second display signal, and the second electrode coupled to the control electrode of the second transistor (T41) and the second end of the first capacitor (C41); wherein the voltage value of the second display signal is the inverse of the voltage value of the first display signal; and the PWM signal generating module further includes a fourth transistor (T42), the control electrode of the fourth transistor (T42) receiving the charging signal, the first electrode receiving a high level, and the second electrode coupled to the first electrode of the second transistor (T41).

[0016] Particularly, the constant current module further comprises a fifth transistor (T45), the control electrode of the fifth transistor (T45) receives the enable signal, the first electrode receives a high level, and the second electrode is coupled to the first electrode of the first transistor (T44).

[0017] In particular, the constant current module further includes a sixth transistor (T46), a seventh transistor (T47) and a second capacitor (C42), wherein the control electrode of the sixth transistor (T46) is coupled to the second end of the second capacitor (C42), the first electrode is coupled to the second electrode of the first transistor (T44), and the second electrode is coupled to the first electrode of the first transistor (T44); the first end of the second capacitor (C42) is grounded; the control electrode of the seventh transistor (T47) receives a constant current scanning signal, and the first electrode receives a constant current display signal.

[0018] In particular, the comparison unit further includes an eighth transistor (T53 or T63), and the PWM signal generation module further includes a ninth transistor (T56 or T66), a tenth transistor (T52 or T62), and an eleventh transistor (T55 or T67), wherein the control electrode of the eighth transistor (T53 or T63) receives the scan signal, the second electrode receives the second display signal, and the first electrode is coupled to the second electrode of the second transistor (T51 or T61); wherein the voltage value of the second display signal is the inverse of the voltage value of the first display signal; the control electrode of the ninth transistor (T56 or T66) receives the scan signal, the second electrode receives the second display signal, and the first electrode is coupled to the second electrode of the second transistor (T51 or T61); wherein the voltage value of the second display signal is the inverse of the voltage value of the first display signal; The first electrode of the tenth transistor (T52 or T62) receives a charging signal, the first electrode receives a high level, and the second electrode is coupled to the first electrode of the second transistor (T51 or T61); and the control electrode of the eleventh transistor (T55 or T67) receives the enable signal, the first electrode is coupled to the second electrode of the second transistor (T51 or T61), and the second electrode is grounded.

[0019] Particularly, the constant current module further comprises a first current bias unit, a first end of the first current bias unit receives a high level, and a second end is coupled to the first electrode of the first transistor (T54).

[0020] Particularly, the constant current module further comprises a twelfth transistor (T65), the control electrode of the twelfth transistor (T65) receives the enable signal, the first electrode receives a high level, and the second electrode is coupled to the first electrode of the first transistor (T64).

[0021] In particular, the constant current module further includes a thirteenth transistor (T610), a fourteenth transistor (T611), a fifteenth transistor (T69), a sixteenth transistor (T68) and a third capacitor (C62), wherein the control electrode of the thirteenth transistor (T610) receives the charging signal, the first electrode receives a high level, and the second electrode is coupled to the second electrode of the twelfth transistor (T65); the control electrode of the fourteenth transistor (T611) receives the reset signal, the first electrode is coupled to the second electrode of the twelfth transistor (T65), and the second electrode is coupled to the second end of the third capacitor (C62); the first end of the third capacitor (C62) is grounded; the control electrode of the fifteenth transistor (T69) is coupled to the second end of the third capacitor (C62), the first electrode is coupled to the second electrode of the twelfth transistor (T65), and the second electrode is coupled to the first electrode of the first transistor (T64); the control electrode of the sixteenth transistor (T68) receives the constant current scanning signal, the first electrode is coupled to the first electrode of the first transistor (T64), and the second electrode receives the constant current display signal.

[0022] In particular, the comparison unit includes a seventeenth transistor (T21) and an eighteenth transistor (T22), and the PWM signal generation module includes a fourth capacitor (C21); the first end of the fourth capacitor (C21) is configured to receive the reference signal; the control electrode of the seventeenth transistor (T21) is coupled to the second end of the fourth capacitor (C21), and the first electrode is coupled to the control electrode of the switching transistor (204); the control electrode of the eighteenth transistor (T22) is coupled to the control electrode of the seventeenth transistor (T21) as the input end of the comparison unit, the second electrode receives a high level, and the first electrode is coupled to the seventeenth transistor (T21) ) is coupled as the output terminal of the comparison unit; the eighteenth transistor (T22) is of opposite type to the seventeenth transistor (T21), and is connected in series to form an inverter amplifier, and the second electrode of the seventeenth transistor (T21) is grounded; the PWM signal generating module includes a nineteenth transistor (T23), the first electrode of the nineteenth transistor (T23) receives the second display signal, the second electrode of the nineteenth transistor (T23) is coupled to the control electrodes of the seventeenth transistor (T21) and the eighteenth transistor (T22), and the control electrode of the nineteenth transistor (T23) receives the scanning signal, wherein the voltage value of the second display signal is the opposite of the voltage value of the first display signal.

[0023] Particularly, the constant current module further comprises a second current bias unit, a first end of the second current bias unit receives a high level, and a second end is coupled to the first electrode of the first transistor (T24).

[0024] In particular, the PWM signal generating module includes a twentieth transistor (T33) and a fifth capacitor (C31), wherein the control electrode of the twentieth transistor (T33) receives the scanning signal, the first electrode is coupled to the second end of the fifth capacitor (C31), and the second electrode receives the second display signal; the first end of the fifth capacitor (C31) is grounded; wherein the voltage value of the second display signal is equal to the voltage value of the first display signal; the PWM signal generating module also includes a buffer, the input end of the buffer is coupled to the output end of the comparison unit, and the output end is coupled to the control electrode of the switching transistor; the comparison unit includes a twenty-first (T31), a twenty-second (T32), a twenty-third (T36), and a twenty-fourth transistor (T37), wherein the twenty-first transistor (T31) is of the same type as the twenty-second transistor (T32) and of the opposite type to the twenty-third transistor (T36), the control electrode and the second electrode of the twenty-first transistor (T31) are coupled to the control electrode of the twenty-second transistor (T32), the first electrode receives a high level; therefore, the second electrode of the twenty-second transistor (T32) receives a high level, and the second electrode of the twenty-third transistor (T36) receives a high level. One electrode is coupled to the input end of the buffer and serves as the output end of the comparison unit; the twenty-third transistor (T36) is of the same type as the twenty-fourth transistor (T37), the control electrode receives the reference signal, and the second electrode is coupled to the first electrode of the twenty-fourth transistor (T37); the control electrode of the twenty-fourth transistor (T37) is coupled to the second electrode of the twentieth transistor, the first electrode is coupled to the second electrode of the twenty-third transistor (T36), and the first electrode is coupled to the first electrode of the twenty-second transistor (T32); the comparison unit also includes a twenty-fifth transistor (T38), a twenty-sixth transistor (T35), and a first current source; the twenty-fifth transistor (T38) is of the same type as the twenty-sixth transistor (T35), the control electrode and the second electrode are coupled to the control electrode of the twenty-sixth transistor (T35), the first electrode is coupled to the second electrode of the twenty-sixth transistor (T35) and is grounded; the first electrode of the twenty-sixth transistor (T35) is coupled to the second electrode of the twenty-third transistor (T36); one end of the first current source is connected to a high level, and the other end is coupled to the second electrode of the twenty-fifth transistor (T38).

[0025] The present application also provides a display device, which includes a Micro-LED pixel array, wherein the pixel array includes any one of the pixel circuits described above, and also includes a timing control circuit, a gate drive circuit, and a data drive circuit; wherein the gate drive circuit is coupled to the timing control circuit and the pixel array, and is configured to provide an enable signal, a scan signal, and a reference signal to the pixel array under the control of the timing control circuit; the data drive circuit is coupled to the timing control circuit and the pixel array, and is configured to provide a first display signal to the pixel array under the control of the timing control circuit.

[0026] The present application also proposes an electronic device, comprising the display device as described above.

[0027] The driving method disclosed in this application combines the advantages of high precision, long effective luminescence time, and good stability. It can be applied to traditional displays such as OLED and new display circuits such as Micro-LED, and has a wide range of uses. In addition, by adopting the solution of this application, it is possible to effectively increase the proportion of pixel circuit luminescence time while improving the accuracy of grayscale control, thereby improving the display quality of the pixel circuit, improving the operating efficiency of the display device, reducing the display driver power consumption, and achieving better performance of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0029] Figure 1A is a schematic structural diagram of an active display pixel circuit according to an embodiment of the present application;

[0030] Figure 1B This is a schematic diagram of the working timing of the pixel circuit during the light-emitting period according to one embodiment of the present application;

[0031] Figure 1C is a schematic diagram of the working timing of a pixel circuit during the light-emitting period according to another embodiment of the present application;

[0032] Figure 2A is a structural diagram of an active display pixel circuit according to an embodiment of the present application;

[0033] Figure 2B yes Figure 2A A schematic diagram of a sub-frame operation timing of a pixel circuit shown;

[0034] Figure 3A is a structural diagram of an active display pixel circuit according to another embodiment of the present application;

[0035] Figure 3B yes Figure 3A A schematic diagram of a sub-frame operation timing of a pixel circuit shown;

[0036] Figure 4A is a structural diagram of an active display pixel circuit according to yet another embodiment of the present application;

[0037] Figure 4B yes Figure 4A A schematic diagram of a sub-frame operation timing of a pixel circuit shown;

[0038] Figure 5A is a structural diagram of an active display pixel circuit according to another embodiment of the present application;

[0039] Figure 5B yes Figure 5A A schematic diagram of a sub-frame operation timing of a pixel circuit shown;

[0040] Figure 6A is a structural diagram of an active display pixel circuit according to yet another embodiment of the present application;

[0041] Figure 6B is a schematic diagram of the working timing of a pixel circuit for one frame when the first display data is an octal number;

[0042] Figure 6C is a schematic diagram of the working timing of a pixel circuit for one frame when the first display data is a hexadecimal number; and

[0043] Figure 7 Schematic diagram of the structure of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0045] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0046] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit the unconnected elements from being unable to communicate. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in the communication between the two elements or at least the number of outputs provided, and is not intended to limit the two elements to communicating only with the signals shown in the figure.

[0047] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be single crystal silicon, hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carrier is an electron or a hole, it can be divided into an N-type transistor and a P-type transistor. Its control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, the corresponding second electrode may be the source or drain of the field effect transistor, and the control electrode or the third electrode may be the gate; when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, the corresponding second electrode may be the emitter or collector of the bipolar transistor, and the control electrode or the third electrode may be the base. The transistor may be manufactured using single crystal silicon, amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS process or CMOS process. The following description takes the high level as the effective level as an example for explanation.

[0048] The PWM display drive method maintains a constant light-emitting current and changes the average current level within a frame by controlling the duration of the light-emitting current. The average current level determines the brightness of the light-emitting element, reflecting different display grayscales.

[0049] The display time of a frame can be divided into multiple subframes (SF), and the number of subframes is related to the display data. Each frame of display data can be divided into multiple parts, one of which is written into each subframe. Each display grayscale can correspond to a unique part of the above display data. Therefore, a subframe can be understood as the time between two consecutive write operations on the same row in each frame. In addition, in addition to the time occupied by the write operation, the subframe also includes the longest possible light-emitting time of the light-emitting element in the subframe. The light-emitting time in each subframe is related to the data written into each subframe, and the integral of the light-emitting time of each subframe corresponds to the display grayscale within one frame of the row.

[0050] In common digital PWM drive methods, display data is a binary number. The value of each bit of this binary number determines whether the light-emitting element in the corresponding subframe emits light. In other words, within each subframe, the light-emitting element can be either illuminated or not (0 or 1). Subframes corresponding to the same bit of the binary number in different rows have the same duration. Furthermore, the maximum possible duration of light emission in adjacent subframes in the same row is two times the duration of the other. For example, the duration of light emission in the subframe corresponding to the least significant bit (LSB) of the display data is half the duration of the adjacent subframe.

[0051] However, existing digital PWM drive methods require a large number of display data bits, resulting in long addressing and programming times and insufficient effective luminescence duration. In display applications where simultaneous luminescence is performed while writing row by row, the large number of subframes means that most of the time within a frame is dedicated to writing, resulting in a very short luminescence duration. Even at high frame rates, the writing time can exceed the entire frame, making digital PWM drive methods unsuitable for high frame rate requirements.

[0052] In order to solve the technical problems in the above-mentioned PWM driving method and its display circuit, the present application proposes a new pulse width modulation (PWM) driving method and an active display pixel circuit, which can increase the luminous time and improve the grayscale control accuracy, thereby enabling the active display device to achieve better performance.

[0053] Figure 1A 1 is a schematic diagram of the structure of an active display pixel circuit according to an embodiment of the present application.

[0054] According to one embodiment, Figure 1A As shown, the pixel circuit 100 may include a PWM signal generating module 101, which is coupled to the gate driving circuit and configured to receive an enable signal, a scan signal and a reference signal. Display pixels in the same row share the same scan and reference signals.

[0055] According to one embodiment, the PWM signal generation module 101 may also be coupled to the data driving circuit and configured to receive a first display signal. According to one embodiment, the PWM signal generation module 101 may include a comparison unit 111 configured to compare the first display signal with a reference signal and output a PWM signal based on the comparison result to control the light emission of the pixel circuit 100.

[0056] According to one embodiment, the pixel circuit 100 may further include a light emitting element 103 and a switch module 104. According to the embodiment of the present application, the light emitting element 103 may include OLED, LED, Micro-LED, QLED, etc., depending on actual needs.

[0057] According to one embodiment, the pixel circuit 100 may further include a constant current module 102 coupled to the light-emitting element 103 via a switch module 104 under the control of a PWM signal output by the PWM signal generating module 101, and configured to provide a constant luminous current to the light-emitting element 103. The constant current module 102 may also be coupled to a gate drive circuit and configured to receive an enable signal. According to other embodiments of the present application, the constant current module 102 may have a certain degree of adjustability to meet the different relationships between the luminous efficiency and luminous current of the R, G, and B sub-pixel LEDs, thereby maintaining the highest operating efficiency for each sub-pixel.

[0058] According to one embodiment, J columns of pixel circuits can receive a first display signal from a data driver circuit. Accordingly, the data driver circuit can include J digital-to-analog converter (DAC) units, with pixel circuits in the same column sharing one DAC unit, where J is an integer greater than 0. These DAC units are configured to receive initial display data expressed in X-bit L-ary form. Each DAC unit converts the L-ary initial display data into corresponding Y-bit K-ary first display data and outputs the first display signal to an input terminal of the comparison unit 111, where X is an integer greater than or equal to 2, Y is an integer greater than 0, and X is greater than Y; L and K are integers greater than or equal to 2, and L is less than K. In this way, the time of a frame is correspondingly divided into Y subframes. According to one embodiment of the present application, the write time for each bit of the first display data can be the same, which can be referred to as a unit write time. Therefore, compared with traditional digital PWM drive methods, the write time of a frame is shortened from X unit write times to Y unit write times.

[0059] According to an embodiment, the first display signal mentioned above may include a corresponding voltage generated based on the value of each bit of the first display data, or may be other electrical signals, depending on actual needs.

[0060] According to one embodiment of the present application, in order to ensure that the light-emitting element can emit the maximum light-emitting time or zero in each subframe, the maximum value of the reference signal should be less than the maximum possible value of the first display signal, and the minimum value of the reference signal should be greater than the minimum possible value of the first display signal.

[0061] According to one embodiment of the present application, both the first display signal and the reference signal described above can be transformed based on other factors such as the specific device structure, for example, to amplify or reduce the signal accordingly. Whether it is the first display signal and its transformation or the reference signal and its transformation, the original signals before transformation must satisfy the aforementioned relative relationship. The specific signal input to the display pixel circuit is determined based on actual needs. For ease of description, the reference signal transformation and the first original signal transformation that are transformed based on actual needs will be referred to as the reference signal and the first original signal together with the original signals.

[0062] Depending on the embodiment, the first display data may correspond to the total time the light-emitting element is illuminated in a frame, or the total time the light-emitting element is not illuminated in a frame, depending on the specific circuit structure. In the following embodiment of the present application, the first display data corresponds to the total time the light-emitting element is not illuminated in each frame, and the first display signal in each subframe corresponds to the time the light-emitting element is not illuminated in each subframe.

[0063] Figure 1B : This is a schematic diagram of the working timing of the pixel circuit during the luminous time according to an embodiment of the present application. According to an embodiment, within a subframe, I rows of pixel circuits can receive a reference signal from the gate drive circuit, where I is an integer greater than 0. The duration of the reference signal in different subframes is different, and the duration of the reference signal in each subframe is the same as the longest possible luminous time length of the subframe. According to an embodiment of the present application, the reference signal can be as follows: Figure 1B The ramp signal shown in .

[0064] According to an embodiment of the present application, theoretically, the comparison unit 111 can generate a PWM signal that changes the conduction state of the light emitting element 103 at the moment when the magnitude relationship between the reference signal and the first display signal changes.

[0065] Figure 1C : is a schematic diagram of the working timing of the pixel circuit during the luminous time according to another embodiment of the present application. According to a more preferred embodiment, the reference signal can be a monotonic signal that changes discontinuously with time, for example, it can be a step signal, such as Figure 1C When the reference signal is a step signal, even when the magnitude relationship between the reference signal and the first display signal changes, there is a large voltage difference between the two. Therefore, the comparison unit 111 can quickly output a PWM signal that changes the conduction state of the light-emitting element 103, thereby reducing the error in the light-emitting time and grayscale.

[0066] According to an embodiment of the present application, the step signal serving as a reference signal may include different potentials generated by (K-1) equal-height steps in each subframe, each step having the same duration, and the longest luminous time in each subframe being evenly divided into (K-1) parts.

[0067] According to one embodiment of the present application, the grayscale of a frame is the sum of the grayscales of each subframe, and the actual luminous time of each subframe can be related to the first display data and the unit luminous time corresponding to the subframe. According to an embodiment of the present application, the unit luminous time of each subframe can be expressed as the luminous time T corresponding to the minimum data bit (LSB) of the initial display data. LSB The product of K raised to the power of 0 to (Y-1).

[0068] Figure 2A FIG. 1 is a schematic diagram of an active display pixel circuit structure according to an embodiment of the present application. Figure 2A As shown, the pixel circuit 200 may include a PWM signal generating module 201, a constant current module 202, a light emitting element 203, and a switch transistor 204 coupled to the PWM signal generating module 201. The PWM signal generating module 201 may include a comparison unit 211.

[0069] According to one embodiment of the present application, the PWM signal generating module 201 may include transistors T21, T22, and T23. Figure 2A As shown, comparison unit 211 may include transistors T21 and T22 of opposite types connected in series to form an inverter amplifier. Transistors T21 and T23 are N-type transistors, while T22 is a P-type transistor. The control electrode of transistor T21 is coupled to the control electrode of transistor T22. The second electrode of transistor T22 receives a high voltage level VGH, and the first electrode is coupled to the first electrode of transistor T21. The second electrode of transistor T21 is grounded.

[0070] According to one embodiment, for the pixels in the i-th row and the j-th column, the first electrode of the transistor T23 receives the second display signal DATA corresponding to the pixel one by one. PWM [y], y is any integer from 1 to Y, its second electrode is coupled to the control electrodes of transistors T21 and T22, and its control electrode is configured to receive the scan signal SCAN of the row where the pixel is located PWM [i].

[0071] According to an embodiment of the present application, the PWM signal generating module 201 may further include a capacitor C21, a first terminal of which receives a reference signal such as a step reference signal V STEP [y], the second end is coupled to the second electrode of the transistor T23 at point A, ie, the input end of the comparison unit 211, and is coupled to the control electrodes of the transistors T21 and T22.

[0072] According to an embodiment of the present application, the constant current module 202 may include a transistor T24. The control electrode of the transistor T24 receives an enable signal EM, and the second electrode is coupled to the first electrode of the transistor 204 to control the conduction of the light-emitting element 203. The first electrode of the transistor T24 receives a constant current signal to provide a light-emitting current to the light-emitting element 203. According to an embodiment of the present application, the first electrode of the transistor T24 may be coupled to a current bias unit outside the pixel circuit 200 that receives a high level VGH.

[0073] According to one embodiment of the present application, the pixel circuit 200 may further include a switching transistor 204, whose control electrode is coupled to the output terminal of the comparison unit 211 at point B, that is, coupled to the first electrode of the transistor T22 and the first electrode of the transistor T21, receives the PWM signal output by the PWM signal generation module 201, and the first electrode is coupled to the second electrode of the transistor T24, and the second electrode is coupled to the anode of the light-emitting element 203. According to an embodiment of the present application, the transistors T24 and 204 may be N-type transistors.

[0074] According to an embodiment of the present application, the transistors T21 , T22 , T23 , T24 , T25 and 204 may be made of thin film transistors (TFTs), for example, low temperature polycrystalline oxide thin film transistors (LTPO TFTs).

[0075] Figure 2B Shown Figure 2A The sub-frame operation timing diagram of the pixel circuit is shown in FIG. According to one embodiment of the present application, the pixel circuit 200 in the i-th row and the j-th column includes a writing phase and a light emitting phase in a sub-frame.

[0076] In the write phase, Figure 2A and 2B As shown, the transistor T23 receives the scan signal SCAN of the i-th row. PWM [i] and conducts, the second display signal DATA PWM [y] is transmitted to the input terminal A of the comparison unit 211. At this time, the potential at point A is DATA PWM [y].

[0077] According to one embodiment, the present application adopts a mechanism of writing and emitting light row by row, so after each row receives a high level of the overscan signal, that is, after each row of pixels receives the second display signal of the yth subframe, the light-emitting stage is turned on.

[0078] In the light-emitting stage, the enable signal EM jumps to a high level, turning on the transistor T24. At this time, the reference signal V is provided at the first end of the capacitor C21. STEP [y], the potential V at the second terminal of capacitor C21 IN The corresponding value becomes V IN [i,j]=V STEP [y]+DATA PWM [y], as input to the comparison unit 211.

[0079] According to one embodiment of the present application, when the potential V IN[i, j] is less than the threshold voltage of transistor T21, which means that the second display signal is less than the reference signal. At this time, T21 is turned off and T22 is turned on. The high level VGH is transmitted to the switch transistor 204 through the turned-on transistor T22, turning on the switch transistor 204. At this time, the transistor T24 is also turned on, and the light-emitting element 203 can receive the constant light-emitting current I from the current bias unit outside the pixel circuit 200. LED [i,j], starts to glow.

[0080] According to one embodiment, when V IN [i, j] is greater than the threshold voltage of T21, at this time T21 is turned on, T22 is turned off, the PWM signal generating module 201 outputs a low level to the switching transistor 204, the transistor 204 is turned off, the light-emitting element 203 no longer emits light, and the light-emitting phase of this subframe ends.

[0081] According to one embodiment, the EM signal will maintain a high level for a fixed period of time, corresponding to the longest possible luminous time in a subframe. When the longest possible luminous time in the subframe ends, V IN [i, j] is still smaller than the threshold voltage of T21. At this time, the EM signal jumps to a low level, and the transistor T24 is turned off, so that the light-emitting element 203 no longer emits light, and the light-emitting phase of this subframe ends.

[0082] According to one embodiment of the present application, the reference signal may be a step signal with a potential range of 0-6 V. According to an embodiment of the present application, if Figure 2A In the illustrated pixel circuit 200, the comparison unit 211 does not directly determine the magnitude relationship between the reference signal and the first display signal, or the difference between the two. Instead, it processes the first display signal to obtain a second display signal, and performs a comparison operation based on the sum of the reference signal and the second display signal. Therefore, the amplitude of the second display signal can be a signal generated by adjusting the first display signal according to actual needs, for example, it can include a voltage value that is the inverse of the first display signal. For example, in this embodiment, the first display signal can be a signal with a potential range of -0.5 to 6.5V, and the second display signal can be a signal with a potential range of -6.5 to 0.5V.

[0083] According to an embodiment of the present application, since the reference signal is a step signal, the step potential increases step by step. In order to achieve normal comparison between the reference signal and the second display signal, it is necessary to meet the following conditions: regardless of whether the second display signal corresponds to the luminous or non-luminous time of the light-emitting element, the maximum value of the reference signal should be less than the inverse of the minimum possible value of the second display signal, and the minimum value of the reference signal should be greater than the inverse of the maximum possible value of the second display signal. Specifically, the condition shown in formula (1) needs to be met:

[0084]

[0085] Figure 3A FIG. 1 is a structural diagram of an active display pixel circuit according to another embodiment of the present application. Figure 3A As shown, the pixel circuit 300 may include a PWM signal generating module 301 , a constant current module 302 , a light emitting element 303 , and a switching transistor 304 .

[0086] The PWM signal generating module 301 may include transistors T31, T32, T33, T35, T36, T37 and T38, as well as a buffer 312 and a bias current source I bias The comparison unit 311 may include a dual-input operational amplifier circuit formed by transistors T31, T32, T35, T36, T37, and T38, for comparing the second display signal with the reference signal. According to an embodiment of the present application, transistors T31 and T32 may be P-type transistors, and T33, T35, T36, T37, and T38 may be N-type transistors. The PWM signal generation module may further include a capacitor C31.

[0087] like Figure 3A As shown, the control electrode of transistor T31 is coupled to the control electrode of transistor T32 and the second electrode of T31, and the first electrode is coupled to the second electrode of transistor T32 to receive the high level VGH. The first electrode of transistor T32 is coupled to the second electrode of transistor T37 and the control electrode of transistor T34 at point B, which is the output end of the comparison unit. The first electrode of transistor T37 is coupled to the second electrode of transistor T36, and the control electrode is coupled to the first electrode of transistor T33. The first electrode of transistor T36 is coupled to the second electrode of transistor T31, and the control electrode receives the reference signal V STEP [y] The second electrode of the transistor T33 receives the second display signal DATA PWM [y], the control electrode receives the scan signal SCAN PWM [i], the first electrode is coupled to the second end of the capacitor C31. The first end of the capacitor C31 is grounded.

[0088] According to an embodiment of the present application, the input end of the buffer 312 is coupled to the first electrode of the transistor T32 and the second electrode of the transistor T37 at point B, and the output end is coupled to the control electrode of the switching transistor 304 to output a PWM signal to the switching transistor 304 .

[0089] The control electrode of transistor T38 is coupled to its second electrode and the control electrode of transistor T35, and the first electrode is coupled to the second electrode of transistor T35 and grounded. The first electrode of transistor T35 is coupled to the second electrode of transistor T36 to form a current mirror. The second electrode of transistor T38 is also coupled to the bias current source I biasThe coupling provides a bias current for the transistor T35 to maintain the normal operation of the comparison unit.

[0090] According to one embodiment of the present application, the bias current source I bias It may be located outside the pixel circuit 300 .

[0091] According to one embodiment of the present application, the constant current module 302 may include a transistor T34 and a current bias unit. The control electrode of the transistor T34 receives an enable signal EM, and the second electrode is coupled to the first electrode of the switch transistor 304 to control the conduction state of the light-emitting element 303. The first electrode of the transistor T34 is coupled to the current bias unit and receives a constant current signal to provide a light-emitting current to the light-emitting element 303.

[0092] According to one embodiment of the present application, the pixel circuit 300 may further include a switching transistor 304, whose control electrode is coupled to the output end of the buffer 312 in the PWM signal generating module 301 and receives the PWM signal output by the PWM signal generating module 301. The first electrode of the switching transistor 304 is coupled to the second electrode of the transistor T34, and the second electrode is coupled to the anode of the light-emitting element 303. According to an embodiment of the present application, the transistors T34 and 304 may be N-type transistors.

[0093] According to one embodiment of the present application, the transistors T31 - T39 may be fabricated from CMOS devices.

[0094] Figure 3B yes Figure 3A The sub-frame operation timing diagram of the pixel circuit is shown in FIG. According to one embodiment of the present application, the pixel circuit 300 in the i-th row and the j-th column includes a writing phase and a light emitting phase in a sub-frame.

[0095] According to one embodiment, during the write phase, as Figure 3A and 3B As shown, the transistor T33 receives the scan signal SCAN of the i-th row. PWM [i] and conducts, the second display signal DATA PWM [y] is transmitted to one of the input terminals of the comparison unit 311, ie, the control terminal of the transistor T37.

[0096] According to one embodiment, in the light emitting stage, the enable signal EM jumps to a high level, the transistor T34 is turned on, and the control electrode of the transistor T36 receives the reference signal V STEP [y], the control electrode of the transistor T37 receives the second display signal DATA PWM [y], for the second display signal DATA PWM [y] and the reference signal V STEP[y] are compared and the PWM signal is output to the control electrode of the switching transistor 304 through the buffer 312 .

[0097] According to one embodiment of the present application, when the second display signal is greater than the reference signal, the current flowing through the transistor T36 increases, the current flowing through the transistor T37 decreases, and the transistor T32 is turned on and receives the high level VGH. At this time, the potential at point B is greater than the common mode level V CM , the buffer 312 outputs a high level VGH as a PWM signal to the switching transistor 304 to turn on the transistor 304, and the light emitting element 303 receives a constant current I from the current bias unit outside the pixel circuit 300. LED [i,j], starts to glow.

[0098] According to one embodiment, when the second display signal is smaller than the reference signal, the current flowing through the transistor T36 decreases, the current flowing through the transistor T37 increases, and the potential at point B is smaller than the common-mode level V of the buffer 312. CM , the buffer 312 outputs the ground level to the switch transistor 304, the switch transistor 304 is turned off, the light emitting element 303 no longer emits light, and the light emitting phase of this subframe ends.

[0099] According to one embodiment, the EM signal remains high for a fixed period of time, corresponding to the longest possible luminous duration within a subframe. When the second display signal remains greater than the reference signal at the end of the longest possible luminous duration within the subframe, the EM signal transitions to a low level, turning off transistor T34 and disabling light-emitting element 303, thus ending the luminous phase of the subframe.

[0100] According to one embodiment of the present application, the reference signal may be a stepped signal with a potential range of 0-6V. To ensure proper comparison between the reference signal and the second display signal, the amplitude of the second display signal may be adjusted according to actual needs and may also be equal to the voltage value of the first display signal. For example, in this embodiment, the second display signal may be a signal with a potential range of -0.5 to 6.5V.

[0101] According to one embodiment of the present application, Figure 3A In the illustrated pixel circuit 300, to ensure that the reference signal is less than the second display signal and the light-emitting element emits light, the current flowing through transistor T36 must be greater than the current flowing through transistor T37 to ensure that the potential at point B is greater than the common-mode level of buffer 312. In other words, the bias voltage of transistor T36 must be greater than the bias voltage of transistor T37, and the difference between the two must be greater than the common-mode level of buffer 312. Therefore, in this embodiment, the difference between the maximum possible value of the second display signal and the maximum value of the reference signal must be greater than the common-mode level V of buffer 312. CMSimilarly, in order to satisfy the requirement that the reference signal is greater than the second display signal to turn off the light-emitting element, the difference between the minimum possible value of the second display signal and the minimum value of the reference signal should be less than the common mode level V CM Specifically, the conditions shown in formula (2) need to be met:

[0102]

[0103] Figure 4A FIG. 1 is a structural diagram of an active display pixel circuit according to another embodiment of the present application. Figure 4A As shown, the pixel circuit 400 located in the i-th row and the j-th column may include a PWM signal generating module 401 , a constant current module 402 , a light emitting element 403 and a switching transistor 404 .

[0104] According to one embodiment of the present application, the PWM signal generating module 401 may include a transistor T41 as a comparison transistor. The control electrode of the transistor T41 is coupled to the second electrode of the transistor T43 at point A, and is coupled to the second end of the capacitor C41. The first end of the capacitor C41 receives the reference signal V STEP [y] The control electrode of the transistor T43 receives the scan signal SCAN PWM [i], the first electrode receives the second display signal DATA PWM [y] The control electrode of transistor T42 receives the charging signal CHG, the first electrode receives the high level VGH, and the second electrode is coupled to the first electrode of transistor T41 at point B, serving as the output of the PWM signal generating module 401 and coupled to the control electrode of transistor T44. Transistors T41, T42, and T43 may be N-type transistors.

[0105] According to one embodiment of the present application, the constant current module 402 may include transistors T44 and T45. The control electrode of the transistor T44 receives the enable signal EM, and the first electrode is coupled to the second electrode of the transistor T45. The control electrode of the transistor T45 receives the enable signal EM, and the first electrode receives the high level VGH, so as to provide the constant light-emitting current I required by the light-emitting element 403. LED [i,j].

[0106] The constant current module 402 may further include transistors T46, T47, and a capacitor C42. The first electrode of transistor T46 is coupled to the second electrode of transistor T45, the second electrode is coupled to the first electrode of transistor T44, and the control electrode is coupled to point D with transistor T47 and the second end of capacitor C42. The first end of capacitor C42 is grounded. The control electrode of transistor T47 receives a constant current scan signal SCAN. PAM , the first electrode receives the constant current display signal DATA PAM .

[0107] According to one embodiment of the present application, the pixel circuit 400 may further include a switching transistor 404, whose control electrode is coupled to the first electrode of the transistor T41 at point B, receives the PWM signal output by the PWM signal generating module 401, the first electrode is coupled to the second electrode of the transistor T44, and the second electrode is coupled to the anode of the light-emitting element 403.

[0108] Figure 4B yes Figure 4A According to an embodiment of the present application, the pixel circuit 400 in the i-th row and j-th column includes a charging phase, a writing phase, and a light emitting phase in a sub-frame.

[0109] In the charging phase, the enable signal EM is at a low level and the charging signal CHG is at a high level. At this time, the transistor T42 is turned on and the potential V IN At this time, VGH-V th(42) , to realize the charging of point B in the PWM signal generating module 401. th(42) This operation can reduce the correlation between the previous and next display frames.

[0110] In the write phase, the enable signal EM continues to be low, the charge signal CHG jumps to a low level, and the scan signal SCAN PWM [i] jumps to high level. At this time, transistor T43 is turned on and receives the second display signal DATA PWM [y].

[0111] According to an embodiment of the present application, the constant current module 402 may further include transistors T46, T47 and C42 for adjusting the light emitting current of the light emitting element 403. At this time, the transistor T47 receives the constant current scanning signal DATA PAM And conduction, the potential of point D becomes DATA PAM .

[0112] In the light-emitting stage, the enable signal EM jumps to a high level, and other signals are all low levels. At this time, transistors T45 and T44 are turned on, point B is at a high level, the switch transistor 404 is turned on, and the light-emitting element 403 starts to emit light. According to one embodiment of the present application, the light-emitting current I required by the light-emitting element 403 at this time is LED [i, j] is provided by the conducting transistor T46, and the conduction condition of the transistor T46 is affected by the constant current display signal DATA PAM According to other embodiments of the present application, the light-emitting currents of different columns may be different, and the light-emitting currents of the same column may be the same to meet display requirements.

[0113] When EM jumps to high level, point A receives the reference signal V STEP [y], reference signal VSTEP [y] is a step waveform that increases with time. According to one embodiment, if before EM jumps to a low level, when the reference signal V STEP [y] jumps to a certain step, making V IN -V th(41) >0, transistor T41 is turned on, and point B discharges through transistor T41, where V th(41) is the threshold voltage of the transistor T41. The switching transistor 404 is turned off, and the light emitting element 403 stops emitting light.

[0114] According to one embodiment of the present application, if before EM jumps to a low level, V IN -V th1 Since the enable signal EM is always less than zero, transistor T41 is turned off, and point B maintains a high level, which is transmitted to the control electrode of switching transistor 404. At this time, since the enable signal EM jumps to a low level, transistor T44 is turned off, and light-emitting element 403 stops emitting light. In other words, pixel circuit 400 continues to emit light for the longest possible emission time in this subframe until the writing phase of the next subframe begins.

[0115] According to one embodiment of the present application, the reference signal may be a step signal with a potential range of 0-6V. Figure 4A In the illustrated pixel circuit 400, the comparison unit cannot directly compare the reference signal and the first display signal or determine the difference between the two. Instead, the comparison unit processes the first display signal to obtain a second display signal, and performs the comparison operation based on the sum of the reference signal and the second display signal. Therefore, the amplitude of the second display signal can be a signal generated by adjusting the first display signal according to actual needs, for example, it can include a voltage value that is the inverse of the first display signal. For example, in this embodiment, the first display signal can be a signal with a potential range of -0.5 to 6.5 V, and the second display signal can be a signal with a potential range of -6.5 to 0.5 V.

[0116] According to one embodiment of the present application, Figure 4A In the pixel circuit 400 shown in FIG. 4 , in order to satisfy the requirement that the reference signal is less than the second display signal so that the light emitting element emits light, it is necessary to ensure that DATA PWM [y]+V STEP [y]>V th(41) That is, in this embodiment, the sum of the minimum possible value of the second display signal and the maximum value of the reference signal should be less than the threshold voltage V th(41) Similarly, in order to satisfy the requirement that the reference signal is greater than the second display signal to turn off the light emitting element, the sum of the maximum possible value of the second display signal and the minimum value of the reference signal should be greater than the threshold voltage V th Specifically, the conditions shown in formula (3) need to be met:

[0117]

[0118] According to embodiments of the present application, when a pixel circuit uses a single transistor as a comparator to compare signals, the threshold voltage of the transistor may drift, potentially affecting the grayscale control accuracy of the PWM signal generation module. Therefore, a more preferred embodiment includes a threshold voltage compensation circuit and a corresponding signal driving method.

[0119] Figure 5A FIG. 1 is a structural diagram of an active display pixel circuit according to another embodiment of the present application. Figure 5A As shown, the pixel circuit 500 located in the i-th row and the j-th column may include a PWM signal generating module 501 , a constant current module 502 , a light emitting element 503 and a switching transistor 504 .

[0120] According to an embodiment of the present application, the PWM signal generating module 501 may include transistors T51, T52, T53, T55, and T56. The control electrode of transistor T51 is coupled to the second electrode of transistor T56 and the second end of capacitor C51, the first electrode is coupled to the second electrode of transistor T52 to point B, and the second electrode is coupled to the first electrode of transistor T55, serving as a comparison transistor. The control electrode of transistor T56 receives a reset signal RST, and the first electrode is coupled to the first electrode of transistor T51 to point B. The control electrode of transistor T52 receives a charging signal CHG, and the second electrode receives a high level. The control electrode of transistor T53 receives a scan signal SCAN of the row where the pixel is located. PWM [i], the second electrode receives the second display signal DATA PWM [y], the first electrode is coupled to the second electrode of the transistor T51 and the first electrode of the transistor T55. The control electrode of the transistor T55 receives the enable signal EM, and the second electrode is grounded. The first end of the capacitor C51 receives the reference signal V STEP [y] According to an embodiment of the present application, the transistors T51 , T52 , T53 , T55 , and T56 may be N-type transistors.

[0121] According to an embodiment of the present application, the constant current module 502 may include a transistor T54 and a current bias unit. The control electrode of the transistor T54 receives an enable signal EM, and the second electrode is coupled to the first electrode of the switch transistor 504 to control the conduction of the light-emitting element 503. The first electrode of the transistor T54 is coupled to the current bias unit to receive a constant current signal to provide a light-emitting current I to the light-emitting element 503. LED [i,j].

[0122] According to one embodiment of the present application, the pixel circuit 500 may further include a switching transistor 504, whose control electrode is coupled to the first electrode of the comparison transistor T51 at point B and receives the PWM signal output by the PWM signal generation module 501. The first electrode of the switching transistor 504 is coupled to the second electrode of the transistor T54, and the second electrode is coupled to the anode of the light-emitting element 503. According to an embodiment of the present application, the transistors T54 and 504 may be N-type transistors.

[0123] According to an embodiment of the present application, the transistors T51 , T52 , T53 , T54 , T55 , T56 , and 504 may be N-type thin film transistors (TFTs).

[0124] Figure 5B yes Figure 5A According to an embodiment of the present application, the pixel circuit 500 in the i-th row and j-th column includes a charging phase, a writing and compensation phase, a recharging phase, and a light emitting phase in a subframe.

[0125] In the reset phase, the enable signal EM is low, the charge signal CHG is high, and the reset signal RST is high. At this time, the transistor T52 is turned on, the transistor T56 is turned on, and the potential V IN At this time, VGH-V th(m) , to achieve the reset of point A in the PWM signal generating module 501. th(m) is the threshold voltage of the transistor, and m is the number of the transistor. According to the embodiment of the present application, m here can be one of 52 or 56, and the potential of point A is the difference between the high level VGH and the larger threshold voltage of transistor T52 or T56. Taking transistor T52 as an example, when the threshold voltage of transistor T52 is greater than that of transistor T56, the potential of point A at this time is VGH-Vth(52). This operation can reduce the correlation between the previous and next display frames, and prepare for the subsequent writing of the threshold voltage compensation voltage of transistor T51.

[0126] During the writing and compensation phase, the enable signal EM continues to be low, the charging signal CHG jumps to a low level, and the reset signal RST remains high. PWM [i] jumps to high level.

[0127] In SCAN PWM When [i] is high, in the pixel circuit 500, transistors T56 and T53 are turned on. Since the potential V IN VGH-V th(52) , at this time, transistor T51 is also turned on. Transistor T53 receives the second display signal DATA PWM [y], the potential of point A is DATAPWM [y]+V th(51) Among them, V th(51) is the threshold voltage of transistor T51.

[0128] In the pre-charge phase, the charging signal CHG is at a high level, the enable signal EM and the reset signal RST are at a low level. At this time, the transistor T52 is turned on again, and the potential of point B is charged to VGH-V th(52) Among them, V th(52) is the threshold voltage of transistor T52.

[0129] During the light-emitting phase, the enable signal EM jumps to a high level, and all other signals are at a low level. At this time, transistor T55 is turned on, and transistor T54 is turned on. Since point B is charged to a high level during the pre-charging phase, the switching transistor 504 is also turned on, and the light-emitting element 503 begins to emit light.

[0130] When EM jumps to high level, point A receives the reference signal VS TEP [y], reference signal V STEP [y] is a step waveform that increases with time. Specifically, the potential at point A becomes V IN =DATA PWM [y]+V th(51) +V STEP [y], where V th(51) is the threshold voltage of transistor T51.

[0131] According to one embodiment, if before EM jumps to a low level, when the reference signal V STEP [y] jumps to a certain step, making V IN -V th(51) >0, that is, DATA PWM [y]+V STEP When [y]>0, transistor T51 is turned on, and point B is discharged through transistors T51 and T55. When the potential of point B is less than the threshold voltage of switching transistor 504, switching transistor 504 is turned off, and light emitting element 503 stops emitting light.

[0132] According to one embodiment of the present application, if before EM jumps to a low level, V IN -V th(51) Always less than zero, that is, DATA PWM [y]+V STEP When [y] is less than 0, transistor T51 is turned off, and point B maintains a high level and transmits the signal to the control electrode of switching transistor 504. At this point, because enable signal EM transitions to a low level, transistor T54 is turned off, and light-emitting element 503 stops emitting light. In other words, pixel circuit 500 continues emitting light for the longest possible duration within the subframe until the next subframe begins.

[0133] According to one embodiment of the present application, the reference signal may be a step signal with a potential range of 0-6V. Figure 5A In the illustrated pixel circuit 500, the comparison unit does not directly determine the magnitude relationship between the reference signal and the first display signal, or the difference between the two. Instead, it processes the first display signal to obtain a second display signal, and performs a comparison operation based on the sum of the reference signal and the second display signal. Therefore, the amplitude of the second display signal can be a signal generated by adjusting the first display signal according to actual needs, for example, it can include a voltage value that is the inverse of the first display signal. For example, in this embodiment, the first display signal can be a signal with a potential range of -0.5 to 6.5 V, and the second display signal can be a signal with a potential range of -6.5 to 0.5 V.

[0134] According to one embodiment of the present application, Figure 5A In the pixel circuit 500 shown in FIG. 1 , in order to satisfy the requirement that the reference signal is less than the second display signal so that the light emitting element emits light, it is necessary to ensure that DATA PWM [y]+V STEP [y]>0, that is, in this embodiment, the sum of the minimum possible value of the second display signal and the maximum value of the reference signal should be less than 0. Similarly, in order to satisfy the requirement that the reference signal is greater than the second display signal to turn off the light-emitting element, the sum of the maximum possible value of the second display signal and the minimum value of the reference signal should be greater than 0. Specifically, the condition shown in formula (4) needs to be satisfied:

[0135]

[0136] Figure 6A FIG. 1 is a structural diagram of an active display pixel circuit according to another embodiment of the present application. Figure 6A As shown, the pixel circuit 600 may include a PWM signal generating module 601 , a constant current module 602 , a light emitting element 603 and a switching transistor 604 .

[0137] like Figure 6A As shown, the PWM signal generating module 601 may include transistors T61, T62, T63, T66, and T67. Among them, the transistor T61 is used as a comparison transistor, the control electrode and the second end of the capacitor C61 and the second electrode of the transistor T66 are coupled to point A, the first electrode and the second electrode of the transistor T62 are coupled at point B, and the second electrode is coupled to the first electrode of the transistor T67. The first end of the capacitor C61 receives the reference signal V STEP[y] The control electrode of transistor T66 receives the reset signal RST, and the first electrode is coupled to the first electrode of transistor T61 and the second electrode of transistor T62 to point B. The control electrode of transistor T62 receives the charge signal CHG, and the first electrode receives the high level VGH. The control electrode of transistor T63 receives the scan signal SCAN. PWM [i], the second electrode receives the second display signal DATA PWM [y], a first electrode is coupled to a second electrode of transistor T61. A control electrode of transistor T67 receives an enable signal EM, and a second electrode is grounded. According to an embodiment of the present application, transistors T61, T62, T63, T66, and T67 may be N-type transistors.

[0138] According to one embodiment of the present application, the constant current module 602 may include transistors T64, T65, and T69. The control electrode of transistor T64 receives an enable signal EM, the second electrode is coupled to the first electrode of the switch transistor 604, and the first electrode is coupled to the second electrode of transistor T69, thereby controlling the conduction of the light-emitting element 603 together with the switch transistor 604. The first electrode of transistor T69 and the second electrode of transistor T65 are coupled to point E. The control electrode of transistor T65 receives the enable signal EM, and the first electrode receives a high voltage VGH to provide the constant light-emitting current I required by the light-emitting element 603. LED [i, j] According to one embodiment of the present application, the transistors T64 , T65 and T69 may be N-type transistors.

[0139] Optionally, the constant current module 602 may further include transistors T610 and T611, and a capacitor C62. The second terminal of capacitor C62 is coupled to the control electrode of transistor T69 at point D, and the first terminal is grounded. The control electrode of transistor T611 receives a reset signal RST, the first terminal is coupled to the second terminals of transistors T610 and T65 at point E, and the second terminal is coupled to the second terminal of capacitor C62 at point D. The control electrode of transistor T610 receives a charge signal CHG, and the first terminal receives a high voltage level VGH.

[0140] Optionally, the constant current module 602 may further include a transistor T68. The control electrode of the transistor T68 receives a constant current scan signal SCAN. PAM The second electrode receives the constant current display signal DATA PAM The first electrode is coupled to the second electrode of the transistor T69. The constant current display signal received by the transistor T68 can adjust the control electrode voltage of the transistor T69, thereby changing the light-emitting current I transmitted by the light-emitting elements 603 in different rows. LED The size of [i, j] satisfies the needs of the device. The light-emitting current I of the light-emitting element 603 LEDThe size of [i, j] may be different in different columns and the same in the same column. According to an embodiment of the present application, T68, T610, and T611 may be pure N-type transistors.

[0141] According to one embodiment of the present application, the pixel circuit 600 may further include a switching transistor 604, whose control electrode is coupled to the first electrode of the transistor T61 at point B and receives the PWM signal output by the PWM signal generating module 601. The first electrode of the switching transistor 604 is coupled to the second electrode of the transistor T64, and the second electrode is coupled to the anode of the light-emitting element 603.

[0142] According to an embodiment of the present application, some or all transistors in the pixel circuit 600 may include pure N-type thin film transistors (TFTs).

[0143] According to an embodiment of the present application, the second display signal is a signal obtained by processing the first display signal. The first display signal includes a voltage or other electrical signal corresponding to each value of each bit of the first display data. Each bit of the first display data corresponds to the actual non-luminous time within the longest possible luminous time of the subframe. Taking the octal data 1420 as an example, the first display data written in each subframe is 1420 in sequence. The octal display data corresponding to the actual luminous time of the pixel circuit 600 in these subframes is 6357 (from the highest bit, that is, 8 3 to 8 0 ).

[0144] According to one embodiment of the present application, when displaying a grayscale number, that is, when the initial display data received by the pixel circuit 600 is a 10-bit binary number, the 10-bit binary data is first converted into a 4-bit octal number by a digital-to-analog converter (not shown), so that the corresponding frame will be divided into 4 sub-frames. Since 3-bit octal data corresponds to 9-bit binary data, the 10-bit binary data corresponds to a 4-bit octal number after conversion, the most significant bit of which corresponds to the most significant bit in the binary number (rather than each bit in other octal numbers corresponding to 3 bits in the binary number). In other words, the value of the most significant bit in the 4-bit octal number can only be 0 or 1.

[0145] According to one embodiment, the unit luminous time of each subframe is increased step by step from low to high according to the corresponding first display data. For octal display data, the relative relationship between the unit luminous time of each subframe is 8 3 , 8 2 , 8 1 , 8 0 (from most significant bit to least significant bit).

[0146] According to one embodiment, the relative relationship between the possible longest luminous time of each subframe in a frame is 8 3 *(2-1), 8 2*(8-1), 8 1 *(8-1), 8 0 *(8-1)(from most significant bit to least significant bit).

[0147] Figure 6B FIG2 is a schematic diagram showing the operation timing of a pixel circuit in one frame when the first display data is an octal number. It is understood that for the sake of convenience, the luminous duration of each subframe in the figure is only for illustration.

[0148] like Figure 6B As shown, the first three bits of the octal display data from low to high correspond to each of the subframes SF0-SF2, which can display eight grayscales. The first display data of each subframe can be any one of 0-7. The subframe corresponding to the highest bit in the octal display data can only display two grayscales. The first display data of this subframe can only be 0 or 1. The total luminous time of one frame is T EM(8) It can be expressed by formula (5).

[0149] T EM(8) =(8 3 T LSB )·x3+(8 2 T LSB )·x2+(8 1 T LSB )·x1+(8 0 T LSB )·x0 (5)

[0150] Among them, T LSB The length of the luminous time in the smallest subframe when the display frame is divided into multiple subframes according to binary data. x corresponds to the data corresponding to the luminous time in different subframes, where x3 is 6, x2 is 3, x1 is 5, and x0 is 7.

[0151] According to one embodiment of the present application, Figure 6B As shown, the operation of the pixel circuit 600 in the i-th row and j-th column in the y-th subframe specifically includes the following stages:

[0152] Phase (1): Reset phase

[0153] In the reset phase, the enable signal EM is low, the charge signal CHG is high, and the reset signal RST is high. At this time, transistors T62 and T610 are turned on, transistors T66 and T611 are turned on, and the potential V at point A is IN At this time, VGH-V th(m1) , the potential at point D is VGH-V th(m2) , to achieve the reset of point A in the PWM signal generating module 601 and point D in the constant current module 602. th(m1) and Vth(m2) are the threshold voltages of the transistors, m1 and m2 are the numbers of the transistors. According to the embodiment of the present application, taking m1 as 62 as an example, m1 can be either 62 or 66, and the potential of A can be the difference between the high level VGH and the larger threshold voltage of the transistor T62 or T66. When the threshold voltage of the transistor T62 is greater than that of the transistor T66, the potential of point A is VGH-V th(62) According to one embodiment of the present application, V th(m1) and V th(m2) It can be the threshold voltage V of transistors T62 and T610 th(62) and V th(610) This operation can reduce the correlation between the previous and next display frames, and prepare for the subsequent writing of the threshold voltage compensation voltage into the transistors T61 and T69.

[0154] Phase (2): Writing and compensation phase

[0155] During the writing and compensation phase, the enable signal EM continues to be low, the charging signal CHG jumps to a low level, and the reset signal RST remains high. PWM [i] jumps to high level.

[0156] In SCAN PWM When [i] is high, in the pixel circuit 600, transistors T66 and T63 are turned on. Since the potential V IN VGH-V th(62) , at this time, transistor T61 is also turned on. Transistor T63 receives the second display signal DATA PWM [y], the potential of point A is DATA PWM [y]+V th(61) .

[0157] According to an embodiment of the present application, the constant current module 602 may further include a transistor T68 for adjusting the light emitting current of the light emitting element 603. At this time, the transistors T611 and T68 are turned on, the transistor T69 is turned on under the high level control of the D point, and the transistor T68 receives the constant current display signal DATA PAM , the potential of point D becomes DATA PAM +V th(69) .

[0158] According to an embodiment of the present application, the potential at point A is determined by the scan signal SCAN. PWM [i] Control, complete the data writing of the second display signal and the preparation for threshold voltage compensation, and point D also performs constant current data writing and threshold voltage compensation preparation at this stage, so that the threshold voltage compensation of the transistor T69 that drives the light-emitting element 603 to emit light is more accurate.

[0159] Stage (3): Pre-charge stage

[0160] In the pre-charge phase, the charging signal CHG is high, the enable signal EM and the reset signal RST are low. At this time, the transistors T62 and T610 are turned on again, and the potential of point B is charged to VGH-V th(62) , the potential of point E is charged to VGH-V th(610) Among them, V th(62) and V th(610) are the threshold voltages of transistors T62 and T610 respectively.

[0161] Stage (4): Luminous Stage

[0162] In the light-emitting stage, the enable signal EM jumps to a high level, and other signals are all low levels. At this time, transistors T67 and T65 are turned on, and transistor T64 is turned on. Since point B is charged to a high level in the pre-charging stage, the switching transistor 604 is also turned on, and the light-emitting element 603 begins to emit light. According to one embodiment of the present application, the light-emitting current ILED[i, j] required by the light-emitting element 603 is provided by the turned-on transistor T69, and the conduction condition of the transistor T69 is affected by the constant current display signal DATA received by the transistor T68. PAM impact.

[0163] When EM jumps to high level, point A receives the reference signal V STEP [y], reference signal V STEP [y] is the step waveform V that grows with time STEP [y](t)=nΔV STEP , n is an integer from 0 to (K-1). Wherein, V STEP [y] There are n=(K-1) possible step potentials, for example 8-1=7. At this time, the potential at point A becomes V IN =DATA PWM [y]+V th(61) +V STEP [y].

[0164] According to one embodiment, if before EM jumps to a low level, when the reference signal VSTEP[y] jumps to a certain step, V IN -V th(61) >0, that is, DATA PWM [y]+V STEP When [y]>0, transistor T61 is turned on, and the B point is discharged through transistors T61 and T67. Switching transistor 604 is turned off, and light emitting element 603 stops emitting light.

[0165] According to one embodiment of the present application, if before EM jumps to a low level, V IN -V th(61) Always less than zero, that is, DATA PWM [y]+V STEP When [y] is less than 0, transistor T61 remains off, and point B maintains a high level, transmitting the signal to the control electrode of switch transistor 604. At this point, because enable signal EM transitions to a low level, transistor T64 is turned off, and light-emitting element 603 ceases to emit light. In other words, at this point, the first display data does not limit the light-emitting time of pixel circuit 600 in this subframe. Pixel circuit 600 continues to emit light for the longest possible light-emitting time in this subframe until the next subframe begins.

[0166] According to an embodiment of the present application, the threshold voltages of the transistors T61 and T69 may gradually increase as the pixel circuit 600 operates. The threshold voltages of the transistors T62, T66, T610, and T611 may be equal and constant.

[0167] According to one embodiment of the present application, the reference signal may be a step signal with a potential range of 0-6V. Figure 6A In the illustrated pixel circuit 600, the comparison unit cannot directly determine the magnitude relationship between the reference signal and the first display signal, or the difference between the two. Instead, the comparison operation is performed based on the sum of the reference signal and the second display signal. Therefore, the amplitude of the second display signal can be a signal generated by adjusting the first display signal according to actual needs. For example, it can include a voltage value that is the inverse of the first display signal. For example, in this embodiment, the first display signal can be a signal with a potential range of -0.5 to 6.5 V, and the second display signal can be a signal with a potential range of -6.5 to 0.5 V.

[0168] According to one embodiment of the present application, Figure 6A In the pixel circuit 600 shown in FIG. 1 , in order to satisfy the requirement that the reference signal is less than the second display signal so that the light emitting element emits light, it is necessary to ensure that DATA PWM [y]+V STEP [y]>0, that is, in this embodiment, the sum of the minimum possible value of the second display signal and the maximum value of the reference signal should be less than 0. Similarly, in order to satisfy the requirement that the reference signal is greater than the second display signal to turn off the light-emitting element, the sum of the maximum possible value of the second display signal and the minimum value of the reference signal should be greater than 0. Specifically, the condition shown in formula (6) needs to be satisfied:

[0169]

[0170] According to one embodiment of the present application, if the 10-bit binary initial display data received by the pixel circuit 600 is converted into a 3-bit hexadecimal number through a digital-to-analog converter (not shown), then the corresponding frame will be divided into 3 sub-frames. Since 2-bit hexadecimal data corresponds to 8-bit binary data, the 10-bit binary data corresponds to a 3-bit hexadecimal number after conversion, and the most significant bit corresponds to the 2 most significant bits in the binary number (rather than each bit in other hexadecimal numbers corresponding to 4 bits in the binary number). That is, the value of the most significant bit in the 3-bit hexadecimal number can only be any one of 0-3.

[0171] According to one embodiment, the unit luminous time of each subframe is increased step by step from low to high according to the corresponding first display data. For hexadecimal display data, the relative relationship between the unit luminous time of each subframe is 16 2 , 16 1 , 16 0 (from most significant bit to least significant bit).

[0172] According to an embodiment of the present application, the relative relationship between the longest possible luminous time of each subframe in a frame is 16 2 *(4-1), 16 1 *(16-1), 16 0 *(16-1)(from most significant bit to least significant bit).

[0173] Figure 6C FIG1 is a schematic diagram of the working timing of a pixel circuit in one frame when the first display data is a hexadecimal number. It is understood that for the sake of convenience, the luminous duration of each subframe in the figure is only for illustration.

[0174] According to the embodiment of the present application, the first display data written into each subframe is 170 in sequence. The hexadecimal display data corresponding to the actual light-emitting time of the pixel circuit 600 in these subframes is D8E (from the highest bit, that is, 16 2 to 16 0 ).

[0175] like Figure 6C As shown, the first two bits of the hexadecimal display data from low to high correspond to each of the subframes SF0 and SF1, which can represent 16 grayscales. The first display data of each subframe can be any of 0-E. The subframe corresponding to the highest bit in the hexadecimal display data can only represent 4 grayscales. The first display data of this subframe can be any of 0-3. The total luminous time of one frame is T EM(16) The expression can be expressed by formula (7).

[0176] T EM(16) =(16 2 T LSB)·x2+(16 1 T LSB )·x1+(16 0 T LSB )·x0 (7)

[0177] Among them, T LSB The length of the luminous time in the smallest subframe when the display frame is divided into multiple subframes according to binary data. x corresponds to the data corresponding to the luminous time in different subframes, where x2 is D, x1 is 8, and x0 is E.

[0178] According to an embodiment of the present application, when the base number of the multi-base PWM driving method is higher and the number of subframes included in each display frame is smaller, the time used for writing the first display data line by line in each display frame is shorter and the time used for luminescence is longer.

[0179] According to the above and other embodiments of the present application, other devices, such as P-type oxide LTPS TFT, complementary oxide LTPO TFT, CMOS, etc., can be used to design a PWM signal generating module and a constant current module respectively, and other circuits can be derived from this to realize the functions of the above-mentioned PWM signal generating module and constant current module.

[0180] According to other embodiments of the present application, the comparison unit in the PWM signal generation module and the constant current module of the pixel circuit may also include other circuit structures, which are not limited by the present application and are determined according to actual production needs. The devices are not limited to N-type TFT transistors or certain transistors and may also include LTPO, CMOS and other devices.

[0181] Figure 7 FIG. 1 is a schematic diagram of a display device structure according to an embodiment of the present application. Figure 7 As shown, the present application also provides a display device, including a Micro-LED display pixel array with I rows and J columns, wherein the Micro-LED display pixel array includes any of the display pixel circuits described above. The display device also includes a timing control circuit (Timing Control, TCON), a gate driver circuit (Gate Driver), and a data driver circuit (Data Driver).

[0182] According to an embodiment of the present application, the timing control circuit receives external data and control signals, and transmits a display signal to the data driver circuit and a scan signal and a reference signal to the gate driver circuit. According to one embodiment of the present application, pixel circuits in the same column of the pixel array receive their respective first display signals from the data driver circuit, and pixel circuits in the same row of the pixel array receive their respective scan signals and reference signals from the gate driver circuit.

[0183] According to an embodiment of the present application, the pixel circuit of the display device may be driven by using the aforementioned multi-bit pulse width modulation driving method.

[0184] The present application also provides an electronic device, which also includes the display device as described above.

[0185] The present application also provides a new pulse width modulation driving method, which may include the following operations.

[0186] Initial display data is received. For one display pixel circuit, the initial display data of each frame includes an X-bit binary number, where X is an integer greater than or equal to 2.

[0187] The initial display data is converted into first display data, where the first display data includes a K-based number having Y bits, where Y is an integer greater than 0, X is greater than Y, and K is an integer greater than or equal to 3; wherein each frame is divided into Y subframes, each subframe includes a writing time and a maximum luminous time, the writing time in each subframe is the same, and the maximum luminous time in each subframe is at least a function of K and a sequence number y of the subframe, where y is an integer greater than 0 and less than or equal to Y.

[0188] The first display data is written into the pixel circuit during the writing time of each subframe.

[0189] A light-emitting element in a pixel circuit is driven to emit light based on first display data; wherein an actual light-emitting time of the light-emitting element in each subframe is at least a function of a value of a corresponding bit of the first display data, K, and a sequence number y of the subframe, and the actual light-emitting time is less than or equal to a maximum light-emitting time of the subframe.

[0190] A first display signal is compared with a reference signal in each subframe. When the relative relationship between the first display signal and the reference signal changes, the light-emitting state of the light-emitting element changes. The first display signal includes a voltage corresponding to each bit value of the first display data.

[0191] The driving method disclosed in this application has the advantages of high precision, long effective luminescence time, and good stability. It has a wide range of uses and can be applied to active organic light-emitting diode displays (AM-OLED) and active micro-diode displays (AM-Micro-LED) to form smartphone displays, flat panel displays, and TV display products; it can also be applied to micro-displays with single-crystal silicon CMOS backplanes to form wearable watch displays, helmet displays, and glasses displays, serving diverse scenarios such as augmented reality / virtual reality / fused reality (AR / VR / MR). In addition, by adopting the solution of this application, the luminescence time ratio of the pixel circuit can be effectively improved while improving the accuracy of grayscale control, thereby improving the display quality of the pixel circuit, improving the working efficiency of the display device, reducing the display drive power consumption, and enabling the display device to achieve better performance.

[0192] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A pulse width modulation driving method for a display pixel circuit, comprising: receiving initial display data, wherein for a display pixel circuit, the initial display data of each frame includes an X-bit binary number, where X is an integer greater than or equal to 2; Converting the initial display data into first display data, the first display data comprising a K-ary number having Y bits, wherein Y is an integer greater than 0, X is greater than Y, and K is an integer greater than or equal to 3; wherein each frame is divided into Y subframes, each subframe comprising a writing time and a maximum light-emitting time, the maximum light-emitting time in each subframe being a function of at least K and a sequence number y of the subframe, wherein y is an integer greater than 0 and less than or equal to Y; writing the first display data into the display pixel circuit during the writing time of each subframe; and A light-emitting element in the display pixel circuit is driven to emit light based on the first display data; wherein the actual light-emitting time of the light-emitting element in each subframe is at least a function of the value of the corresponding bit of the first display data, K, and the sequence number y of the subframe, and the actual light-emitting time is less than or equal to the longest light-emitting time of the subframe.

2. The driving method according to claim 1, further comprising A first display signal is compared with a reference signal in each subframe, and when the relative relationship between the first display signal and the reference signal changes, the light-emitting state of the light-emitting element changes, wherein the first display signal includes a voltage corresponding to each bit value of the first display data.

3. The driving method according to claim 2, wherein When the reference signal is a step signal, the reference signal includes (K-1) steps of equal height, each step has the same duration, and the longest luminous time of each subframe is evenly divided into (K-1) parts.

4. An active display pixel circuit comprising: Light-emitting element; a PWM signal generating module configured to receive a scanning signal, a reference signal, and a first display signal, and output a PWM signal; wherein the PWM signal generating module includes a comparing unit configured to compare the first display signal with the reference signal, and to cause the PWM signal to jump when a comparison result changes; a constant current module, configured to provide a light-emitting current to the light-emitting element; A switch module is coupled between the constant current module and the light emitting element; the PWM signal generating module is configured to control the on or off state of the switch module using the PWM signal; The first display data includes a K-ary number having Y bits, where Y is an integer greater than 0 and K is an integer greater than or equal to 3, and the first display signal includes a voltage corresponding to each bit value of the first display data; For the display pixel circuit, one frame includes Y subframes, each subframe includes a writing time and a maximum light-emitting time, and the maximum light-emitting time in each subframe is at least a function of K and a sequence number y of the subframe, where y is an integer greater than 0 and less than or equal to Y; During the writing time of each subframe, the PWM signal generating module is configured to receive the first display signal; The actual light emitting time of the light emitting element in each subframe is at least a function of the first display signal, K and the sequence number y of the subframe, and the actual light emitting time is less than or equal to the longest light emitting time of the subframe.

5. The pixel circuit according to claim 4, wherein When the reference signal is a step signal, the reference signal includes (K-1) steps of equal height, each step has the same duration, and the longest luminous time of each subframe is evenly divided into (K-1) parts. The pixel circuit according to claim 4 , wherein The switch module includes a switch transistor (204, 304, 404, 504 or 604), a control electrode of the switch transistor (204, 304, 404, 504 or 604) is coupled to the PWM signal generating module to receive the PWM signal, a first electrode is coupled to the constant current module, and a second electrode is coupled to the anode of the light-emitting element; and The constant current module includes a first transistor (T24, T34, T44, T54 or T64), the control electrode of the first transistor (T24, T34, T44, T54 or T64) receives an enable signal, the first electrode is configured to receive a high level, and the second electrode is coupled to the first electrode of the switching transistor (204, 304, 404, 504 or 604).

7. The pixel circuit according to claim 6, wherein The comparison unit in the PWM signal generating module includes a second transistor (T41, T51 or T61) and a first capacitor (C41, C51 or C61); a first end of the first capacitor (C41, C51 or C61) is configured to receive the reference signal; a control electrode of the second transistor (T41, T51 or T61) is coupled to the second end of the first capacitor (C41, C51 or C61), and a first electrode is coupled to the control electrode of the first transistor (T44, T54 or T64).

8. The pixel circuit according to claim 7, wherein The comparison unit further includes a third transistor (T43), wherein the control electrode of the third transistor (T43) receives the scanning signal, the first electrode receives the second display signal, and the second electrode is coupled to the control electrode of the second transistor (T41) and the second end of the first capacitor (C41); wherein, The voltage value of the second display signal is the opposite of the voltage value of the first display signal; The PWM signal generating module further comprises a fourth transistor (T42), wherein a control electrode of the fourth transistor (T42) receives a charging signal, a first electrode receives a high level, and a second electrode is coupled to the first electrode of the second transistor (T41).

9. The pixel circuit according to claim 8, wherein The constant current module further includes a fifth transistor (T45), a control electrode of the fifth transistor (T45) receiving the enable signal, a first electrode receiving a high level, and a second electrode coupled to the first electrode of the first transistor (T44).

10. The pixel circuit according to claim 9, wherein The constant current module further includes a sixth transistor (T46), a seventh transistor (T47) and a second capacitor (C42), wherein The control electrode of the sixth transistor (T46) is coupled to the second end of the second capacitor (C42), the first electrode is coupled to the second electrode of the fifth transistor (T45), and the second electrode is coupled to the first electrode of the first transistor (T44); the first end of the second capacitor (C42) is grounded; The control electrode of the seventh transistor (T47) receives a constant current scanning signal, and the first electrode receives a constant current display signal.

11. The pixel circuit according to claim 7, wherein The comparison unit further includes an eighth transistor (T53 or T63), and the PWM signal generation module further includes a ninth transistor (T56 or T66), a tenth transistor (T52 or T62), and an eleventh transistor (T55 or T67), wherein The control electrode of the eighth transistor (T53 or T63) receives the scan signal, the second electrode receives the second display signal, and the first electrode is coupled to the second electrode of the second transistor (T51 or T61); wherein, The voltage value of the second display signal is the opposite of the voltage value of the first display signal; The control electrode of the ninth transistor (T56 or T66) receives a reset signal, the first electrode is coupled to the first electrode of the second transistor (T51 or T61), and the second electrode is coupled to the control electrode of the second transistor (T51 or T61) and the second end of the first capacitor (C51 or C61); The control electrode of the tenth transistor (T52 or T62) receives a charging signal, the first electrode receives a high level, and the second electrode is coupled to the first electrode of the second transistor (T51 or T61); and The control electrode of the eleventh transistor (T55 or T67) receives the enable signal, the first electrode is coupled to the second electrode of the second transistor (T51 or T61), and the second electrode is grounded.

12. The pixel circuit according to claim 11, wherein The constant current module further includes a first current bias unit, a first end of which receives a high level, and a second end of which is coupled to a first electrode of the first transistor (T54).

13. The pixel circuit according to claim 11, wherein The constant current module further includes a twelfth transistor (T65), a control electrode of the twelfth transistor (T65) receiving the enable signal, a first electrode receiving a high level, and a second electrode coupled to the first electrode of the first transistor (T64).

14. The pixel circuit according to claim 13, wherein The constant current module further includes a thirteenth transistor (T610), a fourteenth transistor (T611), a fifteenth transistor (T69), a sixteenth transistor (T68) and a third capacitor (C62), wherein The control electrode of the thirteenth transistor (T610) receives the charging signal, the first electrode receives a high level, and the second electrode is coupled to the second electrode of the twelfth transistor (T65); The control electrode of the fourteenth transistor (T611) receives the reset signal, the first electrode is coupled to the second electrode of the twelfth transistor (T65), and the second electrode is coupled to the second end of the third capacitor (C62); the first end of the third capacitor (C62) is grounded; The control electrode of the fifteenth transistor (T69) is coupled to the second end of the third capacitor (C62), the first electrode is coupled to the second electrode of the twelfth transistor (T65), and the second electrode is coupled to the first electrode of the first transistor (T64); The control electrode of the sixteenth transistor (T68) receives a constant current scanning signal, the first electrode is coupled to the first electrode of the first transistor (T64), and the second electrode receives a constant current display signal.

15. The pixel circuit according to claim 6, wherein The comparison unit includes a seventeenth transistor (T21) and an eighteenth transistor (T22), and the PWM signal generation module includes a fourth capacitor (C21); the first end of the fourth capacitor (C21) is configured to receive the reference signal; the control electrode of the seventeenth transistor (T21) is coupled to the second end of the fourth capacitor (C21), and the first electrode is coupled to the control electrode of the switching transistor (204); the control electrode of the eighteenth transistor (T22) is coupled to the control electrode of the seventeenth transistor (T21) as the input end of the comparison unit, the second electrode receives a high level, and the first electrode is coupled to the first electrode of the seventeenth transistor (T21) as the output end of the comparison unit; the eighteenth transistor (T22) and the seventeenth transistor (T21) are of opposite types and are connected in series to form an inverter amplifier, and the second electrode of the seventeenth transistor (T21) is grounded; The PWM signal generating module includes a nineteenth transistor (T23), a first electrode of the nineteenth transistor (T23) receiving a second display signal, a second electrode thereof coupled to control electrodes of the seventeenth transistor (T21) and the eighteenth transistor (T22), and a control electrode thereof receiving the scan signal, wherein: The voltage value of the second display signal is the opposite of the voltage value of the first display signal.

16. The pixel circuit according to claim 6, wherein The constant current module further includes a second current bias unit, a first end of which receives a high level, and a second end of which is coupled to the first electrode of the first transistor (T24).

17. The pixel circuit according to claim 6, wherein The PWM signal generating module includes a twentieth transistor (T33) and a fifth capacitor (C31), wherein a control electrode of the twentieth transistor (T33) receives the scanning signal, a first electrode is coupled to the second end of the fifth capacitor (C31), and a second electrode receives a second display signal; a first end of the fifth capacitor (C31) is grounded; wherein, The voltage value of the second display signal is equal to the voltage value of the first display signal; The PWM signal generating module further includes a buffer, wherein an input end of the buffer is coupled to an output end of the comparison unit, and an output end of the buffer is coupled to a control electrode of the switching transistor; The comparison unit includes a twenty-first (T31), a twenty-second (T32), a twenty-third (T36), and a twenty-fourth transistor (T37), wherein The twenty-first transistor (T31) is of the same type as the twenty-second transistor (T32) and of a type opposite to the twenty-third transistor (T36). The control electrode and the second electrode of the twenty-first transistor (T31) are coupled to the control electrode of the twenty-second transistor (T32), and the first electrode receives a high level. Therefore, the second electrode of the twenty-second transistor (T32) receives a high level, and the first electrode is coupled to the input terminal of the buffer to serve as the output terminal of the comparison unit. The twenty-third transistor (T36) and the twenty-fourth transistor (T37) are of the same type, a control electrode receives the reference signal, and a second electrode is coupled to the first electrode of the twenty-fourth transistor (T37); the control electrode of the twenty-fourth transistor (T37) is coupled to the second electrode of the twentieth transistor, the first electrode is coupled to the second electrode of the twenty-third transistor (T36), and the first electrode is coupled to the first electrode of the twenty-second transistor (T32); The comparison unit further includes a twenty-fifth transistor (T38), a twenty-sixth transistor (T35) and a first current source. The twenty-fifth transistor (T38) is of the same type as the twenty-sixth transistor (T35), and its control electrode and second electrode are coupled to the control electrode of the twenty-sixth transistor (T35). The first electrode is coupled to the second electrode of the twenty-sixth transistor (T35) and is grounded. The first electrode of the twenty-sixth transistor (T35) is coupled to the second electrode of the twenty-third transistor (T36). One end of the first current source is connected to a high level, and the other end is coupled to the second electrode of the twenty-fifth transistor (T38).

18. A display device comprising a Micro-LED display pixel array, wherein the Micro-LED display pixel array comprises any one of the display pixel circuits according to claims 4-17, and further comprises a timing control circuit, a gate drive circuit, and a data drive circuit; The gate driving circuit is coupled to the timing control circuit and the pixel array, and is configured to provide an enable signal, a scan signal and a reference signal to the pixel array under the control of the timing control circuit; the data driving circuit is coupled to the timing control circuit and the pixel array, and is configured to provide a first display signal to the pixel array under the control of the timing control circuit.

19. An electronic device comprising the display device according to claim 18.

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