Method for optimizing transmission signal of memory, memory controller and electronic device

Abstract

The present application relates to a method for optimizing the transmission signal of a memory, a memory controller and an electronic device, and belongs to the field of electronic technology. The method for optimizing the transmission signal of the memory includes: adjusting the value of the DCA register, and generating a DQS clock signal and a DQ data signal based on the adjusted value of the DCA register, wherein the DQS clock signal and the DQ data signal are transmission signals between the memory and the memory controller; obtaining the maximum eye diagram of the correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal; using the value of the DCA register corresponding to the maximum eye diagram as the optimal value of the DCA register; and generating a new DQS clock signal and a new DQ data signal based on the optimal value of the DCA register. The transmission signal quality of the memory is optimized by adjusting the value of the DCA register, thereby improving the read and write reliability of the memory.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and specifically relates to a method for optimizing a transmission signal of a memory, a memory controller, and an electronic device. Background Art

[0002] Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM) is a memory whose data rate is twice the clock rate, referred to as DDR memory. Figure 1 As shown in the figure, in the DDR system, the transmission data DQ is synchronized with the rising and falling edges of the clock DQS respectively. The memory controller interacts with the DDR memory through the physical layer interface (PHY). The interface between the PHY and the DDR memory is referred to as the DDR interface. The PHY can be built into the memory controller. The reliability of the DDR interface reading and writing determines the reliability of the memory controller.

[0003] As the operating frequency of the central processing unit (CPU) increases, the frequency of the DDR interface is also required to be higher and higher. Higher frequencies are prone to cause problems such as signal duty cycle distortion and clock jitter, which cause a more and more significant reduction in read and write reliability. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a method for optimizing the transmission signal of a memory, a memory controller, and an electronic device to improve the transmission signal quality of the memory, thereby improving the read and write reliability of the memory.

[0005] The embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a method for optimizing a transmission signal of a memory, comprising: adjusting the value of a DCA register, and generating a DQS clock signal and a DQ data signal based on the adjusted value of the DCA register, wherein the DQS clock signal and the DQ data signal are transmission signals between the memory and a memory controller; obtaining a maximum eye diagram of correctly sampled data by sampling data transmitted by the DQ data signal using the DQS clock signal; using the value of the DCA register corresponding to the maximum eye diagram as the optimal value of the DCA register; and generating a new DQS clock signal and a new DQ data signal based on the optimal value of the DCA register.

[0007] In the above implementation scheme, a set of DCA registers that can improve the phase relationship of the system clock is provided in the DDR5 (5th generation DDR) specification. The value of the DCA register is related to the phase of the system clock signal in the DDR memory, and the system clock signal is used to generate the transmission signal of the signal of the DDR memory (including DQS clock signal and DQ data signal). The change of the value of the DCA register will cause the phase of the system clock signal to change, thereby changing the high level time and low level time of the DQS clock signal and the DQ data signal; therefore, the present application adopts a relatively novel approach, by adjusting the value of the DCA register, and taking the value of the DCA register corresponding to the maximum eye diagram as the optimal value of the DCA register, so that the optimal duty cycle setting can be obtained to improve the transmission quality of the DQS clock signal and the DQ data signal, thereby improving the read and write reliability of the memory.

[0008] In combination with a possible implementation method of the first aspect, adjusting the value of the DCA register includes: adjusting the value of the DCA register multiple times, and accordingly, obtaining a maximum eye diagram of correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal, including: obtaining an eye diagram corresponding to each adjustment of the value of the DCA register to obtain multiple eye diagrams; and screening out an eye diagram with the largest eye width from the multiple eye diagrams.

[0009] In the above implementation scheme, by continuously adjusting the value of the DCA register, each time the value of the DCA register is adjusted, an eye diagram width that can correctly sample data can be obtained. After multiple adjustments, multiple eye diagrams can be obtained, from which the eye diagram with the largest eye width (referred to as the maximum eye diagram) is screened out, and the value of the DCA register corresponding to the maximum eye diagram is used as the optimal value of the DCA register. In this way, the optimal duty cycle setting can be obtained, which can solve the problem of duty cycle distortion of DQ and DQS signals and improve the read and write speed and reliability of the memory.

[0010] In combination with a possible implementation manner of the embodiment of the first aspect, the value of the DCA register is related to the phase of a system clock signal inside the memory, and the system clock signal is used to generate the DQS clock signal and the DQ data signal; the system clock signal includes 2 nphase clock signals, each phase clock signal has an independent DCA register, and n is an integer greater than or equal to 2; adjusting the value of the DCA register, including: adjusting the value of the DCA register corresponding to the first type of phase clock signal to obtain the optimal value of the DCA register corresponding to the first type of phase clock signal, wherein the first type of phase clock signal is a phase clock signal related to the clock jitter of the DQS clock signal and the DQ data signal; based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment, adjusting the value of the DCA register corresponding to the second type of phase clock signal to obtain the optimal value of the DCA register corresponding to the second type of phase clock signal, wherein the second type of phase clock signal is a phase clock signal related to the duty cycle of the DQS clock signal and the DQ data signal.

[0011] In the above implementation scheme, the value of the DCA register corresponding to the first type of phase clock signal is first adjusted to obtain the optimal value of the DCA register corresponding to the first type of phase clock signal to optimize the clock jitter of the transmission signal of the memory, and then the value of the DCA register corresponding to the second type of phase clock signal is adjusted to obtain the optimal value of the DCA register corresponding to the second type of phase clock signal to optimize the duty cycle distortion of the transmission signal of the memory. In this way, while achieving the purpose, the adjustment time can be reduced, so that the training optimization time and the number of phases of the system clock satisfy a linear relationship.

[0012] In combination with a possible implementation method of the first aspect, adjusting the value of the DCA register corresponding to the first type of phase clock signal includes: adjusting the value of the DCA register corresponding to the first type of phase clock signal, obtaining a first maximum eye diagram of correctly sampled data by sampling data transmitted by the DQ data signal using the DQS clock signal; and using the value of the DCA register corresponding to the first maximum eye diagram as the optimal value of the DCA register corresponding to the first type of phase clock signal.

[0013] In the above implementation scheme, when adjusting the value of the DCA register corresponding to the first type of phase clock signal, by continuously adjusting the value of the DCA register, each time the value of the DCA register is adjusted, an eye diagram width that can correctly sample data can be obtained. After multiple adjustments, multiple eye diagrams can be obtained, from which the largest eye diagram is screened out, and the value of the DCA register corresponding to the largest eye diagram is used as the optimal value of the DCA register. In this way, the best DCA setting can be obtained, so that the periods of adjacent clock cycles are consistent, which can solve the jitter problem between the DQ and DQS signal cycles and improve the read and write speed and reliability of the memory.

[0014] In combination with a possible implementation manner of the embodiment of the first aspect, adjusting the value of the DCA register corresponding to the first type of phase clock signal, obtaining a first maximum eye diagram of correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal, including: involving n-1 rounds of adjusting the value of the DCA register corresponding to the first type of phase clock signal; the first round of adjusting the value of the DCA register corresponding to the first type of phase clock signal includes: multiple adjustments of the second n-1 +1 phase clock signal until the first maximum eye diagram of the correctly sampled data is obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal; i is taken from 2 to n-1 in sequence, and the value of the DCA register corresponding to the first type of phase clock signal is adjusted in the i-th round, including: based on the optimal value of the DCA register obtained by the i-1th round of adjustment, multiple adjustments are made to the m*2 n-i +1 phase clock signal of the DCA register until the data transmitted by the new DQ data signal is sampled using the new DQS clock signal to obtain the first maximum eye diagram of the correctly sampled data, where m is [1, 2 i ) is an odd number in the range .

[0015] In the above implementation scheme, by adjusting the value of the DCA register corresponding to the first type of phase clock signal in the above n-1 rounds, the second type of phase clock signal can be n-1 +1 phase clock signal corresponding to the DCA register value, m*2 n-i +1 phase clock signal DCA register value is adjusted to the optimal value, which can solve the cycle jitter problem of DQS clock signal and DQ data signal, and the above method can be applied to 2 n -The scenario of DQS clock signal and DQ data signal generated by the pahse system clock greatly improves the usage scenario of this application.

[0016] In combination with a possible implementation method of the first aspect, the value of the DCA register corresponding to the first type of phase clock signal is adjusted to obtain a first maximum eye diagram of correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal, including: if n=2, the value of the DCA register corresponding to the third phase clock signal is adjusted multiple times, and under each value of the DCA register, the data transmitted by the DQ data signal is sampled using two adjacent rising edges in the DQS clock signal to obtain a first eye diagram of correctly sampled data; and the first maximum eye diagram is screened out from the multiple first eye diagrams obtained.

[0017] In the above implementation scheme, if n=2, the value of the DCA register corresponding to the third phase clock signal is adjusted multiple times, and the first maximum eye diagram is screened out from the multiple first eye diagrams obtained, so as to ensure that the phase between the first phase clock signal to the third phase clock signal (the phase in the interval of 0° to 180°) is equal to the phase between the third phase clock signal to the first phase clock signal (the phase in the interval of 180° to 360°) as much as possible, thereby eliminating the inter-cycle jitter problem.

[0018] In combination with a possible implementation method of the first aspect embodiment, based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment, the value of the DCA register corresponding to the second type of phase clock signal is adjusted, including: generating a new DQS clock signal and a new DQ data signal based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment; adjusting the value of the DCA register corresponding to the second type of phase clock signal, obtaining a second maximum eye diagram of correctly sampled data by sampling the data transmitted by the new DQ data signal using the new DQS clock signal; and using the value of the DCA register corresponding to the second maximum eye diagram as the optimal value of the DCA register corresponding to the second type of phase clock signal.

[0019] In the above implementation scheme, when adjusting the value of the DCA register corresponding to the second type of phase clock signal, by continuously adjusting the value of the DCA register, each time the value of the DCA register is adjusted, an eye diagram width that can correctly sample data can be obtained. After multiple adjustments, multiple eye diagrams can be obtained, from which the largest eye diagram is screened out, and the value of the DCA register corresponding to the largest eye diagram is used as the optimal value of the DCA register. In this way, the optimal duty cycle setting can be obtained, so that the duty cycles of odd cycles and even cycles are adjusted to the optimal level, thereby improving the read and write speed and reliability of the memory.

[0020] In combination with a possible implementation manner of the embodiment of the first aspect, adjusting the value of the DCA register corresponding to the second type of phase clock signal, obtaining a second maximum eye diagram of correctly sampled data by sampling the data transmitted by the new DQ data signal using the new DQS clock signal, including: adjusting the value of the DCA register of the k+1th phase clock signal multiple times until the data transmitted by the new DQ data signal using the new DQS clock signal is sampled to obtain the second maximum eye diagram of correctly sampled data, wherein k is [1, 2 n ) is an odd number in the range .

[0021] In the above implementation scheme, through the above adjustment, the value of the DCA register corresponding to the k+1th phase clock signal can be adjusted to the optimal value, so that the duty cycle of the DQS clock signal is optimized, and the above method can be applied to 2 n-The scenario of DQS clock signal and DQ data signal generated by the pahse system clock greatly improves the usage scenario of this application.

[0022] In combination with a possible implementation manner of the embodiment of the first aspect, the value of the DCA register corresponding to the second type of phase clock signal is adjusted to obtain a second maximum eye diagram of correctly sampled data by sampling the data transmitted by the new DQ data signal using the new DQS clock signal, including: if n is 2, the value of the DCA register corresponding to the second phase clock signal is adjusted to obtain the second maximum eye diagram of correctly sampled data by sampling the data transmitted by the new DQ data signal using the rising edge and falling edge of the even cycle of the new DQS clock signal; the value of the DCA register corresponding to the fourth phase clock signal is adjusted to obtain the second maximum eye diagram of correctly sampled data by sampling the data transmitted by the new DQ data signal using the rising edge and falling edge of the odd cycle of the new DQS clock signal.

[0023] In the above implementation scheme, if n is 2, the duty cycle of the even cycle can be adjusted by adjusting the value of the DCA register corresponding to the second phase clock signal, and the duty cycle of the odd cycle can be adjusted by adjusting the value of the DCA register corresponding to the fourth phase clock signal. By obtaining the maximum eye diagram, the duty cycle of the even cycle can be adjusted to the optimal position, and the duty cycle of the odd cycle can be adjusted to the optimal position.

[0024] In a second aspect, an embodiment of the present application further provides a memory controller, which is connected to the memory through a DQS clock line and a DQ data line, wherein the DQS clock line is used to transmit a DQS clock signal, and the DQ data line is used to transmit a DQ data signal, and the memory controller includes: a training engine, configured to instruct the memory to adjust the value of a DCA register to obtain an optimal value of the DCA register, wherein the optimal value of the DCA register is the value of the DCA register corresponding to a maximum eye diagram, and the maximum eye diagram is the maximum eye diagram of correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal; wherein the value of the DCA register is related to the phase of a system clock signal in the memory, and the system clock signal is used to generate the DQS clock signal and the DQ data signal, and a change in the value of the DCA register will cause the phase of the system clock signal to change, thereby changing the high level time and low level time of the DQS clock signal and the DQ data signal.

[0025] In combination with a possible implementation manner of the second aspect embodiment, the memory controller also includes: a measurement unit, configured to obtain a maximum eye diagram of correctly sampled data obtained by sampling data transmitted by a DQ data signal using a DQS clock signal; the training engine is also configured to instruct the memory to use the value of a DCA register corresponding to the maximum eye diagram as the optimal value of the DCA register.

[0026] In the third aspect, an embodiment of the present application also provides an electronic device, comprising: a memory and a memory controller shown in the embodiment of the second aspect above, the memory controller being connected to the memory via a DQS clock line and a DQ data line, the DQS clock line being used to transmit a DQS clock signal, and the DQ data line being used to transmit a DQ data signal; the memory comprising a DCA register and a signal generating unit, the signal generating unit being configured to adjust the phase of a system clock signal based on the value of the DCA register, and to generate the DQS clock signal and the DQ data signal based on the system clock signal.

[0027] For the beneficial effects of the embodiments of the second to third aspects, please refer to the effective effects of the embodiments of the first aspect and any possible implementation methods of the embodiments of the first aspect.

[0028] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The above and other purposes, features and advantages of the present application will be more clear as shown in the drawings.

[0030] Figure 1 A schematic diagram showing the connection between a memory controller and a DDR memory in a DDR system is shown.

[0031] Figure 2 A schematic diagram showing the principle of generating a transmission signal of a memory based on a 4-phase system clock provided in an embodiment of the present application is shown.

[0032] Figure 3 A schematic diagram of a different DDR DQS signal provided in an embodiment of the present application is shown.

[0033] Figure 4A schematic flow chart of a method for optimizing transmission signals of a memory provided in an embodiment of the present application is shown.

[0034] Figure 5 A schematic diagram of a data mode for optimizing clock jitter provided in an embodiment of the present application is shown.

[0035] Figure 6 A data pattern schematic diagram of a duty cycle optimization provided in an embodiment of the present application is shown.

[0036] Figure 7 A schematic diagram showing the principle of a transmission signal of an 8-phase system clock generating memory provided in an embodiment of the present application is shown.

[0037] Figure 8 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0039] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in the subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also include elements inherent to such process, method, article or device. Furthermore, the term "and / or" in this application is only a kind of association relationship describing the associated objects, indicating that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. In the description of the embodiments of the present application, unless otherwise clearly specified and limited, the technical term "connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0040] In order to optimize the transmission signal (including DQS clock signal and DQ data signal) between the memory and the memory controller, and improve the quality of the transmission signal, such as by reducing the duty cycle distortion of the transmission signal of the memory, or clock jitter and duty cycle distortion, to improve the quality of the transmission signal. The embodiment of the present application provides a method for optimizing the transmission signal of the memory by adjusting the value of the DCA (DutyCycle Adjuster) register.

[0041] The DDR5 (5th generation DDR) specification provides a set of features that can improve the system clock (including 2 n Phase clock signals, n is an integer greater than or equal to 1) registers that are in phase relationship, referred to as DCA registers. Among them, each phase clock signal has an independent DCA register, and the value of the DCA register is related to the phase of the system clock signal inside the DDR memory, and the system clock is used to generate the transmission signal of the DDR memory, that is, to generate the DQS clock signal and the DQ data signal. The change in the value of the DCA register will cause the phase of the system clock signal to change, and then the high level time and low level time of the DQS clock signal and the DQ data signal will change, thereby optimizing the duty cycle distortion. In addition, the change in the value of the DCA register may also change the duration distribution between different clock cycles of the DQS clock signal and the DQ data signal, thereby optimizing the clock jitter. Therefore, by training the values ​​of these registers, the transmission signal quality of the memory can be improved, thereby improving the read and write reliability of the memory. The method shown in the present application can be applied to other memories that also generate the transmission signal of the memory based on the system clock signal and use the DCA register to change the phase of the system clock signal.

[0042] The memory is connected to the memory controller via a DQS clock line and a DQ data line. The DQS clock line is used to transmit a DQS clock signal, and the DQ data line is used to transmit a DQ data signal. The DQ data signal is used to transmit data, and the DQS clock signal is used to sample the DQ data signal to obtain data transmitted by the DQ data signal.

[0043] In the DDR5 specification, the DQS clock signal and DQ data signal of DDR can be generated by the 2-phase and 4-phase system clock signals. Figure 2It is a schematic diagram of a 4-phase system clock (including 4 phase clock signals, such as ICLK, QCLK, IBCLK, and QBCLK) generating a DQ data signal and a DQS clock signal, where "0", "1", "2", and "3" represent phase 0, phase 1, phase 2, and phase 3 of the DQ data signal and the DQS clock signal, respectively. The phase relationship between the ICLK phase clock signal and the QCLK phase clock signal determines the eye width of phase 0, the phase relationship between the QCLK phase clock signal and the IBCLK phase clock signal determines the eye width of phase 1, the phase relationship between the IBCLK phase clock signal and the QBCLK phase clock signal determines the eye width of phase 2, and the phase relationship between the QBCLK phase clock signal and the ICLK phase clock signal determines the eye width of phase 3. The four different phase clock signals will cause the phase 0, phase 1, phase 2, and phase 3 of the DQS clock signal (or DQ data signal) to be mismatched, which will not only worsen the duty cycle distortion problem within the DDR interface cycle, but also make the clock jitter problem more serious, and the amplitude of the duty cycle distortion in adjacent cycles is also inconsistent.

[0044] in, Figure 2 The ICLK, QCLK, IBCLK, and QBCLK shown in the figure can also be represented by other numbers or letters, just to distinguish clock signals of different phases. Among them, clock jitter will cause the cycle lengths between adjacent cycles to be inconsistent, such as the length of the odd cycle is inconsistent with the length of the even cycle. Figure 2 In the DQS clock signal, the first r0~r1 represents a cycle (which can be called an even cycle), and r1~next r0 represents the next cycle (which can be called an odd cycle). Due to clock jitter, the duration of these two cycles will be different. For example, the duration of the first cycle is 9ns and the duration of the second cycle is 11ns. The purpose of optimization is to make the duration between these two cycles consistent, such as 10ns.

[0045] The 2-phase system clock contains 2 phase clock signals with different phases, and the corresponding ideal phases are 0° and 180°. The 4-phase system clock contains 4 phase clock signals with different phases, and the ideal phases of the 4 phase clock signals are 0°, 90°, 180°, and 270°. Similarly, the 8-phase system clock contains 8 phase clock signals with different phases, and the corresponding ideal phases are 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°.

[0046] In some implementations, the DQ data signal and the DQS clock signal can be generated based on the same system clock signal. In some possible implementations, the DQ data signal and the DQS clock signal can be generated based on different system clock signals. The present application is mainly aimed at the scenario where the DQ data signal and the DQS clock signal are generated based on the same system clock signal. The present application adopts a relatively novel approach to improve the quality of the DQS clock signal and the DQ data signal by training and adjusting the value of the DCA register, instead of adjusting the duty cycle of the DQS clock signal and the DQ data signal through additional hardware circuits on the memory controller side after generating the DQS clock signal and the DQ data signal, thereby eliminating the need to add additional hardware circuits.

[0047] The method for optimizing the transmission signal of the memory provided in the present application can first train and optimize the clock jitter of the transmission signal of the memory, and then train and optimize the duty cycle distortion of the transmission signal of the memory. The total training optimization time is linearly related to the number of phases of the system clock and will not increase exponentially with the increase of the number of phases. Assuming that the unit time of each round of optimization adjustment is T, and the number of phases of the system clock that generates the DQS clock signal and the DQ data signal is N, then the total training optimization time is T*logN, for example:

[0048] When a 2-phase clock is used to generate a DQS clock signal, the total training optimization time is 1*T.

[0049] When a 4-phase clock is used to generate a DQS clock signal, the total training optimization time is 2*T.

[0050] When an 8-phase clock is used to generate a DQS clock signal, the total training optimization time is 3*T.

[0051] For a DQS clock signal or DQ data signal generated by a 2-phase clock, only duty cycle distortion may exist without clock jitter. For a DQS clock signal or DQ data signal generated by a 4-phase or more phase clock, both duty cycle distortion and clock jitter may exist.

[0052] The method of adjusting the signal duty cycle in the related art is not suitable for DDR5, because this type of adjustment method can only adjust the duty cycle of the DDR interface signal, but cannot improve the clock jitter. Figure 3 The schematic diagram shows the DQS clock signal under the DDR interface of different SDRAM specifications. The method of adjusting the signal duty cycle in the related art is more suitable for optimizing signals such as DDR3 and DDR4. Such signals have small jitter between cycles and have the same magnitude of duty cycle distortion in each cycle. The introduction of the 4-phase system clock in DDR5 will produce Figure 3 The DQS_DDR5 signal in the image not only has cycle-to-cycle jitter, but also has inconsistent duty cycle distortion amplitudes in adjacent cycles. The optimization of this signal requires a new solution.

[0053] Among them, in the method of optimizing the transmission signal of the memory, the process can be as follows Figure 4 shown.

[0054] S1: Adjust the value of the DCA register, and generate a DQS clock signal and a DQ data signal based on the adjusted value of the DCA register.

[0055] The value of the DCA register is related to the phase of the system clock signal inside the memory. The system clock signal is used to generate the DQS clock signal and the DQ data signal. The change of the value of the DCA register will change the phase of the system clock signal, thereby obtaining a new DQS clock signal and a new DQ data signal.

[0056] S2: Acquire a maximum eye diagram of correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal.

[0057] By adjusting the value of the DCA register, the 2 n The phase relationship between the two phase clock signals is close to the ideal correlation relationship. In one implementation, when the eye diagram of the correctly sampled data is obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal, it is considered that 2 n The phase relationship between the phase clock signals is close to the ideal correlation.

[0058] S3: taking the value of the DCA register corresponding to the maximum eye diagram as the optimal value of the DCA register.

[0059] S4: Generate a new DQS clock signal and a new DQ data signal based on the optimal value of the DCA register.

[0060] The subsequent memory exchanges data with the memory controller based on the new DQS clock signal and the new DQ data signal. Since the quality of the transmission signal is good at this time, the read and write reliability of the memory can be improved.

[0061] In one implementation, when adjusting the value of the DCA register, the value of the DCA register may be adjusted according to a value obtained by experiment or simulation, and by adjusting the value of the DCA register to an optimal value obtained by experiment or simulation, the eye diagram of the correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal is maximized, so that the value of the DCA register corresponding to the maximum eye diagram is used as the optimal value of the DCA register, thereby optimizing the duty cycle distortion of the transmission signal of the memory, or optimizing the clock jitter and duty cycle distortion of the transmission signal of the DDR memory. In this implementation, the value of the DCA register may be adjusted to the optimal value at one time.

[0062] In one implementation, when adjusting the value of the DCA register to obtain the maximum eye diagram of the correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal, it may involve adjusting the value of the DCA register multiple times. Each time the value of the DCA register is adjusted, an eye diagram can be obtained. After multiple adjustments, multiple eye diagrams can be obtained, from which the maximum eye diagram is screened out, and the value of the DCA register corresponding to the maximum eye diagram is used as the optimal value of the DCA register, thus completing the adjustment of the value of the DCA register. It should be noted that each time the value of the DCA register is adjusted, the DQS clock signal and the DQ data signal need to be regenerated, and the data transmitted by the new DQ data signal is sampled using the new DQS clock signal to obtain the eye diagram corresponding to each adjustment of the value of the DCA register.

[0063] For example, assuming that the initial value of a DCA register is 0, a DQS clock signal and a DQ data signal can be generated based on the initial value, and the data transmitted by the DQ data signal can be sampled using the DQS clock signal. By continuously delaying the DQS clock signal, an eye diagram width that can sample the correct data can be obtained, that is, the correct data can be sampled within the eye diagram width. Afterwards, the initial value of the DCA register is adjusted to 1, and a new DQS clock signal and a new DQ data signal can be generated based on the adjusted value of the DCA register, and the data transmitted by the new DQ data signal can be sampled using the new DQS clock signal. By continuously delaying the DQS clock signal, a new eye diagram width that can sample the correct data can be obtained. This is repeated continuously, and the maximum eye diagram can be screened out, wherein the maximum eye diagram can be an eye diagram with the largest eye diagram width.

[0064] For example, taking the adjustment of the value of the DCA register corresponding to the BCLK phase clock signal in the above example as an example, when adjusting the value of the DCA register, the value of the DCA register corresponding to the IBCLK phase clock signal may be increased. If the eye diagram increases, the value of the DCA register corresponding to the IBCLK phase clock signal may continue to be increased until the eye diagram decreases. Alternatively, the value of the DCA register corresponding to the phase clock signal may be decreased. If the eye diagram increases, the value of the DCA register corresponding to the IBCLK phase clock signal may continue to be decreased until the eye diagram decreases. If the value of the DCA register corresponding to the IBCLK phase clock signal is increased and the eye diagram decreases, the value of the previous DCA register is returned to, and the value of the DCA register corresponding to the IBCLK phase clock signal is decreased. If the eye diagram also decreases at this time, the value of the previous DCA register is the optimal value of the DCA register.

[0065] The eye width can be obtained in the following way. When the DQS clock signal is used to sample the data transmitted by the DQ data signal, the first delay of the DQS clock signal when the first sampling of the wrong data to the flip point of the correct data can be recorded, and then the DQS clock signal is continuously delayed. If the correct data is sampled, the DQS clock signal is continuously delayed until the wrong data is sampled, and then the second delay of the DQS clock signal when the first sampling of the correct data to the flip point of the wrong data is recorded. Then the eye width can be the delay difference between the first delay and the second delay.

[0066] Among them, the system clock signal includes 2 n phase clock signals, each phase clock signal has an independent DCA register, and n is an integer greater than or equal to 2. The process of adjusting the value of the DCA register may be: adjusting the value of the DCA register corresponding to the first type of phase clock signal to obtain an optimal value of the DCA register corresponding to the first type of phase clock signal, so as to optimize the clock jitter of the transmission signal of the DDR memory; based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment, adjusting the value of the DCA register corresponding to the second type of phase clock signal to obtain an optimal value of the DCA register corresponding to the second type of phase clock signal, so as to optimize the duty cycle distortion of the transmission signal of the DDR memory.

[0067] In one implementation, the value of the DCA register corresponding to the first type of phase clock signal may not be adjusted, and the value of the DCA register corresponding to the second type of phase clock signal may be directly adjusted. Compared with first adjusting the value of the DCA register corresponding to the first type of phase clock signal and then adjusting the value of the DCA register corresponding to the second type of phase clock signal, this method requires more time to adjust.

[0068] When n is 1, the process of adjusting the value of the DCA register may be: adjusting the value of the DCA register corresponding to the second type phase clock signal to optimize the duty cycle distortion of the transmission signal of the DDR memory.

[0069] The first type of phase clock signal is a phase clock signal related to the clock jitter of the transmission signal of the memory, and the second type of phase clock signal is a phase clock signal related to the duty cycle of the transmission signal of the memory.

[0070] In one possible implementation, the process of adjusting the values ​​of the DCA registers corresponding to the first type of phase clock signal and the second type of phase clock signal may be: adjusting the values ​​of the DCA registers corresponding to the first type of phase clock signal and the second type of phase clock signal according to values ​​obtained through experiments or simulations.

[0071] In one possible implementation, the process of adjusting the value of the DCA register corresponding to the first type of phase clock signal may be: adjusting the value of the DCA register corresponding to the first type of phase clock signal, obtaining the first maximum eye diagram of the correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal; using the value of the DCA register corresponding to the first maximum eye diagram as the optimal value of the DCA register corresponding to the first type of phase clock signal. In this implementation, the adjustment process is similar to the above-mentioned process of adjusting the value of the DCA register, and will also involve multiple adjustments to the value of the DCA register corresponding to the first type of phase clock signal. Each time the value of the DCA register is adjusted, an eye diagram can be obtained. After multiple adjustments, multiple eye diagrams can be obtained, from which the maximum eye diagram is screened out, and the value of the DCA register corresponding to the maximum eye diagram is used as the optimal value of the DCA register corresponding to the first type of phase clock signal. In this way, the adjustment of the value of the DCA register corresponding to the first type of phase clock signal is completed.

[0072] In a possible implementation, based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment, the process of adjusting the value of the DCA register corresponding to the second type of phase clock signal can be: generating a new DQS clock signal and a new DQ data signal based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment; adjusting the value of the DCA register corresponding to the second type of phase clock signal, obtaining a second maximum eye diagram of the correctly sampled data by sampling the data transmitted by the new DQ data signal using the new DQS clock signal; and using the value of the DCA register corresponding to the second maximum eye diagram as the optimal value of the DCA register corresponding to the second type of phase clock signal. This process is similar to the process of adjusting the value of the DCA register described above, and will not be repeated.

[0073] The first type of phase clock signal and the second type of phase clock signal are related to the phase number of the system clock. For example, for a 2-phase system clock, the second type of phase clock signal is the second phase clock signal. For a 4-phase system clock, the second type of phase clock signal is the second phase clock signal and the fourth phase clock signal, and the first type of phase clock signal is the third phase clock signal. For an 8-phase system clock, the first type of phase clock signal is the fifth phase clock signal, the third phase clock signal, and the seventh phase clock signal, and the second type of phase clock signal is the second phase clock signal, the fourth phase clock signal, the sixth phase clock signal, and the eighth phase clock signal.

[0074] The first type of phase clock signal and the second type of phase clock signal can be determined in the following manner, assuming that the number of phase clock signals is N=2 n , the total number of training optimization rounds is n rounds. If the single round training optimization time is T, the total training optimization time is n*T. The phase clock signal of the last round of training optimization is the second type of phase clock signal, and the remaining phase clock signals are all first type of phase clock signals. For example, for a 4-phase system clock, the total number of training optimization rounds is 2 rounds, and for an 8-phase system clock, the total number of training optimization rounds is 3 rounds. Each round of training optimization may involve multiple adjustments to the value of the DCA register.

[0075] When training and optimizing the value of the DCA register corresponding to the phase clock signal, n rounds of adjusting the value of the DCA register are involved. The first round of adjusting the value of the DCA register includes: adjusting the value of the second round multiple times. n-1 +1 phase clock signal corresponding to the DCA register value, obtain the first maximum eye diagram of the correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal; i is taken from 2 to n-1 in sequence, and the value of the DCA register is adjusted in the i-th round, including: based on the optimal value of the DCA register obtained by the i-1th round of adjustment, multiple adjustments are made to the m*N / 2th i +1(or m*2 n-i +1) phase clock signal of the DCA register until the data transmitted by the new DQ data signal is sampled using the new DQS clock signal to obtain the first maximum eye diagram of the correctly sampled data, where m is [1, 2 i ). The nth round of adjusting the value of the DCA register includes: adjusting the value of the DCA register of the k+1th phase clock signal multiple times based on the optimal value of the DCA register obtained by the n-1th round of adjustment, until the second maximum eye diagram of the correctly sampled data is obtained by sampling the data transmitted by the new DQ data signal using the new DQS clock signal, wherein k is [1, 2 n) is an odd number in the range .

[0076] The value of m will change with the increase of i. For example, when i=2, m takes values ​​1 and 3 in sequence; when i=3, m takes values ​​1, 3, 5, and 7 in sequence; when i=4, m takes values ​​1, 3, 5, 7, 9, 11, 13, and 15 in sequence. The value of k will change with the increase of n. For example, when n=2, k takes values ​​1 and 3 in sequence; when n=3, k takes values ​​1, 3, 5, and 7 in sequence; when n=4, k takes values ​​1, 3, 5, 7, 9, 11, 13, and 15 in sequence.

[0077] Among them, in the process of adjusting the value of the DCA register in the above n rounds, it involves n-1 rounds of adjusting the value of the DCA register corresponding to the first type of phase clock signal, and the last round of adjusting the value of the DCA register corresponding to the second type of phase clock signal. That is, in the process of adjusting the value of the DCA register corresponding to the first type of phase clock signal and obtaining the first maximum eye diagram of the correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal, it involves n-1 rounds of adjusting the value of the DCA register corresponding to the first type of phase clock signal; the first round of adjusting the value of the DCA register corresponding to the first type of phase clock signal includes: adjusting the value of the DCA register corresponding to the second type of phase clock signal multiple times; n-1 +1 phase clock signal until the first maximum eye diagram of the correctly sampled data is obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal; i is taken from 2 to n-1 in sequence, and the value of the DCA register corresponding to the first type of phase clock signal is adjusted in the i-th round, including: based on the optimal value of the DCA register obtained by the i-1th round of adjustment, multiple adjustments are made to the m*2 n-i +1 phase clock signal's DCA register value until the first maximum eye diagram of the correctly sampled data is obtained by sampling the data transmitted by the new DQ data signal using the new DQS clock signal.

[0078] In the process of adjusting the value of the DCA register corresponding to the second type of phase clock signal to obtain the second maximum eye diagram of the correctly sampled data by sampling the data transmitted by the new DQ data signal using the new DQS clock signal, the value of the DCA register of the k+1th phase clock signal may be adjusted multiple times until the second maximum eye diagram of the correctly sampled data is obtained by sampling the data transmitted by the new DQ data signal using the new DQS clock signal, wherein k is [1, 2 n ) is an odd number in the range .

[0079] For example, when training and optimizing the value of the DCA register corresponding to the phase clock signal, the first round of training optimizes the value of the DCA register of the N / 2+1th phase clock signal; the second round of training optimizes the value of the DCA register of the N / 4+1th and 3N / 4+1th phase clock signals; the third round of training optimizes the value of the DCA register of the N / 8+1th, 3N / 8+1th, 5N / 8+1th, and 7N / 8+1th phase clock signals; the fourth round of training optimizes the value of the DCA register of the N / 16+1th, 3N / 16+1th, 5N / 16+1th, 7N / 16+1th, 9N / 16+1th, 11N / 16+1th, 13N / 16+1th, and 15N / 16+1th phase clock signals, and so on. If N=4, only the first round of training optimization and the second round of training optimization processes are involved; if N=8, only the first round of training optimization, the second round of training optimization processes, and the third round of training optimization processes are involved.

[0080] Taking n=2 as an example, the process of adjusting the value of the DCA register corresponding to the first type of phase clock signal and obtaining the first maximum eye diagram of the correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal can be: adjusting the value of the DCA register corresponding to the third phase clock signal (such as the above-mentioned IBCLK) multiple times, obtaining the value of each DCA register, and using two adjacent rising edges in the DQS clock signal to sample the data transmitted by the DQ data signal to obtain the first eye diagram of the correctly sampled data; and screening out the first maximum eye diagram from the multiple first eye diagrams obtained.

[0081] Taking n=2 as an example, the process of adjusting the value of the DCA register corresponding to the second type of phase clock signal to obtain the second maximum eye diagram of the correctly sampled data by sampling the data transmitted by the new DQ data signal using the new DQS clock signal can be: adjusting the value of the DCA register corresponding to the second phase clock signal to obtain the second maximum eye diagram of the correctly sampled data by sampling the data transmitted by the new DQ data signal using the rising edge and falling edge of the even cycle of the new DQS clock signal; adjusting the value of the DCA register corresponding to the fourth phase clock signal to obtain the second maximum eye diagram of the correctly sampled data by sampling the data transmitted by the new DQ data signal using the rising edge and falling edge of the odd cycle of the new DQS clock signal.

[0082] In order to better understand the above process, a specific example is provided below for explanation.

[0083] Embodiment 1:

[0084] Taking the ICLK, QCLK, IBCLK, and QBCLK phase clock signals shown above as an example, Figure 5A data mode schematic diagram for optimizing clock jitter is shown, and the DQ data is set to 1100 (or other values, such as 0011), r0 and r1 are two rising edges of adjacent cycles of the DQS clock signal, and the phase of the IBCLK phase clock signal (the value of the DCA register) determines the eye width of the DQ data "1" and the eye width of "0" and the clock cycle of r0 and r1 in the DQS clock signal. The DQ data is sampled with the DQS clock signal, and the data sampled at the rising edge of r0 and the rising edge of r1 are compared. If the rising edge of r0 samples data 1 and the rising edge of r1 samples data 0, the data is considered correct. The DQS clock signal is gradually delayed, and the flip point from the first sampling of the wrong data to the correct data is recorded as the first delay, and the flip point from the first sampling of the correct data to the wrong data is recorded as the second delay. Based on the first delay and the second delay, the eye width can be obtained, and the eye width is determined by the width of the DQ data "1" and "0" and the clock cycle of r0 and r1 in the DQS clock signal. By gradually changing the value of the DCA register corresponding to the IBCLK phase clock signal, multiple eye widths can be obtained. The value of the DCA register when the eye width is the largest is the optimal value of the DCA register. The process of adjusting the value of the DCA register corresponding to the IBCLK phase clock signal is as follows:

[0085] If the value of the DCA register of IBCLK is increased and the eye diagram increases, then continue to increase the value of the DCA register of IBCLK until the eye diagram decreases; if the value of the DCA register of IBCLK is decreased and the eye diagram increases, then continue to decrease the value of the DCA register of IBCLK until the eye diagram decreases; if the value of the DCA register of IBCLK is increased and the eye diagram decreases, then return to the value of the DCA register of the previous IBCLK and then decrease the value of the DCA register of IBCLK. If the eye diagram also decreases at this time, the value of the previous DCA register is the optimal value of the DCA register.

[0086] Figure 6A data mode for optimizing the duty cycle is shown. After writing the value of the DCA register corresponding to the optimal IBCLK phase clock signal into the DCA register, the DQ data is set to 1010 (or other values, such as 0101). r0 and f0 are the rising edge and falling edge of the even cycle of the DQS clock signal, and r1 and f1 are the rising edge and falling edge of the odd cycle of the DQS clock signal. The duty cycle of the even cycle can be adjusted by adjusting the phase of the QCLK phase clock signal (the value of the DCA register), and the duty cycle of the odd cycle can be adjusted by adjusting the phase of the QBCLK phase clock signal (DCA). The DQ data is sampled with the DQS clock signal, and the data sampled by the rising edge of r0 and the falling edge of f0 are compared. If the rising edge of r0 samples data 1 and the falling edge of f0 samples data 0, the data is considered correct. The eye width of the even cycle can be obtained by gradually delaying the DQS clock signal. The size of the eye width depends on the duty cycle of the DQ data signal (or DQS clock signal) of the even cycle. The value of the DCA register corresponding to the QCLK phase clock signal is gradually changed, and the value of the DCA register corresponding to the QCLK phase clock signal when the eye width is the largest is the optimal value of the DCA register.

[0087] Similarly, for the DQS clock signal and DQ data of odd cycles, compare the data sampled at the rising edge of r1 and the falling edge of f1. If the rising edge of r1 samples data 1 and the falling edge of f1 samples data 0, the data is considered correct. By gradually delaying the DQS clock signal, the eye width of the odd cycle can be obtained. The size of the eye width depends on the duty cycle of the DQ data signal (or DQS clock signal) of the odd cycle. Gradually change the value of the DCA register corresponding to the QBCLK phase clock signal, and the value of the DCA register when the eye width is the largest is the optimal value of the DCA register. The scheme for adjusting the value of the DCA register corresponding to the QCLK and QBCLK phase clock signals is the same as adjusting the value of the DCA register corresponding to the IBCLK phase clock signal.

[0088] The above adjustment process can be simply summarized as follows:

[0089]

[101] Set the initial value of the DCA register to 0. QCLK, IBCLK, and QBCLK all have independent DCA registers.

[0090]

[102] Set the DQ data to 1100, and judge the DQ data sampled by the rising edge of r0 and r1. When the rising edge return value is 10, it is considered that the correct data is sampled. Gradually delay the DQS clock signal, and the eye width can be obtained according to the delay interval of sampling to obtain the correct data.

[0091]

[103] Gradually change the value of the DCA register of IBCLK, that is, adjust the phase of IBCLK, until the eye diagram is maximized. Write the value of the DCA register of IBCLK corresponding to the maximum eye diagram into the DCA register as the optimal value. At this point, the process of improving clock jitter ends.

[0092]

[104] Set the DQ data to 1010, and judge the sampling data of the rising edge r0 and falling edge f0 of the even cycle of the DQS clock signal. When the rising and falling edge return values ​​are 10, it is considered that the correct data is sampled. The DQS clock signal is gradually delayed, and the eye width can be obtained according to the delay interval of sampling to obtain the correct data.

[0093]

[105] The value of the DCA register of QCLK is gradually changed, that is, the phase of QCLK is adjusted until the eye diagram is maximized. The value of the DCA register of QCLK when the eye diagram is maximized is written into the DCA register as the optimal value. At this point, the duty cycle of the even cycle is adjusted to the optimal value.

[0094]

[106] Set the DQ data to 1010, and judge the sampling data of the rising edge r1 and the falling edge f1 of the DQS odd cycle. When the rising and falling edge return values ​​are 10, it is considered that the correct data is sampled. Gradually delay the DQS clock signal, and the eye width can be obtained according to the delay interval of sampling to obtain the correct data.

[0095]

[107] Change the value of the DCA register of QBCLK, that is, adjust the phase of QBCLK until the eye diagram is maximized. Write the value of the DCA register of QBCLK when the eye diagram is maximized into the DCA register as the optimal value. At this point, the duty cycle of the odd cycle is adjusted to the optimal value.

[0096] The above steps

[104] ,

[105] ,

[106] , and

[107] can be performed simultaneously, that is, the duty cycle adjustment of the even-numbered cycles and the odd-numbered cycles can be performed simultaneously.

[0097] Embodiment 2:

[0098] by Figure 7 Taking the transmission signal of the memory generated by the 8-phase system clock as an example, each phase clock signal has its own DCA register. The adjustment process is as follows:

[0099]

[201] Set the initial value of the DCA register to 0. The 2nd to 8th phase clock signals (corresponding to numbers 1 to 7) have independent DCA registers.

[0100]

[202] Set the DQ data to 11110000 (or other values, such as 00001111), determine the DQ data sampled at the rising edges 0 and 4 of DQS, and when the rising edge return value is 10, it is considered that the correct data is sampled. Gradually delay the DQS clock signal, and the eye width can be obtained based on the delay interval of sampling to obtain the correct data.

[0101]

[203] Gradually change the 5th phase clock signal (corresponding to Figure 7 The value of the DCA register corresponding to number 4) in the figure is written into the DCA register as the optimal value when the eye diagram is at its maximum.

[0102]

[204] Set the DQ data to 11001100 (or other values, such as 00110011), determine the rising edges 0 and 2 of the DQS clock signal and the sampled data, and when the return value is 10, it is considered that the correct data is sampled. Gradually delay the DQS clock signal, and the eye width can be obtained based on the delay interval of sampling to obtain the correct data.

[0103]

[205] Gradually change the value of the DCA register corresponding to the third phase clock signal (corresponding to number 2) until the eye diagram is maximized, and write the value of the DCA register when the eye diagram is maximized into the DCA register as the optimal value.

[0104]

[206] Set the DQ data to 11001100 (or other values, such as 00110011), determine the rising edges 4 and 6 of the DQS clock signal and the sampled data, and when the return value is 10, it is considered that the correct data is sampled. Gradually delay the DQS clock signal, and the eye width can be obtained based on the delay interval of sampling to obtain the correct data.

[0105]

[207] Gradually change the value of the DCA register corresponding to the 7th phase clock signal (corresponding to number 6) until the eye diagram is maximized, and write the value of the DCA register when the eye diagram is maximized into the DCA register as the optimal value.

[0106] Steps

[204] to

[207] may be performed simultaneously.

[0107]

[208] Set the DQ data to 10101010 (or other values, such as 01010101), determine the sampled data of the rising edge 0 and the falling edge 1 of the DQS clock signal, and when the return value is 10, it is considered that the correct data is sampled. Gradually delay the DQS clock signal, and the eye width can be obtained based on the delay interval of sampling to obtain the correct data.

[0108]

[209] The value of the DCA register corresponding to the second phase clock signal (corresponding to number 1) is gradually increased until the eye diagram is maximized, and the value of the DCA register when the eye diagram is maximized is written into the DCA register as the optimal value.

[0109]

[210] Set the DQ data to 10101010 (or other values, such as 01010101), determine the sampled data of the rising edge 2 and the falling edge 3 of the DQS clock signal, and when the return value is 10, it is considered that the correct data is sampled. The DQS clock signal is gradually delayed, and the eye width can be obtained based on the delay interval of sampling to obtain the correct data.

[0110]

[211] Gradually change the value of the DCA register corresponding to the fourth phase clock signal (corresponding to number 3) until the eye diagram is maximized, and write the value of the DCA register when the eye diagram is maximized into the DCA register as the optimal value.

[0111]

[212] Set the DQ data to 10101010 (or other values, such as 01010101), determine the sampled data of the rising edge 4 and the falling edge 5 of the DQS clock signal, and when the return value is 10, it is considered that the correct data is sampled. The DQS clock signal is gradually delayed, and the eye width can be obtained based on the delay interval of sampling to obtain the correct data.

[0112]

[213] Gradually change the value of the DCA register corresponding to the sixth phase clock signal (corresponding to number 5) until the eye diagram is maximized, and write the value of the DCA register when the eye diagram is maximized into the DCA register as the optimal value.

[0113]

[214] Set the DQ data to 10101010 (or other values, such as 01010101), determine the sampled data of the rising edge 6 and the falling edge 7 of the DQS clock signal, and when the return value is 10, it is considered that the correct data is sampled. Gradually delay the DQS clock signal, and the eye width can be obtained based on the delay interval of sampling to obtain the correct data.

[0114]

[215] Gradually change the value of the DCA register corresponding to the 8th phase clock signal (corresponding to number 7) until the eye diagram is maximized, and write the value of the DCA register when the eye diagram is maximized into the DCA register as the optimal value.

[0115] Steps

[208] to

[215] may be performed simultaneously.

[0116] In one implementation, the above-mentioned DCA register may be built into a DDR memory. In this case, the DDR memory may include a DCA register and a signal generating unit, wherein the signal generating unit is configured to adjust the phase of the system clock signal based on the value of the DCA register, that is, to change the phase relationship between the system clock signals by modifying the value of the DCA register, and further change the high level time and low level time of the transmission signal of the DDR memory generated by the system clock signal.

[0117] The above training process can be implemented by a memory controller. Based on the same inventive concept, the embodiment of the present application also provides a memory controller, which can be a memory controller. The memory controller is connected to the memory through a DQS clock line and a DQ data line.

[0118] The memory controller includes: a training engine, the training engine is configured to instruct the adjustment of the value of the DCA register. If the DCA register is built in the DDR memory, the training engine is configured to instruct the DDR memory to adjust the value of the DCA register to obtain the optimal value of the DCA register, wherein the optimal value of the DCA register is the value of the DCA register corresponding to the maximum eye diagram, and the maximum eye diagram is the maximum eye diagram of the correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal, so as to optimize the duty cycle distortion of the transmission signal of the DDR memory, or optimize the clock jitter and duty cycle distortion of the transmission signal of the DDR memory; wherein the value of the DCA register is related to the phase of the system clock signal in the DDR memory, and the system clock signal is used to generate the transmission signal of the DDR memory.

[0119] In one embodiment, the memory controller also includes: a measurement unit, which is configured to obtain a maximum eye diagram of correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal. Accordingly, the training engine is also configured to instruct the memory to use the value of the DCA register corresponding to the maximum eye diagram as the optimal value of the DCA register.

[0120] The training engine is also configured to instruct the DDR memory to adjust the value of the DCA register corresponding to the first type of phase clock signal to optimize the clock jitter of the transmission signal of the DDR memory; and to instruct the DDR memory to adjust the value of the DCA register corresponding to the second type of phase clock signal to optimize the duty cycle distortion of the transmission signal of the DDR memory.

[0121] The training engine can be implemented using various microprocessors, such as ARM (Advanced RISC Machines), RISCV (RISC-V Instruction Set Architecture), etc. The training engine can also be a hardware control circuit. The measurement unit can be a delay measurement circuit, which records the first delay and the second delay and calculates the eye width based on them.

[0122] The implementation principle and technical effect of adjusting the value of the DCA register provided by the memory controller embodiment are the same as those of the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the memory controller embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0123] An embodiment of the present application also provides an electronic device, which includes a DDR memory and the above-mentioned memory controller, wherein the memory controller is connected to the DDR memory via a DQS clock line and a DQ data line; the DDR memory includes a DCA register and a signal generating unit, and the signal generating unit is configured to adjust the phase of a system clock signal based on the value of the DCA register, and generate a transmission signal of the DDR memory based on the system clock signal.

[0124] In one implementation manner, the structural block diagram of the electronic device may be as follows: Figure 8 The electronic device 200 includes: a transceiver 210, a DDR memory 220, a communication bus 230 and a processor 240. The processor 240 may include a memory controller (such as a memory controller).

[0125] The transceiver 210, the DDR memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses 230 or signal lines.

[0126] The processor 240 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. Alternatively, the processor 240 may also be any conventional processor, etc.

[0127] The electronic device 200 mentioned above includes but is not limited to a mobile phone, a tablet, a computer, a server, etc.

[0128] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0129] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0130] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for optimizing a transmission signal of a memory, characterized in that: include: Adjust the value of the DCA register, and generate a DQS clock signal and a DQ data signal based on the adjusted value of the DCA register, wherein the DQS clock signal and the DQ data signal are transmission signals between the memory and the memory controller, and the DQ data signal and the DQS clock signal are generated based on the same system clock signal; Acquire a maximum eye diagram of correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal; Using the value of the DCA register corresponding to the maximum eye diagram as the optimal value of the DCA register; Based on the optimal value of the DCA register, a new DQS clock signal and a new DQ data signal are generated.

2. The method according to claim 1, characterized in that Adjust the value of the DCA register, including: The value of the DCA register is adjusted multiple times; accordingly, a maximum eye diagram of correctly sampled data is obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal, including: Obtain an eye diagram corresponding to each adjustment of the value of the DCA register to obtain multiple eye diagrams; An eye diagram with the largest eye width is selected from the multiple eye diagrams to obtain the largest eye diagram.

3. The method according to claim 1, characterized in that The value of the DCA register is related to the phase of the system clock signal inside the memory, and the system clock signal is used to generate the DQS clock signal and the DQ data signal; the system clock signal includes 2 n phase clock signals, each phase clock signal has an independent DCA register, and n is an integer greater than or equal to 2; Adjust the value of the DCA register, including: Adjusting a value of a DCA register corresponding to a first type of phase clock signal to obtain an optimal value of the DCA register corresponding to the first type of phase clock signal, wherein the first type of phase clock signal is a phase clock signal related to clock jitter of the DQS clock signal and the DQ data signal; Based on the adjusted optimal value of the DCA register corresponding to the first type of phase clock signal, the value of the DCA register corresponding to the second type of phase clock signal is adjusted to obtain the optimal value of the DCA register corresponding to the second type of phase clock signal, wherein the second type of phase clock signal is a phase clock signal related to the duty cycle of the DQS clock signal and the DQ data signal.

4. The method according to claim 3, characterized in that Adjust the value of the DCA register corresponding to the first type of phase clock signal, including: Adjust the value of the DCA register corresponding to the first type of phase clock signal to obtain a first maximum eye diagram of correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal; The value of the DCA register corresponding to the first maximum eye diagram is used as the optimal value of the DCA register corresponding to the first type of phase clock signal.

5. The method according to claim 4, characterized in that Adjusting the value of the DCA register corresponding to the first type of phase clock signal to obtain a first maximum eye diagram of correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal, including: Involving n-1 rounds of adjusting the value of the DCA register corresponding to the first type of phase clock signal; The first round of adjusting the value of the DCA register corresponding to the first type of phase clock signal includes: Multiple adjustments 2 n-1 +1 phase clock signal corresponding to the DCA register value until the first maximum eye diagram of the correctly sampled data is obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal; i is sequentially 2 to n-1, and the value of the DCA register corresponding to the first type of phase clock signal is adjusted in the i-th round, including: Based on the optimal value of the DCA register obtained in the i-1th round of adjustment, adjust the m*2th round of adjustment multiple times n-i +1 phase clock signal of the DCA register until the data transmitted by the new DQ data signal is sampled using the new DQS clock signal to obtain the first maximum eye diagram of the correctly sampled data, where m is [1, 2 i ) is an odd number in the range .

6. The method according to claim 3, characterized in that Adjusting the value of the DCA register corresponding to the second type of phase clock signal based on the adjusted optimal value of the DCA register corresponding to the first type of phase clock signal includes: Generate a new DQS clock signal and a new DQ data signal based on the optimal value of the DCA register corresponding to the adjusted first-type phase clock signal; Adjust the value of the DCA register corresponding to the second type of phase clock signal, obtain a second maximum eye diagram of correctly sampled data by sampling the data transmitted by the new DQ data signal using the new DQS clock signal; The value of the DCA register corresponding to the second largest eye diagram is used as the optimal value of the DCA register corresponding to the second type of phase clock signal.

7. The method according to claim 6, characterized in that Adjusting the value of the DCA register corresponding to the second type of phase clock signal, obtaining a second maximum eye diagram of correctly sampled data by sampling the data transmitted by the new DQ data signal using the new DQS clock signal, including: The value of the DCA register of the k+1th phase clock signal is adjusted multiple times until the second maximum eye diagram of the correctly sampled data is obtained by sampling the data transmitted by the new DQ data signal using the new DQS clock signal, where k is [1, 2 n ) is an odd number in the range .

8. A memory controller, characterized in that: The memory controller is connected to the memory via a DQS clock line and a DQ data line, wherein the DQS clock line is used to transmit a DQS clock signal, and the DQ data line is used to transmit a DQ data signal, wherein the DQ data signal and the DQS clock signal are generated based on the same system clock signal, and the memory controller comprises: A training engine is configured to instruct the memory to adjust the value of a DCA register to obtain an optimal value of the DCA register, wherein the optimal value of the DCA register is the value of the DCA register corresponding to a maximum eye diagram, and the maximum eye diagram is a maximum eye diagram of correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal; the value of the DCA register is related to the phase of a system clock signal inside the memory, and the system clock signal is used to generate the DQS clock signal and the DQ data signal.

9. The memory controller according to claim 8, wherein: The memory controller further includes: A measuring unit is configured to obtain a maximum eye diagram of correctly sampled data by sampling data transmitted by a DQ data signal using a DQS clock signal; The training engine is further configured to instruct the memory to use the value of the DCA register corresponding to the maximum eye diagram as the optimal value of the DCA register.

10. An electronic device, characterized in that: include: A memory and a memory controller as claimed in claim 8 or 9, wherein the memory controller is connected to the memory via a DQS clock line and a DQ data line, wherein the DQS clock line is used to transmit a DQS clock signal, and the DQ data line is used to transmit a DQ data signal; The memory includes a DCA register and a signal generating unit, wherein the signal generating unit is configured to adjust the phase of a system clock signal based on a value of the DCA register and generate the DQS clock signal and the DQ data signal based on the system clock signal.

Images