A semiconductor memory test system and test method

Abstract

The present invention discloses a semiconductor memory test system and test method, which relates to the field of memory test technology. The system includes: a test board for directly inserting at least one semiconductor memory to be tested; a microclimate chamber placed on the test board for regulating the temperature environment of the test board; an offline software / test converter for writing a long vector test mode and downloading it to a vector tester to perform the test; the vector tester includes a controller and a multiplexer, a comparison logic device and a pin electronic device connected in sequence, which are used to generate a test signal according to the downloaded long vector test mode, send the test signal to the corresponding at least one semiconductor memory to be tested, and perform a logical comparison judgment according to the test feedback signal fed back by the semiconductor memory to be tested, so as to obtain the final test result. The present invention can realize semiconductor memory testing with lower cost and higher precision.

Description

Technical Field

[0001] The present invention relates to the field of memory testing technology, and in particular to a semiconductor memory testing system and a testing method. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a widely used semiconductor memory. Its working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0, so as to store data. At present, DRAM components are usually soldered to the PCB substrate to form a module, and then inserted into the motherboard of the computer system for application. Usually, the packaged DRAM components need to undergo aging tests, weak unit tests (or core tests) and speed tests to ensure that the storage components can operate normally.

[0003] During the above test process, multiple tests need to be performed under different temperature environments. However, since DRAM, a semiconductor memory, is usually soldered on a PCB substrate, temperature changes during the test process will cause processing damage to the solder contacts (such as the contact balls of FBGA components), thereby affecting subsequent tests. Currently, specific tools such as HIFIX (high-fidelity test interface board) are usually used to feed and process DRAM components during testing and electrically connect them to the test head. However, this specific tool is product-specific and must be provided for each individual DRAM. Its testing cost is high and difficult to promote. In addition, since the thermal welding process may degrade the performance of certain storage units, and due to signal noise or shared signaling, the performance of DRAM in the application may be different from the performance in the component test environment, resulting in inaccurate final test results. Summary of the invention

[0004] In order to solve the deficiencies of the above-mentioned prior art, the present invention provides a semiconductor memory testing system and a testing method. A test board that can directly grab the semiconductor memory is designed, and the test board is connected to the pin electronic equipment of a vector tester through a connector bridge, so as to realize the electrical connection between the memory and the test device. The system has low cost and is convenient to disassemble, and can effectively avoid the problem of incorrect testing caused by welding. A corresponding testing method is also designed. By calling the test mode for different types of devices under test (DUT, Device Under Test), a test signal is generated and sent to the vector tester. After the test signal is processed by the vector tester, it is transmitted to the DUT by the corresponding pin of the pin electronic equipment for testing, so as to realize semiconductor memory testing with lower cost and higher precision.

[0005] In a first aspect, the present disclosure provides a semiconductor memory testing system.

[0006] A semiconductor memory testing system, comprising:

[0007] A test board, for directly inserting at least one semiconductor memory to be tested;

[0008] A microclimate chamber is placed on the test board to control the temperature environment of the test board;

[0009] Offline software / test converter to write long vector test patterns and download to the vector tester to execute the test;

[0010] The vector tester includes a controller and a multiplexer, a comparison logic device and a pin electronic device connected in sequence, which is used to generate a test signal according to a downloaded long vector test mode, send the test signal to at least one corresponding semiconductor memory to be tested, and perform logic comparison and judgment based on the test feedback signal fed back by the semiconductor memory to be tested, so as to obtain the final test result.

[0011] A further technical solution is that the semiconductor memory to be tested is inserted into a test board, all electrical activation signals of the semiconductor memory to be tested are connected to a vector tester through the test board, and the electrical signals of the semiconductor memory to be tested are controlled by the vector tester; wherein, the semiconductor memory to be tested is placed horizontally relative to the surface of the vector tester, or the semiconductor memory to be tested is placed vertically relative to the surface of the vector tester.

[0012] In a further technical solution, the test board is connected to the pin electronics of the vector tester via a connector bridge, the microclimate chamber is electrically connected to the vector tester, and the offline software / test converter is electrically connected to the vector tester.

[0013] According to a further technical solution, a plurality of slots arranged in a matrix are provided on the upper surface or the lower surface of the test board, and the slots are used to accommodate semiconductor memories;

[0014] The test board is provided with a connector bridge. When the test board is inserted into a vector tester to test the semiconductor memory, at least one connector bridge connects at least one semiconductor memory signal to the vector tester.

[0015] In a further technical solution, the test signal includes a command signal, an address signal and a data signal;

[0016] The command signal is used to send a write or read command to the semiconductor memory under test;

[0017] The address signal is used to send the row or column address location data of the required data to the semiconductor memory under test;

[0018] The data signal is used to write data into the semiconductor memory under test or read data from the semiconductor memory under test.

[0019] A further technical solution is that for the slots arranged in a matrix in the test board, each row corresponds to a command / address bus, and the command / address bus transmits the command / address signal to all the memories under test; the semiconductor memory slots under test in the corresponding columns in each row share the same data bus.

[0020] In a further technical solution, the multiplexer is used to multiplex the same vector memory test pattern into a plurality of semiconductor memories under test DUT-1…DUT-N;

[0021] The comparison logic is used to perform logic comparison and judgment based on the data in the test signal and the test feedback signal to generate a final test result;

[0022] The pin electronics are used to transmit and drive test signals.

[0023] According to a further technical solution, the pin electronic devices are connected one-to-one with the electronic pins of the connector bridge, and each electronic pin is provided with four types of drivers, including a command driver, an address driver, a DQ / DQS driver / receiver, and two power storage signal VDD and VSS drivers.

[0024] In a second aspect, the present disclosure provides a semiconductor memory testing method.

[0025] A semiconductor memory testing method, implemented based on the semiconductor memory testing system proposed in the first aspect, comprises:

[0026] Write long vector test patterns based on offline software / test converter and download to vector tester to execute the test;

[0027] The vector tester generates a test signal according to the long vector test mode, sends the test signal to at least one corresponding semiconductor memory to be tested, and controls and adjusts the micro-climate chamber so that the semiconductor memory DUT to be tested on the test board is in a set test environment;

[0028] The vector tester receives a test feedback signal fed back by the semiconductor memory to be tested, and performs a logical comparison and judgment between the test signal and the test feedback signal to obtain a final test result.

[0029] In a further technical solution, the test signal includes a command signal, an address signal and a data signal;

[0030] During the process of sending the test signal, data is written and read to the semiconductor memory to be tested at the corresponding row and column position according to the command, address and data signal;

[0031] For each semiconductor memory to be tested, a test feedback signal is generated based on the read data and returned;

[0032] Perform logical comparison and judgment based on the data in the test signal and the test feedback signal to generate the final test result and complete the test.

[0033] One or more of the above technical solutions have the following beneficial effects:

[0034] 1. The present invention provides a semiconductor memory testing system and a testing method. A test board that can directly grab a semiconductor memory is designed, and the test board is connected to the pin electronic equipment of a vector tester through a connector bridge, so as to achieve electrical connection between the memory and the test device. The system has low cost and is easy to disassemble, and can effectively avoid the problem of incorrect testing caused by welding. A corresponding testing method is also designed. By calling test modes for different types of devices under test (DUTs), a test signal is generated and sent to a vector tester. After the test signal is processed by the vector tester, it is transmitted to the DUT by the corresponding pin of the pin electronic equipment for testing, so as to achieve lower cost and higher precision semiconductor memory testing.

[0035] 2. The present invention provides a tester resource allocation method. For each electronic pin, four types of drivers are set: a command driver, an address driver, a DQ / DQS driver / receiver and two power storage signal VDD and VSS drivers, which are respectively used to drive the command, address, and data signals in the transmission test signal and provide power signals, so as to obtain maximum flexibility for testing, so that any test board can be connected to the tester pin resources, thereby improving applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0037] Figure 1 A schematic diagram of the structure of a semiconductor memory test system according to an embodiment of the present invention;

[0038] Figure 2 Schematic diagram of the structure of the existing test board and the test board proposed in the embodiment of the present invention; wherein ( a ) is a schematic diagram of the structure of the existing test board, ( b ) is a schematic diagram of the structure of a test board proposed in an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of the structure of a vector tester in an embodiment of the present invention;

[0040] Figure 4Schematic diagram of the connection structure of the electronic pins in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] It should be noted that the following detailed descriptions are exemplary only, are intended to describe specific embodiments, are intended to provide further explanation of the present invention, and are not intended to limit exemplary embodiments according to the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those of ordinary skill in the art to which the present invention belongs. In addition, it should also be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0042] Embodiment 1

[0043] This embodiment provides a semiconductor memory test system. Figure 1 As shown, including:

[0044] A test board, for directly inserting at least one semiconductor memory to be tested;

[0045] A microclimate chamber is placed on the test board to control the temperature environment of the test board;

[0046] Offline software / test converter to write long vector test patterns and download to the vector tester to execute the test;

[0047] The vector tester includes a controller and a multiplexer, a comparison logic device and a pin electronic device connected in sequence, which is used to generate a test signal according to a downloaded long vector test mode, send the test signal to at least one corresponding semiconductor memory to be tested, and perform logic comparison and judgment based on the test feedback signal fed back by the semiconductor memory to be tested, so as to obtain the final test result.

[0048] Further, the test board is connected to the pin electronics of the vector tester via a connector bridge, the microclimate chamber is electrically connected to the vector tester, and the offline software / test converter is electrically connected to the vector tester.

[0049] Specifically, considering that the existing memory production test system usually uses a soldering load board and a patching process to connect the DRAM to the tester, it is expensive and inflexible to use. For example, in actual applications, soldering the DRAM to the Figure 2 middle( a) is provided with only a single row of welding grooves, and then multiple test boards are inserted into the computer, which often has power supply and signal integrity problems. To this end, the present embodiment proposes a test board, which may also be called an acquisition card, in which the semiconductor memory to be tested is inserted into the test board, and all electrical activation signals of the semiconductor memory to be tested are connected to the vector tester through the test board, and the electrical signals of the semiconductor memory to be tested are controlled by the vector tester; wherein the semiconductor memory to be tested is placed horizontally relative to the surface of the vector tester, or the semiconductor memory to be tested is placed vertically relative to the surface of the vector tester. The test board proposed in the present embodiment is used to accommodate all devices to be tested / tested, and the test board is as follows Figure 2 middle( b ), its design is similar to that of the existing memory acquisition card, however, in the test board proposed in this embodiment, multiple rows of semiconductor memory slots to be tested are provided, each row corresponds to a command / address bus (i.e., addr / cmd), the command / address bus transmits the command / address to all the memories under test, and uses Rtt (Real-Time Terminal) as a high-performance log output, in addition, the semiconductor memory slots to be tested in the corresponding columns in each row share the same data bus: shared data and data selection lines (i.e., DQ and DQS), thereby achieving parallel testing of more devices.

[0050] The test board proposed in this embodiment only needs fewer processing / contact storage components, thus further improving quality and reducing costs. In addition, the test board has a corresponding pin allocation design, which will follow the resources defined by the vector tester.

[0051] A microclimate chamber, also known as a microclimate box, is a highly insulated chamber with the same size as the test board. The microclimate chamber is placed on the test board to create a high or low temperature environment. The temperature of the microclimate chamber is controlled by a vector tester. Ideally, the climate box supports a temperature range of -40°C to 150°C to allow testing of various types of memory and multiple test conditions such as aging conditions.

[0052] The offline software / test converter is used to write long vector test patterns and download them to the vector tester to perform the test. Furthermore, the offline software / test converter can be used for test vector generation, vector parsing and conversion, etc.

[0053] The vector tester can be used to test any memory component. It can generate a test signal according to the downloaded long vector test pattern to test at least one semiconductor memory to be tested on the test board. During the test, the entire memory is first traversed in the X direction and then in the Y direction and 1 is written, and then the entire array is traversed in the X direction, and then the entire array is traversed in the Y direction, and 1 is read and modified to 0. That is, a vector of its own is written into the memory for each address, and then the content data is read, so as to test the pattern from the actual application program.

[0054] The above-mentioned vector tester is used to generate a test signal according to a downloaded long vector test pattern, and the test signal includes a command signal, an address signal and a data signal. The command signal is used to send a write or read command to the semiconductor memory under test, the address signal is used to send the row or column address position data of the required data to the semiconductor memory under test, and the data signal is used to write data into the semiconductor memory under test or read data from the semiconductor memory under test.

[0055] Furthermore, the upper surface or the lower surface of the test board is provided with a plurality of slots arranged in a matrix, and the slots are used to accommodate semiconductor memories; the test board is provided with a connector bridge, and when the test board is inserted into a vector tester to test the semiconductor memory, at least one connector bridge connects at least one semiconductor memory signal to the vector tester. Figure 3 As shown, the vector tester includes a multiplexer, a comparison logic device and a pin electronic device connected in sequence, and also includes a tester CPU and a vector memory (i.e., a memory device) electrically connected to the multiplexer. Figure 3 The vector memory test vector 1DUT shown.

[0056] The vector memory contains all test vectors such as temperature, various test algorithms, and frequency of a single DUT (i.e., the device under test). The test vector is transmitted and presented in the form of a test signal. The acquired test signal is integrated in a memory. Since all DUTs are memories of the same type, the same test mode can be used to test all modes of each DUT. In order to save data space, a multiplexer is used to multiplex the same vector memory test mode (presented in the form of a test signal) into multiple semiconductor memories under test DUT-1...DUT-N. Since each DUT is independent and identical, the test content is unified to each DUT. It is no longer necessary to measure each DUT separately, but the multiplexer is used to test them simultaneously, realizing one-to-many simultaneous testing, improving test efficiency, and realizing mass production mode.

[0057] Furthermore, the vector tester sends a test signal to the semiconductor memory to be tested, and the electronic pin will generate an actual electrical signal for each DUT pin on the test board, write and read data to the semiconductor memory to be tested at the corresponding row and column position according to the command, address, and data signal, and generate a test feedback signal based on the read data for each semiconductor memory to be tested, and the vector tester then performs a logical comparison and judgment based on the test signal and the data in the test feedback signal. Among them, the comparison logic is used to store and execute comparison and control logic, and store processing results, that is, in this embodiment, the comparison logic is used to compare the data read from the DUT on the test board with the expected data, generate the final test result, and complete the test.

[0058] In addition to the above-mentioned command, address, and data signals, the test signals also include power signals and other signals. Take the following signals to be controlled during the test of the example 4G DDR-3 x4 memory in the BGA-78 package as an example. The test signals include (for simplicity, the polarity of the signal is not considered here. For example, there are actually two CK signals, namely, the CK signal and the anti-CK signal):

[0059] 19 address signals: A0-A15 and BA0-2;

[0060] 7 command signals: RAS, CAS, WE, CS, RESET, CK, ODT;

[0061] 9 data signals: DQ0-7 and DQS;

[0062] 15 ground voltage signals: VSS and VSSQ;

[0063] 7 power supply signals: VDD;

[0064] 4 power supply signals: VDDQ;

[0065] 1 power signal: VREFCA;

[0066] 1 signal: ZQ (connected to an external 240 Ohm high precision resistor for calibration);

[0067] 3 No connection signal: NC;

[0068] Among the above signals, the CK signal represents the differential clock input signal, the RAS signal represents the row address signal, the CAS signal represents the column address signal, the WE signal represents the read / write control signal, the CS signal represents the chip select signal, the RESET signal represents the reset signal, the ODT signal can enable the terminal resistance inside the memory, and DRAM turns off the terminal resistance for each DQ, DQS, etc. through the ODT control pin. The DQ signal represents data input and output, the DQS signal represents the differential data selection signal, the VSS and VSSQ signals represent CA power supply and grounding, the VDD and VDDQ signals represent input / output power supply and grounding respectively, the VREFCA signal represents the reference voltage, the ZQ signal represents the calibration reference resistance, and the NC signal represents no electrical connection. The above signals are common signals of existing memory storage devices and will not be repeated here.

[0069] The vector tester drives the above signals through pin electronic devices. Among them, the vector tester is also equipped with a delay register, which controls the issuance of each pin drive signal to ensure synchronous transmission of data signals, thereby ensuring the accuracy of subsequent test results.

[0070] Furthermore, for the driving of the above-mentioned signals, the address signal, command signal, data signal and power signal are mainly analyzed. Obviously, the command signal (unidirectional) or data signal (bidirectional) or power signal (connected to a fixed potential) requires different pin electronic devices to generate and / or read the relevant signals, while the existing test system provides different signal groups and connects them to the DUT through expensive boards, which limits the flexibility of the tester and requires a new connector board for the new product DUT. For example, 4G x8 DDR-3 memory and 8G x4 DDR-4 memory require completely different connector boards. For this reason, in this embodiment, in combination with the above-mentioned test method, a completely different tester resource allocation method is also proposed, such as Figure 4 As shown, the command pin CMD (corresponding to the command signal) only needs one signal driver, and the address pin Addr is the same, but the data pin DQ / DQS needs a driver / receiver to read and write data to the DUT, and the power pin only needs to be connected to the wire of the relevant power storage device, which is realized by VDD (connected to the power supply) and VSS (grounded). In this embodiment, a test board with 69 pins is used, that is, the electronic pin must provide at least 69 pins. In order to obtain maximum configuration flexibility, the electronic pin is provided with all possible signal drivers / receivers for each pin required to be connected to the DUT, so 4 types of drivers are set for each electronic pin: command driver, address driver, DQ / DQS driver / receiver and two power storage signals VDD and VSS, so as to obtain maximum test flexibility.

[0071] Furthermore, the actual configuration of the test board connectors is done via a connector bridge, allowing for maximum flexibility, and any test board can be connected to the tester pin resources. Before starting semiconductor memory testing, a simple mechanical connector bridge is inserted to configure the tester to any DUT required.

[0072] Embodiment 2

[0073] This embodiment provides a semiconductor memory testing method, which is implemented based on the semiconductor memory testing system proposed in Embodiment 1 and includes the following steps:

[0074] Write long vector test patterns based on offline software / test converter and download to vector tester to execute the test;

[0075] The vector tester generates a test signal according to the long vector test mode, sends the test signal to at least one corresponding semiconductor memory to be tested, and controls and adjusts the micro-climate chamber so that the semiconductor memory DUT to be tested on the test board is in a set test environment;

[0076] The vector tester receives a test feedback signal fed back by the semiconductor memory to be tested, and performs a logical comparison and judgment between the test signal and the test feedback signal to obtain a final test result.

[0077] Furthermore, in the process of generating the test signal, the test signal is multiplexed into a plurality of semiconductor memories under test DUT-1 . . . DUT-N.

[0078] Further, the test signal includes a command signal, an address signal and a data signal;

[0079] During the process of sending the test signal, data is written and read to the semiconductor memory to be tested at the corresponding row and column position according to the command, address and data signal;

[0080] For each semiconductor memory to be tested, a test feedback signal is generated based on the read data and returned;

[0081] Perform logical comparison and judgment based on the data in the test signal and the test feedback signal to generate the final test result and complete the test.

[0082] Specifically, in a vector tester, a multiplexer multiplexes the test signal into multiple DUTs of the same type, and transmits the test signal (including command, address, and data signals) to the DUT through pin electronic devices and connector bridges, wherein the data (i.e., data signal) is transmitted to the correct position of the DUT according to the address signal, and the feedback data in the DUT is read (the data signal is a bidirectional signal line), and a logical comparison of the data is performed with the expected data in a comparison logic device to complete the test.

[0083] Further, the generated test results are output to the offline software / test converter for display.

[0084] Those skilled in the art should understand that the modules or steps of the present invention described above can be implemented by a general-purpose computer device, or alternatively, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. The present invention is not limited to any specific combination of hardware and software.

[0085] The above description is only a preferred embodiment of the present invention. Although the specific implementation mode of the present invention is described in conjunction with the accompanying drawings, it is not a limitation of the protection scope of the present invention. Those skilled in the art should understand that on the basis of the technical solution of the present invention, various modifications or variations that can be made by those skilled in the art without creative work are still within the protection scope of the present invention.

Claims

1. A semiconductor memory test system, characterized in that: include: A test board, for directly inserting at least one semiconductor memory to be tested; A microclimate chamber is placed on the test board to control the temperature environment of the test board; Offline software / test converter to write long vector test patterns and download to the vector tester to execute the test; The vector tester includes a controller and a multiplexer, a comparison logic device and a pin electronic device connected in sequence, which is used to generate a test signal according to a downloaded long vector test pattern, send the test signal to at least one corresponding semiconductor memory to be tested, and perform logic comparison and judgment according to the test feedback signal fed back by the semiconductor memory to be tested, so as to obtain a final test result; The test signals include command signals, address signals and data signals; The command signal is used to send a write or read command to the semiconductor memory under test; The address signal is used to send the row or column address location data of the required data to the semiconductor memory under test; The data signal is used to write data into the semiconductor memory under test or read data from the semiconductor memory under test; The multiplexer is used to multiplex the same vector memory test pattern into a plurality of semiconductor memories under test DUT-1 ... DUT-N; The comparison logic is used to perform logic comparison and judgment based on the data in the test signal and the test feedback signal to generate a final test result; The pin electronic device is used to transmit and drive the test signal; The pin electronics are connected one-to-one with the electronic pins of the connector bridge, and each electronic pin is provided with four types of drivers, including a command driver, an address driver, a DQ / DQS driver / receiver, and two power storage signal VDD and VSS drivers.

2. The semiconductor memory test system according to claim 1, wherein: The semiconductor memory to be tested is inserted into the test board, and all electrical activation signals of the semiconductor memory to be tested are connected to the vector tester through the test board, and the electrical signals of the semiconductor memory to be tested are controlled by the vector tester; The semiconductor memory to be tested is placed horizontally relative to the surface of the vector tester, or the semiconductor memory to be tested is placed vertically relative to the surface of the vector tester.

3. The semiconductor memory test system according to claim 1, wherein: The test board is connected to the pin electronics of the vector tester through a connector bridge, the microclimate chamber is electrically connected to the vector tester, and the offline software / test converter is electrically connected to the vector tester.

4. The semiconductor memory test system according to claim 3, characterized in that: The upper surface or the lower surface of the test board is provided with a plurality of slots arranged in a matrix, and the slots are used to accommodate semiconductor memories; The test board is provided with a connector bridge. When the test board is inserted into a vector tester to test the semiconductor memory, at least one connector bridge connects at least one semiconductor memory signal to the vector tester.

5. The semiconductor memory test system according to claim 1, wherein: For the slots arranged in a matrix in the test board, each row corresponds to a command / address bus, which transmits command / address signals to all the memories under test; the semiconductor memory slots under test in the corresponding columns in each row share the same data bus.

6. A semiconductor memory testing method, characterized in that: The semiconductor memory test system according to any one of claims 1 to 5 is implemented, comprising: Write long vector test patterns based on offline software / test converter and download to vector tester to execute the test; The vector tester generates a test signal according to the long vector test mode, sends the test signal to at least one corresponding semiconductor memory to be tested, and controls and adjusts the micro-climate chamber so that the semiconductor memory DUT to be tested on the test board is in a set test environment; The vector tester receives a test feedback signal fed back by the semiconductor memory to be tested, and performs a logical comparison and judgment between the test signal and the test feedback signal to obtain a final test result.

7. The semiconductor memory testing method according to claim 6, wherein: The test signal includes a command signal, an address signal and a data signal; During the process of sending the test signal, data is written and read to the semiconductor memory to be tested at the corresponding row and column position according to the command, address and data signal; For each semiconductor memory to be tested, a test feedback signal is generated based on the read data and returned; Perform logical comparison and judgment based on the data in the test signal and the test feedback signal to generate the final test result and complete the test.

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