Detector chip structure and preparation method thereof

Abstract

The present invention discloses a detector chip structure and a preparation method. By setting an annular diffusion area on the periphery of the detector, a discrete capacitor is formed to form an electrostatic charging and discharging channel, thereby improving the detector's electrostatic breakdown resistance to a certain extent; by forming a groove between the annular diffusion area and the device active area (absorption layer and cap layer in the table structure) for isolation, the size of the actual active area of ​​the device is not affected, and the bandwidth of the device is not affected. In addition, the discrete capacitor formed by setting the annular diffusion area can be connected to the ground through the first electrode of the detector, which can reduce the capacitance value at the device electrode, thereby reducing the overall C value of the device, and to a certain extent, the bandwidth of the device can be improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor device manufacturing, and in particular relates to a detector chip structure and a preparation method thereof. Background Art

[0002] Optical communication is one of the most important information and communication infrastructures. With the commercialization of new technologies such as cloud computing and big data, data center traffic and bandwidth have grown exponentially. The construction of large and super-large data centers has gradually increased, and the data center market's demand for bandwidth has also continued to increase, which has led to a growing demand for the development of 400G and even 800G / 1.6T higher-speed optical communication products. As the core component of high-speed optical modules, the modulation bandwidth, device reliability, and stability of high-speed detectors strictly restrict and affect the further development and use of high-speed optical modules.

[0003] The bandwidth of InP / InGaAs PIN detector is mainly related to the carrier transit time and RC constant (product of resistance and capacitance), among which RC constant is the main influencing factor. Therefore, in order to obtain higher bandwidth, an effective method is to reduce the size of the active area of ​​the device, reduce the thickness of the absorption area, reduce the ohmic contact resistance of the device, etc. However, the reduction of the thickness of the absorption area will lead to a significant decrease in the responsiveness of the device, so the solution of reducing the size of the active area of ​​the device is usually adopted to improve the bandwidth of the detector. However, as the size of the active area of ​​the device is reduced, the electrostatic breakdown voltage of the device is also reduced, which makes the device prone to electrostatic breakdown failure during the module assembly process.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a detector chip structure and a preparation method thereof, which can improve the anti-static breakdown capability of the detector to a certain extent without affecting the bandwidth of the device, and can even improve the bandwidth of the device to a certain extent.

[0006] In order to achieve the above object, a specific embodiment of the present invention provides a detector chip structure, including:

[0007] a substrate having opposing first and second surfaces;

[0008] An epitaxial structure is formed on the first surface of the substrate, the epitaxial structure comprises a contact layer, a transition layer, an absorption layer, and a cap layer arranged in sequence in a direction away from the substrate; the epitaxial structure comprises a mesa structure located in the middle and a torus structure arranged around the mesa structure, and an annular diffusion region is formed in the cap layer located in the torus structure;

[0009] A passivation layer is formed on the surface of the epitaxial structure, a first window is formed on the passivation layer on the surface of the mesa structure to expose the cap layer, a second window is formed on the surface of the contact layer to expose the contact layer, and a third window is formed on the surface of the annular structure to expose the annular diffusion region;

[0010] A first electrode formed in the first window and electrically connected to the cap layer;

[0011] a second electrode formed in the second window and electrically connected to the contact layer;

[0012] The third electrode is formed in the third window and electrically connected to the annular diffusion region.

[0013] In one or more embodiments of the present invention, a first diffusion region is formed in the cap layer of the mesa structure, the first window exposes the first diffusion region, and the first electrode is formed on a surface of the first diffusion region.

[0014] In one or more embodiments of the present invention, a second diffusion region is formed in the cap layer of the mesa structure, and the second diffusion region extends below the first diffusion region and is located within the coverage of the first diffusion region.

[0015] In one or more embodiments of the present invention, a size of the first diffusion region is 10 μm to 16 μm.

[0016] In one or more embodiments of the present invention, the sum of the depths of the first diffusion region and the second diffusion region does not exceed 0.5 μm.

[0017] In one or more embodiments of the present invention, a groove exposing the contact layer is formed between the mesa structure and the ring structure.

[0018] In one or more embodiments of the present invention, the groove is filled with polyimide material.

[0019] In one or more embodiments of the present invention, the second surface of the substrate is divided into a photosensitive area and a non-photosensitive area, the photosensitive area is arranged corresponding to the mesa structure, an anti-reflection film is arranged on the substrate in the photosensitive area, and an anti-reflection film is arranged on the substrate in the non-photosensitive area.

[0020] In one or more embodiments of the present invention, the material of the substrate includes InP.

[0021] In one or more embodiments of the present invention, the material of the contact layer includes InP, the thickness of the contact layer is 0.5 μm to 2 μm, and the contact layer is a doped layer with a doping concentration of 5e18 cm 3 ~1e19 / cm 3 .

[0022] In one or more embodiments of the present invention, the transition layer includes multiple InGaAsP layers with gradient energy bands, and the thickness of each InGaAsP layer is 0.02 μm to 0.04 μm.

[0023] In one or more embodiments of the present invention, the material of the absorption layer includes InGaAs, the thickness of the absorption layer is 0.3 μm to 0.5 μm, and the absorption layer is a doped layer with a doping concentration of 5e14 cm 3 ~1e15 / cm 3 .

[0024] In one or more embodiments of the present invention, the material of the cap layer includes InP, the thickness of the cap layer is 0.5 μm to 1 μm, the cap layer is a non-doped layer or a lightly doped layer, and when the cap layer is a lightly doped layer, the doping concentration is 1e15 / cm 3 -5e16 / cm 3 .

[0025] In one or more embodiments of the present invention, the depth of the annular diffusion region does not exceed the thickness of the cap layer.

[0026] In one or more embodiments of the present invention, the depth of the annular diffusion region is 0.2 μm to 0.5 μm, and the width of the annular diffusion region is 2 μm to 5 μm.

[0027] A specific embodiment of the present invention further provides a method for preparing a detector chip, comprising:

[0028] Providing a substrate having a first surface and a second surface disposed opposite to each other;

[0029] Growing an epitaxial structure on the first surface of the substrate, the epitaxial structure comprising a contact layer, a transition layer, an absorption layer, and a cap layer grown in sequence;

[0030] Performing annular diffusion on the periphery of the cap layer of the epitaxial structure to form an annular diffusion zone;

[0031] Diffusion is performed in the middle of the cap layer of the epitaxial structure to form a first diffusion region;

[0032] Etching the epitaxial structure until the contact layer is exposed to form a mesa structure in the middle and a torus structure in the periphery, wherein the first diffusion region is located in the mesa structure and the annular diffusion region is located in the torus structure;

[0033] forming a passivation layer on the surface of the epitaxial structure;

[0034] Etching the passivation layer to expose a portion of the contact layer, a portion of the first diffusion region located on the surface of the mesa structure, and a portion of the annular diffusion region located on the surface of the annular structure;

[0035] A first electrode electrically connected to the first diffusion region, a second electrode electrically connected to the contact layer, and a third electrode electrically connected to the annular diffusion region are formed.

[0036] In one or more embodiments of the present invention, after the step of diffusing in the middle of the cap layer of the epitaxial structure to form a first diffusion region, the step further includes:

[0037] A secondary diffusion is performed in the middle of the cap layer of the epitaxial structure to form a second diffusion region, wherein the second diffusion region extends below the first diffusion region and is located within the coverage of the first diffusion region.

[0038] In one or more embodiments of the present invention, in the step of etching the epitaxial structure to expose the contact layer to form a mesa structure in the middle and an annular structure at the periphery, a groove between the mesa structure and the annular structure is also formed by etching.

[0039] In one or more embodiments of the present invention, after the step of forming a passivation layer on the surface of the epitaxial structure, the method further includes:

[0040] The groove is filled with a polyimide material.

[0041] In one or more embodiments of the present invention, the preparation method further comprises:

[0042] thinning the substrate;

[0043] An anti-reflection film is formed on the area of ​​the second surface of the substrate corresponding to the mesa structure, and an anti-reflection film is formed on other areas of the second surface of the substrate.

[0044] In one or more embodiments of the present invention, a first diffusion region with a size of 10 μm to 16 μm is formed in the middle of the cap layer of the epitaxial structure through a diffusion process.

[0045] In one or more embodiments of the present invention, the thickness of the absorption layer is controlled to be 0.3 μm to 0.5 μm.

[0046] In one or more embodiments of the present invention, before forming a first electrode electrically connected to the first diffusion region, a second electrode electrically connected to the contact layer, and a third electrode electrically connected to the annular diffusion region, it also includes forming an ohmic contact layer and performing an annealing process.

[0047] Compared with the prior art, the detector chip structure and preparation method thereof of the present invention form discrete capacitors and electrostatic charging and discharging channels by setting an annular diffusion zone on the periphery of the detector, thereby improving the detector's ability to withstand electrostatic breakdown to a certain extent.

[0048] The detector chip structure and preparation method of the present invention, since the annular diffusion region is isolated from the device active region (absorption layer and cap layer in the mesa structure) by a groove formed by an etching process, the setting of the annular diffusion region will not affect the size of the actual active region of the device, and thus will not affect the bandwidth of the device.

[0049] The detector chip structure and preparation method thereof of the present invention, due to the discrete capacitor formed by setting the annular diffusion zone, can be connected to the ground through the first electrode of the detector, which can reduce the capacitance value at the device electrode, thereby reducing the overall C value of the device, and to a certain extent, can improve the bandwidth of the device.

[0050] The detector chip structure and preparation method thereof of the present invention optimize the size of the device active area (absorption layer and cap layer in the table structure), reduce the thickness of the absorption layer in the table structure, and reduce the ohmic contact resistance of the device by selecting a suitable metal film system and annealing process, thereby effectively improving the bandwidth of the detector. At the same time, it can also ensure the electrostatic breakdown voltage of the device and avoid electrostatic breakdown failure during module assembly.

[0051] The detector chip structure and preparation method thereof of the present invention adopt a two-step diffusion technology to ensure the uniformity and accuracy of diffusion of the active area and the annular diffusion area, thereby ensuring the stable performance of the detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 A schematic cross-sectional view of a detector chip structure in one embodiment of the present invention;

[0054] Figure 2 is a process flow chart of a method for preparing a detector chip in one embodiment of the present invention;

[0055] Figure 3a-3f It is a schematic diagram of the steps of a method for preparing a detector chip in one embodiment of the present invention;

[0056] Figure 4 This is a test diagram of electrostatic breakdown voltage after the ESD HBM test of the device in Example 2;

[0057] Figure 5 This is a test diagram of electrostatic breakdown voltage after the ESD HBM test of the device in Comparative Example 1;

[0058] Figure 6 This is a diagram showing the electrostatic breakdown position observed by Thermal after the ESD test of the device in Example 2;

[0059] Figure 7 This is a diagram showing the electrostatic breakdown position observed by Thermal after the ESD test of the device in Comparative Example 1;

[0060] Figure 8 This is a device bandwidth test diagram in Example 2;

[0061] Fig. 9 This is a device bandwidth test diagram in comparative example 1. DETAILED DESCRIPTION

[0062] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0063] As mentioned in the background technology, in the field of semiconductor device manufacturing technology, high-speed detectors are an important electronic device, widely used in optical communications, radar detection and other fields. Among them, InP / InGaAs PIN detectors are a common high-speed detector, and their modulation bandwidth and device reliability and stability strictly restrict and affect the further development and use of high-speed optical modules.

[0064] Factors that affect the response speed of photodetectors include, in addition to the carrier transit time in the device (including carrier drift and diffusion), the circuit response time after the device is connected to the external test circuit. The light-to-electric conversion speed of the detector is limited by the carrier transport time in the device and the external parasitic RC time constant. Therefore, the main measures to improve the device's photoelectric conversion speed, i.e., the frequency domain bandwidth, include reducing the size of the device's active area, reducing the thickness of the intrinsic absorption region, reducing the device's depletion region capacitance, reducing the device's metal contact resistance, and reducing the device's electrode lead capacitance.

[0065] The modulation bandwidth strictly restricts and affects the data receiving rate of high-speed optical modules. In the existing technology, in order to improve the bandwidth of the detector, the commonly used method is to reduce the size of the active area of ​​the device, reduce the thickness of the absorption area, reduce the ohmic contact resistance of the device, etc. The reduction in the thickness of the absorption area will lead to a significant decrease in the responsiveness of the device, so the solution of reducing the size of the active area of ​​the device is usually adopted to increase the bandwidth of the detector. However, although this method can increase the bandwidth of the detector, it will reduce the electrostatic breakdown voltage of the device, making the device prone to electrostatic breakdown failure during the module assembly process.

[0066] Therefore, while the existing technology improves the bandwidth of the detector, it often reduces the electrostatic breakdown voltage of the device, making the device prone to electrostatic breakdown failure during module assembly. This not only affects the performance and reliability of the detector, but also brings great trouble to practical applications. Therefore, how to improve the detector's resistance to electrostatic breakdown while increasing its bandwidth is an urgent problem to be solved in the current technological development.

[0067] In order to solve the problems in the prior art, the present invention proposes a detector chip structure and a preparation method thereof, wherein an annular diffusion area is provided at the periphery of the detector to form a discrete capacitor and an electrostatic charging and discharging channel, thereby improving the detector's ability to withstand electrostatic breakdown to a certain extent; a groove is formed between the annular diffusion area and the device active area (absorption layer and cap layer in the table structure) for isolation, thereby not affecting the size of the actual active area of ​​the device and not affecting the bandwidth of the device. In addition, the discrete capacitor formed by the provision of the annular diffusion area can be connected to the ground through the first electrode of the detector, which can reduce the capacitance value at the device electrode, thereby reducing the overall C value of the device, and to a certain extent, can improve the bandwidth of the device.

[0068] like Figure 1 As shown, the detector chip structure in an embodiment of the present invention includes a substrate 10 , an epitaxial structure 20 , a passivation layer 30 , a first electrode 40 , a second electrode 50 and a third electrode 60 .

[0069] The substrate 10 is preferably an intrinsic InP substrate and has a first surface 10a and a second surface 10b opposite to each other.

[0070] The epitaxial structure 20 is formed on the first surface 10 a of the substrate 10 , and includes a contact layer 21 , a transition layer 22 , an absorption layer 23 , and a cap layer 24 , which are sequentially arranged in a direction away from the substrate 10 .

[0071] The material of the contact layer 21 includes InP. The thickness of the contact layer 21 is 0.5 μm to 2 μm. The contact layer 21 is an N++ type doped layer with a doping concentration of 5e18 cm 3 ~1e19 / cm 3 .

[0072] The transition layer 22 includes a plurality of intrinsic InGaAsP layers with gradient energy bands, and the thickness of each InGaAsP layer is 0.02 μm to 0.04 μm.

[0073] It is understandable that the gradual change of the energy band can be achieved by changing the components of the multinary compound InGaAsP. Since this method belongs to the prior art and is not the innovation of the present application, the present application will not elaborate on it in detail.

[0074] The material of the absorption layer 23 includes InGaAs. The thickness of the absorption layer 23 is 0.3 μm to 0.5 μm. The absorption layer 23 is a doped layer with a doping concentration of 5e14 cm 3 ~1e15 / cm 3 .

[0075] The material of the cap layer 24 includes InP. The thickness of the cap layer 24 is 0.5 μm to 1 μm. The cap layer 24 is a non-doped layer or a lightly N-type doped layer. When the cap layer 24 is a lightly N-type doped layer, the doping concentration is 1e15 / cm 3 -5e16 / cm 3 .

[0076] The epitaxial structure 20 includes a mesa structure 20a located in the middle and a ring structure 20b arranged around the mesa structure 20a, and an annular diffusion region 241 is formed in the cap layer 24 located in the ring structure 20b. The depth of the annular diffusion region 241 does not exceed the thickness of the cap layer 24. Preferably, the depth of the annular diffusion region 241 is 0.2μm to 0.5μm, and the width of the annular diffusion region 241 is 2μm to 5μm.

[0077] A first diffusion region 242 is formed in the cap layer 24 of the mesa structure 20a. The size of the first diffusion region 242 is 10 μm to 16 μm.

[0078] A second diffusion region 243 is formed in the cap layer 24 of the mesa structure 20a. The second diffusion region 243 extends below the first diffusion region 242 and is located within the coverage of the first diffusion region 242. The sum of the depths of the first diffusion region 242 and the second diffusion region 243 does not exceed 0.5 μm.

[0079] In the above technical solution, the setting of the first diffusion zone 242 and the second diffusion zone 243 changes the lateral size of the active area (absorption layer and cap layer) located in the table structure 20a, which can improve the bandwidth of the detector; and the setting of the annular diffusion zone 241 improves the detector's resistance to electrostatic breakdown.

[0080] In one embodiment, a groove c is formed between the mesa structure 20a and the ring structure 20b to expose the contact layer 21. The size of the groove c is preferably 5 μm to 10 μm. The setting of the groove c limits the size of the active area, so that the set annular diffusion area 241 does not affect the size of the actual active area of ​​the device, and thus does not affect the bandwidth of the device.

[0081] The passivation layer 30 is formed on the surface of the epitaxial structure 20. Specifically, the passivation layer 30 covers the exposed upper surface of the contact layer 21 (the surface facing away from the substrate), including the upper surface of the contact layer 21 exposed by the groove c, the sidewall and upper surface of the ring structure 20b (the surface facing away from the substrate), and the sidewall and upper surface of the mesa structure 20a (the surface facing away from the substrate).

[0082] A first window is formed on the passivation layer 30 on the upper surface of the mesa structure 20a to expose the first diffusion region 242 of the cap layer 24, a second window is formed on the surface of the contact layer 21 to expose the contact layer 21, and a third window is formed on the upper surface of the annular structure 20b to expose the annular diffusion region 241. The third window is also arranged in an annular shape to match the annular diffusion region 241.

[0083] The first electrode 40 is formed in the first window and electrically connected to the first diffusion region 242 of the cap layer 24 .

[0084] The second electrode 50 is formed in the second window and electrically connected to the contact layer 21 .

[0085] The third electrode 60 is formed in the third window and electrically connected to the annular diffusion region 241 of the cap layer 24 .

[0086] In order to further improve the stability and reliability of the device, in one embodiment, the groove c between the mesa structure 20 a and the ring structure 20 c is filled with a polyimide material d.

[0087] The second surface 10b of the substrate 10 is divided into a photosensitive area and a non-photosensitive area. The photosensitive area is arranged corresponding to the mesa structure 20a. Preferably, the size of the photosensitive area is equal to the size of the mesa structure, and the mesa structure covers the photosensitive area in the thickness direction of the device. A near-infrared band light anti-reflection film 11 is arranged on the substrate 10 in the photosensitive area, and an anti-reflection film 12 is arranged on the substrate 10 in the non-photosensitive area.

[0088] In the above embodiment, the thickness of the absorption layer 23 is set within 0.5 μm, and the sizes of the first diffusion region 242 and the second diffusion region 243 are set at 10 μm to 16 μm, further increasing the bandwidth of the device; but due to the setting of the annular diffusion region 241, the electrostatic breakdown voltage of the device increases instead of decreases.

[0089] like Figure 2 As shown, an embodiment of the present application provides a method for preparing the above-mentioned detector chip, which specifically includes the following steps:

[0090] S1, providing a substrate, wherein the substrate has a first surface and a second surface arranged opposite to each other.

[0091] S2, growing an epitaxial structure on the first surface of the substrate. The epitaxial structure includes a contact layer, a transition layer, an absorption layer, and a cap layer grown in sequence.

[0092] S3, performing annular diffusion on the periphery of the cap layer of the epitaxial structure to form an annular diffusion zone.

[0093] S4, diffusion is performed in the middle of the cap layer of the epitaxial structure to form a first diffusion region.

[0094] S5, etching the epitaxial structure until the contact layer is exposed, so as to form a mesa structure in the middle and a torus structure in the periphery. The first diffusion region is located in the mesa structure, and the annular diffusion region is located in the torus structure.

[0095] S6, forming a passivation layer on the surface of the epitaxial structure.

[0096] S7, etching the passivation layer to expose a portion of the contact layer, a portion of the first diffusion region located on the surface of the mesa structure, and a portion of the annular diffusion region located on the surface of the annular structure.

[0097] S8, forming a first electrode electrically connected to the first diffusion region, a second electrode electrically connected to the contact layer, and a third electrode electrically connected to the annular diffusion region.

[0098] S9, thinning the substrate, forming an anti-reflection film on the area of ​​the second surface of the substrate corresponding to the mesa structure, and forming an anti-reflection film on other areas of the second surface of the substrate.

[0099] The order of step S3, step S4 and step S5 can be changed at will. For example, the etching of the mesa structure and the annular structure can be performed first, and then the annular diffusion region and the first diffusion region can be prepared. The first diffusion region can also be prepared first, and then the etching of the mesa structure and the annular structure can be performed, and finally the annular diffusion region can be prepared. Of course, the annular diffusion region and the first diffusion region can also be prepared simultaneously in one step.

[0100] After step S3: performing diffusion in the middle of the cap layer of the epitaxial structure to form a first diffusion region, the method further includes performing secondary diffusion in the middle of the cap layer of the epitaxial structure to form a second diffusion region. The second diffusion region extends below the first diffusion region and is located within the coverage of the first diffusion region.

[0101] It is understandable that the above step is only required to be performed after the first diffusion region is prepared and formed, but does not emphasize that the second diffusion region needs to be prepared immediately after the first diffusion region is prepared. Therefore, this step has no sequence with step S4 and step S5.

[0102] In step S5 , a trench located between the mesa structure and the ring structure is formed in the epitaxial structure by an etching process.

[0103] In order to improve the stability and reliability of the device, after step S6: forming a passivation layer on the surface of the epitaxial structure, the method further includes: filling the trench with a polyimide material.

[0104] Before the step S8 of forming electrical connection: the first electrode of the first diffusion region, the second electrode of the electrical connection contact layer, and the third electrode of the electrical connection ring diffusion region, an ohmic contact layer is formed and an annealing process is performed. The ohmic contact resistance of the device can be reduced by selecting a suitable metal film system as the ohmic contact layer and an annealing process.

[0105] Figure 3a to Figure 3f is a schematic diagram of the steps of the method for preparing the detector chip of the present invention, Figure 3a to Figure 3f The process shown can be used to manufacture the above-mentioned detector chip structure. The description of the detector chip structure in the above text can be combined here.

[0106] like Figure 3a As shown, an intrinsic InP substrate 10 is provided. The substrate 10 has a first surface 10a and a second surface 10b opposite to each other.

[0107] An N++-doped InP contact layer 21 is grown on the first surface 10a of the intrinsic InP substrate 10 by using an epitaxial growth process, with a thickness of 0.5 μm to 2 μm and a doping concentration of 5e18 cm 3 ~1e19 / cm 3 .

[0108] An InGaAsP transition layer 22 is grown on the N++-doped InP contact layer 21. The InGaAsP transition layer 22 is a multi-layer intrinsic InGaAsP layer with a gradient energy band, and each layer has a thickness of 0.02 μm to 0.04 μm.

[0109] An InGaAs absorption layer 23 is grown on the InGaAsP transition layer 22, with a thickness of 0.3 μm to 0.5 μm and a doping concentration of 5e14 cm 3 ~1e15 / cm 3 .

[0110] An intrinsic or lightly N-doped InP cap layer 24 is grown on the InGaAs absorption layer 23. The cap layer 24 has a thickness of 0.5 μm to 1 μm and a doping concentration of 1e15 / cm 3 -5e16 / cm 3 .

[0111] like Figure 3b As shown, a circular shallow diffusion of doping material Zn is performed on the periphery of the epitaxial structure of the detector, and a central shallow diffusion of doping material Zn is performed in the middle of the epitaxial structure of the detector. Specifically, the above epitaxial structure is placed in a high-temperature diffusion furnace, and the diffusion temperature is set to 560°C and the diffusion time is 15 minutes. Under this condition, Zn diffusion is performed to form a circular diffusion area 241 with a depth of 0.2μm to 0.5μm and a width of 2μm to 5um; and a first diffusion area 242 with a width of 10μm to 16μm is formed.

[0112] like Figure 3c As shown, the position of the second diffusion region 243 is defined above the first diffusion region 242 by a photolithography patterning process, and then Zn diffusion is performed by secondary diffusion to form the second diffusion region 243 in the cap layer 24 below the first diffusion region 242. The second diffusion region 243 is located within the coverage of the first diffusion region 242. The sum of the depths of the first diffusion region 242 and the second diffusion region 243 does not exceed 0.5 μm.

[0113] like Figure 3d As shown, the mesa structure 20a and the ring structure 20b are respectively prepared by photolithography patterning process and wet etching process, and a trench c for isolation is formed between the annular diffusion region 241 of the ring structure 20b and the first diffusion region 242 of the mesa structure 20a.

[0114] like Figure 3e As shown, the sidewall multilayer passivation layer 30 is grown by the ALD process, and the material of the passivation layer 30 is Al 2 O 3 , and fill the groove c with polyimide material d.

[0115] like Figure 3f As shown, the first electrode 40 , the second electrode 50 and the third electrode 60 are prepared by photolithography patterning process, electron beam coating process and lift-off process.

[0116] like Figure 1 As shown, after thinning and polishing, the second surface 10b of the substrate 10 is plated and patterned to form a light coupling area (photosensitive surface). The photosensitive area is arranged corresponding to the mesa structure 20a, and a near-infrared light anti-reflection film 11 is arranged on the photosensitive area, and an anti-reflection film 12 is arranged on the non-photosensitive area.

[0117] Embodiment 1:

[0118] The detector chip structure includes a substrate, an epitaxial structure, a passivation layer, a first electrode, a second electrode and a third electrode.

[0119] The substrate is an intrinsic InP substrate.

[0120] The epitaxial structure is formed on the first surface of the substrate and comprises an InP contact layer, an InGaAsP transition layer, an InGaAs absorption layer, and an InP cap layer which are sequentially arranged in a direction away from the substrate.

[0121] The thickness of the InP contact layer is 1 μm. The contact layer is an N++ type doped layer with a doping concentration of 5e18 cm3.

[0122] The InGaAsP transition layer includes three intrinsic InGaAsP layers with gradient energy bands, and the thickness of each InGaAsP layer is 0.02 μm.

[0123] The thickness of the InGaAs absorption layer is 0.5 μm. The absorption layer is a doped layer with a doping concentration of 5e14 cm3.

[0124] The thickness of the InP cap layer is 0.5 μm and the cap layer is a non-doped layer.

[0125] The depth of the annular diffusion region is 0.5 μm, and the width of the annular diffusion region is 5 μm.

[0126] The size of the first diffusion region is 10 μm to 16 μm.

[0127] The second diffusion region extends below the first diffusion region and is located within the coverage of the first diffusion region. The sum of the depths of the first diffusion region and the second diffusion region is 0.5 μm.

[0128] No groove is provided between the table structure and the ring structure.

[0129] Embodiment 2:

[0130] The detector chip structure includes a substrate, an epitaxial structure, a passivation layer, a first electrode, a second electrode and a third electrode.

[0131] The substrate is an intrinsic InP substrate.

[0132] The epitaxial structure is formed on the first surface of the substrate and comprises an InP contact layer, an InGaAsP transition layer, an InGaAs absorption layer, and an InP cap layer which are sequentially arranged in a direction away from the substrate.

[0133] The thickness of the InP contact layer is 1 μm. The contact layer is an N++ type doped layer with a doping concentration of 5e18 cm 3 .

[0134] The InGaAsP transition layer includes three intrinsic InGaAsP layers with gradient energy bands, and the gradient value is the same as that in Embodiment 1. The thickness of each InGaAsP layer is 0.02 μm.

[0135] The thickness of the InGaAs absorption layer is 0.5 μm. The absorption layer is a doped layer with a doping concentration of 5e14 cm 3 .

[0136] The thickness of the InP cap layer is 0.5 μm and the cap layer is a non-doped layer.

[0137] The depth of the annular diffusion region is 0.5 μm, and the width of the annular diffusion region is 5 μm.

[0138] The size of the first diffusion region is 10 μm to 16 μm.

[0139] The second diffusion region extends below the first diffusion region and is located within the coverage of the first diffusion region. The sum of the depths of the first diffusion region and the second diffusion region is 0.5 μm.

[0140] A groove exposing the contact layer is formed between the mesa structure and the ring structure, and the groove is filled with polyimide material.

[0141] The overall device size of Example 2 is consistent with that of Example 1.

[0142] Comparative Example 1:

[0143] The detector chip structure includes a substrate, an epitaxial structure, a passivation layer, a first electrode, a second electrode and a third electrode.

[0144] The substrate is an intrinsic InP substrate.

[0145] The epitaxial structure is formed on the first surface of the substrate and comprises an InP contact layer, an InGaAsP transition layer, an InGaAs absorption layer, and an InP cap layer which are sequentially arranged in a direction away from the substrate.

[0146] The thickness of the InP contact layer is 1 μm. The contact layer is an N++ type doped layer with a doping concentration of 5e18 cm 3 .

[0147] The InGaAsP transition layer includes three intrinsic InGaAsP layers with gradient energy bands, and the gradient values ​​are the same as those in Embodiment 1 and Embodiment 2. The thickness of each InGaAsP layer is 0.02 μm.

[0148] The thickness of the InGaAs absorption layer is 0.5 μm. The absorption layer is a doped layer with a doping concentration of 5e14 cm 3 .

[0149] The thickness of the InP cap layer is 0.5 μm and the cap layer is a non-doped layer.

[0150] No annular diffusion region is formed in the annular structure.

[0151] The size of the first diffusion region is 10 μm to 16 μm.

[0152] The second diffusion region extends below the first diffusion region and is located within the coverage of the first diffusion region. The sum of the depths of the first diffusion region and the second diffusion region is 0.5 μm.

[0153] No groove is arranged between the table structure and the ring structure.

[0154] The overall device size of Comparative Example 1 is consistent with that of Examples 1 and 2.

[0155] Figure 4 This is a test diagram of electrostatic breakdown voltage after the ESD HBM test of the device in Example 2; Figure 5 This is the electrostatic breakdown voltage test diagram of the device in Comparative Example 1 after the ESD HBM test. Figure 4 and Figure 5 As shown, the electrostatic breakdown voltage of the device in Example 2 is 150V, and the electrostatic breakdown voltage of the device in Comparative Example 1 is 80V. The electrostatic breakdown voltage of the device in Example 1 is also 150V.

[0156] Figure 6 This is a diagram showing the electrostatic breakdown position observed by Thermal after the ESD test of the device in Example 2; Figure 7 This is the location diagram of the electrostatic breakdown observed by Thermal after the ESD test of the device in Comparative Example 1. Figure 6 and Figure 7 As shown, the electrostatic breakdown position of the device in Example 2 is located in the annular diffusion region; the electrostatic breakdown position of the device in Comparative Example 1 is located inside the active region. The electrostatic breakdown position of the device in Example 1 is located in the annular diffusion region.

[0157] Figure 8 This is a device bandwidth test diagram in Example 2; Fig. 9 This is the device bandwidth test diagram in comparative example 1. Figure 8 and Fig. 9 As shown, the bandwidth of the device in Example 2 is 35 GHz, and the bandwidth of the device in Comparative Example 1 is 31.7 GHz. The bandwidth of the device in Example 1 is 31.7 GHz.

[0158] By comparing the above embodiments and comparative examples, it can be concluded that the detector chip structure of the present invention can effectively improve the electrostatic breakdown resistance of high-speed detectors. This is crucial for fields such as optical communications and radar detection, because in these fields, detectors need to work in an environment with strong electromagnetic interference, and the electrostatic breakdown problem has always been an important factor affecting the reliability of equipment. The detector chip structure of the present invention can improve the bandwidth of the detector while improving the electrostatic breakdown resistance of the detector, and will not affect the actual active area size of the device, and therefore will not affect the performance of the device. For the field of electronic equipment manufacturing, this means that electronic products with better performance and higher reliability can be produced.

[0159] Compared with the prior art, the detector chip structure and preparation method thereof of the present invention form discrete capacitors and electrostatic charging and discharging channels by setting an annular diffusion zone on the periphery of the detector, thereby improving the detector's ability to withstand electrostatic breakdown to a certain extent.

[0160] The detector chip structure and preparation method of the present invention, since the annular diffusion region is isolated from the device active region (absorption layer and cap layer in the mesa structure) by a groove formed by an etching process, the setting of the annular diffusion region will not affect the size of the actual active region of the device, and thus will not affect the bandwidth of the device.

[0161] The detector chip structure and preparation method thereof of the present invention, due to the discrete capacitor formed by setting the annular diffusion zone, can be connected to the ground through the first electrode of the detector, which can reduce the capacitance value at the device electrode, thereby reducing the overall C value of the device, and to a certain extent, can improve the bandwidth of the device.

[0162] The detector chip structure and preparation method thereof of the present invention optimize the size of the device active area (absorption layer and cap layer in the table structure), reduce the thickness of the absorption layer in the table structure, and reduce the ohmic contact resistance of the device by selecting a suitable metal film system and annealing process, thereby effectively improving the bandwidth of the detector. At the same time, it can also ensure the electrostatic breakdown voltage of the device and avoid electrostatic breakdown failure during the module assembly process.

[0163] The detector chip structure and the preparation method thereof of the present invention adopt a two-step diffusion technology to ensure the uniformity and accuracy of the diffusion of the active area and the annular diffusion area, thereby ensuring the stable performance of the detector.

[0164] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0165] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A detector chip structure, characterized in that: include: a substrate having opposing first and second surfaces; An epitaxial structure is formed on the first surface of the substrate, the epitaxial structure comprises a contact layer, a transition layer, an absorption layer, and a cap layer arranged in sequence in a direction away from the substrate; the epitaxial structure comprises a mesa structure located in the middle and a torus structure arranged around the mesa structure, and an annular diffusion region is formed in the cap layer located in the torus structure; A passivation layer is formed on the surface of the epitaxial structure, a first window is formed on the passivation layer on the surface of the mesa structure to expose the cap layer, a second window is formed on the surface of the contact layer to expose the contact layer, and a third window is formed on the surface of the annular structure to expose the annular diffusion region; A first electrode formed in the first window and electrically connected to the cap layer; a second electrode formed in the second window and electrically connected to the contact layer; A third electrode formed in the third window and electrically connected to the annular diffusion region; A first diffusion region is formed in the cap layer located in the mesa structure, the first window exposes the first diffusion region, and the first electrode is formed on the surface of the first diffusion region; A second diffusion region is formed in the cap layer of the mesa structure, the second diffusion region extends below the first diffusion region and is located within the coverage of the first diffusion region; A groove exposing the contact layer is formed between the mesa structure and the ring structure.

2. The detector chip structure according to claim 1, characterized in that: The size of the first diffusion region is 10 μm to 16 μm; and / or, The sum of the depths of the first diffusion region and the second diffusion region does not exceed 0.5 μm.

3. The detector chip structure according to claim 1, characterized in that: The groove is filled with polyimide material.

4. The detector chip structure according to claim 1, characterized in that: The second surface of the substrate is divided into a photosensitive area and a non-photosensitive area, the photosensitive area is arranged corresponding to the mesa structure, an anti-reflection film is arranged on the substrate in the photosensitive area, and an anti-reflection film is arranged on the substrate in the non-photosensitive area; and / or, The material of the substrate includes InP; and / or, The material of the contact layer includes InP, the thickness of the contact layer is 0.5 μm to 2 μm, and the contact layer is a doped layer with a doping concentration of 5e18 cm 3 ~1e19 / cm 3 and / or, The transition layer comprises multiple InGaAsP layers with gradient energy band, and the thickness of each InGaAsP layer is 0.02 μm to 0.04 μm; and / or, The material of the absorption layer includes InGaAs, the thickness of the absorption layer is 0.3 μm to 0.5 μm, and the absorption layer is a doped layer with a doping concentration of 5e14 cm 3 ~1e15 / cm 3 and / or, The material of the cap layer includes InP, the thickness of the cap layer is 0.5 μm to 1 μm, the cap layer is a non-doped layer or a lightly doped layer, and when the cap layer is a lightly doped layer, the doping concentration is 1e15 / cm 3 -5e16 / cm 3 and / or, The depth of the annular diffusion zone does not exceed the thickness of the cap layer; and / or, The depth of the annular diffusion zone is 0.2 μm to 0.5 μm, and the width of the annular diffusion zone is 2 μm to 5 μm.

5. A method for preparing a detector chip, characterized in that: include: Providing a substrate having a first surface and a second surface disposed opposite to each other; Growing an epitaxial structure on the first surface of the substrate, the epitaxial structure comprising a contact layer, a transition layer, an absorption layer, and a cap layer grown in sequence; Performing annular diffusion on the periphery of the cap layer of the epitaxial structure to form an annular diffusion zone; Diffusion is performed in the middle of the cap layer of the epitaxial structure to form a first diffusion region; Etching the epitaxial structure until the contact layer is exposed to form a mesa structure in the middle and a torus structure in the periphery, wherein the first diffusion region is located in the mesa structure and the annular diffusion region is located in the torus structure; forming a passivation layer on the surface of the epitaxial structure; Etching the passivation layer to expose a portion of the contact layer, a portion of the first diffusion region located on the surface of the mesa structure, and a portion of the annular diffusion region located on the surface of the annular structure; A first electrode electrically connected to the first diffusion region, a second electrode electrically connected to the contact layer, and a third electrode electrically connected to the annular diffusion region are formed.

6. The method for preparing the detector chip according to claim 5, characterized in that: After the step of diffusing in the middle of the cap layer of the epitaxial structure to form a first diffusion region, the method further includes: Performing secondary diffusion in the middle of the cap layer of the epitaxial structure to form a second diffusion region, wherein the second diffusion region extends below the first diffusion region and is located within the coverage of the first diffusion region; and / or, In the step of etching the epitaxial structure until the contact layer is exposed to form a mesa structure in the middle and a ring structure in the periphery, a groove between the mesa structure and the ring structure is formed by etching; After the step of forming a passivation layer on the surface of the epitaxial structure, the method further includes: filling the groove with a polyimide material.

7. The method for preparing a detector chip according to claim 5, characterized in that: Also includes: thinning the substrate; An anti-reflection film is formed on the area of ​​the second surface of the substrate corresponding to the mesa structure, and an anti-reflection film is formed on other areas of the second surface of the substrate.

8. The method for preparing a detector chip according to claim 5, characterized in that: By means of a diffusion process, a first diffusion region having a size of 10 μm to 16 μm is formed in the middle of the cap layer of the epitaxial structure; and / or, The thickness of the absorption layer is controlled to be 0.3 μm to 0.5 μm.

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