Semiconductor device, semiconductor memory, and method for forming semiconductor device

Abstract

The embodiment of the present disclosure provides a semiconductor device, comprising: a plurality of active regions arranged repeatedly along a first direction and a second direction, wherein, in a third direction, each active region comprises a first connection end and a second connection end located on the first connection end; in the first direction, a first insulating medium layer is arranged between each second connection end of each active region, and in the second direction, a second insulating medium layer is arranged between each second connection end of each active region; in the first direction and the second direction, a third insulating medium layer is arranged between each first connection end of each active region. The semiconductor device provided by the embodiment of the present disclosure has higher reliability.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular, to a semiconductor device, a semiconductor memory, and a semiconductor device forming method. BACKGROUND

[0002] With the increase of the integration of semiconductor devices, various elements in the semiconductor devices are arranged more closely, and the effective isolation between the various elements becomes more and more important.

[0003] Various isolation film deposition techniques, such as using atomic layer deposition (ALD) technology to deposit an isolation film on a three-dimensional structure, are widely used. The unique self-limiting growth mechanism of ALD enables the isolation film to have perfect consistency and thickness uniformity even on a complex three-dimensional structure; however, for some gap filling with a large aspect ratio, the growth rate of the film at the entrance of the gap will be greater than that of the film inside the gap, resulting in that the gap cannot be well covered by the film, and a seam is generated therein. The existence of the seam leaves hidden dangers for subsequent manufacturing processes and affects the final reliability of the device. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor device with higher reliability.

[0005] The problems to be solved by the technical spirits of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] According to an example embodiment of the present disclosure, a semiconductor device includes: a plurality of active regions arranged repeatedly along a first direction and a second direction, each active region including a first connection end and a second connection end on the first connection end in a third direction; a first insulating medium layer is arranged between each second connection end of each active region in the first direction, and a second insulating medium layer is arranged between each second connection end of each active region in the second direction; and a third insulating medium layer is arranged between each first connection end of each active region in the first direction and the second direction.

[0007] According to an example embodiment of the present disclosure, the first insulating medium layer between each second connection end in the first direction has a first maximum width, and the second insulating medium layer between each second connection end in the second direction has a second maximum width, the first maximum width being not greater than the second maximum width.

[0008] According to an example embodiment of the present disclosure, the second insulating medium layer includes a laminated structure composed of two or more insulating medium layers.

[0009] According to an example embodiment of the present disclosure, the first insulating medium layer and the second insulating medium layer comprise at least one same element; the first insulating medium layer has a smaller dielectric constant than the second insulating medium layer.

[0010] According to an example embodiment of the present disclosure, each active region further comprises a channel region between the first connection end and the second connection end, and a surface of the channel region is provided with a gate medium layer and a gate electrode; in the first direction, the gates are separated by the first insulating medium layer.

[0011] According to an example embodiment of the present disclosure, in the first direction, the first insulating medium layer is further provided between each first connection end.

[0012] According to an example embodiment of the present disclosure, in the first direction, the second connection end comprises a first part and a second part, and the first part and the second part are separated by an oxide medium layer.

[0013] According to an example embodiment of the present disclosure, the first part and the second part have different lattice structures.

[0014] According to an example embodiment of the present disclosure, the semiconductor device further comprises a bit line structure connected to the first connection end and a charge storage structure connected to the second connection end.

[0015] According to an example embodiment of the present disclosure, a semiconductor memory comprises a first semiconductor device and a second semiconductor device electrically connected, wherein the first semiconductor device comprises: a plurality of active regions arranged repeatedly in a first direction and a second direction, each active region comprising a first connection end and a second connection end on the first connection end in a third direction; in the first direction, each second connection end of each active region is separated by a first insulating medium layer, and in the second direction, each second connection end of each active region is separated by a second insulating medium layer; in the first direction and the second direction, each first connection end of each active region is separated by a third insulating medium layer.

[0016] According to an example embodiment of the present disclosure, the first semiconductor device is a memory device, and the second semiconductor device is a logic device or a memory device.

[0017] According to an example embodiment of the present disclosure, the second semiconductor device is the same as the first semiconductor device.

[0018] According to an example embodiment of the present disclosure, the second semiconductor device is electrically connected to the first semiconductor device through surfaces bonded to each other.

[0019] According to an example embodiment of the present disclosure, a method of forming a semiconductor device includes: providing a substrate, forming a plurality of active regions arranged repeatedly along a first direction and a second direction on the substrate, each active region including a first connection end and a second connection end body portion on the first connection end in a third direction; forming a first insulating medium layer between each active region in the first direction and a third insulating medium layer on a surface of the first insulating medium layer for isolating each active region; forming the third insulating medium layer between each active region in the second direction for isolating each active region; removing the third insulating medium layer outside a periphery of the second connection end body portion of each active region, forming a first gap between each second connection end body portion in the first direction, and forming a second gap between each second connection end body portion in the second direction; forming an extension portion of the second connection end body portion between each second connection end body portion to form a second connection end, the extension portion filling the first gap, the extension portion being formed in the second gap at the same time, filling part of the second gap, and a portion of the second gap not filled by the extension portion forming a third gap; and forming a second insulating medium layer in the third gap.

[0020] According to an example embodiment of the present disclosure, the step of forming an extension portion of the second connection end body portion between each second connection end body portion to form a second connection end includes: epitaxially growing the second connection end body portion to form the extension portion, the extension portion and the second connection end body portion forming the second connection end.

[0021] According to an example embodiment of the present disclosure, the step of forming an extension portion of the second connection end body portion between each second connection end body portion to form a second connection end includes: depositing the extension portion on a surface of the second connection end body portion, the extension portion and the second connection end body portion forming the second connection end.

[0022] According to an example embodiment of the present disclosure, the active region further includes a channel region between the first connection end and the second connection end, and the method further includes: removing the third insulating medium layer outside a periphery of the channel region along the third gap, forming a fourth gap outside the periphery of the channel region, and forming a gate medium layer and a gate in the fourth gap.

[0023] According to an example embodiment of the present disclosure, the step of forming a gate medium layer and a gate in the fourth gap includes: performing a surface oxidation treatment on the channel region such that an exposed surface of the channel region is oxidized to form the gate medium layer, and forming the gate on a surface of the gate medium layer.

[0024] According to an example embodiment of the present disclosure, the gate medium layer is further formed on a sidewall of the third gap.

[0025] According to an example embodiment of the present disclosure, the step of forming the second insulating medium layer in the third gap comprises: depositing a first insulating material on the sidewall of the third gap before forming the fourth gap; and depositing a second insulating material in the part of the third gap that is not filled with the first insulating material after forming the gate, the first insulating material and the second insulating material forming the second insulating medium layer.

[0026] The semiconductor device provided by the embodiments of the present disclosure has a device different from the active region isolation structure of a conventional semiconductor device, and in particular, the active region has an insulating isolation at one connection end. When the connection end of the active region is interconnected with other electrical structures, the short circuit problem between adjacent devices can be effectively avoided. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the embodiments of the present disclosure.

[0028] Figures 1A-1G is a schematic diagram of a semiconductor device provided by some embodiments of the present disclosure;

[0029] Figures 2A-2B is a schematic diagram of a semiconductor device provided by some embodiments of the present disclosure;

[0030] Figures 3A-3J is a cross-sectional view of a specific position in a step of manufacturing a semiconductor device provided by some embodiments of the present disclosure, used to describe a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0031] Figures 4A-4C is a schematic diagram of a memory provided by some embodiments of the present disclosure.

[0032] Through the above-described drawings, specific embodiments of the embodiments of the present disclosure have been shown, and will be described in more detail hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of the embodiments of the present disclosure in any way, but to illustrate the concept of the embodiments of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related disclosure, and not to limit the disclosure. In addition, it should be noted that only the relevant parts are shown in the drawings for convenience of description. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first", "second", "third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described.

[0034] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0035] In some embodiments of the present disclosure, referring to Figures 1A-1G , a semiconductor device 1 is provided.

[0036] Figure 1A and Figure 1B is a top plan view of the semiconductor device 1, which includes a plurality of active areas 11. Here, the active area refers to a region formed on a semiconductor substrate by doping or other means, in which the concentration of carriers (electrons or holes) is higher, and the flow of current can be controlled. The plurality of active areas 11 are repeatedly arranged in a first direction and a second direction, which are two directions perpendicular to each other in the top plan view of the semiconductor device 1. Figure 1A It is shown that the active area 11 has a substantially circular shape in the top plan view, Figure 1B It is shown that the active area 11 has a substantially elliptical shape in the top plan view. In some embodiments, the active area 11 can be island-shaped or any other suitable shape for a semiconductor active area in the top plan view.

[0037] In some embodiments, the active regions 11 may be uniformly distributed in the first direction and the second direction, that is, the spacing D2 between the active regions 11 in the first direction may be equal to the spacing D1 between the active regions 11 in the second direction; in some embodiments, the spacing D2 between the active regions 11 in the first direction may be different from the spacing D1 between the active regions 11 in the second direction, for example, the spacing D2 between the active regions 11 in the first direction may be smaller than the spacing D1 between the active regions 11 in the second direction.

[0038] Continue to see Figure 1A and Figure 1B In the first direction, a first insulating dielectric layer 20 is disposed between each active region 11, and in the second direction, a second insulating dielectric layer 21 is disposed between each active region 11. The first insulating dielectric layer 20 and the second insulating dielectric layer 21 form an isolation portion that isolates each active region 11.

[0039] In some embodiments, the first insulating dielectric layer 20 may include one or more insulating materials such as silicon dioxide, silicon nitride, silicon carbonitride, silicon oxycarbide, LK dielectric material, etc.; the second insulating dielectric layer 21 may include one or more insulating materials such as silicon dioxide, silicon nitride, silicon carbonitride, silicon oxycarbide, LK dielectric material, etc.

[0040] In some embodiments, the first insulating dielectric layer 20 and the second insulating dielectric layer 21 may include at least one insulating material of the same element. For example, the first insulating dielectric layer 20 and the second insulating dielectric layer 21 both include silicon, such as silicon dioxide, silicon nitride, silicon carbonitride, or silicon oxycarbide.

[0041] In some embodiments, the dielectric constant of the first insulating dielectric layer 20 is less than the dielectric constant of the second insulating dielectric layer 21. For example, the first insulating dielectric layer 20 is a low-K dielectric with a dielectric constant K not greater than 2.8, and the dielectric constant K of the second insulating dielectric layer 21 is between 3.9 and 2.8.

[0042] In some embodiments, the first insulating dielectric layer 20 is a single layer of insulating material, and the second insulating dielectric layer 21 is a multilayer insulating material. For example, the first insulating dielectric layer 20 is silicon dioxide, silicon nitride, silicon carbonitride, or silicon oxycarbide, and the second insulating dielectric layer 21 is a stacked structure formed of at least two of the following materials: silicon dioxide, silicon nitride, silicon carbonitride, or silicon oxycarbide. In some embodiments, the second insulating dielectric layer can be a stacked structure formed of two of the same material.

[0043] Figure 1C and Figure 1D They are Figure 1A 、 Figure 1B The cross-sectional view taken along line A-A' and Figure 1A 、Figure 1B FIG. 2 is a cross-sectional view taken along line B-B’ of FIG. 1. Please refer to FIG. 1 first. Figure 1C In the third direction perpendicular to the substrate 10, the semiconductor device 1 comprises the substrate 10 and active regions 11 disposed in the substrate 10, the active regions 11 comprising first connection ends 111 and second connection ends 112 located on the first connection ends 111. In the first direction, the first insulating medium layer 20 is formed on the outer periphery of the second connection ends 112, i.e. between adjacent second connection ends 112; the third insulating medium layer 22 is formed on the outer periphery of the first connection ends 111 of the active regions 11, i.e. between adjacent first connection ends 111.

[0044] In some embodiments, the first connection ends 111 can be output ends of the active regions 11 for controlling current, such as drains, and the second connection ends 112 can be input ends of the active regions 11 for controlling current, such as sources. In some embodiments, the first connection ends 111 can be input ends of the active regions 11 for controlling current, and the second connection ends 112 can be output ends of the active regions 11 for controlling current. In other embodiments, the first connection ends 111 and the second connection ends 112 can also be configured as connection ends with other functions, and the present disclosure is not limited in this regard.

[0045] Please continue to refer to FIG. 2. Figure 1D In the third direction, the semiconductor device 1 further comprises the second insulating medium layer 21 disposed on the outer periphery of the second connection ends 112 and the third insulating medium layer 22 disposed on the outer periphery of the first connection ends 111. In the second direction, the third insulating medium layer 22 is disposed between adjacent first connection ends 111, and the second insulating medium layer 21 is disposed between adjacent second connection ends 112.

[0046] In some embodiments, the first insulating medium layer 20 between adjacent active regions 11 has substantially the same width in the first direction, wherein the width of the first insulating medium layer 20 with the maximum width value is defined as the first maximum width; the second insulating medium layer 21 between adjacent active regions 11 has substantially the same width in the second direction, wherein the width of the second insulating medium layer 21 with the maximum width value is defined as the second maximum width, and the first maximum width can be equal to the second maximum width, as shown in FIG. 2, i.e. the pitch D2 of each second connection end 112 in the first direction is equal to or substantially equal to the pitch D1 of each second connection end 112 in the second direction. Figure 1A In some embodiments, the first maximum width can be less than the second maximum width, as shown in FIG. 3. Figure 1BAs shown in FIG. 1, the distance D2 of each second connection end 112 in the first direction is smaller than the distance D1 of each second connection end 112 in the second direction. It is to be noted that due to process error, the case that the first maximum width and the second maximum width are the same means that the measured values of the first maximum width and the second maximum width differ by a range of 0.1 nm to 1 nm.

[0047] In some embodiments, the third insulating medium layer 22 between adjacent active regions 11 has a third maximum width in the second direction, which is greater than the second maximum width.

[0048] In some embodiments, the third insulating medium layer 22 is one of silicon dioxide, silicon nitride, silicon carbon nitride, or silicon carbon oxide.

[0049] In some embodiments, the first insulating medium layer 20 and the second insulating medium layer 21 comprise the same insulating material, and the third insulating medium layer 22 comprises an insulating material different from the first insulating medium layer 20 and different from the second insulating medium layer 21, for example, the first insulating medium layer 20 and the second insulating medium layer 21 can be silicon nitride, and the third insulating medium layer 22 can be silicon dioxide.

[0050] In some embodiments, please continue to refer to Figure 1E , the second insulating medium layer 21 comprises a stacked structure of an insulating medium layer 210 and an insulating medium layer 211. The insulating medium layer 210 and the insulating medium layer 211 can comprise the same material or different materials. For example, the insulating medium layer 210 and the insulating medium layer 211 can both be silicon dioxide, silicon nitride, silicon carbon nitride, or silicon carbon oxide, or the insulating medium layer 210 can be one of silicon dioxide, silicon nitride, silicon carbon nitride, or silicon carbon oxide, and the insulating medium layer 211 can be another one of silicon dioxide, silicon nitride, silicon carbon nitride, or silicon carbon oxide different from the insulating medium layer 210. In some embodiments, when the insulating medium layer 210 and the insulating medium layer 211 are the same material, the insulating medium layer 210 and the insulating medium layer 211 can have a boundary due to different formation processes, so that the insulating medium layer 210 and the insulating medium layer 211 can be distinguished, for example, the insulating medium layer 210 is formed by a chemical vapor deposition process, such as ALD, and the insulating medium layer 211 is formed by a physical vapor deposition process or another chemical vapor deposition process different from the deposition process of the insulating medium layer 210. In other embodiments, when the insulating medium layer 210 and the insulating medium layer 211 are the same material, the insulating medium layer 210 and the insulating medium layer 211 can also be distinguished due to different formation times, for example, the insulating medium layer 210 is formed first, and then the insulating medium layer 211 is formed.

[0051] In some embodiments, in the second direction, the width of the insulating medium layer 210 is greater than the width of the insulating medium layer 211.

[0052] In some embodiments, the second insulating medium layer 21 can also be a three-layer structure or a stack structure with more than three layers, and the specific implementation is not limited thereto.

[0053] Please continue to see Figures 1C-1E In some embodiments, the active region 11 further comprises a channel region 113 between the first connection end 111 and the second connection end 112, and the surface of the channel region 113 is sequentially provided with the gate medium layer 12 and the gate electrode 13. In the first direction, the adjacent gate electrodes 13 are provided with the first insulating medium layer 20; in the second direction, the adjacent gate electrodes 13 are connected together to surround the channel region 113 together with the gate medium layer 12.

[0054] In some embodiments, the channel region 113 is a conductive path between the first connection end 111 and the second connection end 112, and the gate medium layer 12 and the gate electrode 13 control whether the conductive path is open or disconnected, thereby realizing the control of the current between the first connection end 111 and the second connection end 112. In some embodiments, the channel region 113 can have the same doping type as the first connection end 111 and the second connection end 112, or a different doping type.

[0055] In some embodiments, in the first direction, the width of the first connection end 111 is greater than the width of the channel region 112, and the width of the channel region 112 is less than the width of the second connection end 112. In the second direction, the width of the first connection end 111 is also greater than the width of the channel region 112, and the width of the channel region 112 is also less than the width of the second connection end 112. In other embodiments, the width of the first connection end 111 in the first direction can be substantially the same as or different from the width of the second connection end 112, and in the second direction, the similar is not described here. It should be noted that since there are multiple active regions 11, the number of the first connection end 111, the second connection end 112 and the channel region 113 is also multiple. The value of the width referred to in the disclosure refers to the average value of the width of a certain number of the first connection end 111, the second connection end 112 and the channel region 113 in a selected area. The same referred to in the disclosure means that the difference of the width value belongs to the process error range, and the measured value must be the same; the different referred to in the disclosure means that the difference of the width value has exceeded the process error range.

[0056] In some embodiments, the gate medium layer 12 can be a silicon dioxide film, or other dielectric film.

[0057] In some embodiments, the gate 13 can be a single layer of conductive thin film, such as a thin film of polysilicon, metal nitride, metal, etc., or can be a multi-layer of conductive thin film, such as a stack structure composed of two or more of metal nitride, polysilicon, metal, etc.

[0058] In some embodiments, the gate dielectric layer 12 and the gate 13 surround the channel region 113, forming a gate portion of a transistor with a vertical channel.

[0059] Please continue to see Figures 1C-1E In some embodiments, in the first direction, the outer periphery of the first connection end 111 is provided with the first insulating dielectric layer 20, and the first insulating dielectric layer 20 is arranged on the outer surface of the third insulating dielectric layer 22, i.e. in the first direction, the adjacent first connection ends 111 are isolated by the first insulating dielectric layer 20 and the third insulating dielectric layer 22, while in the second direction, the adjacent first connection ends 111 are isolated by the third insulating dielectric layer 22.

[0060] Please continue to see Figures 1F-1G , Figure 1F and Figure 1G are respectively Figure 1A or Figure 1B cross-sectional views taken along the line A-A' in FIG. 11B and Figure 1A or Figure 1B cross-sectional views taken along the line B-B' in FIG. 11C. In some embodiments, the second connection end 112 includes a body portion 1120 and an extension portion 1121, in the first direction, the extension portion 1121 is closer to the first insulating dielectric layer 20 relative to the body portion 1120, and in the second direction, the extension portion 1121 is closer to the second insulating dielectric layer 21 relative to the body portion 1120.

[0061] In some embodiments, the body portion 1120 and the extension portion 1121 are composed of the same material, but have different lattice structures, for example, the body portion 1120 can be single crystal silicon, while the extension portion 1121 can be polycrystalline silicon. In other embodiments, the body portion 1120 and the extension portion 1121 are composed of the same material and have the same lattice structure, for example, the body portion 1120 can be single crystal silicon, and the extension portion 1121 can also be single crystal silicon, or vice versa, the body portion 1120 can be polycrystalline silicon, and the extension portion 1121 can also be polycrystalline silicon. In other embodiments, the body portion 1120 and the extension portion 1121 can also be other materials suitable for being used as the current input / output end of the active region of the semiconductor device. The disclosure is not limited in this regard.

[0062] In some embodiments, the body portion 1120 is formed prior to the extension portion 1121, and the body portion 1120 formed first reacts with substances in the environment to form an interface layer due to exposure to the environment, for example, when the body portion 1120 contains silicon, it is easy to react with oxygen in the environment to form an oxide medium layer on the surface of the body portion 1120, and then the extension portion 1121 is formed on the surface thereof. It should be noted that the oxide medium layer can be a film layer located between the body portion 1120 and the extension portion 1121, or an irregular region formed by the penetration of oxygen elements into the surface of the body portion 1120.

[0063] In the above disclosed embodiments, by forming the second connection end with the body portion and the extension portion, a second connection end with a larger surface area is obtained, which means better electrical connection effect and reliability, and at the same time, the surface area of the first connection end 111 is not affected, and the density of the active region is not reduced.

[0064] Please continue to see Figures 2A-2B , Figure 2A and Figure 2B are cross-sectional views of the semiconductor device 1 in the first direction and the second direction, respectively. In some embodiments, the semiconductor device 1 further includes a bit line structure 30 connected to the first connection end 111 and a charge storage structure 40 connected to the second connection end 112, thereby forming a plurality of memory cells, such as DRAM cells.

[0065] In some embodiments, in the first direction, the bit line structure 30 has a continuously extended structure, and in the second direction, an insulating medium layer is provided between adjacent bit line structures 30 to isolate each bit line structure, for example, the insulating medium layer between each bit line structure 30 can be the third insulating medium layer 22. In some embodiments, the bit line structure 30 is arranged perpendicularly to the gate 13, and the charge storage structure 40 is arranged one-to-one corresponding to the active region 11. In some embodiments, the bit line structure 30 and the gate 13 can also be arranged in a non-perpendicular manner, and the charge storage structure 40 can also be arranged corresponding to a plurality of active regions 11.

[0066] In some embodiments, the bit line structure 30 can further include a bit line contact structure directly connected to the first connection end 111 and a bit line layer connecting the bit line contact structure, and the charge storage structure 40 can be a capacitor, such as a double-sided capacitor or a columnar capacitor. The charge storage structure 40 can be connected to the second connection end 112 through a contact plug, or can be directly connected to the second connection end 112. In other embodiments, the bit line structure 30 and the charge storage structure 40 adopt designs suitable for memory known to those skilled in the art, which will not be described here.

[0067] The semiconductor device provided by the embodiments of the present disclosure has the first connection end 111 and the second connection end 112 of the active region 11, and the periphery of the first connection end 111 and the second connection end 112 is provided with an insulating medium layer composed of different process sequences or different materials. In the first direction, that is, the direction perpendicular to the distribution direction of the gate 13, each adjacent first connection end 111 is isolated from each other by the third insulating medium layer 22 and the first insulating medium layer 20, and the second connection end 112 is isolated from each other by the first insulating medium layer 20. In the second direction, that is, the direction parallel to the distribution direction of the gate 13, each adjacent first connection end 111 is isolated from each other by the third insulating medium layer 22, and each adjacent second connection end 112 is isolated from each other by the second insulating medium layer 21. Through such a setting, better overall isolation effect of the device can be obtained on the premise of improving the surface area of the second connection end 112, and the reliability is improved.

[0068] In order to make the content of the present disclosure clearer, the following further describes the process of forming the semiconductor device.

[0069] Please refer to Figures 3A-3F . Figure 3A The top-down plan view of the semiconductor device in the embodiments of the present disclosure provided in the order of formation is as follows, Figures 3B-3E The cross-sectional view of the semiconductor device in the embodiments of the present disclosure provided in the order of formation is as follows, Figure 3A along the A-A' line and along the B-B' line in the process of forming the semiconductor device.

[0070] In some embodiments, as shown in Figure 3A , a plurality of repeatedly arranged active regions 11 are provided first, and each active region 11 is spaced apart from each other. In the first direction, the third insulating medium layer 22 and the first insulating medium layer 20 are arranged between the active regions 11 spaced apart from each other. The first insulating medium layer 20 is located between the adjacent active regions 11, and the active region 11 is arranged in the third insulating medium layer 22. And the first insulating medium layer 20 extends in the second direction. In the second direction, the third insulating medium layer 22 is arranged between the adjacent active regions 11. In the first direction, the spacing between the adjacent active regions 11 is D2', and in the second direction, the spacing between the adjacent active regions 11 is D1'. In some embodiments, D1' and D2' can be substantially equal or different.

[0071] In some embodiments, as shown in Figure 3BAs shown, the active region 11 is formed in the semiconductor substrate 10, and in the third direction perpendicular to the substrate, the active region 11 includes a first connecting end 111 near the bottom of the substrate 10, a second connecting end body portion 112' near the top of the substrate 10, and a channel region 113 between the first connecting end 111 and the second connecting end body portion 112'. In some embodiments, due to the limitation of the etching process, the width of the first connecting end 111 near the bottom of the substrate 10 and the width of the second connecting end body portion 112' near the top of the substrate 10 are different, for example, the width of the second connecting end body portion 112' is smaller than the width of the first connecting end 111. In some embodiments, the width of the channel region 113 is also different from the width of the first connecting end 111 and the width of the second connecting end body portion 112', for example, smaller than the width of the first connecting end 111 and larger than the width of the second connecting end body portion 112'.

[0072] In some embodiments, the first connecting end 111 and the second connecting end body portion 112' are both silicon materials, for example, single crystal silicon, polycrystalline silicon, doped single crystal silicon, and other materials suitable for the active region of a semiconductor device known to those skilled in the art.

[0073] A mask is provided, and the third insulating medium layer 22 is patterned, for example, by etching, as shown in FIG. 4B. Figure 3B As shown, in the first direction, the third insulating medium layer 22 outside the second connecting end body portion 112' is removed to form a first gap 50, and in the second direction, the third insulating medium layer 22 outside the second connecting end body portion 112' is removed to form a second gap 51. In some embodiments, the first insulating medium layer 20 and the third insulating medium layer 22 have an etching selectivity greater than 1.

[0074] Referring next to FIG. 5A, Figure 3C An extension portion 114 of the second connecting end body portion 112' is formed in the first gap 50, and the first gap 50 can be filled with the extension portion 114; the extension portion 114 is also formed in the second gap 51, and the second gap 51 is not filled with the extension portion 114, and the portion not filled with the extension portion forms a third gap 52; the second connecting end body portion 112' and the extension portion 114 together form the first connecting end 112 of the active region.

[0075] The formation of the extension portion 114 can be obtained by epitaxial growth, that is, the second connecting end body portion 112' exposed in the first gap 50 and the second gap 51 is epitaxially grown to obtain a film layer having the same lattice structure as the second connecting end body portion 112', for example, a single crystal silicon layer.

[0076] The formation of the extension 114 can be performed by depositing a semiconductor thin film in the first gap 50 and the second gap 51, for example, a polysilicon thin film can be deposited. It is to be noted that when the extension 114 is formed by deposition, the bottom surface of the second gap 51 will also form the extension 114, so that the width of the finally formed second connection end 112 in the first direction and the second direction is the same or substantially the same, i.e., the width of the first insulating medium layer 20 between the second connection ends 112 in the first direction is equal to or substantially equal to the width of the second insulating medium layer 21 between the second connection ends in the second direction. The extension 114 on the bottom surface of the second gap 51 can be removed later, only leaving the extension 114 on the sidewall of the second gap 51, in which case the width of the finally formed second connection end 112 in the first direction will be greater than its width in the second direction, i.e., the width of the first insulating medium layer 20 between the second connection ends 112 in the first direction is less than the width of the second insulating medium layer 21 between the second connection ends in the second direction.

[0077] In the above disclosed embodiments, by forming the extension 114 around the body portion 112' of the second connection end, the surface area of the body portion of the second connection end of the active region 11 is expanded, i.e., the spacing D1' and / or D2' between adjacent active regions 11 is reduced, a second connection end 112 with a larger surface area is obtained, which means better electrical connection effect and reliability, at the same time, the surface area of the first connection end 111 will not be affected, and the density of the active regions will not be reduced.

[0078] Please continue to refer to Figure 3D After the third gap 52 is formed, etching continues downward along the third gap 52 to remove the third insulating medium layer 22 around the channel region 113, forming a fourth gap 53.

[0079] Please continue to refer to Figure 3E After the fourth gap 53 is formed, a gate medium layer 12 is formed on the surface of the exposed channel region 113, the formation of the gate medium layer 12 includes: first, the surface of the active region exposed in the fourth gap 53 is subjected to an oxidation treatment to form a first gate medium layer, then a second gate medium layer is deposited on the surface of the first gate medium layer by a thin film deposition process, and finally the gate medium layer 12 is formed. In some embodiments, the steps of forming the first gate medium layer and forming the second gate medium layer can also be performed simultaneously. In some embodiments, the first gate medium layer is formed by in-situ steam generation (ISSG) and the second gate medium layer is formed by ALD. In some embodiments, the gate medium layer 12 can be formed only by oxidizing the surface of the channel region 113 or only by a thin film deposition process. In some embodiments, the first gate medium layer and the second gate medium layer are both silicon dioxide thin films. Figure 3DThe diagram illustrates the simultaneous formation of the gate dielectric layer 12 by oxidation of the channel region 113 surface and thin film deposition. When the gate dielectric layer 12 or the second gate dielectric layer is formed using a thin film deposition process, a thin film is also formed on the surface and a portion of the sidewall of the second connection terminal 112. These portions of the thin film are subsequently removed by etching or other process steps, including a post-etching cleaning process, which will not be further described here.

[0080] The gate dielectric layer 12 is also formed on the portion of the surface of the third insulating dielectric layer 22 exposed in the fourth gap 53. Figure 3D After forming the gate dielectric layer 12, the gate 13 is formed. The gate 13 fills the portion of the fourth gap 53 that is not filled by the gate dielectric layer 12, thereby forming a gate structure. This gate structure is isolated from each other in the first direction and connected to each other in the second direction. The gate 13 is formed by a thin film deposition process, such as an ALD process or other suitable thin film deposition process. In some embodiments, the gate 13 is a single-layer thin film structure, such as a titanium nitride film or a tungsten film; in other embodiments, the gate 13 can be a stacked thin film structure, such as a composite film of titanium nitride and tungsten. In the process of forming the gate 13, a gate film is also formed on the surface and part of the side wall of the first connecting terminal 112. Therefore, in addition to the deposition process, the process of forming the gate 13 is also accompanied by etching, cleaning and other process steps. The specific details are not repeated here. After the gate 13 is formed, a fifth gap 54 is also formed between adjacent first connecting terminals 112 in the second direction.

[0081] Continue to see Figure 3F After the gate 13 is formed, a second insulating dielectric layer 21 is deposited in the fifth gap 54 in the second direction to achieve isolation between the second connection terminals 112 and isolation between the second connection terminals 112 and the gate 13. In some embodiments, the second insulating dielectric layer 21 can be a single-layer thin film structure formed by a one-step thin film deposition process, such as a silicon dioxide film, a silicon nitride film, a silicon carbonitride film, or a silicon oxycarbide film. In some embodiments, the second insulating dielectric layer 21 can be a multi-layer structure formed by a multi-step thin film deposition process, such as Figure 3EThe first insulating material 210 is formed on the sidewall of the second connection end 112 in the fifth gap 54 first, and the second insulating material 211 is formed in a subsequent deposition process. In some embodiments, the first insulating material 210 is formed on the sidewall surface of the second connection end 112 after the third gap 52 is formed and before the fourth gap 53 is formed, and the second insulating material 211 is formed by depositing insulating material in the fifth gap 54 after the fifth gap 54 is formed. In some embodiments, the first insulating material 210 and the second insulating material 211 can be the same material or different materials. In some embodiments, the first insulating material 210 is a different material from the third insulating medium layer 22 and has an etching selectivity greater than 1. In some embodiments, the second insulating material 211 can be the same material or a different material from the third insulating medium layer 22. In some embodiments, the first insulating material 210 and the second insulating material 211 can be silicon nitride, and the third insulating medium layer can be silicon dioxide.

[0082] Please continue to see Figures 3G-3J , provides another method of forming a semiconductor device. Figures 3G-3J The cross-sectional view of the semiconductor device in the embodiments of the present disclosure is provided in the order of formation.

[0083] Please see Figure 3G In some embodiments, when the third insulating medium layer 22 between the adjacent second connection end body portions 112' in the first direction is removed to form the first gap 50, the third insulating medium layer 22 in the second direction is not patterned, and the specific implementation can be achieved by providing a mask in the second direction, so that when the third insulating medium layer 22 in the first direction is etched, the third insulating medium layer 22 in the second direction is protected. The mask is removed after the first gap 50 is formed.

[0084] Please continue to see Figure 3H After the first gap 50 is formed, an extension portion 114 is formed in the first gap 50, and the extension portion 114 abuts against the second connection end body portion 112'. After the extension portion 114 is formed, the third insulating layer 22 in the second direction is patterned, and the second gap 51 is formed in the adjacent second connection end body portion 112'.

[0085] The formation of the extension portion 14 can be achieved by epitaxial growth, that is, epitaxial growth is performed on the second connection end body portion 112' exposed in the first gap 50 to obtain a film layer having the same lattice structure as the second connection end body portion 112', such as a single crystal silicon layer.

[0086] The formation of the extension 114 can be formed by depositing a semiconductor thin film in the first gap 50, for example, a polysilicon thin film can be deposited. Since the second connection end body portion 112' in the second direction is not exposed during the formation of the extension 114, the extension 114 is not formed on the periphery of the second connection end body portion 112' in the second direction, so that the finally formed second connection end 112 has different widths in the first direction and in the second direction, i.e., the width of the first insulating medium layer 20 between the second connection ends 112 in the first direction is smaller than the width of the second insulating medium layer 21 between the second connection ends in the second direction.

[0087] Continuing to refer to Figure 3I , the third insulating medium layer 22 is etched along the second gap 51 to remove the third insulating medium layer 22 on the periphery of the channel region 113, forming a fourth gap 53 in the first direction and a third gap 52 in the second direction.

[0088] Continuing to refer to Figure 3J , the surface of the exposed channel region 113 in the formed fourth gap 53 and the second gap 52 forms the gate medium layer 12 and the gate electrode 13, respectively. The specific formation of the gate medium layer 12 and the gate electrode 13 can refer to the description of Figure 3D , which will not be repeated here. In some embodiments, the second insulating medium layer 21 includes a first portion 212 and a second portion 213, the first portion 212 is formed in the same step as the gate medium layer 12, i.e., when the gate medium layer 12 is formed, the surface of the second connection end 112 exposed in the third gap 52 will also be oxidized and / or deposited with a gate medium layer thin film, and then the second portion 213 is filled in the remaining space of the third gap 52 to form the second insulating medium layer 21.

[0089] The semiconductor device preparation method provided by the above disclosed embodiments can obtain a semiconductor device with higher reliability, and the advantages include but are not limited to avoiding the use of dielectric thin film to fill the gap and generate a seam during the filling process of each thin film, such as the filling of a gap with a radial width of less than 5 nm. Finally, the second connection end 112 with increased surface area is obtained, and the electrical properties between adjacent second connection ends will not be degraded due to the increase in surface area.

[0090] In other embodiments, a bitline structure and a charge storage structure are further formed, wherein the bitline structure is connected to the first connection terminal 111, and the charge storage structure is formed on the second connection terminal 112. In some embodiments, the bitline structure can be formed in the substrate 10, that is, in the substrate below the first connection terminal 111. In some embodiments, the first connection terminal 111 can be exposed by thinning the substrate 10, and then the bitline structure connected to the first connection terminal 111 can be formed. Of course, other methods known to those skilled in the art can also be used, and this disclosure is not limited thereto.

[0091] The present disclosure also provides a variety of memories. Figures 4A-4C Explain separately.

[0092] like Figure 4A As shown, in some embodiments, the memory 2 may include a cell region and a peripheral region, with the peripheral region being disposed outside the cell region. The semiconductor devices in the aforementioned embodiments are formed within the cell region, while the peripheral region includes logic devices, which form a logic circuit that controls the current input and output of the semiconductor devices in the cell region, such as a logic circuit composed of CMOS transistors. In some embodiments, the cell region and the peripheral region are formed within the same wafer or die.

[0093] like Figure 4B As shown, in some embodiments, the memory 2 may include a stacked unit region and a peripheral region. The peripheral region may be arranged above or below the unit region. A bonding surface is provided between the peripheral region and the unit region, such as a bonding surface formed by hybrid bonding, melt bonding, micro-bump bonding, or the like, and electrical connection is achieved through an electrical connection structure formed in the bonding surface. The unit region includes the semiconductor devices described in the aforementioned embodiments, and the peripheral region includes logic devices. The logic devices constitute a logic circuit to control the current input and output of the semiconductor devices in the unit region, such as a logic circuit composed of CMOS transistors. In some embodiments, the unit region and the peripheral region are formed in the same wafer or the same die. In other embodiments, the unit region and the peripheral region are formed in different wafers or different dies.

[0094] like Figure 4CAs shown, in some embodiments, the memory 2 can include two stacked cell regions, each cell region including the semiconductor device in the foregoing embodiments, and each cell region is interconnected by a bonding surface, for example, a bonding surface formed by a connection mode such as hybrid bonding, fusion bonding or micro-bump bonding. In some embodiments, the number of stacked cell regions can be more than two. In some embodiments, a peripheral region is also included and arranged in a stacked manner with the cell regions, and the peripheral region is interconnected with the cell regions by a bonding surface, for example, a bonding surface formed by a connection mode such as hybrid bonding, fusion bonding or micro-bump bonding. The peripheral region includes a logic device, and the logic device constitutes a logic circuit to control the current input and output of the semiconductor device in the cell region, for example, a logic circuit composed of CMOS transistors. In some embodiments, the peripheral region can also be located between the cell regions. In some embodiments, each cell region and the peripheral region are formed in the same wafer or the same die, and in other embodiments, each cell region and the peripheral region are formed in different wafers or different dies, respectively.

[0095] Those skilled in the art can understand that the first direction, the second direction and the third direction used in each of the above embodiments are not limited to the directions identified in the drawings, and the specific directions are determined by the device structure itself, for example, the first direction can be a direction perpendicular to the gate word line in the device structure, and the second direction can be a direction perpendicular to the gate word line in the device structure.

[0096] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A semiconductor device, comprising: a plurality of active regions arranged repeatedly in a first direction and a second direction, each of the active regions comprising a first connection end and a second connection end on the first connection end in a third direction; a first insulating medium layer arranged between each of the second connection ends of each of the active regions in the first direction, and a second insulating medium layer arranged between each of the second connection ends of each of the active regions in the second direction; and a third insulating medium layer arranged between each of the first connection ends of each of the active regions in the first direction and in the second direction; the first insulating medium layer between each of the second connection ends in the first direction has a first maximum width, and the second insulating medium layer between each of the second connection ends in the second direction has a second maximum width, the first maximum width being not greater than the second maximum width.

2. The semiconductor device according to claim 1, characterized by the second insulating medium layer comprises a laminated structure of two or more insulating medium layers.

3. The semiconductor device of claim 1, wherein the first insulating medium layer and the second insulating medium layer contain at least one same element; and a dielectric constant of the first insulating medium layer is smaller than a dielectric constant of the second insulating medium layer.

4. The semiconductor device of claim 1, wherein each of the active regions further comprises a channel region between the first connection end and the second connection end, a surface of the channel region being provided with a gate medium layer and a gate in the first direction, each of the gates being provided with the first insulating medium layer. the first insulating medium layer is further arranged between each of the first connection ends in the first direction. the second connection end in the first direction comprises a first portion and a second portion, the first portion and the second portion being provided with an oxide medium layer therebetween.

5. The semiconductor device of claim 1, wherein the first portion and the second portion have different lattice structures.

8. The semiconductor device according to claim 1, further comprising a bit line structure connected to the first connection end and a charge storage structure connected to the second connection end.

6. The semiconductor device of claim 1, wherein 9. A semiconductor memory comprising a first semiconductor device and a second semiconductor device electrically connected to each other, wherein the first semiconductor device comprises: a plurality of active regions arranged repeatedly in a first direction and a second direction, each of the active regions comprising a first connection end and a second connection end on the first connection end in a third direction; 7. The semiconductor device of claim 6, wherein a first insulating medium layer arranged between each of the second connection ends of each of the active regions in the first direction, and a second insulating medium layer arranged between each of the second connection ends of each of the active regions in the second direction; and a third insulating medium layer arranged between each of the first connection ends of each of the active regions in the first direction and in the second direction; the first insulating medium layer between each of the second connection ends in the first direction has a first maximum width, and the second insulating medium layer between each of the second connection ends in the second direction has a second maximum width, the first maximum width being not greater than the second maximum width. ​ ​ ​ ​ ​ ​ 10. The memory of claim 9, wherein, The first semiconductor device is a memory device, and the The second semiconductor device is a logic device or a memory device.

11. The memory of claim 9, wherein, The second semiconductor device is the same as the first semiconductor device.

12. The memory of claim 9, wherein, The second semiconductor device is electrically connected to the first semiconductor device through surfaces bonded to each other.

13. A method of forming a semiconductor device, comprising: providing a substrate, forming a plurality of active regions on the substrate, the active regions being repeatedly arranged in a first direction and a second direction, in a third direction each of the active regions includes a first connection end and a second connection end body portion on the first connection end; in the first direction, a first insulating medium layer is formed between each of the active regions, and a third insulating medium layer is formed on a surface of the first insulating medium layer, for isolating each of the active regions; in the second direction, the third insulating medium layer is formed between each of the active regions, for isolating each of the active regions; the third insulating medium layer outside the second connection end body portion of each active region is removed, forming a first gap between each of the second connection end body portions in the first direction, and forming a second gap between each of the second connection end body portions in the second direction; forming an extension portion of the second connection end body portion between the second connection end body portions, forming a second connection end, the extension portion filling the first gap, the extension portion being formed in the second gap at the same time, filling part of the second gap, the part of the second gap not filled by the extension portion forming a third gap; a second insulating medium layer is formed in the third gap.

14. The method of claim 13, wherein, the step of forming an extension portion of the second connection end body portion between the second connection end body portions, forming a second connection end, includes: epitaxially growing the second connection end body portion to form the extension portion, the extension portion and the second connection end body portion forming the second connection end. the step of forming an extension portion of the second connection end body portion between the second connection end body portions, forming a second connection end, includes: depositing the extension portion on a surface of the second connection end body portion, the extension portion and the second connection end body portion forming the second connection end.

15. The method of claim 13, wherein, each of the active regions further includes a channel region between the first connection end and the second connection end, and the method further includes: removing the third insulating medium layer outside the channel region along the third gap, forming a fourth gap outside the channel region, and forming a gate medium layer and a gate in the fourth gap.

16. The method of claim 13, wherein, the step of forming a gate medium layer and a gate in the fourth gap includes: performing a surface oxidation process on the channel region, so that the exposed surface of the channel region is oxidized to form the gate medium layer, and the gate is formed on a surface of the gate medium layer. the gate medium layer is also formed on a side 17. The method of claim 16, wherein, wall of the third gap. the step of forming a second insulating medium layer in the third gap includes:

18. The method of claim 16, wherein, depositing a first insulating material on a side wall of the third gap before forming the fourth gap; ​ 19. The method of claim 16, wherein, ​ ​ After the gate is formed, a second insulating material is deposited in portions of the third gap not filled by the first insulating material, the first and second insulating materials forming the second insulating medium layer.

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