Display panel and display device

Abstract

The present application provides a display panel and a display device; the display panel includes a second active layer and a second light-shielding layer, the second light-shielding layer is arranged between a substrate and a second active layer, and the pattern of the second light-shielding layer is the same as the pattern of the second active layer, and the pattern of the second light-shielding layer is arranged corresponding to the pattern of the second active layer, so that the second light-shielding layer can be arranged corresponding to the active pattern of the transistor in the second active layer, and the second light-shielding layer can shield the active pattern of the transistor in the second active layer to prevent the active pattern of the transistor in the second active layer from being affected by light, thereby improving the photosensitivity and electrical properties of the transistor and improving the performance of the display panel; and the second light-shielding layer has the same pattern as the second active layer, so the second light-shielding layer can be formed by using a mask plate for forming the second active layer, thereby eliminating the need to increase the mask plate, reducing process complexity and cost.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display devices, existing display devices have higher and higher requirements for power consumption and screen-to-body ratio. In order to reduce power consumption and increase screen-to-body ratio, existing display devices will adopt low-temperature polysilicon oxide (LTPO) technology. LTPO technology refers to the use of low-temperature polysilicon thin-film transistors and oxide thin-film transistors at the same time, so that the driving circuit takes into account the advantages of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, thereby reducing power consumption and leakage current. However, existing display devices using LTPO technology have a large number of film layers, and the corresponding number of mask plates required is large, resulting in a more complex process and higher cost. In order to reduce the number of mask plates, existing display devices will remove some gate layers and insulating layers, but this will cause the bottom gate of the oxide thin-film transistor to be missing, and the photosensitivity and electrical properties of the thin-film transistor will deteriorate.

[0003] Therefore, existing display devices using LTPO technology have technical problems such as poor photosensitivity and electrical properties caused by the absence of the bottom gate of the oxide thin film transistor. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem of poor photosensitivity and electrical properties caused by the bottom gate loss of oxide thin film transistors in existing display devices using LTPO technology.

[0005] An embodiment of the present application provides a display panel, the display panel comprising:

[0006] substrate;

[0007] A driving circuit layer, arranged on one side of the substrate, the driving circuit layer comprising a first light shielding layer, a second light shielding layer, a first active layer and a second active layer, the first light shielding layer being arranged between the substrate and the first active layer, the first active layer being arranged between the first light shielding layer and the second active layer, and the second light shielding layer being arranged between the substrate and the second active layer;

[0008] The pattern of the second light shielding layer is the same as the pattern of the second active layer, and the pattern of the second light shielding layer is arranged correspondingly to the pattern of the second active layer.

[0009] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0010] Beneficial effects: The present application provides a display panel and a display device; the display panel includes a second active layer and a second light-shielding layer, the second light-shielding layer is arranged between the substrate and the second active layer, and the pattern of the second light-shielding layer is the same as the pattern of the second active layer, the pattern of the second light-shielding layer is arranged corresponding to the pattern of the second active layer, so that the second light-shielding layer can be arranged corresponding to the active pattern of the transistor in the second active layer, then the second light-shielding layer can shield the active pattern of the transistor in the second active layer, and prevent the active pattern of the transistor in the second active layer from being affected by light, thereby improving the photosensitivity and electrical properties of the transistor, and improving the performance of the display panel; and the second light-shielding layer has the same pattern as the second active layer, then the second light-shielding layer can be formed by using a mask plate for forming the second active layer, thereby eliminating the need to increase the mask plate, reducing process complexity and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0012] Figure 1 A schematic diagram of a first comparative display device provided in an embodiment of the present application.

[0013] Figure 2 A schematic diagram of a second comparative display device provided in an embodiment of the present application.

[0014] Figure 3 A schematic diagram of a third comparative display device provided in an embodiment of the present application.

[0015] Figure 4 A schematic diagram of a fourth comparative display device provided in an embodiment of the present application.

[0016] Figure 5 for Figure 4 Schematic diagram of the light-shielding film of the comparative display device.

[0017] Figure 6 A schematic diagram of a film layer of a display panel provided in an embodiment of the present application.

[0018] Figure 7 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application.

[0019] Figure 8 A stacking diagram of the film layers of the display panel provided in an embodiment of the present application.

[0020] Fig. 9 for Figure 8 Exploded view of the second light-shielding layer of the display panel.

[0021] Fig.10 for Figure 8Exploded view of the first light shielding layer of the display panel.

[0022] Fig.11 for Figure 8 Exploded view of the first active layer of the display panel in FIG.

[0023] Fig.12 for Figure 8 An exploded view of the first gate layer of the display panel in FIG.

[0024] Fig.13 for Figure 8 Exploded view of the second active layer of the display panel in FIG.

[0025] Fig.14 for Figure 8 An exploded view of the second gate layer of the display panel in FIG.

[0026] Fig.15 for Figure 8 An exploded view of the first source-drain layer of the display panel in FIG.

[0027] Fig.16 for Figure 8 An exploded view of the second source-drain layer of the display panel in FIG.

[0028] Fig.17 for Figure 8 Exploded view of the first via hole of the display panel.

[0029] Fig.18 for Figure 8 Exploded view of the second via hole of the display panel.

[0030] Fig.19 for Figure 8 An exploded view of the third via hole of the display panel in FIG.

[0031] Fig. 20 for Figure 8 An exploded view of the fourth via hole of the display panel in FIG. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0033] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0034] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0035] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0036] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0037] Figure 1 A schematic diagram of a first comparative display device provided in an embodiment of the present application. Figure 2 A schematic diagram of a second comparative display device provided in an embodiment of the present application. Figure 3 A schematic diagram of a third comparative display device provided in an embodiment of the present application. Figure 4 A schematic diagram of a fourth comparative display device provided in an embodiment of the present application. Figure 5 for Figure 4 Schematic diagram of the light-shielding film of the comparative display device.

[0038] like Figures 1 to 5 As shown, as an introduction to the embodiments of the present application, some comparative display devices are provided to illustrate the principle of the technical problem to be solved by the embodiments of the present application. Figure 1 As shown, a comparative display device using LTPO technology includes a substrate 101, a light shielding film 102, a barrier film 103, a buffer film 104, a low-temperature polysilicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source-drain film 116, a first planarizing film 117, a second source-drain film 118, a second planarizing film 119, a third source-drain film 121, a third planarizing film 122, an anode film 123, a pixel definition film 124, and a support film 125. Figure 1 It can be seen that the comparative display device includes three layers of source and drain films and three layers of gate films, so that the comparative display device needs to be formed using 16 mask plates, the process is relatively complex and the cost is relatively high.

[0039] In order to solve the problem of complex process of the comparative display device, another comparative display device removes one layer of the gate film and the insulating film, such as Figure 2As shown, it can be seen that the second gate film 109 and the second gate insulating film 108 are removed from the comparative display device, so that the number of mask plates can be reduced to 14, but there are still problems such as a large number of mask plates, a complex process, and a high cost.

[0040] In order to solve the problem of complex process of the comparative display device, another comparative display device further removes a layer of source and drain film and insulating film, such as Figure 3 As shown in FIG. 1 , by removing the third source-drain film 121 and the third planarization film 122, the number of mask plates can be reduced to 13; Figure 2 , Figure 3 It can be seen that there is no shielding under the oxide semiconductor film 112, resulting in the loss of the bottom gate of the oxide thin film transistor, and the photosensitivity and electrical properties of the thin film transistor are deteriorated. Therefore, the existing display devices using LTPO technology have the technical problem of poor photosensitivity and electrical properties caused by the loss of the bottom gate of the oxide thin film transistor.

[0041] Even in some comparative display devices, in order to solve the problem of bottom gate missing of oxide thin film transistors existing in the comparative display devices, a light shielding film is used to shield the oxide semiconductor film, such as Figure 4 , Figure 5 As shown, it can be seen that a shading film 102 is provided under the oxide semiconductor film 112, but this will cause the shading film to be only connected horizontally but not vertically, which will cause the impedance of the shading film to gradually increase from both sides to the middle, and thus cause differences in the electrical properties of the low-temperature polycrystalline silicon thin film transistor, resulting in poor display, which will introduce new problems.

[0042] In view of the above technical problems, the embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0043] Figure 6 A schematic diagram of a film layer of a display panel provided in an embodiment of the present application. Figure 7 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application. Figure 8 A stacking diagram of the film layers of the display panel provided in an embodiment of the present application. Fig. 9 for Figure 8 Exploded view of the second light-shielding layer of the display panel. Fig.10 for Figure 8 Exploded view of the first light shielding layer of the display panel. Fig.11 for Figure 8 Exploded view of the first active layer of the display panel in FIG. Fig.12 for Figure 8 An exploded view of the first gate layer of the display panel in FIG. Fig.13 for Figure 8 Exploded view of the second active layer of the display panel in FIG. Fig.14 for Figure 8 An exploded view of the second gate layer of the display panel in FIG. Fig.15 for Figure 8 An exploded view of the first source-drain layer of the display panel in FIG. Fig.16 for Figure 8 An exploded view of the second source-drain layer of the display panel in FIG. Fig.17 for Figure 8 Exploded view of the first via hole of the display panel. Fig.18 for Figure 8 Exploded view of the second via hole of the display panel. Fig.19 for Figure 8 An exploded view of the third via hole of the display panel in FIG. Fig. 20 for Figure 8 An exploded view of the fourth via hole of the display panel in FIG.

[0044] The present application embodiment provides a display panel, such as Figures 6 to 20 As shown, the display panel 2 includes a substrate 201 and a driving circuit layer 22; the driving circuit layer 22 is arranged on one side of the substrate 201, and the driving circuit layer 22 includes a first light shielding layer 204, a second light shielding layer 202, a first active layer 207 and a second active layer 212, the first light shielding layer 204 is arranged between the substrate 201 and the first active layer 207, the first active layer 207 is arranged between the first light shielding layer 204 and the second active layer 212, and the second light shielding layer 202 is arranged between the substrate 201 and the second active layer 212;

[0045] The pattern of the second light shielding layer 202 is the same as the pattern of the second active layer 212 , and the pattern of the second light shielding layer 202 is arranged correspondingly to the pattern of the second active layer 212 .

[0046] An embodiment of the present application provides a display panel, which includes a second active layer and a second light-shielding layer. The second light-shielding layer is arranged between the substrate and the second active layer, and the pattern of the second light-shielding layer is the same as the pattern of the second active layer. The pattern of the second light-shielding layer is arranged corresponding to the pattern of the second active layer, so that the second light-shielding layer can be arranged corresponding to the active pattern of the transistor in the second active layer. The second light-shielding layer can shield the active pattern of the transistor in the second active layer to prevent the active pattern of the transistor in the second active layer from being affected by light, thereby improving the photosensitivity and electrical properties of the transistor and improving the performance of the display panel; and the second light-shielding layer has the same pattern as the second active layer, so the second light-shielding layer can be formed by using a mask plate for forming the second active layer, thereby eliminating the need to increase the mask plate and reducing the process complexity and cost.

[0047] Specifically, the pattern of the second light-shielding layer and the pattern of the second active layer referred to in the embodiments of the present application are the same, which means that the pattern of the second light-shielding layer is basically the same as the pattern of the second active layer. The two may be exactly the same, but considering the process errors, there may be certain differences between the two. At this time, the pattern of the second light-shielding layer can still be considered to be the same as the pattern of the second active layer. For example, the pattern of the second light-shielding layer is basically the same as the pattern of the second active layer, but when etching the two film layers, due to certain process errors, there is a certain difference between the shape of a certain edge of the second light-shielding layer and the shape of the corresponding edge of the second active layer. At this time, the pattern of the second light-shielding layer is still considered to be the same as the pattern of the second active layer.

[0048] Specifically, the second light shielding layer and the second active layer can be formed by the same mask plate, so that when forming the display panel, the active pattern of the second active layer can be shielded by the second light shielding layer without increasing the number of mask plates required for forming the display panel. Compared with some display devices in which a new film layer is added to shield the active pattern in the second active layer (including the active pattern of the compensation transistor and the active pattern of the first initialization transistor), which will increase the number of mask plates, resulting in increased process complexity and increased costs, the second light shielding layer and the second active layer are formed by the same mask plate in the embodiment of the present application, which can shield the active pattern of the second active layer without adding a mask plate, thereby reducing process complexity and reducing costs.

[0049] Specifically, when the second light-shielding layer and the second active layer are formed by using the same mask plate, it can be understood that, in theory, the patterns of the two should be the same pattern, but in the actual production process, it can be understood that the deviation of the process may cause slight differences between the second light-shielding layer and the second active layer. In particular, when the material of the second light-shielding layer is different from the material of the second active layer, different etching methods may be used when etching the two. Even if the same etching method is used, the differences in material properties will lead to certain differences in the patterns of the two. At this time, the pattern of the second light-shielding layer can still be considered to be the same as the pattern of the second active layer.

[0050] Specifically, the corresponding arrangement of the pattern of the second shading layer and the pattern of the second active layer described in the embodiment of the present application means that the projection of the pattern of the second shading layer on the substrate coincides with the projection of the pattern of the second active layer on the substrate. Similarly, in the following embodiments, the corresponding arrangement of the shading pattern and the active pattern of the transistor means that the projection of the shading pattern on the substrate coincides with the projection of the active pattern of the transistor on the substrate. It can be understood that the active pattern of each transistor includes a doped portion and a channel portion, and the channel portion is easily affected by light, resulting in changes in performance. Therefore, the shading pattern and the active pattern of the transistor can be arranged in correspondence. Specifically, for example, the corresponding arrangement of the shading pattern and the active pattern of the compensation transistor means that the projection of the shading pattern on the substrate coincides with the projection of the active pattern of the compensation transistor on the substrate.

[0051] Specifically, compared with the solution of using a first light-shielding layer to form an active pattern that blocks the second active layer, the voltage drop of the first light-shielding layer will increase from the two sides to the middle area, resulting in poor display. In the embodiment of the present application, a second light-shielding layer is set so that the first light-shielding layer can adopt a mesh structure, thereby improving the uniformity of the signal on the first light-shielding layer and reducing the voltage drop. The second light-shielding layer can shield the active pattern of the second active layer, thereby preventing the transistor using the active pattern of the second active layer from being affected by light, improving the electrical properties and photosensitivity of the thin film transistor, and improving the performance of the display panel. The second light-shielding layer has the same pattern as the second active layer, and the same mask plate can be used to form the second light-shielding layer and the second active layer, without the need to add a mask plate to form the second light-shielding layer.

[0052] In some embodiments, Figure 6 , Figure 8 As shown, the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array, and each of the repeating units 30 includes two pixel driving circuits 31 that are symmetrically arranged.

[0053] Specifically, it can be understood that the display panel may include a plurality of repeating units arranged in an array, and the pixel driving circuit in each repeating unit may refer to the design in a repeating unit described in the embodiment of the present application.

[0054] Specifically, it is understood that in order to illustrate the specific design of a certain film layer or a certain structure, the embodiments of the present application will name each part separately, but it is understood that multiple parts of a certain film layer or a certain structure will be formed at the same time, and when they are connected together, they will transmit the same signal. Multiple parts belonging to the same structure can actually use the same name. For example, Fig.10As shown, the first light shielding layer 204 includes a light blocking pattern 204a and a connecting line 204b, but in fact the light blocking pattern 204a and the connecting line 204b are multiple parts of the same structure, and the two are connected to each other. Without considering the voltage drop, the multiple parts of this structure transmit the same signal, and they can be named the same, for example, each part can be named as a part of the light blocking pattern. Similarly, for other film layers and other structures, please refer to the above description, and will not be repeated in the following embodiments.

[0055] Specifically, Figure 8 As shown, in order to show the structure of the second light-shielding layer in the stacking diagram of each film layer of the display panel, the second light-shielding layer is set on the top side, but it can be understood that, in fact, the second light-shielding layer is located between the substrate and the second active layer. The specific setting of the film layer can refer to the description in the following embodiments.

[0056] In some embodiments, Figure 6 , Figure 7 As shown, the driving circuit layer 22 includes a pixel driving circuit 31, and the pixel driving circuit 31 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3 and a first initialization transistor T4, the switching transistor T2 and the driving transistor T1 are connected to a first node A; one electrode of the compensation transistor T3, one electrode of the first initialization transistor T4 and the driving transistor T1 are connected to a second node Q, and the other electrode of the compensation transistor T3 and the driving transistor T1 are connected to a third node B;

[0057] The second active layer 212 includes the active pattern T3A of the compensation transistor T3 and the active pattern T4A of the first initialization transistor T4, and the second light shielding layer 202 includes a light shielding pattern 202a, the light shielding pattern 202a is the same as the active pattern T3A of the compensation transistor T3 and the active pattern T4A of the first initialization transistor T4, and the light shielding pattern 202a is arranged correspondingly to the active pattern T3A of the compensation transistor T3 and the active pattern T4A of the first initialization transistor T4. By making the light shielding pattern the same as the active pattern of the compensation transistor and the active pattern of the first initialization transistor, and the light shielding pattern is arranged correspondingly to the active pattern of the compensation transistor and the active pattern of the first initialization transistor, the active pattern of the compensation transistor and the active pattern of the first initialization transistor can be shielded by the light shielding pattern, so that the electrical properties and photosensitivity of the compensation transistor and the first initialization transistor can be improved.

[0058] In some embodiments, Figure 7 , Figure 8 , Fig. 9As shown, the pixel driving circuit 31 also includes a storage capacitor Cst, the second active layer 212 also includes a plate of the storage capacitor Cst, and the second light shielding layer 202 also includes an auxiliary pattern 202b, the auxiliary pattern 202b is the same as the pattern of the plate of the storage capacitor Cst, and the auxiliary pattern is arranged corresponding to the plate of the storage capacitor. When two gate layers are used in the display panel, the second active layer is used to form a plate of the storage capacitor, and accordingly, the second light shielding layer can be formed into an auxiliary pattern, the auxiliary pattern is the same as the pattern of the plate of the storage capacitor, and the auxiliary pattern is arranged corresponding to the plate of the storage capacitor.

[0059] Specifically, the second active layer can form a second plate of the storage capacitor.

[0060] Specifically, it can be understood that the second active layer forms the second electrode of the storage capacitor. Therefore, it is necessary to make the second electrode of the storage capacitor have better electrical properties. The second electrode of the storage capacitor can be doped to keep the electrical properties of the second electrode of the storage capacitor consistent with or even higher than the electrical properties of the doped portion of the active pattern, so that the electrical properties of the storage capacitor are better.

[0061] In some embodiments, Figure 7 As shown, the gate of the switching transistor T2 is connected to the first scanning signal line Pscan, the first electrode of the switching transistor T2 is connected to the data line DATA, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 at the first node A; the gate of the compensation transistor T3 is connected to the second scanning signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the first initialization transistor T4 is connected to the third scanning signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node Q; the pixel driving circuit 31 also includes:

[0062] a first light emission control transistor T5, wherein a gate of the first light emission control transistor T5 is connected to the light emission control signal line EM, a first electrode of the first light emission control transistor T5 is connected to the high potential power line VDD, and a second electrode of the first light emission control transistor T5 is connected to the first electrode of the driving transistor T1 and a first node A;

[0063] A second light emission control transistor T6, wherein a gate of the second light emission control transistor T6 is connected to the light emission control signal line EM, and a first electrode of the second light emission control transistor T6 and a second electrode of the driving transistor T1 are connected to a third node B;

[0064] a second initialization transistor T7, wherein a gate of the second initialization transistor T7 is connected to a fourth scanning signal line Pscan2, a first electrode of the second initialization transistor T7 is connected to a second initialization signal line VI-ANO, and a second electrode of the second initialization transistor T7 and a second electrode of the second light emission control transistor T6 are connected to a fourth node C;

[0065] a third initialization transistor T8, wherein a gate of the third initialization transistor T8 is connected to the fourth scan signal line Pscan2, a first electrode of the third initialization transistor T8 is connected to the third initialization signal line VI3, and a second electrode of the third initialization transistor T8 is connected to the first electrode of the driving transistor T1 to a first node A;

[0066] A storage capacitor Cst, one plate of the storage capacitor Cst is connected to the high potential power line VDD, and the other plate of the storage capacitor Cst is connected to the gate of the driving transistor T1 at a second node Q;

[0067] A boost capacitor Cboost, one plate of the boost capacitor Cboost is connected to the first scan signal line Pscan, and the other plate of the boost capacitor Cboost is connected to the second electrode of the first initialization transistor T4.

[0068] Specifically, Figure 6 , Figure 7 As shown, the display panel 2 also includes a light-emitting layer 23, which includes a light-emitting device LED. The light-emitting device LED is connected to the pixel driving circuit, the positive electrode of the light-emitting device LED is connected to the second electrode of the second initialization transistor T7, and the negative electrode of the light-emitting device LED is connected to the low potential power line VSS.

[0069] In some embodiments, Figure 6As shown, the driving circuit layer 22 further includes a first gate layer 209, a second gate layer 214, a first source-drain electrode layer 216, and a second source-drain electrode layer 218. The first gate layer 209 is disposed between the first active layer 207 and the second active layer 212, the second gate layer 214 is disposed between the second active layer 212 and the first source-drain electrode layer 216, and the first source-drain electrode layer 216 is disposed between the second gate layer 214 and the second source-drain electrode layer 218. By making the driving circuit layer include the first gate layer, the second gate layer, the first source-drain electrode layer, and the second source-drain electrode layer, the process steps of the display panel can be reduced, and the mask plates required to form the display panel can be reduced.

[0070] In some embodiments, Figures 6 to 8 , Fig.11 As shown, the first active layer 207 includes an active pattern T1A of a driving transistor T1, an active pattern T2A of a switching transistor T2, an active pattern T5A of a first light-emitting control transistor T5, an active pattern T6A of a second light-emitting control transistor T6, an active pattern T7A of a second initialization transistor T7, and an active pattern T8A of a third initialization transistor T8, the active pattern T1A of the driving transistor T1 is arranged along a first direction X, and the active pattern T1A of the driving transistor T1 is connected to the active pattern T2A of the switching transistor T2, the active pattern T5A of the first light-emitting control transistor T5, and the active pattern T6A of the second light-emitting control transistor T6, the active pattern T2A of the switching transistor T2 is connected to the active pattern T5A of the first light-emitting control transistor T5, and the active pattern T6A of the second light-emitting control transistor T6. T5A is arranged along the second direction Y, the active pattern T6A of the second light-emitting control transistor T6 and the active pattern T7A of the second initialization transistor T7 are arranged along the second direction Y, and the active pattern T6A of the second light-emitting control transistor T6 is connected to the active pattern T7A of the second initialization transistor T7, the active pattern T8A of the third initialization transistor T8 is arranged at intervals with the active pattern T1A of the driving transistor T1, the active pattern T2A of the switching transistor T2, the active pattern T5A of the first light-emitting control transistor T5, the active pattern T6A of the second light-emitting control transistor T6 and the active pattern T7A of the second initialization transistor T7; the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0071] Specifically, it can be seen that within one repeating unit, the active patterns T7A of the second initialization transistors T7 of two adjacent pixel driving circuits are connected.

[0072] In some embodiments, Figures 6 to 8 , Fig.12As shown, the first gate layer 209 includes a first initialization signal line VI-G, a first scanning signal line Pscan, a light-emitting control signal line EM, a fourth scanning signal line Pscan2, a gate T1G of a driving transistor T1, a gate T2G of a switching transistor T2, a gate T5G of a first light-emitting control transistor T5, a gate T6G of a second light-emitting control transistor T6, a gate T7G of a second initialization transistor T7, a gate T8G of a third initialization transistor T8 and a first electrode Cst1 of a storage capacitor Cst, and the first initialization signal line VI-G, the first scanning signal line Pscan, the first electrode Cst1 of the storage capacitor Cst, the light-emitting control signal line EM and the fourth scanning signal line Pscan2 are sequentially spaced along the second direction Y.

[0073] Specifically, from Fig.12 It can be seen that the gate T2G of the switch transistor T2 is a part of the first scan signal line Pscan. It can be understood that since the gates T2G of all the switch transistors T2 in a row of pixel units are connected to the same first scan signal line Pscan, when the first scan signal line Pscan is formed, the portion of the first scan signal line corresponding to the channel of the switch transistor T2 of each pixel unit serves as the gate of the switch transistor T2 of each pixel unit. Therefore, two reference numerals are used to identify the same structure. Similarly, the gate T1G of the drive transistor T1 serves as both the gate and the first gate of the storage capacitor Cst. The electrode plate Cst1, the portion of the channel of the first light-emitting control transistor T5 corresponding to the light-emitting control signal line EM serves as the gate T5G of the first light-emitting control transistor T5, the portion of the channel of the second light-emitting control transistor T6 corresponding to the light-emitting control signal line EM serves as the gate T6G of the second light-emitting control transistor T6, the portion of the channel of the fourth scanning signal line Pscan2 corresponding to the second initialization transistor T7 serves as the gate T7G of the second initialization transistor T7, and the portion of the channel of the third initialization transistor T8 corresponding to the fourth scanning signal line Pscan2 serves as the gate T8G of the third initialization transistor T8.

[0074] In some embodiments, Figures 6 to 8 , Fig.13As shown, the second active layer 212 includes an active pattern T3A of the compensation transistor T3, an active pattern T4A of the first initialization transistor T4, and a second plate Cst2 of the storage capacitor Cst, the active pattern T3A of the compensation transistor T3 is connected to the active pattern T4A of the first initialization transistor T4, the second plate Cst2 of the storage capacitor Cst is arranged on one side of the active pattern T3A of the compensation transistor T3 along the first direction X, and a through hole 331 is provided on the second plate Cst of the storage capacitor Cst. By forming the second plate of the storage capacitor with the second active layer, a storage capacitor can be provided in the pixel driving circuit, and a through hole is provided on the second plate of the storage capacitor, so that the first electrode of the compensation transistor can be normally connected to the gate of the driving transistor.

[0075] Specifically, it can be understood that the second active layer forms the second electrode of the storage capacitor. Therefore, it is necessary to make the second electrode of the storage capacitor have better electrical properties. The second electrode of the storage capacitor can be doped to keep the electrical properties of the second electrode of the storage capacitor consistent with or even higher than the electrical properties of the doped portion of the active pattern, so that the electrical properties of the storage capacitor are better.

[0076] Specifically, by providing a through hole on the second electrode plate of the storage capacitor, the first electrode of the compensation transistor can pass through the second electrode plate of the storage capacitor and be connected to the gate of the driving transistor, so that the pixel driving circuit can work normally.

[0077] Specifically, Fig.12 , Fig.13 As shown, the first gate layer 209 also includes a first plate Cboost1 of a boost capacitor Cboost, the second active layer 212 also includes a second plate Cboost2 of the boost capacitor Cboost, the overlapping portion of the first scanning signal line Pscan and the active pattern T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and the overlapping portion of the active pattern T4A of the first initialization transistor T4 and the first scanning signal line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

[0078] In some embodiments, Figures 6 to 8 , Fig.14 As shown, the second gate layer 214 includes a second scan signal line Nscan1, a third scan signal line Nscan2, a third initialization signal line VI3, a gate T3G of a compensation transistor T3 and a gate T4G of a first initialization transistor T4, and the third scan signal line Nscan2, the second scan signal line Nscan1 and the third initialization signal line VI3 are arranged in sequence along the second direction Y.

[0079] Specifically, the projection of the shading pattern on the substrate can overlap with the projection of the third scanning signal line on the substrate, thereby reducing the coupling capacitance between the shading pattern and other signal lines. Even if the shading pattern is coupled with the third scanning signal line, since the shading pattern blocks the active pattern of the first initialization transistor, the potential of the third scanning signal line can be increased, and the gate control capability of the first initialization transistor can be improved.

[0080] Specifically, the projection of the shading pattern on the substrate can overlap with the projection of the second scanning signal line on the substrate, thereby reducing the coupling capacitance between the shading pattern and other signal lines. Even if the shading pattern is coupled with the second scanning signal line, the shading pattern can block the active pattern of the compensation transistor, which can improve the potential of the second scanning signal line and the gate control capability of the compensation transistor.

[0081] In some embodiments, Figures 6 to 8 , Fig.15 As shown, the first source-drain layer 216 includes a first data connection line L1, a first electrode T2S of a switching transistor T2, a first electrode T3S of a compensation transistor T3, a second electrode T3D of a compensation transistor T3, a first electrode T4S of a first initialization transistor T4, a second electrode T4D of a first initialization transistor T4, a first electrode T5S of a first light-emitting control transistor T5, a second electrode T5D of a first light-emitting control transistor T5, a first electrode T6S of a second light-emitting control transistor T6, a second electrode T6D of a second light-emitting control transistor T6, a first electrode T7S of a second initialization transistor T7, a second electrode T7D of a second initialization transistor T7, a first electrode T8S of a third initialization transistor T8, a second electrode T8D of a third initialization transistor T8, and a second initialization signal line VI-ANO.

[0082] Specifically, Fig.15 As shown, it can be understood that since the electrodes of each transistor are connected together, in order to improve the aperture ratio in actual design, the electrodes of each transistor share the same structure. Fig.15 In the figure, multiple reference numerals are used to identify the same structure. For example, a structure serves as both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4. Figure 7 As can be seen in , this is the location where the second node Q is connected. Similarly, other structures can also serve as multiple electrodes, and the location of each node can be determined accordingly.

[0083] Specifically, Fig.12 , Fig.15As shown, the first initialization signal line VI-G is connected to the first electrode T4S of the first initialization transistor T4 through the first connection terminal K1. In view of the small spacing between the projections of the first initialization signal line VI-G and the third scanning signal line Nscan2 on the substrate, a via hole is directly formed in the region corresponding to the first electrode of the first initialization transistor to connect the first initialization signal line, which may cause the via hole to be formed on the third scanning signal line Nscan2. Therefore, the first connection terminal K1 may be arranged on the first source-drain layer, and the first electrode of the first initialization transistor T4 may be connected through the first connection terminal K1. At the same time, a via hole is formed in the region corresponding to the first connection terminal K1, so that the first connection terminal K1 is connected to the first initialization signal line VI-G, thereby realizing the connection between the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4. The first connection terminal K1 is arranged on the symmetry axis of the two symmetrically arranged pixel driving circuits, so that the first electrode of the first initialization transistor T4 in the two symmetrically arranged pixel driving circuits can be connected to the first initialization signal line through the same first connection terminal K1, thereby reducing the number of via holes and improving the yield.

[0084] Specifically, Figure 8 , Fig.15 , Fig.16 As shown, since the high potential power line VDD has no overlap with the first electrode T5S of the first light emitting control transistor T5, and the high potential power line VDD will be connected to one plate of the storage capacitor, it is necessary to set a second connection terminal K2 so that the second connection terminal K2 is connected to the high potential power line VDD, so that the signal of the high potential power line VDD can be transmitted to the first electrode T5S of the first light emitting control transistor T5, and a second connection terminal K3 can be set so that the second connection terminal K3 is connected to the second plate Cst2 of the storage capacitor Cst, thereby realizing the connection between one plate of the storage capacitor Cst, the first light emitting control transistor T5 and the high potential power line VDD.

[0085] Specifically, Figures 8 to 15 As shown, the first electrode T3S of the compensation transistor T3 is connected to the gate T1G of the driving transistor T1. Therefore, a fourth connection terminal K4 can be set on the first source and drain layer. The fourth connection terminal K4 passes through the through hole 331 and is connected to the gate T1G of the driving transistor T1, thereby realizing the connection between the gate of the driving transistor T1 and the first electrode T3S of the compensation transistor T3.

[0086] In some embodiments, Figures 6 to 16As shown, the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array, each of the repeating units 30 includes two symmetrically arranged pixel driving circuits 31, and within the repeating unit 30, the second source and drain layer 218 includes two data lines DATA, an initialization signal connection line L3, two high potential power lines VDD and a second data connection line L2, the two data lines DATA are symmetrically arranged, the two high potential power lines VDD are symmetrically arranged, and the initialization signal connection line L3 and the second data connection line L2 are symmetrically arranged.

[0087] Specifically, the high potential power line VDD may be connected to the second connection terminal K2 through the via hole, and the data line may be connected to the first electrode T2S of the switch transistor T2 through the via hole.

[0088] Specifically, Fig.16 As shown, the second source-drain electrode layer 218 further includes a fifth connection terminal K5 , and the fifth connection terminal K5 is connected to the second electrode T6D of the second light emitting control transistor T6 and an electrode of the light emitting device.

[0089] Specifically, it can be understood that due to the design of the pixel driving circuit in the display area shown in the embodiment of the present application, the connection points of some routing lines are located in the non-display area. Therefore, some routing lines may not be connected together, but in fact, they will be connected. For example, in order to adopt the technology of setting the fan-out line in the display area (Fanout InAA, FIAA), the data line DATA will be set along the first direction. The first data connection line L1 set along the second direction and the second data connection line L2 set along the second direction will be connected, and will be connected to the data line outside the display area. However, the embodiment of the present application shows the design of the pixel driving circuit, and therefore, its connection points are not shown, but in fact, they will be connected.

[0090] At the same time, in order to realize the mesh structure design of the initialization signal line, the embodiment of the present application will set the initialization signal connection line L3, and the initialization signal connection line L3 can realize the mesh structure design of at least one of the first initialization signal line, the second initialization signal line and the third initialization signal line. Similarly, the initialization signal connection line will be connected to the initialization signal line.

[0091] For example, the first initialization signal line will be connected to the initialization signal connection line outside the display area, thereby realizing the mesh structure design of the first initialization signal line. Similarly, the mesh structure design of the second initialization signal line and the third initialization signal line can be realized. However, the embodiments of the present application are not limited to this. Some initialization signal connection lines can be connected to one of the first initialization signal line, the second initialization signal line and the third initialization signal line, and some initialization signal connection lines can be connected to another one of the first initialization signal line, the second initialization signal line and the third initialization signal line. Some initialization signal connection lines can also be connected to another one of the first initialization signal line, the second initialization signal line and the third initialization signal line, thereby realizing the mesh structure design of each initialization signal line.

[0092] In some embodiments, Fig.17 As shown, Fig.17 The arrangement position of the first via hole 341 is shown. The first via hole 341 refers to a via hole etched from the first source and drain electrode layer to the first active layer or the first gate layer.

[0093] In some embodiments, Fig.18 As shown, Fig.18 The arrangement position of the second via hole 342 is shown. The second via hole 342 refers to a via hole etched from the first source and drain electrode layer to the second active layer or the second gate layer.

[0094] In some embodiments, Fig.19 As shown, Fig.19 The configuration position of the third via hole 343 is shown. The third via hole 343 refers to a via hole etched from the second source and drain electrode layer to the first source and drain electrode layer.

[0095] In some embodiments, Fig. 20 As shown, Fig. 20 The fourth via hole 344 is shown as a location where the fourth via hole 344 is etched from the anode of the light emitting layer to the second source and drain layer.

[0096] In some embodiments, Fig.10 , Fig.11 As shown, the first active layer 207 includes an active pattern T1A of the driving transistor T1, and the first light shielding layer 204 includes a light blocking pattern 204a and a connecting line 204b, wherein the light blocking pattern 204a is arranged corresponding to the active pattern T1A of the driving transistor T1, and the connecting line 204b connects the adjacent light blocking patterns 204a. By making the first light shielding layer include the light blocking pattern, the active pattern of the driving transistor can be shielded from light, thereby preventing light from affecting the performance of the driving transistor and improving the performance of the driving transistor, and by making the connecting line connect the light blocking pattern, the first light shielding layer can form a mesh structure, so that the uniformity of the signal on the first light shielding layer is better.

[0097] Specifically, Fig.10 As shown, it can be seen that the light-blocking patterns 204a are connected by connecting lines 204b around them, so that a mesh structure design of the first light-shielding layer can be realized, thereby improving the uniformity of the signal transmitted on the first light-shielding layer.

[0098] Specifically, the first light shielding layer can be input with a high potential voltage, and specifically can be connected to a high potential power line.

[0099] In some embodiments, the second light-shielding layer 202 is disposed between the first light-shielding layer 204 and the substrate 201; or the second light-shielding layer 202 is disposed between the first light-shielding layer 204 and the first active layer 207; or the driving circuit layer 22 further includes a first gate layer 209, the first gate layer 209 is disposed between the first active layer 207 and the second active layer 212, and the second light-shielding layer 202 is disposed between the first gate layer 209 and the first active layer 207; or the driving circuit layer 22 further includes a first gate layer 209, the first gate layer 209 is disposed between the first active layer 207 and the second active layer 212, and the second light-shielding layer 202 is disposed between the first gate layer 209 and the second active layer 212.

[0100] Specifically, in order to prevent the second light-shielding layer from affecting the design of other film layers, the second light-shielding layer can be set separately, and the second light-shielding layer can be located between the substrate and the second active layer. The specific setting position is not limited. Therefore, the second light-shielding layer can be set between the first light-shielding layer and the substrate, or between the first light-shielding layer and the first active layer, or between the first active layer and the first gate layer, or between the first gate layer and the second active layer.

[0101] Specifically, depending on the choice of material for the second light-shielding layer, an insulating layer can be provided between the second light-shielding layer and the other film layers, or the second light-shielding layer can be in direct contact with the other film layers. For example, the second light-shielding layer uses a semiconductor material with light-shielding properties, and the second light-shielding layer can be separated from the first light-shielding layer by an insulating layer, or the second light-shielding layer can be in direct contact with the first light-shielding layer. When the second light-shielding layer can improve the electrical properties of other film layers or does not affect the electrical properties of other film layers, the second light-shielding layer can be in direct contact with the other film layers. This will not be repeated here.

[0102] In some embodiments, the second light-shielding layer is suspended. By suspending the second light-shielding layer, the second light-shielding layer can be coupled with the second scanning signal line and the third scanning signal line, so that the second light-shielding layer can be used as the bottom gate of the compensation transistor and the first initialization transistor, thereby improving the gate control ability of the compensation transistor and the first initialization transistor.

[0103] Specifically, the above embodiment is described by taking the second light shielding layer being suspended as an example, but the embodiments of the present application are not limited thereto. For example, the light shielding pattern may be grounded, or the light shielding pattern may be connected to the first light shielding layer.

[0104] In some embodiments, the first light shielding layer and the second light shielding layer are made of different materials.

[0105] In some embodiments, the material of the second light shielding layer includes one of amorphous silicon and polycrystalline silicon. By making the material of the second light shielding layer amorphous silicon or polycrystalline silicon, the second light shielding layer has light shielding properties, and the second light shielding layer is a semiconductor material, and the second light shielding layer can access signals, thereby improving the characteristics of the oxide semiconductor transistor.

[0106] Specifically, Figure 6 As shown, the driving circuit layer 22 also includes a first blocking layer 203 , a second blocking layer 205 , a buffer layer 206 , a first gate insulating layer 208 , a first interlayer insulating layer 211 , a second gate insulating layer 213 , a second interlayer insulating layer 215 , a first planarizing layer 217 and a second planarizing layer 219 .

[0107] Specifically, Figure 6 As shown, the display panel 2 further includes a light-emitting layer 23 , and the light-emitting layer 23 includes a pixel electrode layer 221 , a pixel definition layer 222 , a light-emitting material layer, a common electrode layer and a support column 223 .

[0108] Specifically, the first electrode of the transistor in the above embodiment is a source, and the second electrode is a drain; or the first electrode of the transistor in the above embodiment is a drain, and the second electrode is a source.

[0109] Specifically, the first scanning signal line Pscan, the second scanning signal line Nscan1, the third scanning signal line Nscan2, the fourth scanning signal line Pscan2 and the light-emitting control signal line EM can be respectively connected to different gate driving circuits. Specifically, five groups of gate driving circuits can be used to output signals to the first scanning signal line Pscan, the second scanning signal line Nscan1, the third scanning signal line Nscan2, the fourth scanning signal line Pscan2 and the light-emitting control signal line EM, respectively. Among them, the gate driving circuit connected to the first scanning signal line Pscan can adopt bilateral driving, and the other gate driving circuits adopt unilateral driving.

[0110] Specifically, the material of the first active layer includes silicon semiconductor material, specifically low temperature polysilicon.

[0111] Specifically, the material of the second active layer includes an oxide semiconductor material, specifically a metal oxide semiconductor material, and more specifically, indium gallium zinc oxide.

[0112] Specifically, the material of the first light shielding layer includes metal material.

[0113] Specifically, the driving transistor, the switching transistor, the first light emitting transistor, the second light emitting transistor, the second initialization transistor and the third initialization transistor are P-type transistors, and the first initialization transistor and the compensation transistor are N-type transistors.

[0114] Specifically, the above embodiments respectively describe the display panel in detail from the perspective of the pixel driving circuit, film layer structure, specific structure, material, and potential of each layer in the display panel. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the shading pattern is grounded, or the shading pattern is connected to the first shading layer, and the material of the second shading layer includes one of amorphous silicon and polycrystalline silicon.

[0115] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0116] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0117] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: substrate; A driving circuit layer, arranged on one side of the substrate, the driving circuit layer comprising a first light shielding layer, a second light shielding layer, a first active layer and a second active layer, the first light shielding layer being arranged between the substrate and the first active layer, the first active layer being arranged between the first light shielding layer and the second active layer, and the second light shielding layer being arranged between the substrate and the second active layer; The pattern of the second light shielding layer is the same as the pattern of the second active layer, and the pattern of the second light shielding layer is arranged correspondingly to the pattern of the second active layer; The driving circuit layer includes a pixel driving circuit, and the pixel driving circuit includes a switching transistor, a driving transistor, a compensation transistor and a first initialization transistor, the switching transistor is connected to the driving transistor at a first node; an electrode of the compensation transistor, an electrode of the first initialization transistor and the driving transistor are connected to a second node, and the other electrode of the compensation transistor is connected to the driving transistor at a third node; wherein the second active layer includes an active pattern of the compensation transistor and an active pattern of the first initialization transistor, and the second shading layer includes a shading pattern, the shading pattern is the same as the active pattern of the compensation transistor and the active pattern of the first initialization transistor, and the shading pattern is arranged corresponding to the active pattern of the compensation transistor and the active pattern of the first initialization transistor.

2. The display panel according to claim 1, wherein: The pixel driving circuit also includes a storage capacitor, the second active layer also includes a plate of the storage capacitor, and the second light shielding layer also includes an auxiliary pattern, the auxiliary pattern is the same as the pattern of the plate of the storage capacitor, and the auxiliary pattern is arranged corresponding to the plate of the storage capacitor.

3. The display panel according to claim 2, wherein: The gate of the switch transistor is connected to the first scan signal line, the first electrode of the switch transistor is connected to the data line, and the second electrode of the switch transistor is connected to the first electrode of the drive transistor at a first node; the gate of the compensation transistor is connected to the second scan signal line, the first electrode of the compensation transistor is connected to the gate of the drive transistor at a second node, and the second electrode of the compensation transistor is connected to the second electrode of the drive transistor; the gate of the first initialization transistor is connected to the third scan signal line, the first electrode of the first initialization transistor is connected to the first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate of the drive transistor at a second node; The pixel driving circuit further includes: a first light emission control transistor, wherein a gate of the first light emission control transistor is connected to a light emission control signal line, a first electrode of the first light emission control transistor is connected to a high potential power supply line, and a second electrode of the first light emission control transistor is connected to a first node with a first electrode of the driving transistor; a second light emission control transistor, wherein a gate of the second light emission control transistor is connected to the light emission control signal line, and a first electrode of the second light emission control transistor and a second electrode of the driving transistor are connected to a third node; a second initialization transistor, wherein a gate of the second initialization transistor is connected to a fourth scanning signal line, a first electrode of the second initialization transistor is connected to a second initialization signal line, and a second electrode of the second initialization transistor and a second electrode of the second light emission control transistor are connected to a fourth node; a third initialization transistor, wherein a gate of the third initialization transistor is connected to the fourth scanning signal line, a first electrode of the third initialization transistor is connected to the third initialization signal line, and a second electrode of the third initialization transistor is connected to the first electrode of the driving transistor at a first node; A storage capacitor, wherein one plate of the storage capacitor is connected to the high potential power line, and the other plate of the storage capacitor is connected to the gate of the driving transistor at a second node; A boost capacitor, one plate of the boost capacitor is connected to the first scanning signal line, and the other plate of the boost capacitor is connected to the second electrode of the first initialization transistor.

4. The display panel according to claim 3, wherein: The driving circuit layer also includes a first gate layer, a second gate layer, a first source-drain layer, and a second source-drain layer, the first gate layer is arranged between the first active layer and the second active layer, the second gate layer is arranged between the second active layer and the first source-drain layer, and the first source-drain layer is arranged between the second gate layer and the second source-drain layer.

5. The display panel according to claim 4, wherein: The first active layer includes an active pattern of a driving transistor, an active pattern of a switching transistor, an active pattern of a first light emission control transistor, an active pattern of a second light emission control transistor, an active pattern of a second initialization transistor, and an active pattern of a third initialization transistor, the active pattern of the driving transistor is arranged along a first direction, and the active pattern of the driving transistor is connected to the active pattern of the switching transistor, the active pattern of the first light emission control transistor, and the active pattern of the second light emission control transistor, the active pattern of the switching transistor and the active pattern of the first light emission control transistor are arranged along a second direction, the active pattern of the second light emission control transistor and the active pattern of the second initialization transistor are arranged along the second direction, and the active pattern of the second light emission control transistor is connected to the active pattern of the second initialization transistor, and the active pattern of the third initialization transistor is arranged alternately with the active pattern of the driving transistor, the active pattern of the switching transistor, the active pattern of the first light emission control transistor, the active pattern of the second light emission control transistor, and the active pattern of the second initialization transistor; An included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

6. The display panel according to claim 5, wherein: The first gate layer includes a first initialization signal line, a first scanning signal line, a light-emitting control signal line, a fourth scanning signal line, a gate of the driving transistor, a gate of the switching transistor, a gate of the first light-emitting control transistor, a gate of the second light-emitting control transistor, a gate of the second initialization transistor, a gate of the third initialization transistor and a first plate of a storage capacitor, and the first initialization signal line, the first scanning signal line, the first plate of the storage capacitor, the light-emitting control signal line and the fourth scanning signal line are arranged in sequence along the second direction.

7. The display panel according to claim 6, wherein: The second active layer includes an active pattern of a compensation transistor, an active pattern of a first initialization transistor and a second electrode plate of a storage capacitor, the active pattern of the compensation transistor is connected to the active pattern of the first initialization transistor, the second electrode plate of the storage capacitor is arranged on one side of the active pattern of the compensation transistor along a first direction, and a through hole is provided on the second electrode plate of the storage capacitor.

8. The display panel according to claim 7, wherein: The second gate layer includes a second scan signal line, a third scan signal line, a third initialization signal line, a gate of a compensation transistor and a gate of a first initialization transistor, and the third scan signal line, the second scan signal line and the third initialization signal line are sequentially arranged along the second direction.

9. The display panel according to claim 8, wherein: The first source-drain layer includes a first data connection line, a first electrode of a switching transistor, a first electrode of a compensation transistor, a second electrode of a compensation transistor, a first electrode of a first initialization transistor, a second electrode of a first initialization transistor, a first electrode of a first light-emitting control transistor, a second electrode of a first light-emitting control transistor, a first electrode of a second light-emitting control transistor, a second electrode of a second light-emitting control transistor, a first electrode of a second initialization transistor, a second electrode of a second initialization transistor, a first electrode of a third initialization transistor, a second electrode of a third initialization transistor, and a second initialization signal line.

10. The display panel according to claim 9, wherein: The driving circuit layer includes a plurality of repeating units arranged in an array, each of the repeating units includes two symmetrically arranged pixel driving circuits, and within the repeating units, the second source and drain layer includes two data lines, an initialization signal connection line, two high potential power lines and a second data connection line, the two data lines are symmetrically arranged, the two high potential power lines are symmetrically arranged, and the initialization signal connection line and the second data connection line are symmetrically arranged.

11. The display panel according to claim 1, wherein: The first active layer includes an active pattern of the driving transistor, the first light shielding layer includes a light blocking pattern and a connecting line, the light blocking pattern is arranged corresponding to the active pattern of the driving transistor, and the connecting line connects adjacent light blocking patterns.

12. The display panel according to claim 1, wherein: The second light-shielding layer is arranged between the first light-shielding layer and the substrate; or the second light-shielding layer is arranged between the first light-shielding layer and the first active layer; or the driving circuit layer also includes a first gate layer, the first gate layer is arranged between the first active layer and the second active layer, and the second light-shielding layer is arranged between the first gate layer and the first active layer, or the driving circuit layer also includes a first gate layer, the first gate layer is arranged between the first active layer and the second active layer, and the second light-shielding layer is arranged between the first gate layer and the second active layer.

13. The display panel according to claim 1, wherein: The second light shielding layer is suspended.

14. The display panel according to claim 1, wherein: The material of the second light shielding layer includes one of amorphous silicon and polycrystalline silicon.

15. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 14.

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