Data sorting method and storage device

Abstract

Data sorting method and storage device. The data sorting method includes: obtaining target verification data corresponding to target user data; if the index table does not contain first verification data identical to the target verification data, recording the target verification data and the target physical address corresponding to the target user data in the index table. In addition, if the index table contains first verification data identical to the target verification data: obtaining the first physical address corresponding to the first verification data from the index table to read the first user data corresponding to the first physical address; determining whether the first user data is identical to the target user data; if so, determining that the target user data is duplicate data, and modifying the address mapping table to set the target logical address corresponding to the target user data and the first logical address corresponding to the first user data to be mapped to the same physical address.

Description

Technical Field

[0001] The present invention relates to a data arrangement technology, and in particular to a storage device equipped with a non-volatile memory and a data arrangement method used therein. Background Art

[0002] Non-volatile memory (NVM) refers to computer memory whose stored data does not disappear when the current is cut off. It has advantages such as data non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Research and practice have shown that application system data stored in storage devices contains a large amount of redundancy. This redundant data (duplicate data) takes up too much physical space, resulting in wasted storage space. This in turn increases the probability of garbage collection during host write operations, thereby affecting host write speeds.

[0004] Existing methods for handling duplicate data primarily rely on compression technology to address data redundancy. However, this approach is limited to compressing data within a single logical cluster (typically 4KB) and is ineffective against data redundancy across logical clusters. To address this issue, controllers have previously developed in-band data deduplication technology, which removes duplicate data before writing it to flash media. However, this method requires significant computation and read operations during the host write process, competing with host write operations for RAM resources, sacrificing host write performance. Summary of the Invention

[0005] The present invention aims to solve the above-mentioned problem by effectively marking the existence of duplicate data and further sorting the duplicate data to increase the storage space and improve the operation efficiency of the storage device.

[0006] One or more embodiments of the present invention provide a data sorting method, comprising: obtaining target verification data corresponding to target user data; determining whether an index table contains first verification data identical to the target verification data; wherein if the index table does not contain the first verification data identical to the target verification data, recording the target verification data and the target physical address corresponding to the target user data in the index table. In addition, if the index table contains the first verification data identical to the target verification data: obtaining a first physical address corresponding to the first verification data from the index table to read the first user data corresponding to the first physical address; determining whether the first user data is identical to the target user data; if the first user data is identical to the target user data, determining that the target user data is duplicate data, and modifying the address mapping table to set the target logical address corresponding to the target user data and the first logical address corresponding to the first user data to be mapped to the same physical address.

[0007] In one or more embodiments of the present invention, after determining whether the first user data is the same as the target user data, if the first user data is not the same as the target user data, the index table is updated to record the target physical address corresponding to the target user data.

[0008] In one or more embodiments of the present invention, when the storage device is in an idle state, a repeated data analysis operation is performed on a plurality of user data stored in the storage device to select one of the plurality of user data as the target user data.

[0009] In one or more embodiments of the present invention, the index table includes the following fields: a check data field for recording check data corresponding to one or more user data; and a physical address field for recording physical addresses corresponding to the one or more user data, wherein the first check data corresponding to the first user data in the index table is mapped to the first physical address corresponding to the first user data.

[0010] In one or more embodiments of the present invention, setting the target logical address corresponding to the target user data and the first logical address corresponding to the first user data to be mapped to the same physical address includes: changing the target logical address to be mapped to the first physical address in the address mapping table; or changing the first logical address to be mapped to the target physical address in the address mapping table.

[0011] In one or more embodiments of the present invention, if the first user data is different from the target user data, updating the index table to record the target physical address corresponding to the target user data includes: changing the first verification data to be mapped to a first pointer address, wherein the first pointer address is used to point to a first physical address list, wherein the first physical address list is used to record the first physical address and the target physical address.

[0012] In one or more embodiments of the present invention, after the target logical address is changed to be mapped to the first physical address, the target physical address is marked as an invalid physical address; and after the first logical address is changed to be mapped to the target physical address, the first physical address is marked as an invalid physical address.

[0013] In one or more embodiments of the present invention, the target verification data and the first verification data are both cyclic redundancy check data.

[0014] One or more embodiments of the present invention provide a storage device comprising: a connection interface circuit for electrically connecting to a host system; a rewritable non-volatile memory module; and a memory controller electrically connected to the connection interface circuit and the rewritable non-volatile memory module. The memory controller is configured to: obtain target check data corresponding to target user data; determine whether an index table contains first check data identical to the target check data; and if the index table does not contain the first check data identical to the target check data, record the target check data and a target physical address corresponding to the target user data in the index table. Furthermore, if the index table contains the first check data identical to the target check data, obtain a first physical address corresponding to the first check data from the index table to read first user data corresponding to the first physical address; determine whether the first user data is identical to the target user data; and if the first user data is identical to the target user data, determine that the target user data is duplicate data and modify an address mapping table to map the target logical address corresponding to the target user data and the first logical address corresponding to the first user data to the same physical address.

[0015] Based on the foregoing, the data storage device and data consolidation method provided by the embodiments of the present invention reduce duplicate data within the storage device and improve the data storage efficiency of the storage device. In addition, data consolidation based on verification data reduces the system's additional computational workload and improves data consolidation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0017] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0018] Figure 2 is a flow chart of a data sorting method according to an embodiment of the present invention;

[0019] Figure 3 Schematic diagram of an index table / checksum to physical mapping table according to an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of modifying a mapping table according to an embodiment of the present invention;

[0021] Figure 5 A schematic diagram of modifying an index table / check-to-physical mapping table according to an embodiment of the present invention;

[0022] Figure 6 Schematic diagram of modifying an index table / check-to-physical mapping table according to an embodiment of the present invention.

[0023] Explanation of Figure Numbers

[0024] 10: Host system

[0025] 20: Storage device

[0026] 211: First processor

[0027] 110: Second processor

[0028] 120: Host memory

[0029] 130: Data transmission interface circuit

[0030] 210: Memory controller

[0031] 212: Data management circuit

[0032] 213: Memory interface control circuit

[0033] 214: Buffer memory

[0034] 220: Rewritable non-volatile memory module

[0035] 230: Connecting interface circuit

[0036] S210, S220, S230, S240, S250, S260, S270, S280: Process steps of the data sorting method

[0037] T31, T51, T52, T61, T62: Index table / checksum to physical mapping table

[0038] CRC1, CRC2: check data

[0039] L2P(1), L2P(2), L2P(3):

[0040] LCA1, LCA2, LCA3, LCA4: logical addresses

[0041] PCA0, PCA1, PCA2, PCA3, PCA4: physical address

[0042] T53: Physical Address List

[0043] IDC(1): indicator address

[0044] A41, A42, A51, A52, A53, A61: Arrow DETAILED DESCRIPTION

[0045] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0046] Figure 1 FIG is a block diagram of a host system and a storage device according to an embodiment of the present invention. Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0047] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0048] In this embodiment, the host system 10 is electrically connected to the storage device 20 via the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0049] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless method. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low-power Bluetooth memory storage device (e.g., iBeacon), etc., based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a display, and a speaker via the system bus.

[0050] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0051] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0052] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0053] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 220 according to instructions from the host system 10 .

[0054] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities that controls the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with a plurality of control instructions / program codes, and when the storage device 20 is operating, these control instructions / program codes are executed to perform operations such as writing, reading, and erasing data. Furthermore, in this embodiment, the control instructions / program codes can be further executed to perform data reading operations to implement the data reading method provided by the present invention. The control instructions / program codes corresponding to the data reading method can be further implemented as a hardware circuit unit to implement the data reading method provided by the present invention.

[0055] It is worth mentioning that in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present invention is not limited thereto.

[0056] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 may also be considered as operations performed by the memory controller 210.

[0057] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is configured to receive instructions from the processor 211 to transmit data. For example, the data management circuit 212 reads data from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 and writes the read data to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed based on a write instruction from the host system 10). For another example, the data management circuit 212 reads data from one or more physical units of the rewritable non-volatile memory module 220 (the data may be read from one or more storage cells in the one or more physical units) via the memory interface control circuit 213 and writes the read data to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed based on a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0058] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also known as programming) operation, a read operation, or an erase operation on the rewritable non-volatile memory module 220 .

[0059] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, and a physical address will be included.

[0060] Furthermore, the memory controller 210 establishes an address mapping table (Logical to Physical address mapping table) to record the mapping relationship between the logical addresses of the logical units (e.g., logical blocks, logical pages, or logical columns) allocated to the rewritable non-volatile memory module 220 and the physical addresses of the physical units (e.g., physical erase units / physical blocks, physical pages, physical columns). In other words, the memory controller 210 can use the address mapping table to look up the physical unit to which a logical unit is mapped (e.g., look up the physical page to which a logical page is mapped; look up the physical address to which a logical address is mapped). Furthermore, the memory controller 210 can use the address mapping table to look up the logical unit to which a physical unit is mapped (e.g., look up the logical page to which a physical page is mapped; look up the logical address to which a physical address is mapped).

[0061] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., various mapping tables, index tables, address tables), so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216.

[0062] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store data written by the host system 10 .

[0063] In this embodiment, the rewritable non-volatile memory module 220 has a plurality of word lines, wherein each of the plurality of word lines is electrically connected to a plurality of memory cells, also known as columns (also known as physical columns). The plurality of columns on the same word line constitute a physical programming unit (also known as a physical page). Each physical page corresponds to a physical address for recording the location of the data stored in the physical page. In addition, the plurality of physical pages can constitute a physical block (also known as a physical erase unit). Each of the plurality of memory dies of the rewritable non-volatile memory module has a plurality of physical blocks. It should be noted that the present invention is not limited to the size of each physical page and logical page.

[0064] In this embodiment, when storing user data from the host system 10, the memory controller 210 performs a cyclic redundancy check (CRC) operation on the user data using the size of each logical address (e.g., 4KB) as a basic unit to generate CRC data (also known as CRC data) corresponding to the user data of each basic unit size. The memory controller 210 then stores the user data and the corresponding CRC data together in the rewritable non-volatile memory module 220.

[0065] It should be noted that the physical address for writing user data is determined by the memory controller 210 based on demand and is not related to the CRC data of the user data or is not converted from the CRC data of the user data.

[0066] A cyclic redundancy check (CRC) is a checksum generation algorithm used to detect data errors. It calculates a fixed-length value (a CRC checksum, also called check data) on the user data and stores it with the user data. When the user data is read, the CRC checksum is recalculated and compared with the stored CRC checksum. If the two CRC checksums are equal, the data is error-free. If they are not equal, there may be an error in the data.

[0067] Figure 2 The figure is a flow chart of a data sorting method according to an embodiment of the present invention.

[0068] Please refer to Figure 2 In step S210 , the memory controller 210 obtains target verification data corresponding to the target user data.

[0069] Specifically, when the storage device is in an idle state, the memory controller 210 (or the processor 211) performs a duplicate data analysis operation on the plurality of user data stored in the rewritable non-volatile memory module 220. Initially, the memory controller 210 selects one of the plurality of user data as the target user data to analyze whether the target user data is duplicate data. In one embodiment, the memory controller 210 reads the target user data and the corresponding target check data (i.e., the CRC check code corresponding to the target user data) from the rewritable non-volatile memory module 220. The read target user data and target check data may be temporarily stored in the buffer memory 214.

[0070] Next, in step S220, the memory controller 210 determines whether the index table contains first verification data that is identical to the target verification data. If so, step S250 is executed; if so, step S230 is executed.

[0071] Specifically, the memory controller 210 may establish an index table (also called a parity-to-physical mapping table) in the buffer memory 214 .

[0072] Figure 3 Schematic diagram of index table / check to physical mapping table according to an embodiment of the present invention. Figure 3 For example, in one embodiment, index table T31 includes at least two fields: a check data field for recording check data corresponding to one or more user data; and a physical address field for recording the physical address corresponding to the one or more user data. For example, index table T31 records two entries, one of which corresponds to first user data and includes first check data CRC1 corresponding to the first user data and a first physical address PCA1, with the first check data CRC1 mapped to the first physical address PCA1; the other entry corresponds to second user data and includes second check data CRC2 corresponding to the second user data and a second physical address PCA2, with the second check data CRC2 mapped to the second physical address PCA2.

[0073] In another embodiment, the index table T31 may further include an index corresponding to the order of each entry, such as Figure 3 As shown, the index 001 corresponding to the first user data and the index 002 corresponding to the second user data. The index can be used to assist the memory controller 210 to quickly locate the verification data to be found or record the position of the corresponding verification data in the index table T31.

[0074] For example, when executing step S220, the memory controller 210 compares the index table T31 sequentially based on the content / value of the target check data to determine whether there is any check data that is equal to the target check data. For example, assuming that the content of the target check data is equal to the check data CRC1 (the check data that is equal to the target check data can be referred to as the first check data), the memory controller 210 determines whether there is any first check data that is equal to the target check data in the index table and checks whether the corresponding user data is also the same.

[0075] It is worth mentioning that since the target verification data and index table are already existing data, no additional computing resources are required for conversion, which reduces the system load.

[0076] Please come back Figure 2If the index table does not contain the same first parity data as the target parity data, the memory controller 210 determines that the target user data is not duplicate data. Then, in step S230, the memory controller 210 records the target parity data and the target physical address corresponding to the target user data in the index table (in the corresponding field, forming a new entry).

[0077] After completing the operation of recording the target check data and the target physical address corresponding to the target user data in the index table, if the buffer memory 214 has available space, the memory controller 210 will retain the target user data in the buffer memory 214. In another embodiment, the target user data may also be retained in the host memory 120 of the host 10. In this way, when the target user data corresponding to the target physical address is to be compared in the future, the target user data in the buffer memory 214 or the host memory 120 can be directly used for the comparison, thereby speeding up the comparison efficiency (because it does not need to be read from the rewritable non-volatile memory module 220 for comparison).

[0078] In one embodiment, after completing the operation of recording the target check data and the target physical address corresponding to the target user data into the index table, the duplicate data analysis of the target user data is completed, and the memory controller 210 can then analyze other user data that has not yet been analyzed to determine whether it is duplicate data.

[0079] That is, after recording the target check data and the target physical address corresponding to the target user data in the index table, the memory controller 210 determines whether there is another user data that has not been analyzed for duplicate data.

[0080] If there is another user data that has not been analyzed for duplicate data, the memory controller 210 uses the another user data as new target user data and obtains new target parity data corresponding to the new target user data (e.g., step S240). Conversely, if there is no other user data that has not been analyzed for duplicate data, the memory controller completes the duplicate data analysis operation.

[0081] On the other hand, if the memory controller 210 determines that the index table contains first verification data that is identical to the target verification data, in step S250, the memory controller 210 obtains a first physical address corresponding to the first verification data from the index table to read the first user data corresponding to the first physical address.

[0082] It should be noted that, in one embodiment, if the memory controller 210 determines that the index table contains first parity data that is identical to the target parity data, the memory controller 210 retrieves the first physical address corresponding to the first parity data from the index table. Before reading the first user data, the memory controller 210 first checks whether the first user data already exists in the buffer memory 214 or the host memory 120. If so, the memory controller 210 reads the first user data corresponding to the first physical address from the buffer memory 214 or the host memory 120. If not, the memory controller 210 reads the first user data from the first physical address of the rewritable non-volatile memory module 220.

[0083] In another embodiment, the memory controller 210 may temporarily store multiple physical addresses corresponding to multiple user data to be checked in the buffer memory 214. When some or all of the temporarily stored physical addresses meet the conditions for a multi-plane read operation, the multi-plane read operation is performed on the multiple physical addresses that meet the conditions to read the user data at these physical addresses in parallel, thereby shortening the time it takes to read the user data from the rewritable non-volatile memory module 220. The condition for the plane read operation is that the multiple physical addresses belong to different planes.

[0084] Next, in step S260, the memory controller 210 determines whether the first user data is the same as the target user data. If so, step S270 is executed; if not, step S280 is executed.

[0085] If the first user data is identical to the target user data, in step S270, the memory controller 210 determines that the target user data is duplicate data, and modifies the address mapping table to set the target logical address corresponding to the target user data and the first logical address corresponding to the first user data to be mapped to the same physical address.

[0086] Figure 4 Schematic diagram of a modified address mapping table according to an embodiment of the present invention. Figure 4, assuming that in the address mapping table L2P(1), the entry corresponding to the first user data is: the first logical address LCA1 of the first user data is mapped to the first physical address PCA1; and the entry corresponding to the target user data is: the target logical address LCA4 of the target user data is mapped to the target physical address PCA4. In addition, it is further assumed that the memory controller 210 performs step S270 to modify the address mapping table L2P(1) to set the target logical address LCA4 corresponding to the target user data and the first logical address LCA1 corresponding to the first user data to be mapped to the same physical address. The implementation method can be: the memory controller 210 changes the target logical address LCA4 to be mapped to the first physical address PCA1, as shown by arrow A41, to obtain an updated address mapping table L2P(2); or the memory controller 210 changes the first logical address LCA1 to be mapped to the target physical address PCA4, as shown by arrow A42, to obtain an updated address mapping table L2P(3).

[0087] In one embodiment, after changing the target logical address in the address mapping table to be mapped to the first physical address, the memory controller 210 marks the target physical address as an invalid physical address.

[0088] In one embodiment, when overwriting or garbage collection occurs subsequently, these invalid physical addresses can be directly recycled to achieve the purpose of releasing physical space.

[0089] In another embodiment, after remapping the first logical address in the address mapping table to the target physical address, the memory controller 210 marks the first physical address as an invalid physical address. For example, a trim table may be used to record physical addresses marked as invalid. In this way, when performing physical block cleanup operations such as garbage collection or physical space release operations in the future, the marked invalid physical addresses can be used to clear the corresponding storage space, thereby improving the space utilization efficiency of the storage device 20.

[0090] Next, in step S280 , the memory controller 210 updates the index table to record the target physical address corresponding to the target user data.

[0091] More specifically, in one embodiment, step S280 includes: the memory controller 210 changes the first verification data to be mapped to a first pointer address, wherein the first pointer address is used to point to a first physical address list; and the memory controller 210 records the first physical address and the target physical address to the first physical address list.

[0092] Figure 5This is a schematic diagram of modifying the index table / check-to-physical mapping table according to an embodiment of the present invention. Figure 5 For example, assuming that the target user data and the first user data have the same check data CRC1, the contents of the target user data and the first user data are different (the target user data is not a duplicate of the first user data), and the physical addresses of the target user data and the first user data are PCA4 and PCA1 respectively.

[0093] In this case, in order to record different physical addresses corresponding to the same check data, the memory controller 210 modifies the index table T51. As shown by arrow A52, the memory controller 210 modifies the physical address PCA1 originally corresponding to the check data CRC1 to the indicator address IDC(1) to obtain an updated index table T52. The memory controller 210 can access the corresponding physical address list T53 (also called the first physical address list) through this indicator address IDC(1). The memory controller 210 records the first physical address PCA1 originally corresponding to the check data CRC1 in the index table T51 to the physical address list T53, and also records the target physical address PCA4 corresponding to the same check data CRC1 to the physical address list T53.

[0094] Through this mechanism, the check data CRC1 can be mapped to the first physical address PCA1 and the target physical address PCA4. Consequently, when step S220 is executed in the future, if the other check data to be compared is determined to be the same as the check data CRC1, there is no need to continue searching the index table (because, under this mechanism, the check data recorded in the index table will not be repeated), thereby saving time in searching the index table.

[0095] In another embodiment, in order to record different physical addresses corresponding to the same verification data, the target verification data and the target physical address corresponding to the target user data may also be directly recorded in the index table.

[0096] Figure 6 This is a schematic diagram of modifying the index table / check to physical mapping table according to an embodiment of the present invention. Figure 6 For example, assuming that the target user data and the first user data have the same check data CRC1, the contents of the target user data and the first user data are different (the target user data is not a duplicate of the first user data), and the physical addresses of the target user data and the first user data are PCA4 and PCA1 respectively.

[0097] In this case, in order to record different physical addresses corresponding to the same check data, the memory controller 210 modifies the index table T61. As shown by arrow A61, the memory controller 210 inserts a new entry corresponding to the target user data after the original entry corresponding to the check data CRC1 to record the target check data CRC1 and the target physical address PCA4 corresponding to the target user data, and obtains an updated index table T62.

[0098] Through this mechanism, the check data CRC1 can be mapped to the first physical address PCA1 and the target physical address PCA4 via two consecutive entries. Consequently, when step S220 is executed in the future, if another check data to be compared is determined to be the same as the check data CRC1, the index table can be searched further down until the check data found is not CRC1, thereby saving time in searching the index table.

[0099] For example, if the memory controller 210 determines that the other target check data corresponding to the other target user data is identical to the check data CRC1, the memory controller 210 continues searching for the next check data and determines that the next check data CRC1 is also identical to the other target check data. The memory controller 210 then continues searching for the next check data and determines that the next check data CRC2 is different from the other target check data. At this point, the memory controller 210 has completed searching the index table and obtained the two physical addresses PCA1 and PCA4 mapped to the two check data CRC1s. The memory controller 210 then reads the corresponding first user data and target user data based on the two physical addresses PCA1 and PCA4 to determine whether the read first user data and target user data are identical to the other target user data.

[0100] Based on the above, the memory controller, storage device and data sorting method provided by the embodiments of the present invention can determine whether the target user data is duplicate data through the verification data and index table of the target user data, and update the index table based on the judgment result to effectively manage the duplicate data stored in the storage device, thereby increasing the space utilization efficiency and operation efficiency of the storage device.

[0101] The memory controller, storage device, and data organizing method provided by the embodiments of the present invention have the following specific advantages.

[0102] Reduce storage space occupancy: By identifying and eliminating duplicate data, the present invention significantly reduces storage space requirements and improves storage utilization efficiency.

[0103] Optimizing garbage collection performance: By marking invalid physical addresses and reducing the amount of duplicate data, the present invention reduces the necessity of garbage collection operations, thereby improving the overall performance of the storage device.

[0104] Improve host write performance: By reducing the calculation and reading operations introduced in the host write process and avoiding the execution of possible garbage collection, the present invention ensures a smooth and efficient data write process and improves the host write performance.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data collating method, characterized in that: include: Obtain target verification data corresponding to target user data; Determining whether the index table contains first verification data that is identical to the target verification data; If the index table does not contain the first verification data that is identical to the target verification data, recording the target verification data and the target physical address corresponding to the target user data into the index table; If the index table contains the first verification data that is identical to the target verification data, obtaining a first physical address corresponding to the first verification data from the index table to read first user data corresponding to the first physical address; determining whether the first user data is the same as the target user data; If the first user data is identical to the target user data, the target user data is determined to be duplicate data, and the address mapping table is modified to set the target logical address corresponding to the target user data and the first logical address corresponding to the first user data to be mapped to the same physical address.

2. The data arrangement method according to claim 1, wherein: After determining whether the first user data is the same as the target user data, the method further includes: If the first user data is different from the target user data, the index table is updated to record the target physical address corresponding to the target user data.

3. The data arrangement method according to claim 1, wherein: in When the storage device is in an idle state, a repeated data analysis operation is performed on a plurality of user data stored in the storage device, and each of the plurality of user data is sequentially selected as the target user data.

4. The data arrangement method according to claim 1, wherein: The index table includes the following fields: a verification data field for recording verification data corresponding to one or more user data; and The physical address field is used to record the physical address corresponding to the one or more user data.

5. The data arrangement method according to claim 1, wherein: The setting of mapping the target logical address corresponding to the target user data and the first logical address corresponding to the first user data to the same physical address includes: Mapping the target logical address to the first physical address in the address mapping table; or The first logical address is changed to be mapped to the target physical address in the address mapping table.

6. The data arrangement method according to claim 5, characterized in that: After the target logical address is changed to be mapped to the first physical address, marking the target physical address as an invalid physical address; as well as After the first logical address is changed to be mapped to the target physical address, the first physical address is marked as an invalid physical address.

7. The data arrangement method according to claim 2, wherein: If the first user data is different from the target user data, the step of updating the index table to record the target physical address corresponding to the target user data includes: Mapping the first check data to a first pointer address, wherein the first pointer address is used to point to a first physical address list; and The first physical address and the target physical address are recorded in the first physical address list.

8. The data arrangement method according to claim 1, wherein: The target verification data and the first verification data are both cyclic redundancy check data.

9. A storage device, characterized in that: include: A connection interface circuit for electrically connecting to a host system; Rewritable non-volatile memory module; as well as a memory controller electrically connected to the connection interface circuit and the rewritable non-volatile memory module, wherein the memory controller is configured to: Obtain target verification data corresponding to target user data; Determining whether the index table contains first verification data that is identical to the target verification data; If the index table does not contain the first verification data that is identical to the target verification data, recording the target verification data and the target physical address corresponding to the target user data into the index table; If the index table contains the first verification data that is the same as the target verification data: Obtaining a first physical address corresponding to the first verification data from the index table to read first user data corresponding to the first physical address; determining whether the first user data is the same as the target user data; If the first user data is identical to the target user data, the target user data is determined to be duplicate data, and the address mapping table is modified to set the target logical address corresponding to the target user data and the first logical address corresponding to the first user data to be mapped to the same physical address.

10. The storage device according to claim 9, wherein: After determining whether the first user data is the same as the target user data, the method further includes: If the first user data is different from the target user data, the index table is updated to record the target physical address corresponding to the target user data.

11. The storage device according to claim 9, wherein: in When the storage device is in an idle state, the memory controller performs a repeated data analysis operation on a plurality of user data stored in the rewritable non-volatile memory module, and sequentially selects each of the plurality of user data as the target user data.

12. The storage device according to claim 9, wherein: The index table includes the following fields: a verification data field for recording verification data corresponding to one or more user data; and The physical address field is used to record the physical address corresponding to the one or more user data.

13. The storage device according to claim 9, wherein: The setting of mapping the target logical address corresponding to the target user data and the first logical address corresponding to the first user data to the same physical address includes: The memory controller maps the target logical address to the first physical address in the address mapping table; or The memory controller maps the first logical address to the target physical address in the address mapping table.

14. The storage device according to claim 13, wherein: After changing the target logical address to be mapped to the first physical address, the memory controller marks the target physical address as an invalid physical address; as well as After changing the first logical address to be mapped to the target physical address, the memory controller marks the first physical address as an invalid physical address.

15. The storage device according to claim 10, wherein: If the first user data is different from the target user data, the operation of updating the index table to record the target physical address corresponding to the target user data includes: The memory controller maps the first check data to a first pointer address, wherein the first pointer address is used to point to a first physical address list; and The memory controller records the first physical address and the target physical address in the first physical address list.

16. The storage device according to claim 9, wherein: The target verification data and the first verification data are both cyclic redundancy check data.

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