Data block erasing method and device, storage medium, and electronic device

Abstract

An embodiment of the present application provides a method and device for erasing a data block, a storage medium, and an electronic device, wherein the method includes: creating a discard queue in the memory of a host, wherein the discard queue is used to store a clear instruction; determining a first position index of a first clear instruction according to a first register, wherein the first register is used to store a position index of a storage device extracting a clear command from the discard queue, and the host and the storage device are located in the same computer device; obtaining a first clear instruction in the discard queue according to the first position index, and erasing an invalid data block corresponding to the first clear instruction in the storage device.

Description

Technical Field

[0001] The embodiments of the present application relate to the computer field, and more specifically, to a method and device for erasing a data block, a storage medium, and an electronic device. Background Art

[0002] Solid State Drive (SSD) has advantages over traditional mechanical hard disk (HDD) such as faster speed, lower access latency, higher durability, lower energy consumption, smaller size and weight, no noise, and better resistance to magnetic field interference. As the price of SSD continues to drop, it will become increasingly popular. Based on the working principle of SSD and the characteristics of flash memory particles, it is impossible to achieve physical data overwriting. It can only erase and then write, repeating this process. Especially when some blocks are completely filled, the actual writing process will erase and write data on the flash memory particles multiple times, resulting in write amplification problems. In order to reduce the Write Amplification Factor (WAF), Trim technology was introduced. It is a data management technology that mainly informs the SSD which data blocks have been deleted or are no longer needed by the operating system, so that the SSD can avoid relocating data blocks that have been deleted or are no longer needed by the operating system during garbage collection (GC). This reduces the relocation of useless data blocks, thereby reducing the write amplification factor and extending the life of the SSD. At the same time, it can also increase the effective bandwidth of the SSD.

[0003] At present, the Trim function of SSD storage devices based on the Non-Volatile Memory Express (NVMe) protocol is implemented through specific NVMe commands (hereinafter referred to as Trim commands). When the host file system deletes a file, it triggers the operating system to send a Trim command to the storage device. By specifying the attributes of the logical block range, the device is informed that a certain logical block range is invalid and can be erased. In the NVMe protocol, the Trim command also belongs to the Input / Output (IO) command. Its principle mechanism is the same as the Read / Write and other commands in the IO command. They are all completed through the IO queue located in the host memory. That is to say, the host Read / Write command and the Trim command share the IO queue located in the host memory. According to the NVMe protocol, the host submits the issued Read / Write / Trim command to the IO submission queue (Submission Queue, SQ for short), and then notifies the storage device to read the command. The controller inside the device reads the command from the IO SQ of the host memory through the PCIe message, and executes the command inside the device. Finally, the result of the executed command is placed in the IO completion queue (Completion Queue, CQ for short) of the corresponding host memory through the PCIe message to complete an IO interaction.

[0004] However, when a large directory on the host (nested with a large number of subdirectories, files, etc.) is deleted, the host will also send a large number of Trim commands to report the storage device to erase useless data blocks. Since Trim commands and host read and write commands are both IO commands, they are shared in SQ / CQ usage. Therefore, in scenarios with high host IO throughput and a large number of Trim interleaving, the coexistence of a large number of Trim operations and high IO throughput affects the overall IO performance of the NVMe storage device.

[0005] Regarding related technologies, there is currently no effective solution to the problem that the overall IO performance of NVMe storage devices is affected by the coexistence of a large number of Trim operations and high IO throughput.

[0006] Therefore, it is necessary to improve the related technology to overcome the above-mentioned defects in the related technology. Summary of the invention

[0007] The embodiments of the present application provide a method and device for erasing a data block, a storage medium, and an electronic device to at least solve the problem in the related art that the overall IO performance of the NVMe storage device is affected by the coexistence of a large number of Trim operations and high IO throughput.

[0008] According to one embodiment of the present application, a method for erasing a data block is provided, comprising: creating a discard queue in the memory of a host, wherein the discard queue is used to store a clear instruction; determining a first position index of a first clear instruction according to a first register, wherein the first register is used to store a position index of a storage device extracting a clear command from the discard queue, and the host and the storage device are located in the same computer device; obtaining a first clear instruction in the discard queue according to the first position index, and erasing an invalid data block corresponding to the first clear instruction in the storage device.

[0009] In an exemplary embodiment, obtaining a first clear instruction in the discard queue according to the first position index includes: obtaining a first clear instruction in the submission queue according to the first position index, wherein the discard queue includes: the submission queue; after erasing the invalid data block corresponding to the first clear instruction in the storage device, the method also includes: storing the first clear instruction and the execution result of the first clear instruction in a completion queue, wherein the discard queue includes: the completion queue.

[0010] In an exemplary embodiment, after creating a discard queue in the memory of the host, the method further includes: obtaining a first address of the discard queue and writing the first address into a third register, wherein the third register is used to store the first address of the discard queue.

[0011] In an exemplary embodiment, obtaining a first clear instruction in the discard queue according to the first position index includes: obtaining the first address of the discard queue in the third register, and determining an offset position according to the first position index; and obtaining the first clear instruction in the discard queue according to the first address and the offset position.

[0012] In an exemplary embodiment, before determining the first position index of the first clear instruction according to the first register, the method also includes: upon receiving a first deletion request sent by the target client, constructing the first clear instruction according to the first deletion request, wherein the first deletion request is used to request deletion of an invalid data block corresponding to the first clear instruction; determining the first position index for writing the first clear instruction according to the second register, and writing the first clear instruction into the discard queue according to the first position index, wherein the second register is used to store the position index of the clear instruction written by the host to the discard queue.

[0013] In an exemplary embodiment, after writing the first clear instruction into the discard queue according to the first position index, the method further includes: updating the value in the second register; upon receiving a second deletion request sent by the target client, constructing a second clear instruction according to the second deletion request; determining a second position index for writing the second clear instruction according to the updated value in the second register, and writing the second clear instruction into the discard queue according to the second position index.

[0014] In an exemplary embodiment, before determining the first position index for writing the first clear instruction according to the second register, the method further includes: determining a first number of clear instructions in the discard queue, and determining a size relationship between the first number and the depth of the discard queue; and determining whether to determine the first position index for writing the first clear instruction according to the second register according to the size relationship.

[0015] In an exemplary embodiment, determining whether to determine the first position index for writing the first clear instruction according to the second register based on the size relationship includes: pausing determining the first position index for writing the first clear instruction according to the second register when the size relationship indicates that the first number is greater than or equal to the depth of the discard queue; and determining the first position index for writing the first clear instruction according to the second register when the size relationship indicates that the first number is less than the depth of the discard queue.

[0016] In an exemplary embodiment, before receiving a first deletion request sent by a target client, the method further includes: receiving request information sent by the target client and determining a type of the request information; when the type indicates that the request information is a first deletion request, constructing the first clear instruction according to the first deletion request; when the type indicates that the request information is an input / output request, constructing an input / output request instruction according to the input / output request, and writing the input / output request instruction into an input / output queue of the host.

[0017] In an exemplary embodiment, after erasing the invalid data block corresponding to the first clear instruction in the storage device, the method further includes: updating the value in the first register; determining a third position index of a third clear instruction based on the updated value in the first register; obtaining a third clear instruction in the discard queue based on the third position index, and erasing the invalid data block corresponding to the third clear instruction in the storage device based on the third clear instruction.

[0018] In an exemplary embodiment, updating the value in the first register includes: obtaining an execution result of the first clear instruction in a completion queue, wherein the discard queue includes: the completion queue; updating the value in the first register when the execution result indicates that the first clear instruction is completed; and prohibiting updating the value in the first register when the execution result indicates that the first clear instruction is not completed.

[0019] In an exemplary embodiment, creating a discard queue in the memory of a host includes: obtaining the depth of the discard queue and the size of a single command in a configuration space capability register of a storage device; and creating the discard queue in the memory of the host according to the depth of the discard queue and the size of the single command.

[0020] In an exemplary embodiment, creating a discard queue in the memory of a host includes: determining the input and output load of the computer device based on performance data of a central processing unit and a disk array card of the computer device; determining a target number of the discard queue based on the input and output load; and creating the discard queue in the memory of the host based on the target number.

[0021] In an exemplary embodiment, determining the target number of the discard queues based on the input and output loads includes: when the input and output loads are greater than a preset load, determining the target number of the discard queues to be a second number; when the input and output loads are less than a preset load, determining the target number of the discard queues to be a third number, wherein the second number is less than the third number.

[0022] In an exemplary embodiment, creating the discard queue in the host's memory according to the target number includes: updating a kernel configuration file of the host according to the second number or the third number; obtaining the target number of the discard queue in the kernel configuration file, and creating the discard queue in the host's memory according to the target number.

[0023] According to another embodiment of the present application, a data block erasing device is provided, including: a creation module, used to create a discard queue in the memory of a host, wherein the discard queue is used to store clear instructions; a determination module, used to determine a first position index of a first clear instruction according to a first register, wherein the first register is used to store a position index of a storage device extracting a clear command from the discard queue, and the host and the storage device are located in the same computer device; an erasing module, used to obtain a first clear instruction in the discard queue according to the first position index, and erase an invalid data block corresponding to the first clear instruction in the storage device.

[0024] According to another embodiment of the present application, a data block erasing system is provided, comprising: a host and a storage device, wherein the host is used to create a discard queue in the host's memory, wherein the discard queue is used to store clear instructions; the storage device is used to determine a first position index of a first clear instruction according to a first register; obtain the first clear instruction in the discard queue according to the first position index, and erase an invalid data block corresponding to the first clear instruction in the storage device, wherein the first register is used to store the position index of the storage device extracting the clear command from the discard queue.

[0025] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0026] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0027] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0028] Through the embodiment of the present application, a discard queue is created in the memory of the host, wherein the discard queue is used to store the clear instruction; the first position index of the first clear instruction is determined according to the first register, wherein the first register is used to store the position index of the storage device extracting the clear command from the discard queue, and the host and the storage device are located in the same computer device; the first clear instruction is obtained in the discard queue according to the first position index, and the invalid data block corresponding to the first clear instruction in the storage device is erased. That is, the present application adds a discard queue specifically used for the host to report useless data blocks to the storage device. When the upper layer application of the host deletes the file, the clear instruction is directly sent to the discard queue, and the device controller of the storage device extracts the clear instruction from the discard queue to complete the erasure of the internal useless data block. Since the embodiment of the present application isolates the path of the read and write command and the clear instruction from the host memory queue mechanism, it not only ensures the performance under high IO throughput, but also ensures the timeliness of the Trim operation, and solves the problem in the related art that the overall IO performance of the NVMe storage device is affected by the coexistence of a large number of Trim operations and high IO throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The exemplary embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0030] Figure 1 It is a hardware structure block diagram of a computer device of a data block erasing method according to an embodiment of the present application;

[0031] Figure 2 is a flow chart of a method for erasing a data block according to an embodiment of the present application;

[0032] Figure 3 It is an architectural diagram of the NVMe queue of the host memory of the prior art;

[0033] Figure 4 is an architectural diagram of an NVMe queue of a host memory according to an optional embodiment of the present application;

[0034] Figure 5 is a flowchart of initializing a host Discard queue according to an optional embodiment of the present application;

[0035] Figure 6 is a flow chart of Trim command interaction between a host and a storage device according to an optional embodiment of the present application;

[0036] Figure 7 is a structural block diagram of a data block erasing device according to an embodiment of the present application;

[0037] Figure 8 It is a structural block diagram of a data block erasing system according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0040] In this embodiment, a method for erasing a data block is also provided. The method embodiment provided in the embodiment of the present application can be executed in a data block erasing device, which can be a computer device or a similar computing device. Taking running on a computer device as an example, Figure 1 1 is a hardware structure block diagram of a computer device for a data block erasing method according to an embodiment of the present application. Figure 1 As shown, the computer device may include one or more ( Figure 1Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned computer device may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0041] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for erasing a data block in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0042] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the computer device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0043] In this embodiment, a method for erasing a data block is provided. Figure 2 is a flow chart of a method for erasing a data block according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0044] Step S202, creating a discard queue in the memory of the host, wherein the discard queue is used to store the clear instruction;

[0045] Step S204, determining a first position index of a first clear instruction according to a first register, wherein the first register is used to store a position index of a clear command extracted from a discard queue by a storage device, and the host and the storage device are located in the same computer device;

[0046] Step S206: Obtain a first clear instruction in the discard queue according to the first position index, and erase the invalid data block corresponding to the first clear instruction in the storage device.

[0047] It should be noted that the above storage device can be understood as a solid state drive (SSD for short). The above storage device is a hard disk made of a solid-state electronic storage chip array, which consists of a control unit and a storage unit (FLASH chip).

[0048] The above-mentioned clearing instruction can be understood as the Trim instruction. Trim is a data management technology used in SSDs. Its purpose is to prevent the SSD from relocating deleted data when performing internal garbage collection (GC), reduce the relocation of useless data, and thus reduce write amplification. This has increased the life of the SSD and can also increase the effective bandwidth of the disk.

[0049] The above-mentioned garbage collection is an automated data management mechanism in the solid-state drive, which is used to manage and optimize the use of flash memory. The main purpose of GC is to perform garbage collection operations in the flash memory to improve write performance and extend the life of the SSD. The process is to first copy the valid data (data still in use) in the data area Block and write it to the blank page Page of a different data area Block, then erase the current data area Block, and then start writing new data to the data area Block that has just been erased.

[0050] Through the above steps, through the embodiment of the present application, a discard queue is created in the memory of the host, wherein the discard queue is used to store the clear instruction; the first position index of the first clear instruction is determined according to the first register, wherein the first register is used to store the position index of the storage device extracting the clear command from the discard queue, and the host and the storage device are located in the same computer device; the first clear instruction is obtained in the discard queue according to the first position index, and the invalid data block corresponding to the first clear instruction in the storage device is erased. That is, the present application adds a discard queue specifically used for the host to report useless data blocks to the storage device. When the upper layer application of the host deletes the file, the clear instruction is directly sent to the discard queue, and the device controller of the storage device extracts the clear instruction from the discard queue to complete the erasure of the internal useless data block. Since the embodiment of the present application isolates the path of the read and write command and the clear instruction from the host memory queue mechanism, it not only ensures the performance under high IO throughput, but also ensures the timeliness of the Trim operation, and solves the problem in the related art that the overall IO performance of the NVMe storage device is affected by the coexistence of a large number of Trim operations and high IO throughput.

[0051] Optionally, in order to better understand the above step S206, the above step S206 may be implemented in the following manner: obtaining a first clear instruction in a submission queue according to the first position index, wherein the discard queue includes: the submission queue;

[0052] Optionally, after erasing the invalid data block corresponding to the first clear instruction in the storage device, the method further includes: storing the first clear instruction and the execution result of the first clear instruction in a completion queue, wherein the discard queue includes: the completion queue.

[0053] In an embodiment of the present application, the discard queue includes: a submission queue and a completion queue, wherein the submission queue is a queue used by the host side to store commands, which is generally created in the host memory, and the address of the queue is informed to the device through the NVMe related registers mapped by the Peripheral Component Interconnect Express (PCIe) Bar space, thereby performing command interaction between the host and device sides.

[0054] The completion queue is a queue used by the device side to store command completion results. It is generally created in the host memory. The address of the queue is notified to the device through the NVMe-related registers mapped in the PCIe Bar space, so that commands can be exchanged between the host and device sides.

[0055] That is, the submission queue is used to store tasks that are about to be executed, while the completion queue is used to store tasks that have been completed. In the embodiment of the present application, when a clear instruction is submitted to the submission queue, it will be executed asynchronously, and after the execution is completed, the result will be stored in the completion queue for further processing.

[0056] Optionally, after creating the discard queue in the memory of the host, the method further includes: obtaining the first address of the discard queue and writing the first address into a third register, wherein the third register is used to store the first address of the discard queue.

[0057] In the embodiment of the present application, writing the first address of the discard queue into the control register of the storage device configuration space can instruct the storage device controller to determine the starting address of the discard queue. Then the storage device controller can directly access the storage location of the discard queue to obtain the clear instruction, thereby realizing the data erasure operation.

[0058] By writing the first address of the discard queue into the Dosian register, the time overhead of the storage device in searching for the location of the discard queue can be reduced, thereby improving the efficiency of clear instruction processing and the overall performance of the system. That is, writing the first address of the discard queue into the third register of the storage device configuration space can help the storage device controller manage and process clear instructions more effectively, thereby improving the performance and efficiency of the system.

[0059] Optionally, obtaining a first clear instruction in the discard queue according to the first position index includes: obtaining the first address of the discard queue in the third register, and determining an offset position according to the first position index; and obtaining a first clear instruction in the discard queue according to the first address and the offset position.

[0060] That is to say, in the embodiment of the present application, the offset position of the first clear instruction can be determined based on the value in the first register, and then the position of the first clear instruction can be determined according to the first address and offset position of the discard queue, and then the storage device can obtain the first clear instruction in the discard queue, thereby realizing the data erasing operation.

[0061] Optionally, before determining the first position index of the first clear instruction according to the first register, it also includes: in case of receiving a first deletion request sent by the target client, constructing the first clear instruction according to the first deletion request, wherein the first deletion request is used to request deletion of an invalid data block corresponding to the first clear instruction; determining the first position index for writing the first clear instruction according to the second register, and writing the first clear instruction into the discard queue according to the first position index, wherein the second register is used to store the position index of the clear instruction written by the host to the discard queue.

[0062] In an embodiment of the present application, when the host receives a deletion request, a clear instruction is constructed according to the deletion request, and then the host obtains the position index for writing the clear instruction to the discard queue in the second register, and writes the constructed clear instruction to the discard queue based on the obtained position index.

[0063] It should be noted that at this time, the clear instruction is written into the submission queue in the discard queue.

[0064] Optionally, after writing the first clear instruction into the discard queue according to the first position index, it also includes: updating the value in the second register; upon receiving a second deletion request sent by the target client, constructing a second clear instruction according to the second deletion request; determining a second position index for writing the second clear instruction according to the updated value in the second register, and writing the second clear instruction into the discard queue according to the second position index.

[0065] That is to say, after the host writes the clear instruction into the discard queue, the value in the second register needs to be updated. When another delete request is received again, the clear instruction is constructed according to the received delete request, and then the host updates the position index in the second register, and writes the constructed clear instruction into the discard queue based on the updated position index.

[0066] Optionally, before determining the first position index for writing the first clear instruction according to the second register, it also includes: determining a first number of clear instructions in the discard queue, and determining a size relationship between the first number and the depth of the discard queue; and determining whether to determine the first position index for writing the first clear instruction according to the second register according to the size relationship.

[0067] It should be noted that in the embodiment of the present application, depth information is set for the discard queue, that is, the maximum number of requests for each discard queue. Therefore, before writing the first clear instruction into the discard queue, it is first necessary to determine the relationship between the first number and the depth of the discard queue, and determine whether to write the first clear instruction into the discard queue based on the relationship between the first number and the depth of the discard queue.

[0068] It should be noted that the greater the depth of the discard queue, the more clear instructions the system can process simultaneously, which can improve the system's throughput and response speed. However, if the queue depth is too large, it may lead to waste of system resources and increased latency. Therefore, the depth of the discard queue needs to be reasonably set according to the actual situation and performance requirements of the system.

[0069] Further, determining whether to determine the first position index for writing the first clear instruction according to the second register is determined according to the size relationship, including: when the size relationship indicates that the first number is greater than or equal to the depth of the discard queue, pausing to determine the first position index for writing the first clear instruction according to the second register; when the size relationship indicates that the first number is less than the depth of the discard queue, determining the first position index for writing the first clear instruction according to the second register.

[0070] In the case where the size relationship indicates that the first number is greater than or equal to the depth of the discard queue, it can be understood that the instructions in the queue exceed the maximum request number of the discard queue, and a new clear instruction cannot be written into the discard queue at this time; in the case where the size relationship indicates that the first number is less than the depth of the discard queue, it can be understood that the instructions in the queue do not exceed the maximum request number of the discard queue, and a new clear instruction can be written into the discard queue at this time, and then the first position index for writing the first clear instruction is determined according to the second register.

[0071] Optionally, before receiving the first deletion request sent by the target client, it also includes: receiving the request information sent by the target client, and determining the type of the request information; when the type indicates that the request information is a first deletion request, constructing the first clear instruction according to the first deletion request; when the type indicates that the request information is an input / output request, constructing an input / output request instruction according to the input / output request, and writing the input / output request instruction into the input / output queue of the host.

[0072] In an embodiment of the present application, the input-output queue and the discard queue are isolated. When the host receives a request message, the type of the request message is first determined. When the request message is a delete request, a corresponding clear instruction is constructed and the clear instruction is written into the corresponding discard queue; when the request message is an input-output request, a corresponding input-output instruction is constructed and the input-output instruction is written into the corresponding input-output queue.

[0073] Through the embodiments of the present application, the isolation of the paths of input and output instructions and clear instructions is achieved, which not only ensures the performance under high IO throughput, but also ensures the timeliness of the clearing operation, which not only improves the overall IO performance and functional completeness of the system, but also ensures that the clearing operation improves the GC efficiency inside the SSD, thereby reducing the loss of SSD life, thereby improving the overall performance of the storage device when high IO throughput and large-scale file deletion operations coexist.

[0074] Optionally, after erasing the invalid data block corresponding to the first clear instruction in the storage device, it also includes: updating the value in the first register; determining a third position index of a third clear instruction based on the updated value in the first register; obtaining a third clear instruction in the discard queue based on the third position index, and erasing the invalid data block corresponding to the third clear instruction in the storage device according to the third clear instruction.

[0075] When the first clear instruction is executed, the value in the first register needs to be updated so that when the clear operation is performed again, the location index of the new clear instruction can be accurately determined based on the value in the first register, and then the new clear instruction is obtained according to the obtained clear index, and the corresponding invalid data block in the storage device is erased according to the third clear instruction.

[0076] Optionally, updating the value in the first register includes: obtaining an execution result of the first clear instruction in a completion queue, wherein the discard queue includes: the completion queue; when the execution result indicates that the first clear instruction is completed, updating the value in the first register; when the execution result indicates that the first clear instruction is not completed, prohibiting the updating of the value in the first register.

[0077] In the embodiment of the present application, when the first clear instruction is completed, the value in the first register can be updated, otherwise the value in the first register is not allowed to be updated.

[0078] Optionally, creating a discard queue in the host's memory includes: obtaining the depth of the discard queue and the size of a single command in a configuration space capability register of a storage device; and creating a discard queue in the host's memory according to the depth of the discard queue and the size of a single command.

[0079] It should be noted that in an embodiment of the present application, the depth of the discard queue and the size of a single command are limited in the configuration space capability register of the storage device, and the depth of the discard queue and the size of a single command can be obtained based on the information in the configuration space capability register, and the depth of the discard queue and the size of a single command can also be changed by modifying the information in the configuration space capability register.

[0080] In an exemplary embodiment, creating a discard queue in the memory of a host includes: determining the input and output load of the computer device based on performance data of a central processing unit and a disk array card of the computer device; determining a target number of the discard queue based on the input and output load; and creating the discard queue in the memory of the host based on the target number.

[0081] Specifically, determining the target number of discard queues according to the input and output loads includes: when the input and output loads are greater than a preset load, determining the target number of discard queues to be a second number; when the input and output loads are less than a preset load, determining the target number of discard queues to be a third number, wherein the second number is less than the third number.

[0082] In the embodiment of the present application, when the load is heavy, the number of IO queues is reduced, and when the load is light, the number of IO queues is increased.

[0083] Through the embodiments of the present application, reducing the number of IO queues under heavy load can reduce contention and waiting time, and improve IO performance and response speed; increasing the number of IO queues under light load can better utilize system resources, avoid resource waste, and improve the overall efficiency of the system; dynamically adjusting the number of IO queues according to load conditions can more flexibly adapt to different load conditions, improve system stability and reliability; avoid excessive or insufficient resource allocation, and improve system performance and efficiency.

[0084] In addition, in an embodiment of the present application, a functional relationship between the load and the number of queues may be set, and the number of queues corresponding to the current load may be determined according to the functional relationship, and then a corresponding discard queue may be created according to the determined number of queues.

[0085] Optionally, creating the discard queue in the host's memory according to the target number includes: updating the host's kernel configuration file according to the second number or the third number; obtaining the target number of the discard queue in the kernel configuration file, and creating the discard queue in the host's memory according to the target number.

[0086] The number of discard queues is stored in a kernel configuration file of the host. When creating a request queue, the target number of the discard queue is obtained from the kernel configuration file, and then the corresponding discard queue is created according to the obtained target number.

[0087] Obviously, the above-described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. In order to better understand the above-mentioned data block erasing method, the above-mentioned process is described below in conjunction with the embodiments, but it is not intended to limit the technical solutions of the embodiments of the present application, specifically:

[0088] In order to better understand the embodiments of the present application, the related art is first described, specifically:

[0089] Based on the synchronization of NVMe command requests and responses, each request command is required to correspond to a response command. The request command is placed in SQ by the host, and the response command is placed in CQ by the controller of the storage device. NVMe stipulates that the storage device can have multiple IO queues (up to 64K), and SQ and CQ can be one-to-one or many-to-one. Its architecture is as follows: Figure 3 As shown, the specific IO command interaction process is as follows:

[0090] 1. The host submits a new IO command and puts it into the host memory IO SQ;

[0091] 2. The host updates the device register through PCIe messages and notifies the device controller to extract IO commands from SQ;

[0092] 3. The storage device controller obtains the IO command in the host SQ through the PCIe message, and updates the position of the SQ to obtain the command to facilitate the next command extraction;

[0093] 4. The storage device controller executes the IO commands submitted from the SQ;

[0094] 5. After the storage device controller completes the command execution, it submits the completion status, writes it to the host memory IO CQ through a PCIe message, and updates the location where the CQ places the command;

[0095] 6. The storage device controller informs the host that the command has been executed through an interrupt;

[0096] 7. The host extracts the command completion status from the memory IO CQ and updates the CQ fetch command position through a PCIe message, informing the device that the CQ information has been processed. At this point, the IO operation sent by the host is processed.

[0097] In the NVMe interaction mode in the related art, when a large directory (nested with a large number of subdirectories, files, etc.) is deleted, the host will also send a large number of Trim commands to report the storage device to erase useless data blocks. Since the Trim command and the host read and write commands are both IO commands, they will be shared in the use of SQ / CQ. Therefore, in the scenario of high IO throughput of the host and a large number of Trim interleaving, the following problems will occur:

[0098] 1) In scenarios with high host IO throughput, a large number of Trim operations reduce the performance of read and write IO, thereby reducing the overall performance of the NVMe storage device;

[0099] 2) In scenarios with high IO throughput of the host, the timeliness of the Trim operation is reduced due to a large number of read and write IO operations, resulting in the inability of the storage device to timely perceive useless data blocks, thereby reducing the efficiency of the garbage collection GC inside the SSD, increasing the write amplification problem of the SSD, and causing the loss of the SSD life.

[0100] In view of the above problems, the present application proposes a new method for implementing Trim in NVMe storage devices, which overcomes the overall IO performance of NVMe storage devices affected by the coexistence of a large number of Trim operations and high IO throughput. In addition to the management command queue and IO command queue defined by the existing NVMe protocol, the present application adds a queue specifically used for the host to report useless data blocks to the storage device, called the Discard queue (equivalent to the Discard queue in the above embodiment). When the upper-layer application of the host deletes a file, the Trim command (equivalent to the clear instruction in the above embodiment) is directly issued to the Discard queue through the file system, block device layer, and device driver layer. The device controller extracts the Trim command from the Discard queue, completes the internal useless data block erasure action, and promptly reports the execution result of the Trim command to the host. This method isolates the paths of read and write commands and Trim commands from the host memory queue mechanism, which ensures the performance under high IO throughput and the timeliness of the Trim operation, which not only improves the overall IO performance and functional integrity of the system, but also ensures the improvement of the internal GC efficiency of the SSD by the Trim operation, thereby reducing the loss of the SSD life. After adding the Discard queue, the NVMe queue framework of the host memory is as follows: Figure 4 shown.

[0101] In the embodiment of the present application, a method for initializing a Discard queue is also provided, such as Figure 5 As shown, Figure 5 This is a flowchart of the host Discard queue initialization according to an optional embodiment of the present application, and the specific steps are as follows:

[0102] Step S501: host initialization;

[0103] Step S502: the host writes the number of the Discard queues of the device and informs the storage device of the number of the Discard queues to be created;

[0104] It should be noted that the host determines the number of Discard queues to be created according to the kernel configuration. Optionally, the number of Discard queues can be dynamically configured according to the foreground IO load.

[0105] Step S503: Read the Discard queue parameters;

[0106] Specifically: The host reads the depth supported by the queue and the size of a single command from the configuration space capability register of the storage device.

[0107] Step S504: Create a Discard queue;

[0108] Specifically: The host creates a Discard queue in memory based on the queue depth and the size of a single command.

[0109] Step S505: write the device Discard queue address;

[0110] Specifically: after successfully creating the Discard queue, the host writes the first address of the Discard queue to the control register of the storage device configuration space (equivalent to the third register in the above embodiment).

[0111] The storage device receives the first address of the Discard queue written by the host through an interrupt and saves it in the internal register of the device.

[0112] Step S506: Initialize the head register (equivalent to the first register in the above embodiment) and the tail register (equivalent to the second register in the above embodiment) of the Discard queue;

[0113] It should be noted that the initial values ​​of the two registers of the Discard queue initialized by the storage device are 0. The two registers represent the index of the elements in the queue, which are called head and tail respectively. The head is used to record the position index of the command extracted from the Discard queue by the storage device, and the tail is used to record the position index of the command put into the Discard queue by the host.

[0114] After the host adds an element to the Discard queue, it needs to update the value of the tail register. After the storage device extracts an element from the Discard queue, it needs to update the value of the head register.

[0115] Step S507: Determine whether the number of Discard queues is greater than 1, and if so, execute step S508; otherwise, execute step S504;

[0116] Step S508: The queue is initialized and waits for the host to send a Trim command.

[0117] It should be noted that when the host deletes a file, the device driver constructs a Trim command, writes the command to the location indicated by the tail register of the Discard queue, then updates the tail register, and waits for the storage device to execute the command and return the status; the storage device extracts the command from the location indicated by the head register of the Discard queue and executes it, and then updates the head register.

[0118] In an embodiment of the present application, a method for interacting between a host and a storage device is also provided, such as Figure 6 As shown, Figure 6 This is a flow chart of the Trim command interaction between the host and the storage device according to an optional embodiment of the present application, and the specific steps are as follows:

[0119] Step S601: the host constructs a Trim command and writes the Trim command into a Discard queue;

[0120] Step S602: the host updates the tail register of the Discard SQ queue;

[0121] Step S603: the storage device extracts a Trim command from the Discard SQ queue;

[0122] Step S604: the storage device updates the head register of the Discard SQ queue;

[0123] Step S605: the storage device executes a Trim command to erase useless data blocks;

[0124] Step S606: The storage device writes the completion status to the Discard CQ queue;

[0125] Step S607: the storage device updates the tail register of the Discard CQ queue;

[0126] Step S608: the storage device sends an interrupt to report to the host that the execution of the Trim instruction is completed;

[0127] Step S609: the host extracts the completion status from the Discard CQ queue;

[0128] Step S610: The host updates the head register of the Discard CQ queue.

[0129] The embodiment of the present application adds a Discard queue for reporting useless data blocks of the device to the NVMe storage device in the host memory, thereby avoiding the impact of the existing IO queue request / response mechanism on the overall performance of the NVMe storage device due to the coexistence of a large number of Trim operations and high IO throughput, and isolates the read and write command and Trim command paths from the host memory queue mechanism, thereby ensuring performance under high IO throughput and the timeliness of the Trim operation, which not only improves the overall IO performance and functional completeness of the system, but also ensures that the Trim operation improves the internal GC efficiency of the SSD, thereby reducing the loss of the SSD life.

[0130] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0131] In this embodiment, a data block erasing device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0132] Figure 7 is a structural block diagram of a data block erasing device according to an embodiment of the present application, such as Figure 7 As shown, the device comprises:

[0133] A creation module 72, configured to create a discard queue in the memory of the host, wherein the discard queue is used to store the clear instruction;

[0134] A determination module 74, configured to determine a first position index of a first clear instruction according to a first register, wherein the first register is used to store a position index of a storage device extracting a clear command from a discard queue, and the host and the storage device are located in the same computer device;

[0135] The erasing module 76 is configured to obtain a first clearing instruction in the discarding queue according to the first position index, and erase an invalid data block corresponding to the first clearing instruction in the storage device.

[0136] Through the device of the present application, through the embodiment of the present application, a discard queue is created in the memory of the host, wherein the discard queue is used to store the clear instruction; the first position index of the first clear instruction is determined according to the first register, wherein the first register is used to store the position index of the storage device extracting the clear command from the discard queue, and the host and the storage device are located in the same computer device; the first clear instruction is obtained in the discard queue according to the first position index, and the invalid data block corresponding to the first clear instruction in the storage device is erased. That is, the present application adds a discard queue specifically used for the host to report useless data blocks to the storage device. When the upper layer application of the host deletes the file, the clear instruction is directly sent to the discard queue, and the device controller of the storage device extracts the clear instruction from the discard queue to complete the erasure of the internal useless data block. Since the embodiment of the present application isolates the path of the read and write command and the clear instruction from the host memory queue mechanism, it not only ensures the performance under high IO throughput, but also ensures the timeliness of the Trim operation, and solves the problem in the related art that the overall IO performance of the NVMe storage device is affected by the coexistence of a large number of Trim operations and high IO throughput.

[0137] In an exemplary embodiment, the above-mentioned device also includes: a writing module, used to obtain a first clear instruction in a submission queue according to the first position index, wherein the discard queue includes: the submission queue; after erasing the invalid data block corresponding to the first clear instruction in the storage device, the method also includes: storing the first clear instruction and the execution result of the first clear instruction in a completion queue, wherein the discard queue includes: the completion queue.

[0138] In an exemplary embodiment, the writing module is further used to obtain the first address of the discard queue and write the first address into a third register, wherein the third register is used to store the first address of the discard queue.

[0139] In an exemplary embodiment, the erasing module 76 is used to obtain the first address of the discard queue in the third register, and determine the offset position according to the first position index; and obtain a first clear instruction in the discard queue according to the first address and the offset position.

[0140] In an exemplary embodiment, the apparatus further includes: a construction module, configured to construct the first clearing instruction according to the first deletion request when receiving the first deletion request sent by the target client, wherein the first deletion request is used to request deletion of the invalid data block corresponding to the first clearing instruction;

[0141] A writing module is used to determine a first position index for writing the first clear instruction according to a second register, and write the first clear instruction into the discard queue according to the first position index, wherein the second register is used to store the position index where the host writes the clear instruction into the discard queue.

[0142] In an exemplary embodiment, the write module is also used to update the value in the second register; upon receiving a second deletion request sent by the target client, construct a second clear instruction according to the second deletion request; determine a second position index for writing the second clear instruction according to the updated value in the second register, and write the second clear instruction into the discard queue according to the second position index.

[0143] In an exemplary embodiment, the write module is also used to determine a first number of clear instructions in the discard queue, and determine a size relationship between the first number and the depth of the discard queue; and determine whether to determine a first position index for writing the first clear instruction based on a second register according to the size relationship.

[0144] In an exemplary embodiment, the write module is also used to suspend determining the first position index for writing the first clear instruction according to the second register when the size relationship indicates that the first number is greater than or equal to the depth of the discard queue; and to determine the first position index for writing the first clear instruction according to the second register when the size relationship indicates that the first number is less than the depth of the discard queue.

[0145] In an exemplary embodiment, the write module is also used to receive request information sent by the target client and determine the type of the request information; when the type indicates that the request information is a first deletion request, construct the first clear instruction according to the first deletion request; when the type indicates that the request information is an input / output request, construct an input / output request instruction according to the input / output request, and write the input / output request instruction into the input / output queue of the host.

[0146] In an exemplary embodiment, the writing module is further used to update the value in the first register;

[0147] A determination module 74, configured to determine a third position index of a third clear instruction according to the updated value in the first register;

[0148] The erasing module 76 is configured to obtain a third clearing instruction in the discarding queue according to the third position index, and erase the invalid data block corresponding to the third clearing instruction in the storage device according to the third clearing instruction.

[0149] In an exemplary embodiment, the write module is also used to obtain the execution result of the first clear instruction in the completion queue, wherein the discard queue includes: the completion queue; when the execution result indicates that the first clear instruction is completed, updating the value in the first register; when the execution result indicates that the first clear instruction is not completed, prohibiting the updating of the value in the first register.

[0150] In an exemplary embodiment, the creation module 72 is used to obtain the depth of the discard queue and the size of a single command in the configuration space capability register of the storage device; and create a discard queue in the host memory according to the depth of the discard queue and the size of the single command.

[0151] In an exemplary embodiment, a creation module 72 is used to determine the input and output load of the computer device based on the performance data of the central processing unit and the disk array card of the computer device; determine the target number of the discard queue based on the input and output load; and create the discard queue in the host's memory based on the target number.

[0152] In an exemplary embodiment, a module 72 is created to determine the target number of the discard queue to be a second number when the input-output load is greater than a preset load; and to determine the target number of the discard queue to be a third number when the input-output load is less than a preset load, wherein the second number is less than the third number.

[0153] In an exemplary embodiment, a creation module 72 is used to update a kernel configuration file of the host according to the second number or the third number; obtain a target number of the discard queue in the kernel configuration file, and create the discard queue in the host's memory according to the target number.

[0154] Optionally, the embodiment of the present application further provides a data block erasing system, Figure 8 is a structural block diagram of a data block erasing system according to an embodiment of the present application, such as Figure 8 As shown, the system includes:

[0155] A host 82 and a storage device 84, wherein

[0156] The host 82 is used to create a discard queue in the memory of the host, wherein the discard queue is used to store clear instructions;

[0157] The storage device 84 is used to determine the first position index of the first clear instruction according to the first register; obtain the first clear instruction in the discard queue according to the first position index, and erase the invalid data block corresponding to the first clear instruction in the storage device, wherein the first register is used to store the position index of the clear command extracted by the storage device from the discard queue.

[0158] Through the above system, through the embodiment of the present application, a discard queue is created in the memory of the host, wherein the discard queue is used to store the clear instruction; the first position index of the first clear instruction is determined according to the first register, wherein the first register is used to store the position index of the storage device extracting the clear command from the discard queue, and the host and the storage device are located in the same computer device; the first clear instruction is obtained in the discard queue according to the first position index, and the invalid data block corresponding to the first clear instruction in the storage device is erased. That is, the present application adds a discard queue specifically used for the host to report useless data blocks to the storage device. When the upper layer application of the host deletes the file, the clear instruction is directly sent to the discard queue, and the device controller of the storage device extracts the clear instruction from the discard queue to complete the erasure of the internal useless data block. Since the embodiment of the present application isolates the path of the read and write command and the clear instruction from the host memory queue mechanism, it not only ensures the performance under high IO throughput, but also ensures the timeliness of the Trim operation, and solves the problem in the related art that the overall IO performance of the NVMe storage device is affected by the coexistence of a large number of Trim operations and high IO throughput.

[0159] In an exemplary embodiment, the storage device 84 is used to obtain a first clear instruction in a submission queue according to the first position index, wherein the discard queue includes: the submission queue;

[0160] The storage device 84 is used to store the first clear instruction and the execution result of the first clear instruction in a completion queue, wherein the discard queue includes: the completion queue.

[0161] In an exemplary embodiment, the host 82 is used to obtain the first address of the discard queue and write the first address into a third register, wherein the third register is used to store the first address of the discard queue.

[0162] In an exemplary embodiment, the storage device 84 is used to obtain the first address of the discard queue in the third register, and determine the offset position according to the first position index; and obtain the first clear instruction in the discard queue according to the first address and the offset position.

[0163] In an exemplary embodiment, the host 82 is used to construct the first clear instruction according to the first delete request sent by the target client, upon receiving the first delete request, wherein the first delete request is used to request deletion of the invalid data block corresponding to the first clear instruction; determine the first position index for writing the first clear instruction according to the second register, and write the first clear instruction into the discard queue according to the first position index, wherein the second register is used to store the position index of the clear instruction written by the host to the discard queue.

[0164] In an exemplary embodiment, the storage device 84 is used to update the value in the second register;

[0165] The host 82 is used to construct a second clear instruction according to the second delete request sent by the target client when receiving the second delete request; determine the second position index for writing the second clear instruction according to the updated value in the second register, and write the second clear instruction into the discard queue according to the second position index.

[0166] In an exemplary embodiment, the host 82 is used to determine a first number of clear instructions in the discard queue, and determine a size relationship between the first number and the depth of the discard queue; and determine whether to determine a first position index for writing the first clear instruction according to a second register based on the size relationship.

[0167] In an exemplary embodiment, the host 82 is used to suspend determining the first position index for writing the first clear instruction according to the second register when the size relationship indicates that the first number is greater than or equal to the depth of the discard queue; and to determine the first position index for writing the first clear instruction according to the second register when the size relationship indicates that the first number is less than the depth of the discard queue.

[0168] In an exemplary embodiment, the host 82 is used to receive the request information sent by the target client and determine the type of the request information; when the type indicates that the request information is a first deletion request, construct the first clear instruction according to the first deletion request; when the type indicates that the request information is an input / output request, construct an input / output request instruction according to the input / output request, and write the input / output request instruction into the input / output queue of the host.

[0169] In an exemplary embodiment, the storage device 84 is used to update the value in the first register; determine the third position index of the third clear instruction according to the updated value in the first register; obtain the third clear instruction in the discard queue according to the third position index, and erase the invalid data block corresponding to the third clear instruction in the storage device according to the third clear instruction.

[0170] In an exemplary embodiment, the storage device 84 is used to obtain the execution result of the first clear instruction in the completion queue, wherein the discard queue includes: the completion queue; when the execution result indicates that the first clear instruction is completed, updating the value in the first register; when the execution result indicates that the first clear instruction is not completed, prohibiting the updating of the value in the first register.

[0171] In an exemplary embodiment, the host 82 is used to obtain the depth of the discard queue and the size of a single command in the configuration space capability register of the storage device; and create a discard queue in the host's memory according to the depth of the discard queue and the size of the single command.

[0172] In an exemplary embodiment, the host 82 is used to determine the input and output load of the computer device based on the performance data of the central processing unit and the disk array card of the computer device; determine the target number of the discard queue based on the input and output load; and create the discard queue in the host's memory based on the target number.

[0173] In an exemplary embodiment, the host 82 is used to determine the target number of the discard queue to be a second number when the input and output loads are greater than a preset load; and to determine the target number of the discard queue to be a third number when the input and output loads are less than a preset load, wherein the second number is less than the third number.

[0174] In an exemplary embodiment, the host 82 is used to update the kernel configuration file of the host according to the second number or the third number; obtain the target number of the discard queue in the kernel configuration file, and create the discard queue in the host's memory according to the target number.

[0175] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0176] Optionally, in this embodiment, the storage medium may be configured to store a computer program for performing the following steps:

[0177] S1, creating a discard queue in the memory of the host, wherein the discard queue is used to store clear instructions;

[0178] S2, determining a first position index of a first clear instruction according to a first register, wherein the first register is used to store a position index of a clear command extracted from a discard queue by a storage device, and the host and the storage device are located in the same computer device;

[0179] S3: Obtain a first clear instruction in the discard queue according to the first position index, and erase the invalid data block corresponding to the first clear instruction in the storage device.

[0180] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0181] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0182] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0183] S1, creating a discard queue in the memory of the host, wherein the discard queue is used to store clear instructions;

[0184] S2, determining a first position index of a first clear instruction according to a first register, wherein the first register is used to store a position index of a clear command extracted from a discard queue by a storage device, and the host and the storage device are located in the same computer device;

[0185] S3: Obtain a first clear instruction in the discard queue according to the first position index, and erase the invalid data block corresponding to the first clear instruction in the storage device.

[0186] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0187] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0188] Optionally, in this embodiment, the computer program product may be configured to perform the following steps through a computer program:

[0189] S1, creating a discard queue in the memory of the host, wherein the discard queue is used to store clear instructions;

[0190] S2, determining a first position index of a first clear instruction according to a first register, wherein the first register is used to store a position index of a clear command extracted from a discard queue by a storage device, and the host and the storage device are located in the same computer device;

[0191] S3: Obtain a first clear instruction in the discard queue according to the first position index, and erase the invalid data block corresponding to the first clear instruction in the storage device.

[0192] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0193] The embodiments of the present application also provide a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the steps in any one of the above method embodiments.

[0194] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0195] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0196] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for erasing a data block, characterized in that: include: Creating a discard queue in a memory of the host, wherein the discard queue is used to store the clear instruction; Determine a first position index of a first clear instruction according to a first register, wherein the first register is used to store a position index of a storage device extracting a clear command from a discard queue, and the host and the storage device are located in the same computer device; Obtaining a first clear instruction in the discard queue according to the first position index, and erasing an invalid data block corresponding to the first clear instruction in a storage device; Before determining the first position index of the first clear instruction according to the first register, the method also includes: upon receiving a first deletion request sent by the target client, constructing the first clear instruction according to the first deletion request, wherein the first deletion request is used to request deletion of an invalid data block corresponding to the first clear instruction; determining the first position index for writing the first clear instruction according to the second register, and writing the first clear instruction into the discard queue according to the first position index, wherein the second register is used to store the position index of the clear instruction written by the host to the discard queue.

2. The method according to claim 1, characterized in that Acquiring a first clear instruction in the discard queue according to the first position index includes: Obtaining a first clear instruction in a submission queue according to the first position index, wherein the discard queue includes: the submission queue; After erasing the invalid data block corresponding to the first clear instruction in the storage device, the method further includes: The first clear instruction and the execution result of the first clear instruction are stored in a completion queue, wherein the discard queue includes: the completion queue.

3. The method according to claim 1, characterized in that After creating the discard queue in the memory of the host, the method further includes: The first address of the discard queue is obtained, and the first address is written into a third register, wherein the third register is used to store the first address of the discard queue.

4. The method according to claim 3, characterized in that Acquiring a first clear instruction in the discard queue according to the first position index includes: Obtaining the first address of the discard queue in the third register, and determining an offset position according to the first position index; A first clear instruction is obtained in the discard queue according to the first address and the offset position.

5. The method according to claim 1, characterized in that After writing the first clear instruction into the discard queue according to the first position index, the method further includes: Updating the value in the second register; Upon receiving a second deletion request sent by the target client, constructing a second clearing instruction according to the second deletion request; A second position index for writing the second clear instruction is determined according to the updated value in the second register, and the second clear instruction is written into the discard queue according to the second position index.

6. The method according to claim 1, characterized in that Before determining the first position index for writing the first clear instruction according to the second register, the method further includes: Determining a first number of clear instructions in the discard queue, and determining a magnitude relationship between the first number and a depth of the discard queue; According to the size relationship, it is determined whether to determine a first position index for writing the first clear instruction according to a second register.

7. The method according to claim 6, characterized in that Determining whether to determine a first position index for writing the first clear instruction according to the size relationship according to the second register includes: In a case where the size relationship indicates that the first number is greater than or equal to the depth of the discard queue, pausing the determination of a first position index for writing the first clear instruction according to the second register; In a case where the size relationship indicates that the first number is smaller than the depth of the discard queue, a first position index for writing the first flush instruction is determined according to a second register.

8. The method according to claim 1, characterized in that Before receiving the first deletion request sent by the target client, the method further includes: Receiving a request message sent by the target client and determining a type of the request message; In a case where the type indicates that the request information is a first deletion request, constructing the first clearing instruction according to the first deletion request; In the case where the type indicates that the request information is an input / output request, an input / output request instruction is constructed according to the input / output request, and the input / output request instruction is written into the input / output queue of the host.

9. The method according to claim 1, characterized in that: After erasing the invalid data block corresponding to the first clear instruction in the storage device, the method further includes: Updating the value in the first register; Determine a third position index of a third clear instruction according to the updated value in the first register; A third clear instruction is obtained in the discard queue according to the third position index, and an invalid data block corresponding to the third clear instruction in the storage device is erased according to the third clear instruction.

10. The method according to claim 9, characterized in that Updating the value in the first register includes: Obtaining the execution result of the first clear instruction in a completion queue, wherein the discard queue includes: the completion queue; When the execution result indicates that the first clear instruction is completed, updating the value in the first register; When the execution result indicates that the first clear instruction is not completed, updating the value in the first register is prohibited.

11. The method according to claim 1, characterized in that: Create a discard queue in the host's memory, including: Obtaining the depth of the discard queue and the size of a single command in a configuration space capability register of the storage device; A discard queue is created in the host's memory according to the depth of the discard queue and the size of a single command.

12. The method according to claim 1, characterized in that Create a discard queue in the host's memory, including: Determine the input and output load of the computer device according to the performance data of the central processing unit and the disk array card of the computer device; Determining a target number of the discard queues according to the input and output loads; The discard queue is created in the memory of the host according to the target number.

13. The method according to claim 12, characterized in that Determining a target number of the discard queues according to the input and output loads includes: When the input and output load is greater than a preset load, determining the target number of the discard queue to be a second number; When the input and output load is less than a preset load, the target number of the discard queue is determined to be a third number, wherein the second number is less than the third number.

14. The method according to claim 13, characterized in that Creating the discard queue in the memory of the host according to the target number includes: Updating a kernel configuration file of the host according to the second number or the third number; The target number of the discard queue is obtained in the kernel configuration file, and the discard queue is created in the memory of the host according to the target number.

15. A data block erasing device, characterized in that: include: A creation module, used to create a discard queue in the memory of the host, wherein the discard queue is used to store the clear instruction; a determination module, configured to determine a first position index of a first clear instruction according to a first register, wherein the first register is used to store a position index of a storage device extracting a clear command from a discard queue, and the host and the storage device are located in the same computer device; an erasing module, configured to obtain a first clearing instruction in the discarding queue according to the first position index, and to erase an invalid data block corresponding to the first clearing instruction in a storage device; The device further includes: a construction module, configured to construct the first clearing instruction according to the first deletion request when receiving the first deletion request sent by the target client, wherein the first deletion request is used to request to delete the invalid data block corresponding to the first clearing instruction; A writing module is used to determine a first position index for writing the first clear instruction according to a second register, and write the first clear instruction into the discard queue according to the first position index, wherein the second register is used to store the position index at which the host writes the clear instruction into the discard queue.

16. A data block erasure system, characterized in that: include: Host and storage device, where The host is used to create a discard queue in a memory of the host, wherein the discard queue is used to store a clear instruction; The storage device is used to determine a first position index of a first clear instruction according to a first register; obtain the first clear instruction in the discard queue according to the first position index, and erase the invalid data block corresponding to the first clear instruction in the storage device, wherein the first register is used to store the position index of the clear command extracted by the storage device from the discard queue; The host is also used to construct the first clear instruction according to the first deletion request sent by the target client when the first deletion request is received, wherein the first deletion request is used to request deletion of the invalid data block corresponding to the first clear instruction; determine the first position index for writing the first clear instruction according to the second register, and write the first clear instruction into the discard queue according to the first position index, wherein the second register is used to store the position index of the clear instruction written by the host to the discard queue.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method according to any one of claims 1 to 14 when executed by a processor.

18. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 14 are implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 14 are implemented.

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