Garbage collection optimization method and device, equipment and medium
By establishing a global invalid data bitmap in the host memory and dynamically updating bit values using an access acceleration engine, the garbage collection process is optimized, solving the problem of low garbage collection efficiency in existing technologies and achieving efficient data migration and resource utilization.
Patent Information
- Application Number
- CN202511877027.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-03-06
AI Technical Summary
In existing garbage collection mechanisms, the inability to track the distribution of valid data within physical blocks leads to the need to sequentially read the logical address of each physical page and load the mapping table for comparison during the garbage collection process, resulting in low efficiency.
A global invalid data bitmap is created in the host memory. The bit values are dynamically updated by the access acceleration engine. During garbage collection, the physical pages with the second bit value in the source physical blocks to be reclaimed are selected according to the bitmap for validity verification and data migration, while physical pages with the first bit value are skipped.
It significantly improves garbage collection efficiency, reduces invalid data reads and mapping table queries, reduces CPU and flash bandwidth consumption, and extends SSD lifespan.
Smart Images

Figure CN121614094A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solid-state drive technology, and in particular to a waste recycling optimization method, apparatus, device, and medium. Background Technology
[0002] NAND flash memory is widely used in storage devices such as SSDs and UFS, providing reliable storage solutions for consumer electronics products such as tablets, mobile phones, and netbooks. The basic components of NAND include DIE (smallest concurrent operation unit), Block (smallest erase unit), and Page (smallest read / write unit). Due to NAND's write-before-write characteristic, a logical address (LPA) to physical address (PPA) mapping table (L2P) needs to be maintained to track data storage locations. As cost control requirements for consumer storage products become increasingly stringent, the internal memory space of SOC chips is shrinking, typically providing only 1-2MB of limited space as a cache for the mapping table, while the complete mapping table must be stored on NAND flash memory. With continuous writing of user data, the number of available physical blocks gradually decreases, triggering a garbage collection (GC) mechanism. During garbage collection, a source physical block is selected, its valid data is moved to a new physical block, and then the source physical block is erased to free up available space. However, since it is impossible to track the distribution of valid data within physical blocks, the logical address of each physical page must be read sequentially during the GC process, and the corresponding mapping table must be loaded for comparison in order to determine the validity of the data. This process involves a large number of invalid data readings and mapping table loading operations, which seriously affects the efficiency of garbage collection. Summary of the Invention
[0003] This invention provides a waste recycling optimization method, apparatus, equipment, and medium, aiming to solve the problem of low efficiency in existing waste recycling.
[0004] In a first aspect, embodiments of the present invention provide a waste recycling optimization method, comprising: A global invalid data bitmap is established in the host memory, wherein each entry in the global invalid data bitmap corresponds to a physical block, and each bitmap bit in the entry corresponds to a physical page within the physical block. The bit value corresponding to the bitmap bit includes a first bit value and a second bit value. By accessing the acceleration engine in response to data update events, the bit values of the corresponding physical pages in the global invalid data bitmap are dynamically updated. When garbage collection is triggered, the physical pages with the bit value of the second bit value in the source physical block to be collected are filtered according to the global invalid data bit chart and the access acceleration engine for validity verification and data migration, and physical pages with the bit value of the first bit value are skipped.
[0005] Secondly, embodiments of the present invention also provide a waste recycling optimization device, comprising: A creation unit is used to create a global invalid data bitmap in the host memory, wherein each entry in the global invalid data bitmap corresponds to a physical block, each bitmap bit in the entry corresponds to a physical page within the physical block, and the bit value corresponding to the bitmap bit includes a first bit value and a second bit value. An update unit is used to dynamically update the bit value of the corresponding physical page in the global invalid data bitmap in response to a data update event by accessing the acceleration engine; The verification skip unit is used to, when garbage collection is triggered, perform validity verification and data migration on physical pages whose bit value is the second bit value in the source physical block to be reclaimed, based on the global invalid data bit chart and the access acceleration engine, and skip physical pages whose bit value is the first bit value.
[0006] Thirdly, embodiments of the present invention also provide a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described method.
[0007] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the above-described method.
[0008] This invention provides a garbage collection optimization method, apparatus, device, and medium. The method includes: establishing a global invalid data bitmap in host memory, wherein each entry in the global invalid data bitmap corresponds to a physical block, and each bitmap bit in the entry corresponds to a physical page within the physical block; the bit value corresponding to the bitmap bit includes a first bit value and a second bit value; dynamically updating the bit value of the corresponding physical page in the global invalid data bitmap in response to a data update event via an access acceleration engine; and, upon triggering garbage collection, filtering physical pages in the source physical block to be collected based on the global invalid data bitmap and the access acceleration engine, performing validity verification and data migration on the physical pages with the second bit value, and skipping physical pages with the first bit value. This technical solution, by maintaining a global invalid data bitmap in host memory, directly skips physical pages with the first bit value during garbage collection, performing validity verification and data migration only on physical pages with the second bit value, significantly reducing invalid data reading and mapping table lookups, thereby improving garbage collection efficiency. Attached Figure Description
[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 This is a schematic flowchart of a waste recycling optimization method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a sub-process of a waste recycling optimization method provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a sub-process of a waste recycling optimization method provided in an embodiment of the present invention; Figure 4 A schematic flowchart of a waste recycling optimization method provided in another embodiment of the present invention; Figure 5 This is a schematic block diagram of a waste recycling optimization device provided in an embodiment of the present invention; Figure 6 This is a schematic block diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation
[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0012] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0013] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0014] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0015] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."
[0016] Please see Figure 1 , Figure 1 This is a schematic flowchart of a waste recycling optimization method according to an embodiment of the present invention. The waste recycling optimization method will be described in detail below. Figure 1 As shown, the method includes the following steps S110-S130.
[0017] S110. Establish a global invalid data bitmap in the host memory, wherein each entry in the global invalid data bitmap corresponds to a physical block, each bitmap bit in the entry corresponds to a physical page within the physical block, and the bit value corresponding to the bitmap bit includes a first bit value and a second bit value.
[0018] In this embodiment of the invention, space is allocated in the host memory using host memory buffer technology to store the global invalid data bitmap. During power-on initialization, compressed bitmap history data is loaded from the NAND flash memory, and the decompressed bitmap history data is written into the global invalid data bitmap in the host memory. Specifically, in DRAM-less solid-state drives, garbage collection efficiency is optimized by establishing a global invalid data bitmap in the host memory. The core of this approach is to utilize host memory buffer (HMB) technology to provide extended memory resources for the solid-state drive. In specific implementation, a contiguous physical address space is first requested and allocated in the host memory using HMB technology. This space is dedicated to storing the global invalid data bitmap. Each entry in the global invalid data bitmap uniquely corresponds to a physical block in the NAND flash memory, and the bitmap bits contained within each entry sequentially correspond one-to-one with the physical pages within its associated physical block. Each bit has a clear semantic definition: when the bit value is the first bit value (e.g., logical '1'), it explicitly indicates that the data stored in the physical page mapped by that bit is invalid; while when the bit value is the second bit value (e.g., logical '0'), it indicates that the validity of the data in that physical page is pending and requires further querying of the logical-to-physical address (L2P) mapping table for confirmation. To ensure a quick recovery of the garbage collection state after a reboot, during the power-on initialization phase, the SSD loads previously lossily compressed bitmap historical data from the system area of its NAND flash memory. After the bitmap historical data is loaded, it is decoded by the SSD's internal decompression module, restoring it to a complete linear bitmap structure. Subsequently, through the access acceleration engine, the decompressed bitmap historical data is efficiently written into the global invalid data bitmap in the host memory space pre-allocated via HMB, thereby completing the bitmap initialization, restoring the historical invalid data distribution information, and laying the foundation for subsequent efficient garbage collection operations.
[0019] S120. By accessing the acceleration engine in response to a data update event, the bit value of the corresponding physical page in the global invalid data bitmap is dynamically updated.
[0020] In this embodiment of the invention, the access acceleration engine communicates with the host memory via a PCIe interface to perform read and write operations on the global invalid data bitmap. It should be noted that in this embodiment, the access acceleration engine acts as a dedicated bridge between the solid-state drive controller and the host memory. Utilizing the high bandwidth and low latency characteristics of the PCIe bus, it directly accesses a specified address space in the host memory buffer by encapsulating and parsing PCIe message data packets. This design allows the solid-state drive firmware to update or query the global invalid data bitmap status located in the host memory efficiently and transparently, just like accessing local memory, thereby significantly improving the efficiency of invalid data identification during garbage collection.
[0021] In this embodiment, such as Figure 2 As shown, step S120 specifically includes steps S121-S122: S121. When a data write operation causes the data of the physical page to become invalid, the access acceleration engine updates the bit value corresponding to the physical page in the global invalid data bitmap to the first bit value. S122. When a new blank physical block is allocated for data writing, the access acceleration engine initializes all bit values in the global invalid data bitmap corresponding to the new blank physical block to the second bit value.
[0022] In this embodiment of the invention, during the operation of the solid-state drive (SSD), it is necessary to maintain the accuracy of the global invalid data bitmap in real time to ensure that it can provide correct guidance during garbage collection. This maintenance is mainly achieved through two key data update scenarios, both of which are efficiently executed by the access acceleration engine. First, dynamic marking of invalid data. When the host initiates a data write operation, it may overwrite the stored logical address, making the data in the physical page that originally stored that logical address become "invalid data" (i.e., logically updated, but physically still containing old data). At the same time, the TRIM command actively issued by the host will also explicitly indicate that data in certain logical address ranges is no longer needed, and the corresponding physical pages are also invalid. Once such a "data update event" is detected, the SSD's mapping management module will immediately initiate a bit write operation to the global invalid data bitmap in the host memory through the access acceleration engine. This operation will locate the entry corresponding to the physical block to which the invalid physical page belongs, and find the corresponding bit according to the offset of the physical page within the block, and update its value from "second bit value" (e.g., 0, indicating that the validity of the physical page data is pending) to "first bit value" (e.g., 1, indicating that the data stored in the physical page has been determined to be invalid). This process ensures that the global invalid data bitmap reflects the latest invalid data distribution in the NAND flash memory in real time and accurately. Secondly, the newly allocated physical block is initialized. During the write process, when a brand new, unused blank physical block needs to be allocated to carry new data, the bitmap management module accesses the acceleration engine to perform a batch initialization operation on the entire global invalid data bitmap entry corresponding to the new blank physical block. This operation uniformly sets all bits in the entry to the "second bit value" (e.g., 0). This is because all physical pages in the new blank physical block are in a "blank" state before data is written; there is no "valid" or "invalid" user data within them, and their validity is naturally in a "pending" state, waiting for subsequent data writing and possible overwrite operations to define. Through this pre-initialized batch initialization, it is ensured that the state of the new blank physical block in the global invalid data bitmap is clear and consistent before it is put into use.
[0023] S130. When garbage collection is triggered, the physical pages with the bit value of the second bit value in the source physical block to be collected are filtered according to the global invalid data bit chart and the access acceleration engine for validity verification and data migration, and the physical pages with the bit value of the first bit value are skipped.
[0024] In embodiments of the present invention, such as Figure 3As shown, step S130 specifically includes steps S131-S134: S131, obtaining the bitmap information corresponding to the physical block to be reclaimed in the global invalid data bitmap through the access acceleration engine; S132, determining the bit values of each physical page within the physical block to be reclaimed according to the bitmap information; S133, performing validity verification and data migration on the physical page with the bit value of the second bit value; S134, skipping the reading and comparison operation of the physical page for the physical page with the bit value of the first bit value. Specifically, firstly, when the garbage collection process is triggered and the physical block to be reclaimed is selected, the garbage collection processing module initiates a read request to the host memory through the access acceleration engine inside the solid-state drive. As a dedicated hardware module, the access acceleration engine can access the host memory with low latency through the PCIe bus and efficiently obtain the bitmap information corresponding to the physical block to be reclaimed in the global invalid data bitmap. Secondly, the obtained bitmap information is scanned, and the state corresponding to each bit is parsed. Each bit represents a physical page within the source physical block to be reclaimed, and its value has a clear semantic meaning: if the bit is the first bit value (e.g., logical '1'), it indicates that the data stored in the physical page has been confirmed as invalid; if it is the second bit value (e.g., logical '0'), it indicates that the validity of the data in the physical page is pending. Finally, for physical pages with a bit value of the second bit value ('0'), since their validity is uncertain, a regular validity verification process is initiated. This process includes reading the metadata (Spare Area) of the physical page to obtain its stored logical address (LPA), and then loading the corresponding logical-to-physical address mapping table (L2P) fragment for comparison. Only after confirming that the data is still valid will it be moved to a new target physical block, i.e., data migration will be performed; for physical pages with a bit value of the first bit value ('1'), the series of operations such as reading the physical page, querying the mapping table, and data migration are skipped directly. This is because these physical pages store confirmed "garbage data" and require no processing. Understandably, through the filtering mechanism based on the global invalid data bitmap described above, the garbage collection process can avoid unnecessary read, write and comparison operations on a large amount of invalid data, significantly reducing the access volume of NAND flash memory and the consumption of CPU resources, thereby greatly improving the overall efficiency of garbage collection.
[0025] Figure 4 This is a flowchart illustrating a waste recycling optimization method according to another embodiment of the present invention, as shown below. Figure 4 As shown, in this embodiment, the method includes steps S110-S140. That is, in this embodiment, after step S130 in the above embodiment, the method further includes step S140: S140. Periodically or according to preset triggering conditions, the global invalid data bitmap in the host memory is lossily compressed and then saved to the NAND flash memory area.
[0026] In this embodiment of the invention, step S140 specifically includes: traversing the global invalid data bitmap in the host memory to identify consecutive bit segments with the first bit value; recording each consecutive bit segment as a triplet; combining all the triplets into a compressed data block, ensuring that the size of the compressed data block does not exceed a preset compression threshold; and saving the compressed data block to the system area of the NAND flash memory. Specifically, In the garbage collection optimization mechanism of solid-state drives (SSDs), the persistent storage of the global invalid data bitmap is a crucial step in ensuring rapid recovery of the garbage collection state after power failure. This process uses an efficient lossy compression algorithm to convert the global invalid data bitmap in host memory into compact triples and store them in the system area of NAND flash memory. First, the global invalid data bitmap in host memory is traversed. The global invalid data bitmap records the data validity status of all physical pages within each physical block. During traversal, the bitmap bits in each entry (corresponding to a physical block) are scanned one by one, identifying bit segments where the first bit value is consecutive (e.g., logic '1', indicating that the data is definitely invalid). For each identified bit segment, it is encoded into a triple data structure. This triple typically contains three key fields: physical block number (block_index), used to locate the physical block to which the bit segment belongs; starting page offset (page_start), indicating the starting physical page position of the bit segment (consecutive invalid data segments) within the physical block; and consecutive page count (page_cnt), recording the total number of physical pages contained in the bit segment. After generating all triples, these triples are combined into a complete compressed data block. To ensure compression efficiency and control storage overhead, a preset compression threshold is set. The compression module ensures that the total size of the final compressed data block does not exceed the preset compression threshold; if it does, it may employ lossy pruning strategies such as prioritizing the preservation of longer contiguous segments. Finally, this compressed data block that meets the size limit is written to the system area of the NAND flash memory, thereby completing the persistent storage of the global invalid data bitmap state and providing a data foundation for rapid recovery during subsequent boots.
[0027] It should be noted that, in this embodiment, the triggering conditions include the number of garbage collection completions reaching a preset value, idle time exceeding a threshold, bitmap update count reaching an upper limit, imminent entry into low-power mode, or user-initiated save command. These conditions are monitored by hardware counters or software timers to ensure timely persistence of globally invalid data bitmap data and prevent data loss.
[0028] In summary, this embodiment establishes a global invalid data bitmap in the host memory, where each entry in the global invalid data bitmap corresponds to a physical block, and each bit corresponds to a physical page within that physical block. During garbage collection, data validity is determined directly based on the bit values in the bitmap: for physical pages marked with the first bit value, the read and comparison operations are skipped; only physical pages marked with the second bit value undergo validity verification and data migration, avoiding unnecessary operations on invalid data and significantly improving garbage collection efficiency; reducing write amplification and extending SSD lifespan; and optimizing system resource utilization, reducing CPU and flash memory bandwidth consumption.
[0029] Figure 5 This is a schematic block diagram of a waste recycling optimization device 200 provided in an embodiment of the present invention. Figure 5 As shown, corresponding to the above-described waste recycling optimization method, the present invention also provides a waste recycling optimization apparatus 200. This waste recycling optimization apparatus 200 includes a unit for performing the above-described waste recycling optimization method, and the apparatus can be configured in a computer device. Specifically, please refer to... Figure 5 The waste recycling optimization device 200 includes a setup unit 201, an update unit 202, and a verification skip unit 203. Detailed descriptions of each functional module are as follows: Establishment unit 201 is used to establish a global invalid data bitmap in the host memory, wherein each entry in the global invalid data bitmap corresponds to a physical block, each bitmap bit in the entry corresponds to a physical page within the physical block, and the bit value corresponding to the bitmap bit includes a first bit value and a second bit value. The update unit 202 is used to dynamically update the bit value of the corresponding physical page in the global invalid data bitmap in response to a data update event by accessing the acceleration engine; The verification skip unit 203 is used to, when garbage collection is triggered, perform validity verification and data migration on the physical pages in the source physical blocks to be reclaimed whose bit value is the second bit value according to the global invalid data bit chart and the access acceleration engine, and skip the physical pages whose bit value is the first bit value.
[0030] In some embodiments, such as this one, the establishment unit 201 is specifically used for: Space is allocated in the host memory using host memory buffering technology to store the global invalid data bitmap; During power-on initialization, compressed bitmap history data is loaded from NAND flash memory, and the decompressed bitmap history data is written into the global invalid data bitmap in the host memory.
[0031] In some embodiments, such as this one, the update unit 202 is specifically used for: When a data write operation causes the data on the physical page to become invalid, the access acceleration engine updates the bit value corresponding to the physical page in the global invalid data bitmap to the first bit value. When a new blank physical block is allocated for data writing, the access acceleration engine initializes all bit values in the global invalid data bitmap corresponding to the new blank physical block to the second bit value.
[0032] In some embodiments, such as this one, the verification skip unit 203 is specifically used for: The access acceleration engine obtains the bitmap information corresponding to the source physical block to be recycled in the global invalid data bitmap; The bit values of each physical page within the physical block to be recycled are determined sequentially based on the bitmap information. For the physical page whose bit value is the second bit value, perform validity verification and data migration on the physical page; For a physical page whose bit value is the first bit value, the reading and comparison operation of the physical page is skipped.
[0033] In some embodiments, such as this one, the waste recycling optimization device 200 further includes: The compression and storage unit is used to periodically or according to preset trigger conditions to compress the global invalid data bitmap in the host memory and then save it to the NAND flash memory area.
[0034] In some embodiments, such as this one, the compression and storage unit is specifically used for: Traverse the global invalid data bitmap in the host memory to identify bit segments with consecutive bit values of the first bit value; Record each consecutive bit segment as a triple; All the triples are combined into a compressed data block, and the size of the compressed data block is ensured not to exceed a preset compression threshold. The compressed data block is saved to the system area of the NAND flash memory.
[0035] The aforementioned waste recycling optimization device can be implemented as a computer program, which can, for example... Figure 6 It runs on the computer device shown.
[0036] Please see Figure 6 , Figure 6 This is a schematic block diagram of a computer device provided in an embodiment of the present invention. The computer device 300 is a device capable of optimizing waste recycling.
[0037] See Figure 6 The computer device 300 includes a processor 302, a memory, and a network interface 305 connected via a system bus 301. The memory may include a non-volatile storage medium 303 and internal memory 304.
[0038] The non-volatile storage medium 303 may store an operating system 3031 and a computer program 3032. When the computer program 3032 is executed, it causes the processor 302 to perform a garbage collection optimization method.
[0039] The processor 302 provides computing and control capabilities to support the operation of the entire computer device 300.
[0040] The internal memory 304 provides an environment for the execution of the computer program 3032 in the non-volatile storage medium 303. When the computer program 3032 is executed by the processor 302, the processor 302 can perform a garbage collection optimization method.
[0041] This network interface 305 is used for network communication with other devices. Those skilled in the art will understand that... Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the computer device 300 to which the present invention is applied. The specific computer device 300 may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.
[0042] The processor 302 is used to run a computer program 3032 stored in a memory to implement any embodiment of the above-described waste recycling optimization method.
[0043] It should be understood that, in this embodiment of the invention, the processor 302 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.
[0044] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a storage medium, which is a computer-readable storage medium. The computer program is executed by a processor in the computer system to implement the process steps of the embodiments of the above methods.
[0045] Therefore, the present invention also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program. When executed by a processor, the computer program causes the processor to perform any embodiment of the above-described garbage collection optimization method.
[0046] The storage medium can be any computer-readable storage medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), magnetic disk, or optical disk.
[0047] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0048] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.
[0049] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0050] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device to execute all or part of the steps of the methods described in the various embodiments of the present invention.
[0051] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0052] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.
[0053] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A garbage collection optimization method, characterized by, The method comprises the following steps: establishing a global invalid data bitmap table in the host memory, wherein each table entry in the global invalid data bitmap table corresponds to a physical block, and a bitmap bit in each table entry corresponds to a physical page in the physical block, and a bit value corresponding to the bitmap bit comprises a first bit value and a second bit value; updating the bit value of the corresponding physical page in the global invalid data bitmap table in response to a data update event through an access acceleration engine; when garbage collection is triggered, performing validity verification and data migration on the physical pages with the second bit value in the source physical block to be recycled according to the global invalid data bitmap table and the access acceleration engine, and skipping the physical pages with the first bit value.
2. The method of claim 1, wherein, The step of establishing a global invalid data bitmap table in the host memory comprises: allocating space in the host memory for storing the global invalid data bitmap table through host memory buffer technology; loading compressed bitmap table history data from a NAND flash memory during power-on initialization, and writing the decompressed bitmap table history data into the global invalid data bitmap table in the host memory.
3. The method of claim 1, wherein, The step of updating the bit value of the corresponding physical page in the global invalid data bitmap table in response to a data update event through an access acceleration engine comprises: when a data write operation causes the data of the physical page to be invalid, updating the bit value corresponding to the physical page in the global invalid data bitmap table to the first bit value through the access acceleration engine; when a new blank physical block is allocated for data writing, initializing all bit values corresponding to the new blank physical block in the global invalid data bitmap table to the second bit value through the access acceleration engine.
4. The method of claim 1, wherein, The step of performing validity verification and data migration on the physical pages with the second bit value in the source physical block to be recycled according to the global invalid data bitmap table and the access acceleration engine, and skipping the physical pages with the first bit value comprises: obtaining bitmap information corresponding to the source physical block to be recycled in the global invalid data bitmap table through the access acceleration engine; judging the bit values of the physical pages in the source physical block to be recycled in sequence according to the bitmap information; for the physical pages with the second bit value, performing validity verification and data migration on the physical pages; for the physical pages with the first bit value, skipping the read and comparison operations of the physical pages.
5. The method of claim 1, wherein, The method further comprises: periodically or according to a preset trigger condition, saving the global invalid data bitmap table in the host memory to a NAND flash memory area after lossy compression.
6. The method of claim 5, wherein, The step of saving the global invalid data bitmap table in the host memory to a NAND flash memory area after lossy compression comprises: traversing the global invalid data bitmap table in the host memory to identify continuous bit segments with the first bit value; recording each continuous bit segment as a triple; Combine all the triples into a compressed data block, and ensure that the size of the compressed data block does not exceed a preset compression threshold; Save the compressed data block to the system area of the NAND flash memory.
7. The method according to any one of claims 1 to 6, characterized in that, The access acceleration engine communicates with the host memory through a PCIe interface to read and write the global invalid data bitmap table.
8. A garbage collection optimization apparatus characterized by comprising: Comprise: The establishing unit is configured to establish a global invalid data bitmap table in the host memory, wherein each table entry in the global invalid data bitmap table corresponds to a physical block, and a bitmap bit in each table entry corresponds to a physical page in the physical block, and a bit value corresponding to the bitmap bit includes a first bit value and a second bit value; The updating unit is configured to dynamically update the bit value of the corresponding physical page in the global invalid data bitmap table in response to a data update event through an access acceleration engine; The verification skipping unit is configured to, when triggering garbage collection, perform validity verification and data migration on the physical pages with the second bit value in the source physical block to be recycled according to the global invalid data bitmap table and the access acceleration engine, and skip the physical pages with the first bit value.
9. A computer device, comprising: The computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the method of any one of claims 1-7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, and the computer program can implement the method of any one of claims 1-7 when executed by a processor.
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