A hardware accelerator and hardware acceleration method based on three-dimensional number theory transform

Abstract

The application discloses a hardware accelerator and a hardware acceleration method based on three-dimensional number theory transformation. The hardware accelerator comprises a control unit, a coefficient storage, a dimension switching rotation factor storage and a calculation component. The method comprises generating an address signal, a control signal, a polynomial coefficient and a dimension switching rotation factor, sequentially receiving the address signal, the control signal, the polynomial coefficient and the dimension switching rotation factor to perform three-dimensional number theory transformation, and outputting a transformation access result. The embodiment of the application can simplify the complex data dependency relationship between stages through a three-dimensional number theory transformation algorithm without additional hardware units, and realizes on-chip access without conflict. The application can be widely applied to the technical field of hardware acceleration.

Description

Technical Field

[0001] The present application relates to the field of hardware acceleration technology, and in particular to a hardware accelerator and a hardware acceleration method based on three-dimensional number theory transformation. Background Art

[0002] Existing hardware architectures for number-theoretic transformations can be divided into iterative and pipelined structures. In large polynomial dimensions, iterative structures introduce complex inter-stage data dependencies, increased control logic overhead, and the need for high memory bandwidth. Pipeline structures often only produce one or two outputs, resulting in low throughput. Furthermore, multidimensional number-theoretic transformations treat a one-dimensional polynomial coefficient vector as a multidimensional tensor and decompose the larger number-theoretic transformation into a series of independent smaller number-theoretic transformations on each dimension of the tensor. However, the transition from one-dimensional vectors to multidimensional tensors introduces more complex storage access, which generally requires additional hardware units. For existing designs using two-dimensional number-theoretic transformations, in order to achieve complex storage access, most designs require an additional transposition unit or involve frequent interactions between the chip and the outside world, resulting in decreased performance.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to propose a hardware accelerator and hardware acceleration method based on three-dimensional number theory transformation, which can simplify complex data dependencies between levels and achieve conflict-free on-chip access through three-dimensional number theory transformation algorithms without the need for additional hardware units.

[0005] To achieve the above objectives, one aspect of an embodiment of the present application proposes a hardware accelerator based on three-dimensional number theory transformation, the hardware accelerator including a control unit, a coefficient storage, a dimension switching rotation factor storage, and a computing unit, wherein the first output end of the control unit is connected to the first input end of the coefficient storage, the second output end of the control unit is connected to the first input end of the dimension switching rotation factor storage, the third output end of the control unit is connected to the first input end of the computing unit, the output end of the coefficient storage is connected to the second input end of the computing unit, the output end of the dimension switching rotation factor storage is connected to the third input end of the computing unit, the first output end of the computing unit is connected to the second input end of the computing unit, and the second output end of the computing unit is connected to the third input end of the computing unit, wherein:

[0006] The control unit is used to generate an address signal and a control signal;

[0007] The coefficient storage is used to generate polynomial coefficients;

[0008] The dimension switching rotation factor storage is used to generate a dimension switching rotation factor;

[0009] The computing component is used to sequentially receive the address signal, the control signal, the polynomial coefficients and the dimension switching rotation factor to perform a three-dimensional number theory transformation and output a transformation access result.

[0010] In some embodiments, the control unit includes a control logic unit and an address generation unit, and the output end of the control logic unit is connected to the input end of the address generation unit, wherein:

[0011] The control logic unit is used to generate the control signal;

[0012] The address generating unit is configured to generate the address signal.

[0013] In some embodiments, the input control signal of the control logic unit includes a first logic input control signal, a second logic input control signal and a third logic input control signal. The first logic input control signal and the second logic input control signal are used to dynamically configure the dimension of the polynomial coefficients. The third logic input control signal is used to control the working mode of the computing component. The working mode of the computing component includes a number theory transformation mode and an inverse number theory transformation mode.

[0014] In some embodiments, the coefficient storage and the calculation component, and the dimension switching rotation factor storage and the calculation component are both connected through a plurality of multiplexers.

[0015] In some embodiments, the computing component includes a plurality of pipelined number-theoretic transformation units, each of which is provided with a modular multiplier group, and the modular multiplier group is used to perform the point multiplication of the rotation factors required for dimension switching.

[0016] In some embodiments, the pipelined number theory transformation unit includes a butterfly unit, a first first-in-first-out memory, a second first-in-first-out memory, a first multiplexer, and a second multiplexer, wherein:

[0017] The butterfly unit is used to perform butterfly calculation and dynamically control the working mode of the calculation component according to the third logic input control signal;

[0018] The first first-in first-out memory and the second first-in first-out memory are used to store data generated by the butterfly unit calculation;

[0019] The first multiplexer and the second multiplexer are used for transmitting data.

[0020] To achieve the above object, another aspect of the embodiment of the present application proposes a hardware acceleration method of a hardware accelerator based on three-dimensional number theory transformation, which comprises:

[0021] Obtaining an address signal and a control signal;

[0022] A one-dimensional polynomial coefficient tensor is stored in the coefficient storage according to the index i in ascending order of the coefficients of each k-j plane in combination with the address signal and the control signal, to obtain polynomial coefficients;

[0023] Obtaining a dimension switching rotation factor;

[0024] According to the polynomial coefficients, in combination with the address signal and the control signal, the first round of number theory transformation calculation is performed in a pipeline manner to obtain the first round of number theory transformation calculation result, which is stored back to the coefficient storage;

[0025] Obtaining the first round of number theory transformation calculation result, in combination with the address signal, the control signal and the dimension switching rotation factor, the second round of number theory transformation calculation is performed in a pipeline manner to obtain the second round of number theory transformation calculation result, which is stored back to the coefficient storage;

[0026] Obtaining the second round of number theory transformation calculation result, in combination with the address signal, the control signal and the dimension switching rotation factor, the third round of number theory transformation calculation is performed in a pipeline manner to obtain the third round of number theory transformation calculation result, which is stored back to the coefficient storage.

[0027] In some embodiments, the first round of number theory transformation calculation comprises:

[0028] According to the address signal and the control signal, the polynomial coefficients are stored in the coefficient storage;

[0029] Based on each clock cycle, according to the address signal, the polynomial coefficients of the coefficient storage are transmitted to the pipeline number theory transformation unit through a multiplexer;

[0030] Until the pipeline is filled, the output result of each cycle of the pipeline number theory transformation unit is obtained, and is written back to the original position of the coefficient storage through the multiplexer according to the address signal.

[0031] In some embodiments, the second round of number theory transformation calculation comprises:

[0032] The first round of number theory transformation calculation result is obtained based on the coefficient storage;

[0033] Based on each clock cycle, according to the address signal, transmitting the first round of number theory transformation calculation results to the modular multiplier group through the multiplexer to multiply them with the dimension switching twiddle factor to obtain a second round of multiplication calculation results;

[0034] The second round of multiplication calculation results are transmitted to the pipeline number theory transformation unit until the pipeline is filled, the output result of each cycle of the pipeline number theory transformation unit is obtained, and according to the address signal, it is written back to the original position of the coefficient storage through the multiplexer.

[0035] In some embodiments, the calculation of the third round of number theory transformation includes:

[0036] Obtaining the calculation result of the second round of number theory transformation based on the coefficient storage;

[0037] Based on each clock cycle, according to the address signal, transmitting the result of the second round of number theory transformation calculation to the modular multiplier group through the multiplexer to multiply it with the dimension switching twiddle factor to obtain a third round of multiplication calculation result;

[0038] The third round of multiplication calculation results are transmitted to the pipeline number theory transformation unit until the pipeline is full. The pipeline number theory transformation unit outputs the results in each cycle and writes them back to the original location of the coefficient storage through the multiplexer according to the address signal.

[0039] The embodiments of the present application include at least the following beneficial effects: The present application provides a hardware accelerator and a hardware acceleration method based on three-dimensional number theory transformation. The scheme uses a computing component to successively receive address signals, control signals, polynomial coefficients and dimension switching rotation factors to perform three-dimensional number theory transformation. The three-dimensional number theory transformation algorithm can be implemented on-chip without conflict and without the need for additional hardware units. The use of the three-dimensional number theory transformation algorithm simplifies the complex data dependencies between levels and is more suitable for scenarios with large-dimensional polynomial multiplication. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 1 is a schematic diagram of the structure of a hardware accelerator based on three-dimensional number theory transformation provided in an embodiment of the present application;

[0041] Figure 2 This is a schematic diagram of the steps of a hardware acceleration method for a hardware accelerator based on three-dimensional number theory transformation provided by an embodiment of the present application;

[0042] Figure 3 Schematic diagram of the structure of the pipeline number theory transformation unit provided in an embodiment of the present application;

[0043] Figure 4 This is a schematic diagram of storage access for the first round of number theory transformation in the three-dimensional number theory transformation provided by an embodiment of the present application;

[0044] Figure 5 1 is a schematic diagram of storage access for the second round of number theory transformation in the three-dimensional number theory transformation provided by an embodiment of the present application;

[0045] Figure 6 This is a schematic diagram of storage access for the third round of number theory transformation in the three-dimensional number theory transformation provided in an embodiment of the present application.

[0046] Figure numerals: 1. butterfly unit; 2. first first-in-first-out memory; 3. second first-in-first-out memory; 4. first multiplexer; 5. second multiplexer. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are merely examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0048] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0049] The terms "at least one", "plurality", "each", "any", etc. used in this application include "at least one", "two" or more, "plurality" or "each", "any" or "any one", "each" or "any one" as used herein.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0051] First of all, it needs to be pointed out that the number theory transform is an important calculation unit in the polynomial multiplication based on the polynomial ring, which can reduce the calculation complexity of the polynomial multiplication, and has important significance in the large dimension polynomial multiplication. In recent years, the cryptographic schemes that attract widespread attention in cryptography involve many large dimension polynomial multiplications based on the polynomial ring, such as homomorphic encryption, zero-knowledge proof, etc. These encryption schemes need to involve the design of the number theory transform.

[0052] The mainstream hardware architecture of the number theory transform can be divided into iterative structure and pipeline structure. The iterative structure instantiates multiple parallel processing units, and allocates a memory block to each processing unit to calculate the butterfly operation of the same level of the number theory transform. By iteratively using these processing units, the butterfly operation of all levels can be completed in turn. In the large polynomial dimension, the iterative structure will bring complex inter-level data dependency relationship and increase of control logic overhead, and high memory bandwidth requirement. The pipeline structure realizes full pipeline calculation between levels by fully expanding the number theory transform. However, this structure can only produce one or two outputs per cycle, and the throughput is not high.

[0053] The multi-dimensional number theory transform regards the one-dimensional polynomial coefficient vector as a multi-dimensional tensor, and decomposes the large point number theory transform into a series of independent small point number theory transforms for each dimension of the tensor. In this way, the same set of small point number theory transform calculation components can be reused to realize the multi-dimensional number theory transform. The reduction of the calculation component dimension simplifies the complex inter-level data dependency relationship, and makes the multi-dimensional number theory transform more suitable for the scenario of large dimension polynomial multiplication. However, the conversion from the one-dimensional vector to the multi-dimensional tensor brings more complex storage access, which generally requires additional hardware units, such as a transpose unit.

[0054] In the related art, some deficiencies exist, such as the need for additional hardware units and the frequent interaction between off-chip and on-chip, which leads to performance degradation.

[0055] Therefore, in the embodiments of the present application, a hardware accelerator based on three-dimensional number theory transform is provided. By adopting the three-dimensional number theory transform algorithm, the complex inter-level data dependency relationship is simplified, and the hardware accelerator is more suitable for the scenario of large dimension polynomial multiplication. The calculation component adopts a multi-group pipeline number theory transform structure, and the calculation component and the on-chip storage interact regularly. By regularly storing the polynomial coefficients in the on-chip storage and regularly reading and writing the on-chip storage, the three-dimensional number theory transform algorithm can be completed on the hardware without conflict, and without introducing any additional hardware units.

[0056] Reference Figure 1 , Figure 1 The flowchart of the hardware accelerator based on the three-dimensional number theory transform provided in the embodiments of the present application is shown in FIG. 1. Figure 1The hardware accelerator includes a control unit, a coefficient storage, a dimension switching rotation factor storage, and a calculation component, wherein a first output terminal of the control unit is connected to a first input terminal of the coefficient storage, a second output terminal of the control unit is connected to a first input terminal of the dimension switching rotation factor storage, a third output terminal of the control unit is connected to a first input terminal of the calculation component, an output terminal of the coefficient storage is connected to a second input terminal of the calculation component, an output terminal of the dimension switching rotation factor storage is connected to a third input terminal of the calculation component, a first output terminal of the calculation component is connected to a second input terminal of the calculation component, and a second output terminal of the calculation component is connected to a third input terminal of the calculation component, wherein:

[0057] like Figure 1 As shown, the hardware accelerator of an embodiment of the present invention comprises four parts: a control unit, a coefficient storage, a dimension switching twiddle factor storage, and a computational unit. The control logic in the control unit provides control signals to the address generation logic and various components, and the address generation logic generates the correct address signals. The coefficient storage and dimension switching twiddle factor storage provide the required polynomial coefficients and dimension switching twiddle factors for the computational unit, and exchange data with the computational unit via a multiplexer. The core of the computational unit is a series of pipelined number-theoretic transformation units, each equipped with two modular multipliers to perform the twiddle factor dot multiplication required for dimension switching. These computational units are reused to perform each round of small-point number-theoretic transformation in the three-dimensional number-theoretic transformation. The overall structure accepts externally provided n, m, and mode as inputs. Mode controls the operation mode between number-theoretic transformation and inverse number-theoretic transformation, while n and m dynamically configure the polynomial dimension. n is fixed at compile time and is the highest polynomial dimension supported by the pipelined number-theoretic transformation unit, while m can be changed at runtime and is a power of 2 or less. We set N = n × n × m, fixing the dimension of the second and third rounds of number-theoretic transformations at n, and dynamically adjusting the dimension of the first round of number-theoretic transformations to m. This structure supports a dynamic configurability range from n × n × 1 to n × n × n, sufficient to support most application scenarios.

[0058] The control unit is used to generate address signals and control signals;

[0059] Specifically, the control unit includes a control logic unit and an address generation unit, wherein the output end of the control logic unit is connected to the input end of the address generation unit, wherein the control logic unit is used to generate a control signal; and the address generation unit is used to generate an address signal.

[0060] In a specific embodiment of the present invention, the input control signal of the control logic unit includes a first logic input control signal, a second logic input control signal and a third logic input control signal. The first logic input control signal and the second logic input control signal are used to dynamically configure the dimension of the polynomial coefficients. The third logic input control signal is used to control the working mode of the computing component. The working mode of the computing component includes a number theory transformation mode and an inverse number theory transformation mode.

[0061] Coefficient storage is used to generate polynomial coefficients;

[0062] Specifically, the coefficient storage and calculation components, and the dimension switching rotation factor storage and calculation components are connected through a plurality of multiplexers.

[0063] The dimension switching rotation factor storage is used to generate the dimension switching rotation factor;

[0064] The computing component is used to successively receive address signals, control signals, polynomial coefficients and dimension switching rotation factors to perform three-dimensional number theory transformation and output the transformation access results.

[0065] Specifically, the computing component includes several pipeline number theory transformation units, and each of the pipeline number theory transformation units is provided with a modular multiplier group, which is used to perform the point multiplication of the rotation factors required for dimension switching.

[0066] Among them, the pipeline number theory transformation unit includes a butterfly unit 1, a first first-in first-out memory 2, a second first-in first-out memory 3, a first multiplexer 4 and a second multiplexer 5. The butterfly unit is used to perform butterfly calculations and dynamically control the working mode of the calculation component according to the third logic input control signal; the first first-in first-out memory and the second first-in first-out memory are used to store data generated by the butterfly unit calculation; the first multiplexer and the second multiplexer are used to transmit data.

[0067] Specifically, the pipelined number theory transformation unit of the embodiment of the present invention is improved based on the multi-path delay commutator (MDC) structure, such as Figure 3 As shown. For n-point number theoretic transformation, the pipeline has log2n processing units. Each processing unit consists of a butterfly unit, two first-in first-out memories, and two multiplexers, where the depth of the first-in first-out memories varies with the stage to provide the required access step size. Our butterfly unit can support both Cooley-Tukey and Gentleman-Sande butterflies. By utilizing this butterfly unit design and dynamically switching the connections between the processing units, our pipeline number theoretic transformation unit can support dynamic switching between number theoretic transformation / inverse number theoretic transformation modes. In addition, by skipping certain stages of the pipeline, our pipeline number theoretic transformation unit can support any power of 2 m (≤n).

[0068] See also Figure 2 The present application also provides a hardware acceleration method for a hardware accelerator based on three-dimensional number theory transformation, which can implement the above-mentioned hardware accelerator based on three-dimensional number theory transformation. The method includes:

[0069] S100, obtaining address signals and control signals;

[0070] S200, storing the one-dimensional polynomial coefficient tensor in the coefficient storage according to the coefficients of each kj plane in the order of increasing index i and combining the address signal and the control signal to obtain the polynomial coefficient;

[0071] S300, obtaining a dimension switching rotation factor;

[0072] S400, performing a first round of number theory transformation calculations in a pipeline manner based on the polynomial coefficients and in combination with the address signal and the control signal, obtaining the first round of number theory transformation calculation results, and storing them back in the coefficient storage;

[0073] Specifically, the polynomial coefficients are stored in the coefficient storage according to the address signal and the control signal; based on each clock cycle, the polynomial coefficients in the coefficient storage are transmitted to the pipeline number theory transformation unit through the multiplexer according to the address signal; until the pipeline is filled, the output result of each cycle of the pipeline number theory transformation unit is obtained, and according to the address signal, it is written back to the original position of the coefficient storage through the multiplexer.

[0074] In the embodiment of the present invention, the polynomial coefficients are as follows: Figure 4 The method shown is stored in eight memory blocks for coefficient storage. Each clock cycle, following a specific address pattern and supplemented by multiplexer selections, it provides the required input to four pipelined number-theoretic transform units. Once the pipeline is full, the four pipelined number-theoretic transform units output eight results per cycle, which are then written back to the original locations of the coefficient storage using the same pattern.

[0075] The specific rules are similar in each kj plane. Taking the i=0 plane as an example, the addresses of the eight memory blocks are initialized to 0, and the addresses are incremented by 1 at each clock.

[0076] S500: Obtain the calculation result of the first round of number theory transformation, combine the address signal, the control signal and the dimension switching rotation factor, perform the calculation of the second round of number theory transformation in a pipeline manner, obtain the calculation result of the second round of number theory transformation, and store it back in the coefficient storage;

[0077] Specifically, the calculation results of the first round of number theoretic transformation are obtained based on the coefficient storage; based on each clock cycle, according to the address signal, the calculation results of the first round of number theoretic transformation are transmitted to the modular multiplier group through the multiplexer for multiplication with the dimension switching rotation factor to obtain the second round of multiplication calculation results; the second round of multiplication calculation results are transmitted to the pipeline number theoretic transformation unit until the pipeline is filled, and the output result of each cycle of the pipeline number theoretic transformation unit is obtained, and according to the address signal, it is written back to the original position of the coefficient storage through the multiplexer.

[0078] In the embodiment of the present invention, since the coefficients are written back to their original locations according to the same rule, the result of the first round of number theory transformation will be as follows: Figure 5 The method shown is stored in eight memory blocks for coefficient storage. Each clock cycle, following a specific address pattern and supplemented by multiplexer selections, the required inputs are provided to four pipelined number-theoretic transform units. Once the pipeline is full, the four pipelined number-theoretic transform units output eight results per cycle, which are then written back to the original locations of the coefficient storage using the same pattern.

[0079] The specific pattern is similar across all kj planes. For example, in plane i = 0, the addresses of memory blocks 0, 1, 4, and 5 are initialized to 0 and increment by m / 4 each clock cycle. The addresses of memory blocks 2, 3, 6, and 7 are initialized to m / 4, decrease by m / 4 in the next cycle, and then increase by 3m / 4 in the next cycle, forming a cyclic pattern.

[0080] S600: Obtain the calculation result of the second round of number theory transformation, combine the address signal, control signal and dimension switching rotation factor, perform the calculation of the third round of number theory transformation in a pipeline manner, obtain the calculation result of the third round of number theory transformation, and store it back to the coefficient storage.

[0081] Specifically, the calculation results of the second round of number theoretic transformation are obtained based on the coefficient storage; based on each clock cycle, according to the address signal, the calculation results of the second round of number theoretic transformation are transmitted to the modular multiplier group through the multiplexer to be multiplied with the dimension switching rotation factor to obtain the third round of multiplication calculation results; the third round of multiplication calculation results are transmitted to the pipeline number theoretic transformation unit until the pipeline is filled. The pipeline number theoretic transformation unit outputs the result in each cycle and writes it back to the original position of the coefficient storage through the multiplexer according to the address signal.

[0082] In the embodiment of the present invention, since the coefficients are written back to their original locations according to the same rule, the result of the second round of number theory transformation will be as follows: Figure 6The method shown is stored in eight memory blocks for coefficient storage. Each clock cycle, following a specific address pattern and supplemented by multiplexer selections, the required inputs are provided to four pipelined number-theoretic transform units. Once the pipeline is full, the four pipelined number-theoretic transform units output eight results per cycle, which are then written back to the original locations of the coefficient storage using the same pattern.

[0083] Unlike the previous two number-theoretic transformations, this one operates on the ji plane, and the specific rules are similar across all ji planes. Taking the k = 0 plane as an example, the addresses of memory blocks 0, 2, 4, and 6 are initialized to 0, and the addresses of memory blocks 1, 3, 5, and 7 are initialized to m*n / 2. Each clock cycle, the addresses of all eight memory blocks increase by m*n / 8.

[0084] Furthermore, we would like to explain that the embodiment of the present invention proposes a conflict-free on-chip memory access mode. By adjusting the memory read and write addresses in each cycle and using a multiplexer to perform data exchange between coefficient storage and calculation components, the additional hardware units are cleverly avoided. Taking the number theory transformation of N = 256 points as an example, we take the one-dimensional polynomial coefficient vector a of length N l ,l∈[0,N) is decomposed into a tensor a of n×n×m (n=8,m=4) ijk , i∈[0,n),j∈[0,n),k∈[0,m). The tensor is stored in the coefficient storage in the order of increasing index i for each kj plane. For each kj plane, the columns with j=0,...,n / 2-1 are placed in storage blocks 0-3, while the columns with j=n / 2,...,n-1 are placed in storage blocks 4-7. The coefficients of each column are interleaved between different storage blocks at different clock cycles to facilitate subsequent on-chip storage access.

[0085] Further, if Figure 4 、 Figure 5 and Figure 6 The figure shows the memory access of three rounds of number theory transformation. Each figure selects two different planes in the step, where each plane marks the first two clock cycles, corresponding to t0, t1 and t′0, t′1 in the figure. Specifically, Figure 4 and 5 The i=0,4 plane is selected, and Figure 6The k = 0, 1 plane is selected. Using four pipelined number-theoretic transform units, we can execute four small-point number-theoretic transforms in parallel. Each clock cycle, the coefficient storage regularly supplies eight data points to the pipelined number-theoretic transform units. After the pipeline is fully filled, the pipelined number-theoretic transform units replace the eight output data points in-place into the coefficient storage according to the same pattern each clock cycle. The color of the coefficients in the coefficient storage corresponds to the four pipelined number-theoretic transform units. Coefficients are regularly sent to different pipelined number-theoretic transform units at different clock cycles.

[0086] The three rounds of number theory transformations have different rules, which are reflected in the coefficient storage read and write addresses in each clock cycle, as well as the data switching achieved by the multiplexer. The first and second rounds of number theory transformations are performed in the kj plane in the order of index i, and each kj plane shows similar rules. Taking the i=0 plane as an example, Figure 4 and 5 As shown, in the first round of number theory transformation, the addresses of the eight storage blocks are initialized to 0 and incremented by 1 in each clock cycle. In the second round of number theory transformation, the addresses of storage blocks 0, 1, 4, and 5 are initialized to 0 and incremented by m / 4 in each clock cycle, while the initial addresses of storage blocks 2, 3, 6, and 7 are m / 4, and decrease by m / 4 in the next cycle, and then increase by 3m / 4 in the next cycle, showing a cyclic pattern. The third round of number theory transformation is performed in the ji plane according to the index k order. Address access needs to span multiple kj planes. Taking the k=0 plane as an example, as shown in Figure 6 As shown, the addresses of even-numbered memory blocks are initialized to 0, while the initial addresses of odd-numbered memory blocks are n×m / 2. With each clock cycle, the addresses of all eight memory blocks increase by n×m / 8. This regular address change, combined with a multiplexer to swap readout data, allows for conflict-free completion of each step of the three-dimensional number theory transformation without the need for additional hardware.

[0087] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0088] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A hardware acceleration method for a hardware accelerator based on three-dimensional number theory transformation, characterized in that: The method comprises the following steps: Get address signals and control signals; The one-dimensional polynomial coefficient tensor is calculated based on the The coefficients of the plane are indexed storing the polynomial coefficients in increasing order into a coefficient storage and combining the address signal with the control signal to obtain polynomial coefficients; Get the dimension switching rotation factor; According to the polynomial coefficients and in combination with the address signal and the control signal, a first round of number theory transformation calculation is performed in a pipeline manner to obtain a first round of number theory transformation calculation result, and the result is stored back into the coefficient storage; Obtaining the result of the first round of number theory transformation calculation, combining the address signal, the control signal and the dimension switching rotation factor, performing the second round of number theory transformation calculation in a pipeline manner, obtaining the result of the second round of number theory transformation calculation, and storing it back into the coefficient storage; Obtain the calculation result of the second round of number theory transformation, combine the address signal, the control signal and the dimension switching rotation factor, perform the calculation of the third round of number theory transformation in a pipeline manner, obtain the calculation result of the third round of number theory transformation, and store it back to the coefficient storage.

2. The method according to claim 1, characterized in that The calculation of the first round of number theory transformation includes: storing the polynomial coefficients in the coefficient storage according to the address signal and the control signal; Based on each clock cycle, transmitting the polynomial coefficients stored in the coefficient storage to the pipeline number theory transformation unit through the multiplexer according to the address signal; After the pipeline is filled, the output result of each cycle of the pipeline number theory transformation unit is obtained and written back to the original position of the coefficient storage through the multiplexer according to the address signal.

3. The method according to claim 2, characterized in that The calculation of the second round of number theory transformation includes: Obtaining the calculation result of the first round of number theory transformation based on the coefficient storage; Based on each clock cycle, according to the address signal, transmitting the first round of number theory transformation calculation results to the modular multiplier group through the multiplexer to multiply them with the dimension switching twiddle factor to obtain a second round of multiplication calculation results; The second round of multiplication calculation results are transmitted to the pipeline number theory transformation unit until the pipeline is filled, the output result of each cycle of the pipeline number theory transformation unit is obtained, and according to the address signal, it is written back to the original position of the coefficient storage through the multiplexer.

4. The method according to claim 2, characterized in that The calculation of the third round of number theory transformation includes: Obtaining the calculation result of the second round of number theory transformation based on the coefficient storage; Based on each clock cycle, according to the address signal, transmitting the result of the second round of number theory transformation calculation to the modular multiplier group through the multiplexer to multiply it with the dimension switching twiddle factor to obtain a third round of multiplication calculation result; The third round of multiplication calculation results are transmitted to the pipeline number theory transformation unit until the pipeline is full. The pipeline number theory transformation unit outputs the results in each cycle and writes them back to the original location of the coefficient storage through the multiplexer according to the address signal.

5. A hardware accelerator based on three-dimensional number theory transformation, characterized in that: The hardware accelerator is applied to the hardware acceleration method according to any one of claims 1 to 4, and includes a control unit, a coefficient storage, a dimension switching rotation factor storage, and a calculation component, wherein a first output end of the control unit is connected to a first input end of the coefficient storage, a second output end of the control unit is connected to a first input end of the dimension switching rotation factor storage, a third output end of the control unit is connected to a first input end of the calculation component, an output end of the coefficient storage is connected to a second input end of the calculation component, an output end of the dimension switching rotation factor storage is connected to a third input end of the calculation component, a first output end of the calculation component is connected to a second input end of the calculation component, and a second output end of the calculation component is connected to a third input end of the calculation component, wherein: The control unit is used to generate an address signal and a control signal; The coefficient storage is used to generate polynomial coefficients; The dimension switching rotation factor storage is used to generate a dimension switching rotation factor; The computing component is used to sequentially receive the address signal, the control signal, the polynomial coefficients and the dimension switching rotation factor to perform a three-dimensional number theory transformation and output a transformation access result.

6. The hardware accelerator according to claim 5, characterized in that The control unit includes a control logic unit and an address generation unit, wherein the output end of the control logic unit is connected to the input end of the address generation unit, wherein: The control logic unit is used to generate the control signal; The address generating unit is configured to generate the address signal.

7. The hardware accelerator according to claim 6, characterized in that The input control signals of the control logic unit include a first logic input control signal, a second logic input control signal and a third logic input control signal. The first logic input control signal and the second logic input control signal are used to dynamically configure the dimensions of the polynomial coefficients. The third logic input control signal is used to control the working mode of the computing component. The working modes of the computing component include a number theoretic transformation mode and an inverse number theoretic transformation mode.

8. The hardware accelerator according to claim 5, characterized in that The coefficient storage and the calculation component, and the dimension switching rotation factor storage and the calculation component are both connected through a plurality of multiplexers.

9. The hardware accelerator according to claim 7, characterized in that: The computing component includes a plurality of pipelined number theory transformation units, and each of the plurality of pipelined number theory transformation units is provided with a modular multiplier group, and the modular multiplier group is used for performing the point multiplication of the rotation factors required for dimension switching.

10. The hardware accelerator according to claim 9, wherein: The pipeline number theory transformation unit includes a butterfly unit, a first first-in first-out memory, a second first-in first-out memory, a first multiplexer and a second multiplexer, wherein: The butterfly unit is used to perform butterfly calculation and dynamically control the working mode of the calculation component according to the third logic input control signal; The first first-in first-out memory and the second first-in first-out memory are used to store data generated by the butterfly unit calculation; The first multiplexer and the second multiplexer are used for transmitting data.

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