Gate drive circuit and display device

Abstract

The present disclosure provides a kind of gate drive circuit and display device, belong to display technical field, it can solve the problem of the difference of the output signal of clock signal corresponding different positions in the shift register in the existing gate drive circuit is larger, influence display effect.The gate drive circuit of the present disclosure comprises: clock signal line and cascaded multiple shift registers;Clock signal line is connected with multiple shift registers, and transmits clock signal to multiple shift registers;Clock signal line includes: first clock signal line;First clock signal line has opposite first end and second end, and signal input end;The resistance between signal input end and first end or second end is less than the resistance between first end and second end.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a gate driving circuit and a display device. BACKGROUND

[0002] With the continuous development of display technology, the development of display in recent years gradually presents a development trend of high integration and low cost. One of the very important technologies is the realization of mass production of array substrate row driving (Gate Driver on Array, GOA) technology. The gate switch circuit composed of thin film transistors (Thin Film Transistor, TFT) is integrated on the array substrate of the display panel to form the scanning driving of the display panel, so that the gate driving integrated circuit part can be omitted. It not only can reduce the product cost from the aspects of material cost and manufacturing process, but also the display panel can be designed to be symmetrical and narrow frame. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a gate driving circuit and a display device.

[0004] In a first aspect, the embodiments of the present disclosure provide a gate driving circuit, comprising: a clock signal line and a plurality of shift registers in cascade; the clock signal line is connected with the plurality of shift registers and transmits a clock signal to the plurality of shift registers; the clock signal line comprises: a first clock signal line; the first clock signal line has opposite first and second ends and a signal input end;

[0005] The resistance between the signal input end and the first end or the second end is less than the resistance between the first end and the second end.

[0006] In some embodiments, the signal input end is located between the first end and the second end.

[0007] In some embodiments, the first end and the second end are both used as the signal input end.

[0008] In some embodiments, the clock signal line further comprises: a second clock signal line; the second clock signal line has opposite third and fourth ends;

[0009] The third end is connected with the first end, and the fourth end is connected with the second end.

[0010] The first end or the second end is used as the signal input end.

[0011] In some embodiments, the clock signal line further comprises: a second clock signal line; the second clock signal line has opposite third and fourth ends;

[0012] the third end is connected to the first end; and the fourth end is connected to the second end;

[0013] the signal input end is located between the first and second ends.

[0014] In some embodiments, the clock signal line further comprises: a second clock signal line; the second clock signal line has opposite third and fourth ends;

[0015] the third end is connected to the first end; and the fourth end is connected to the second end;

[0016] the first and second ends are both used as the signal input end.

[0017] In some embodiments, a plurality of first connection points are provided between the first and second ends; a plurality of second connection points are provided between the third and fourth ends; and the first connection points are connected to the second connection points one by one.

[0018] In some embodiments, the clock signal line further comprises: a second clock signal line; the second clock signal line has opposite third and fourth ends;

[0019] the third end is connected to the first end; or the fourth end is connected to the second end;

[0020] a plurality of first connection points are provided between the first and second ends; a plurality of second connection points are provided between the third and fourth ends; and the first connection points are connected to the second connection points one by one.

[0021] the first or second end is used as the signal input end.

[0022] In some embodiments, the shift register comprises: an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit;

[0023] the input sub-circuit is configured to respond to an input signal of a signal input end and write the input signal to a pull-up node;

[0024] the output sub-circuit is configured to respond to a potential of the pull-up node and output a clock signal input by a clock signal line through a signal output end;

[0025] the pull-up reset sub-circuit is configured to respond to a pull-up reset signal input by a pull-up reset signal end and reset the potential of the pull-up node by a non-working level signal.

[0026] In some embodiments, the signal output end of the mth shift register is connected to the signal input end of the m+i th shift register;

[0027] The pull-up reset signal end of the nth shift register is connected to the signal output end of the n-j th shift register; m, n, i, j are all positive integers.

[0028] In a second aspect, the embodiments of the present disclosure provide a display device, which comprises the gate drive circuit provided in the above. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 It is a structural schematic diagram of an exemplary shift register.

[0030] Figure 2 It is a structural schematic diagram of an exemplary gate drive circuit.

[0031] Figure 3 It is a structural schematic diagram of a first gate drive circuit provided by the embodiments of the present disclosure.

[0032] Figure 4 It is a structural schematic diagram of a second gate drive circuit provided by the embodiments of the present disclosure.

[0033] Figure 5 It is a structural schematic diagram of a third gate drive circuit provided by the embodiments of the present disclosure.

[0034] Figure 6 It is a structural schematic diagram of a fourth gate drive circuit provided by the embodiments of the present disclosure.

[0035] Figure 7 It is a structural schematic diagram of a fifth gate drive circuit provided by the embodiments of the present disclosure.

[0036] Figure 8 It is a structural schematic diagram of a sixth gate drive circuit provided by the embodiments of the present disclosure.

[0037] Figure 9 It is a structural schematic diagram of a seventh gate drive circuit provided by the embodiments of the present disclosure.

[0038] Figure 10 It is a structural schematic diagram of an eighth gate drive circuit provided by the embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure will be further described in detail below in combination with the drawings and specific embodiments.

[0040] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person having ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" do not denote a quantity restriction, but mean that there is at least one. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0041] It should be noted that the transistors used in the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, the source and drain are not distinguished. In the embodiments of the present disclosure, one of the poles is referred to as the first pole, the other pole is referred to as the second pole, and the gate is referred to as the control pole. In addition, the transistors can be divided into N-type and P-type according to their characteristics. In the following embodiments, N-type transistors are used for illustration. When N-type transistors are used, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and the gate is inputted with a high level, so that the source and drain are turned on. The P-type is the opposite. It is conceivable that P-type transistors can be easily thought of by those skilled in the art without creative labor, and therefore are within the protection scope of the embodiments of the present disclosure.

[0042] In the embodiments of the present disclosure, since the transistors used are N-type transistors, the working level signal in the embodiments of the present disclosure refers to the high level signal, and the non-working level signal is the low level signal. Correspondingly, the working level end is the high level signal end, and the non-working level end is the low level signal end.

[0043] Generally, a display panel includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are arranged in a cross manner to define a plurality of pixel regions, and each pixel region is provided with a pixel unit. Taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example, the structure of the display panel is described. When driving the display panel to display, a scanning signal can be written into the gate lines row by row according to the to-be-displayed picture, and a data voltage signal is written into each data line at the same time, so that the pixel units in the display panel are lit row by row.

[0044] The scan signal is provided by a gate driving circuit, and the data voltage signal is provided by a source driving circuit. In the related art, the gate driving circuit can be integrated in a gate driving chip, and the source driving circuit can be integrated in a source driving chip. Currently, in order to reduce the number of chips and achieve a narrow frame or no frame, a technology of integrating the gate driving circuit on an array substrate (Gate Driver on Array, GOA) is provided. The gate driving circuit includes a plurality of cascaded shift registers integrated on the array substrate. Each shift register is connected to a gate line in one-to-one correspondence, and is configured to provide a scan signal for the gate line connected thereto.

[0045] In order to more clearly illustrate how the shift register implements the output of the scan signal, the following describes the shift register in combination with a specific example.

[0046] Figure 1 For an exemplary structure diagram of a shift register, as shown in Figure 1 The shift register includes an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit. The input sub-circuit is configured to respond to an input signal input by a signal input end INPUT and write the input signal to a pull-up node PU to charge the pull-up node PU. The output sub-circuit is configured to respond to a potential of the pull-up node PU and output a clock signal input by a clock signal line CLK through a signal output end OUTPUT. The pull-up reset sub-circuit is configured to respond to a pull-up reset signal output by a pull-up reset signal end RESET_PU and reset the potential of the pull-up node PU through a low-level signal.

[0047] Specifically, as shown in Figure 1 The output sub-circuit includes a first transistor M1. The pull-up reset sub-circuit includes a second transistor M2. The output sub-circuit includes a third transistor M3 and a storage capacitor C. The gate and source of the first transistor M1 are connected to the signal input end INPUT, and the drain is connected to the pull-up node PU. The gate of the second transistor M2 is connected to the pull-up reset signal end RESET_PU, the source is connected to the pull-up node PU, and the drain is connected to a low-level signal end VGL. The gate of the third transistor M3 is connected to the pull-up node PU, the source is connected to the clock signal line CLK, and the drain is connected to the signal output end OUTPUT. The first end of the storage capacitor C is connected to the pull-up node PU, and the second end is connected to the signal output end OUTPUT.

[0048] It should be noted that after the pull-up node PU is reset in the reset phase, the pull-up node PU is at a low level. At this time, the third transistor M3 is turned off, and the signal output end OUTPUT is no longer output, so as to complete the reset of the signal output end OUTPUT.

[0049] As Figure 1As shown, the shift register further comprises: a first pull-down control sub-circuit, a second pull-down control sub-circuit, a first pull-down sub-circuit, a second pull-down sub-circuit, a first noise reduction sub-circuit, a second noise reduction sub-circuit, a pull-down sub-circuit, a first auxiliary sub-circuit, a second auxiliary sub-circuit, and a cascade sub-circuit. The pull-down sub-circuit is responsive to a frame start signal input by a frame start signal terminal STV and discharges the pull-up node PU through a low level input by a low level signal terminal VGL. The first pull-down control sub-circuit and the second pull-down control sub-circuit have the same structure and function, and only work at different times. Similarly, the first pull-down sub-circuit and the second pull-down sub-circuit have the same structure and function. The first auxiliary sub-circuit and the second auxiliary sub-circuit have the same structure and function. The first noise reduction sub-circuit and the second noise reduction sub-circuit have the same structure and function. The input sub-circuit, the output sub-circuit, and the pull-up reset sub-circuit have the same structure and function as described above, and thus will not be repeated here.

[0050] The first auxiliary sub-circuit and the second auxiliary sub-circuit are configured to be responsive to an input signal input by a signal input terminal INPUT and respectively pull down the potential of the first pull-down node PD1 and the potential of the second pull-down node PD2 through a low level signal. The first pull-down control sub-circuit is configured to be responsive to a first power voltage input by a first power voltage signal terminal VDDO to control the potential of the first pull-down node PD1. The second pull-down control sub-circuit is configured to be responsive to a second power voltage input by a second power voltage signal terminal VDDE to control the potential of the second pull-down node PD2. The first pull-down sub-circuit is configured to be responsive to the potential of the pull-up node PU and pull down the potential of the first pull-down node PD1 and the first pull-down control node PD CN1 through a low level signal input by a low level signal terminal VGL. The second pull-down sub-circuit is configured to be responsive to the potential of the pull-up node PU and pull down the potential of the second pull-down node PD2 and the second pull-down control node PD CN2 through a low level signal input by a low level signal terminal VGL. The first noise reduction sub-circuit is configured to be responsive to the potential of the first pull-down node PD1 and reduce noise of a signal output by a signal output terminal OUTPUT through a low level signal input by a low level signal terminal VGL. The cascade sub-circuit is configured to be responsive to the potential of the pull-up node PU and output a clock signal input by a clock signal line CLK to other shift registers in cascade through a cascade signal output terminal OUT C.

[0051] It should be noted that the signals outputted by the cascade signal output end OUT C and the signal output end OUTPUT are the same, but two output ends are provided in the shift register unit, one is the signal output end OUTPUT connected with the gate line, and the other is the cascade signal output end OUT C used for cascade. The reason for separately providing the cascade sub-circuit is to reduce the load of the signal output end OUTPUT to avoid affecting the scanning signal outputted by the signal output end OUTPUT.

[0052] Specifically, as shown in Figure 1 The first pull-down control sub-circuit and the second pull-down control sub-circuit each include a fifth transistor and a ninth transistor; wherein the fifth transistors in the first pull-down control sub-circuit and the second control sub-circuit are represented by M5 and M5', respectively, and the ninth transistors are represented by M9 and M9', respectively. The first pull-down sub-circuit and the second pull-down sub-circuit each include a sixth transistor and an eighth transistor; wherein the sixth transistors in the first pull-down sub-circuit and the second pull-down sub-circuit are represented by M6 and M6', respectively, and the eighth transistors are represented by M8 and M8', respectively. The first noise reduction sub-circuit and the second noise reduction sub-circuit each include a tenth transistor, an eleventh transistor and a twelfth transistor; wherein the tenth transistors in the first noise reduction sub-circuit and the second noise reduction sub-circuit are represented by M10 and M10', respectively, and the eleventh transistors are represented by M11 and M11', respectively; the discharge sub-circuit includes a seventh transistor M7. The first auxiliary sub-circuit and the second auxiliary sub-circuit each include a sixteenth transistor, represented by M16 and M16', respectively.

[0053] The gate and source of the fifth transistor M5 are connected with the first power voltage terminal VDDO, and the drain is connected with the first pull-down control node PD CN1; the gate of the ninth transistor M9 is connected with the first pull-down control node PD CN1, the source is connected with the first power voltage terminal VDDO, and the drain is connected with the first pull-down node PD1; the gate and source of the fifth transistor M5' are connected with the second power voltage terminal VDDE, and the drain is connected with the second pull-down control node PD CN2; the gate of the ninth transistor M9' is connected with the second pull-down control node PD CN2, the source is connected with the second power voltage terminal, and the drain is connected with the first pull-down node PD1; the gate of the sixth transistor M6 is connected with the pull-up node PU, the source is connected with the first pull-down node PD1, and the drain is connected with the low-level signal terminal; the gate of the eighth transistor M8 is connected with the pull-up node PU, the source is connected with the first pull-down control node PD CN1, and the drain is connected with the low-level signal terminal VGL; the gate of the sixth transistor M6' is connected with the pull-up node PU, the source is connected with the second pull-down node PD2, and the drain is connected with the low-level signal terminal VGL; the gate of the eighth transistor M8' is connected with the pull-up node PU, the source is connected with the second pull-down control node PD CN2, and the drain is connected with the low-level signal terminal; the gate of the tenth transistor M10 is connected with the first pull-down node PD1, the source is connected with the pull-up node PU, and the drain is connected with the low-level signal terminal VGL; the gate of the eleventh transistor M11 is connected with the first pull-down node PD1, the source is connected with the signal output terminal OUTPUT, and the drain is connected with the low-level signal terminal VGL; the gate of the tenth transistor M10' is connected with the second pull-down node PD2, the source is connected with the pull-up node PU, and the drain is connected with the low-level signal terminal VGL; the gate of the eleventh transistor M11' is connected with the second pull-down node PD2, the source is connected with the signal output terminal OUTPUT, and the drain is connected with the low-level signal terminal; the gate of the seventh transistor M7 is connected with the frame opening signal terminal, the source is connected with the pull-up node PU, and the drain is connected with the low-level signal terminal VGL; the gate of the thirteenth transistor M13 is connected with the pull-up node PU, the source is connected with the clock signal line CLK, and the drain is connected with the cascade signal output terminal OUT C. The gate of the sixteenth transistor M16 is connected with the signal input terminal INPUT, the source is connected with the first pull-down node PD1, and the drain is connected with the low-level signal terminal. The gate of the sixteenth transistor M16' is connected with the signal input terminal INPUT, the source is connected with the second pull-down node PD2, and the drain is connected with the low-level signal terminal VGL.

[0054] The fifth transistor M5 and the ninth transistor M9 constitute a first pull-down control sub-circuit, and the fifth transistor M5' and the ninth transistor M9' constitute a second pull-down control sub-circuit, which work in time division (i.e. alternately). Correspondingly, the first noise reduction sub-circuit composed of the tenth transistor M10 and the eleventh transistor M11 and the second noise reduction sub-circuit composed of the tenth transistor M10' and the eleventh transistor M11' are controlled by the first pull-down control sub-circuit and the second pull-down control sub-circuit respectively, so the first noise reduction sub-circuit and the second noise reduction sub-circuit also work in time division. The working principle of the first pull-down control sub-circuit and the second pull-down control sub-circuit is the same, and the working principle of the first noise reduction sub-circuit and the second noise reduction sub-circuit is the same. Therefore, the working principle of the shift register is described below when the first pull-down control sub-circuit and the first noise reduction sub-circuit work. It should be noted that, Figure 1 In the circuit structure shown, the low-level signal end VGL can also be represented as LVGL, which can provide a signal with a lower potential of the low-level signal end VGL, and can more fully pull down the potential of the corresponding point.

[0055] In the discharge phase, i.e. before display, a high-level signal is input to the frame start signal end STV, the seventh transistor M7 is turned on, and the low-level signal input by the low-level signal end VGL is used to discharge the pull-up node PU, so as to prevent residual charge of the pull-up node PU from causing display abnormalities.

[0056] In the input phase, a high-level signal is written to the signal input end INPUT, the first transistor M1 is turned on, the potential of the pull-up node PU is pulled up by the high-level signal, and the storage capacitor C is charged.

[0057] In the output phase, since the potential of the pull-up node PU is pulled up in the input phase, the third transistor M3 is turned on, and the high-level signal input by the clock signal line CLK is output to the gate line connected with the shift register through the signal output end OUTPUT.

[0058] In the reset phase, a high-level signal is input to the pull-up reset signal end RESET_PU, the second transistor M2 is turned on, and the potential of the pull-up node PU is pulled down by the low-level signal input by the low-level signal end VGL, so as to reset the pull-up node PU. Since the pull-up node PU is pulled down, the third transistor M3 is turned off, and the signal output end OUTPUT and the cascade signal output end OUT_C no longer output high-level signals. At the same time, the first pull-down control node PD_CN1 and the pull-down node are high-level signals, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the output of the pull-up node PU, the signal output end OUTPUT and the cascade signal output end OUT_C are noise reduced, until the potential of the pull-up node PU is pulled up at the beginning of the next frame scanning.

[0059] AsFigure 1 As shown, in order to reduce the load of the signal output terminal OUTPUT, the signal output by the signal output terminal OUTPUT is only used to control the gate line on and off. A cascade sub-circuit is also provided in the shift register; the cascade sub-circuit responds to the potential of the pull-up node PU and transmits the clock signal input by the clock signal line CLK through the cascade signal output terminal OUT_C. The cascade signal output terminal OUT_C ​​is the same as the signal output by the signal output terminal OUTPUT, that is, it outputs a high-level signal to the pull-up reset signal terminal RESET_PU of the other cascaded shift registers, as well as the signal input terminal INPUT of the other cascaded shift registers. Among them, the cascade sub-circuit includes a thirteenth transistor M13, the gate of the thirteenth transistor M13 is connected to the pull-up node PU, the source is connected to the clock signal line CLK, and the drain is connected to the cascade signal output terminal OUT_C. At the same time, a twelfth transistor is also provided in both the first noise reduction sub-circuit and the second noise reduction sub-circuit, represented by M12 and M12' respectively, for noise reduction of the signal output by the cascade signal output terminal OUT_C. The gate of the twelfth transistor M12 is connected to the first pull-down node PD1, the source is connected to the cascade signal output terminal OUT_C, and the drain is connected to the low-level signal terminal; the gate of the twelfth transistor M12' is connected to the second pull-down node PD2, the source is connected to the cascade signal output terminal OUT_C, and the drain is connected to the low-level signal terminal VGL.

[0060] It should be noted that the gate driving circuit and the display panel driven by the register may be a liquid crystal display panel or an organic light emitting diode display panel. The following description will take the liquid crystal display panel as an example.

[0061] Figure 2 is a schematic structural diagram of an exemplary gate drive circuit, such as Figure 2 As shown, the clock signal line CLK is a single line having a first end A and a second end B opposite to each other. The first end A is used as the signal input end In (the signal input end In here is Figure 1 The clock signal is input from the first terminal A to the second terminal B. As the distance increases, the resistance on the clock signal line CLK increases, and the load becomes larger, causing the clock signal difference to gradually increase. And the larger the size of the display panel, the greater the difference in the clock signal at both ends of the clock signal line CLK. This can easily lead to differences in the output signals of the shift registers corresponding to different positions of the clock signal line CLK (i.e., the scanning signals input to the pixel unit), and the greater the distance, the greater the difference. The difference in the output signals of the shift registers will cause the common voltage uniformity in the liquid crystal display panel to deteriorate, which may cause abnormalities in the display screen, such as uneven display, horizontal stripes, and other defects.

[0062] In order to solve at least one of the above technical problems, the embodiments of the present disclosure provide a gate driving circuit and a display panel. The gate driving circuit and the display panel provided by the embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0063] In a first aspect, an embodiment of the present disclosure provides a gate driving circuit, Figure 3 This is a schematic diagram of the structure of the first gate drive circuit provided by the embodiment of the present disclosure, as shown in FIG. Figure 3 As shown, the gate drive circuit includes: a clock signal line CLK and a plurality of cascaded shift registers (GOA1 to GOA2025); the clock signal line CLK is connected to the plurality of shift registers and transmits a clock signal to the plurality of shift registers; the clock signal line CLK includes: a first clock signal line CLK1; the first clock signal line CLK1 has a first end A and a second end B opposite to each other, and a signal input end In (the signal input end In here is connected to the Figure 1 the resistance between the signal input terminal In and the first terminal A or the second terminal B is less than the resistance between the first terminal A and the second terminal B.

[0064] The present disclosure is a gate drive circuit provided by an embodiment. When a clock signal is input to a signal input terminal In, the clock signal can be transmitted from the signal input terminal In to the first terminal A and the second terminal B. Since the resistance between the signal input terminal In and the first terminal A or the second terminal B is smaller than the resistance between the first terminal A and the second terminal B, the clock signal is transmitted more directly from the first terminal A to the second terminal B, and the resistance from the signal input terminal In to the first terminal A and the second terminal B can be reduced. Therefore, the difference in the output signals of the shift registers at different positions corresponding to the clock signal CLK can be reduced, thereby preventing the common voltage uniformity in the liquid crystal display panel from deteriorating, thereby avoiding abnormalities in the display screen, and further improving the display effect and enhancing the user experience.

[0065] In some embodiments, as Figure 3As shown, the signal input terminal In is located between the first terminal A and the second terminal B. Specifically, the signal input terminal In can be located at the midpoint of the first clock signal line CLK1, that is, the distance between the signal input terminal In and the first terminal A and the second terminal B is equal. The distance between the signal input terminal In and the first terminal A and the second terminal B is only half of the resistance of the entire first clock signal line CLK1. In this way, the resistance between the signal input terminal In and the first terminal A and the second terminal B is only half of the resistance of the entire first clock signal line CLK1. By more directly transmitting the clock signal from the first terminal A to the second terminal B, the resistance between the signal input terminal In and the first terminal A and the second terminal B can be reduced. Therefore, the difference in the output signals of the shift registers at different positions corresponding to the clock signal CLK can be reduced, preventing the common voltage uniformity in the liquid crystal display panel from deteriorating, thereby avoiding abnormal display images, and further improving the display effect and user experience.

[0066] Figure 4 This is a structural diagram of a second gate drive circuit provided by an embodiment of the present disclosure, such as Figure 4 As shown, the first terminal A and the second terminal B are both used as signal input terminals In.

[0067] The first end A and the second end B are both used as the signal input end In. The clock signal can be input simultaneously from the first end A and the second end B, that is, the clock signal is input simultaneously from both ends of the first clock signal CLK1. The clock signal does not have to be transmitted along the entire first clock signal line, thereby reducing the transmission distance of the clock signal. The clock signal is transmitted more directly from the first end A to the second end B, thereby reducing the resistance from the signal input end In to the first end A and the second end B. Therefore, the difference in the output signals of the shift registers at different positions corresponding to the clock signal CLK can be reduced, thereby preventing the common voltage uniformity in the liquid crystal display panel from deteriorating, thereby avoiding abnormalities in the display screen, and further improving the display effect and the user experience.

[0068] Figure 5 This is a schematic structural diagram of a third gate drive circuit provided in an embodiment of the present disclosure. Figure 6 This is a structural diagram of a fourth gate drive circuit provided by an embodiment of the present disclosure, such as Figure 5 and Figure 6 As shown, the clock signal line CLK further includes: a second clock signal line CLK2; the second clock signal line CLK2 has a third terminal C and a fourth terminal D opposite to each other; the third terminal C is connected to the first terminal A; the fourth terminal D is connected to the second terminal B; the first terminal A or the second terminal B is used as a signal input terminal In( Figure 5 The first terminal A is used as the signal input terminal In, Figure 6 The second terminal B is used as the signal input terminal In).

[0069] Figure 5 and Figure 6The gate drive circuit shown in Figure 3 and Figure 4 The difference between the gate drive circuit shown in Figure 3 and Figure 4 In the gate drive circuit shown in Figure 5 and Figure 6 In the gate drive circuit shown in

[0070] As shown in Figure 5 and Figure 6 The third end C is connected to the first end A, and the fourth end D is connected to the second end B, so that the first clock signal line CLK1 and the second clock signal line CLK2 are connected in parallel, which is equivalent to increasing the wiring width of the clock signal line CLK, thereby reducing the resistance of the entire clock signal line CLK, further reducing the difference between the output signals of the shift register corresponding to different positions of the clock signal CLK, preventing the common voltage uniformity in the liquid crystal display panel from deteriorating, thereby avoiding abnormal display of the display picture, and further improving the display effect and user experience.

[0071] Figure 7 The fifth gate drive circuit provided by the embodiment of the present disclosure is shown in the structural schematic diagram Figure 7 As shown in

[0072] Figure 7 The difference between the gate drive circuit shown in Figure 5 and Figure 6 The difference between the gate drive circuit shown in Figure 5 and Figure 6 In the gate drive circuit shown in Figure 7 In the gate drive circuit shown in

[0073] As shown in Figure 7As shown, the third end C is connected to the first end A; the fourth end D is connected to the second end B, so that the first clock signal line CLK1 and the second clock signal line CLK2 are connected in parallel, which is equivalent to increasing the routing width of the clock signal line CLK. At the same time, the signal input end In is located between the first end A and the second end B, reducing the transmission distance of the clock signal, thereby reducing the resistance of the entire clock signal line CLK, and further reducing the difference in the output signals of the shift registers at different positions corresponding to the clock signal CLK, thereby preventing the common voltage uniformity in the liquid crystal display panel from deteriorating, thereby avoiding abnormalities in the display screen, and further improving the display effect and enhancing the user experience.

[0074] Figure 8 This is a structural diagram of a sixth gate drive circuit provided by an embodiment of the present disclosure, such as Figure 8 As shown, the clock signal line CLK also includes: a second clock signal line CLK2; the second clock signal line CLK2 has a third end C and a fourth end D opposite to each other; the third end C is connected to the first end A; the fourth end D is connected to the second end B; the first end A and the second end B are both used as signal input ends In.

[0075] Figure 8 The gate drive circuit shown is Figure 5 and Figure 6 The gate drive circuit shown differs in that Figure 5 and Figure 6 In the gate drive circuit shown, the first terminal A or the second terminal B is used as the signal input terminal In, and the clock signal is transmitted from the first terminal A to the second terminal B, or in the reverse direction. Figure 8 In the gate driving circuit shown, the first terminal A and the second terminal B are both used as signal input terminals In, and the clock signal can be input from the first terminal A and the second terminal B at the same time.

[0076] like Figure 8 As shown, the third end C is connected to the first end A; the fourth end D is connected to the second end B, so that the first clock signal line CLK1 and the second clock signal line CLK2 are connected in parallel, which is equivalent to increasing the routing width of the clock signal line CLK. At the same time, the first end A and the second end B are both used as signal input ends In, reducing the transmission distance of the clock signal, thereby reducing the resistance of the entire clock signal line CLK, and further reducing the difference in the output signals of the shift registers at different positions corresponding to the clock signal CLK, thereby preventing the common voltage uniformity in the liquid crystal display panel from deteriorating, thereby avoiding abnormalities in the display screen, and further improving the display effect and enhancing the user experience.

[0077] In some embodiments, as Figures 3 to 8As shown, a plurality of first connection points P are arranged between the first end A and the second end B; a plurality of second connection points Q are arranged between the third end C and the fourth end D; and the first connection points P and the second connection points Q are connected in one-to-one correspondence.

[0078] The first connection points P in the first clock signal line CLK1 are connected in one-to-one correspondence with the second connection points Q in the second clock signal line CLK2, which can increase the stability of the parallel structure formed between the first clock signal line CLK1 and the second clock signal line CLK2, further reduce the resistance of the entire clock signal line CLK, further reduce the difference between the output signals of the shift registers corresponding to different positions of the clock signal CLK, prevent the uniformity of the common voltage in the liquid crystal display panel from deteriorating, thereby avoiding abnormal display of the display screen, and further improving the display effect and the user experience.

[0079] Figure 9 A seventh structure diagram of a gate drive circuit is provided for the embodiments of the present disclosure, Figure 10 An eighth structure diagram of a gate drive circuit is provided for the embodiments of the present disclosure, as shown in Figure 9 and Figure 10 As shown, the clock signal line CLK further includes a second clock signal line CLK2; the second clock signal line CLK2 has an opposite third end C and a fourth end D; the third end C is connected with the first end A (as shown in Figure 9 ); or, the fourth end D is connected with the second end B (as shown in Figure 10 ); a plurality of first connection points P are arranged between the first end A and the second end B; a plurality of second connection points Q are arranged between the third end C and the fourth end D; the first connection points P and the second connection points Q are connected in one-to-one correspondence; the first end A or the second end B is used as a signal input end (In), Figure 9 the second end B is used as the signal input end (In) in Figure 10 the first end A is used as the signal input end (In).

[0080] Figure 9 and Figure 10 In the gate drive circuit shown, the first end A or the second end B in the first clock signal line CLK1 is disconnected, and the disconnected first end A or second end B is used as the signal input end (In), so that the signal input end (In) does not need to be separately arranged, the clock signal can be input from the middle position of the entire clock signal line CLK, the resistance can be reduced, the difficulty of the preparation process can be reduced, and the preparation cost can be saved.

[0081] In some embodiments, the structure of the shift register in the gate drive circuit is the same as that shown in Figure 1The structures of the illustrated gate drive circuits are the same, which include: an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit; the input sub-circuit is configured to respond to an input signal input by a signal input end INPUT and write the input signal to a pull-up node PU to charge the pull-up node PU; the output sub-circuit is configured to respond to a potential of the pull-up node PU and output a clock signal input by a clock signal line CLK through a signal output end OUTPUT; and the pull-up reset sub-circuit is configured to respond to a pull-up reset signal output by a pull-up reset signal end RESET_PU and reset the potential of the pull-up node PU through a low-level signal. The implementation principle is the same as that of the gate drive circuit in the above Figure 1 , and thus will not be described herein again.

[0082] In some embodiments, as shown in Figures 3 to 10 , a signal output end OUTPUT of an mth shift register is connected to a signal input end INPUT of an m+i th shift register; a pull-up reset signal end RESET_PU of an nth shift register is connected to a signal output end OUTPUT of an n-j th shift register; and m, n, i, and j are all positive integers.

[0083] In the gate drive circuit in Figures 3 to 10 , taking i and j as 1 as an example, the current shift register is cascaded with the next shift register, where the signal output end OUTPUT of the current shift register is connected to the signal input end INPUT of the next shift register, and the pull-up reset signal end RESET_PU of the current shift register is connected to the signal output end OUTPUT of the previous shift register.

[0084] It should be noted that in the gate drive circuit provided by the embodiments of the present disclosure, the number of clock signal lines CLK can be multiple, such as 2, 4, 8, 16, etc., where each clock signal line CLK can be set in the above manner to reduce the resistance and reduce the difference of the output signals of the shift registers corresponding to different positions of the clock signal CLK. Meanwhile, other signal lines are also provided in the gate drive circuit, such as a first power signal line and a second power signal line, which can be set in the manner in the related art, and thus will not be described herein again.

[0085] In a second aspect, the embodiments of the present disclosure provide a display device, which includes the gate drive circuit provided in any of the above embodiments. The display device can be a television, a mobile phone, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function. The implementation principle is similar to that of the display panel described above, and thus will not be described herein again.

[0086] It is understood that the above embodiments are only exemplary for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A gate drive circuit, characterized in that: The gate drive circuit includes: a clock signal line and a plurality of cascaded shift registers; the clock signal line is connected to the plurality of shift registers and transmits a clock signal to the plurality of shift registers; the clock signal line includes: a first clock signal line; the first clock signal line has a first end and a second end opposite to each other, and a signal input end; The resistance between the signal input terminal and the first terminal or the second terminal is smaller than the resistance between the first terminal and the second terminal; The clock signal line further includes: a second clock signal line; the second clock signal line has a third end and a fourth end opposite to each other; The third end is connected to the first end; and / or the fourth end is connected to the second end.

2. The gate drive circuit according to claim 1, wherein: The signal input terminal is located between the first terminal and the second terminal.

3. The gate drive circuit according to claim 1, wherein: The first terminal and the second terminal are both used as the signal input terminals.

4. The gate drive circuit according to claim 1, wherein: The first end or the second end is used as the signal input end.

5. The gate driving circuit according to claim 4, wherein: A plurality of first connection points are provided between the first end and the second end; a plurality of second connection points are provided between the third end and the fourth end; and the first connection points are connected to the second connection points in a one-to-one correspondence.

6. The gate driving circuit according to claim 1, wherein: The shift register comprises: an input subcircuit, an output subcircuit and a pull-up reset subcircuit; The input sub-circuit is configured to respond to an input signal at the signal input terminal and write the input signal into the pull-up node; The output sub-circuit is configured to respond to the potential of the pull-up node and output the clock signal input from the clock signal line through the signal output terminal; The pull-up reset subcircuit is configured to respond to a pull-up reset signal inputted from a pull-up reset signal terminal and reset the potential of the pull-up node through a non-working level signal.

7. The gate driving circuit according to claim 6, wherein: The signal output end of the mth shift register is connected to the signal input end of the m+ith shift register; The pull-up reset signal terminal of the nth shift register is connected to the signal output terminal of the njth shift register; m, n, i, and j are all positive integers.

8. A display device, characterized in that: The display device comprises the gate driving circuit according to any one of claims 1 to 7.

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