A memory and an operating method thereof

Abstract

Embodiments of the present application relate to the field of memory and provide a memory, comprising: a row address pre-decoding circuit, configured to receive an input row address and pre-decode the input row address; a same-segment repair judgment circuit, configured to determine whether a failed address and a redundant address replacing the failed address are in the same storage segment; a first output circuit, connected to the same-segment repair judgment circuit and the row address pre-decoding circuit, configured to receive a segment address obtained by pre-decoding the input row address from the row address pre-decoding circuit based on a determination result of the same-segment repair judgment circuit, and output the segment address when the failed address and the redundant address replacing the failed address are in the same storage segment; and a sense amplifier, configured to perform a threshold voltage compensation operation on the storage segment pointed to by the segment address in response to the segment address.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a memory. Background Art

[0002] To improve memory yield, redundancy techniques (such as row redundancy) are used in memory chip design: if a word line on a chip fails during testing, the corresponding address can be redirected to a redundant word line, thereby reducing the yield drop caused by the word line failure. The failed address is stored in the chip via a non-volatile method such as a fuse or antifuse. When an activation command arrives, the row address carried in the command is compared with the address in the fuse or antifuse to determine whether the address needs to be repaired. However, this comparison process takes a certain amount of time. Summary of the Invention

[0003] The embodiments of the present application provide a memory that is at least beneficial for improving the timing of the row redundancy circuit and increasing the yield rate and high-quality rate of the memory.

[0004] According to some embodiments of the present application, an embodiment of the present application provides a memory, characterized by including:

[0005] A row address pre-decoding circuit is configured to receive an input row address and pre-decode the input row address;

[0006] a same-segment repair determination circuit configured to determine whether a failed address and a redundant address replacing the failed address are in the same storage segment;

[0007] a first output circuit connected to the same-segment repair judgment circuit and the row address pre-decoding circuit, and configured to receive, based on a judgment result of the same-segment repair judgment circuit, a segment address obtained by pre-decoding the input row address from the row address pre-decoding circuit when the failed address and the redundant address replacing the failed address are in the same storage segment, and output the segment address;

[0008] The sense amplifier is configured to perform a threshold voltage compensation operation on the memory segment pointed to by the segment address in response to the segment address.

[0009] According to some embodiments of the present application, another aspect of the present application further provides a memory operation method, characterized by comprising:

[0010] Determine whether the failed address and the redundant address that replaces the failed address are in the same storage segment;

[0011] When the failed address and the redundant address that replaces the failed address are in the same memory segment, the following operations are performed:

[0012] Receive input row address;

[0013] Pre-decode the input row address to obtain the segment address of the input row address;

[0014] performing a threshold voltage compensation operation on the memory segment pointed to by the segment address;

[0015] When the failed address and the redundant address that replaces the failed address are not in the same memory segment, the following operations are performed:

[0016] Receive input row address;

[0017] Pre-decoding the input row address to obtain the segment address of the input row address; at the same time, comparing the input row address with the failed address to determine whether to replace the input row address with a redundant address;

[0018] According to the comparison result, the segment address obtained by pre-decoding the input row address or the segment address of the redundant address is output as the segment address of the actual activation address;

[0019] A threshold voltage compensation operation is performed on the storage segment pointed to by the segment address of the actual activation address.

[0020] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0021] Reducing the time spent on redundant technology during word line activation helps reduce tRCD (RAS to CAS Delay, the delay between row address and column address). tRCD is the minimum number of clocks required between activating a row of memory and accessing the memory cells in a column coupled to the activated row of memory cells. Reducing tRCD can provide more margin for the memory device.

[0022] For chips with certain patterns in failed addresses, a conditional judgment circuit is set up according to the setting and allocation method of redundant resources. For chips that meet the conditions, the waiting time required for address comparison can be reduced, the timing of the row redundancy circuit can be improved, the minimum tRCD can be reduced, and the chip timing can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0024] Figure 1 A circuit framework diagram of a partial structure of a memory provided in one embodiment of the present application;

[0025] Figure 2 A circuit framework diagram of a single memory bank provided in one embodiment of the present application;

[0026] Figure 3 This is a layout diagram of some memory segments and a sense amplifier array in a memory cell provided by an embodiment of the present application;

[0027] Figure 4 A circuit diagram of a partial structure of a memory provided in one embodiment of the present application;

[0028] Figure 5 A circuit diagram of a partial structure of a memory provided in one embodiment of the present application;

[0029] Figure 6 A circuit diagram of a comparison unit provided in one embodiment of the present application;

[0030] Figure 7 A timing diagram corresponding to a memory operation provided in one embodiment of the present application. DETAILED DESCRIPTION

[0031] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways, all without departing from the spirit or scope of the present invention. For example, the exemplary embodiments provided herein are considered to be capable of being combined with each other in whole or in part to achieve this. Specifically, an element described in a particular exemplary embodiment, even if not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless a contrary or contradictory description is provided therein.

[0032] Throughout this specification, when any part is referred to as being “connected” to another part, this includes both the case where the part and the other part are “indirectly connected” to each other due to another part being interposed therebetween, and the case where the part and the other part are “directly connected” to each other. For example, it should be understood that when an element is referred to as being “connected” or “coupled” or “on” another element, it can be directly connected or coupled to or on the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as being “in contact with” or “in contact with” another element, there are no intervening elements at the point of contact.

[0033] Furthermore, "connected" conceptually includes both physical connections and physical disconnections. It will be understood that when terms such as "first" and "second" are used to refer to an element, the element is not limited thereto. They may serve only to distinguish the element from other elements and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

[0034] A row activation (ACT) includes the following process, after the ACT command and address enter the memory bank:

[0035] 1. The address is compared with the failed address information stored in the fuse / antifuse (fuse is used as an example below). If the address needs to be repaired, the corresponding redundant resource address is generated (at the same time, normal address pre-decoding is also performed synchronously, but address pre-decoding takes less time);

[0036] 2. Based on the comparison result, select one of the two options, "normal address pre-decoding" and "redundant resource address pre-decoding", and send it to the post-decoder (X-decoder, XDEC);

[0037] 3. Performing a threshold voltage compensation (offset cancellation, also called offset compensation) operation on the memory segment where the activated word line is located;

[0038] 4. Open the corresponding word line;

[0039] 5. ...

[0040] Step 3 only requires partial address information (segment address information, locating to a specific memory segment), while step 4 requires all address information (segment address information and intra-segment address information, locating to a specific word line). The address comparison process in row redundancy technology takes much longer than the time required for row address pre-decoding. In the existing technology, the subsequent operations of steps 3 and 4 must wait until the address comparison is completed.

[0041] If each failed address is repaired using redundant resources in the same segment, then step 3 does not need to wait for the comparison result in step 1. The segment address information can be directly obtained from the normal address pre-decoding to perform the threshold voltage compensation operation. Step 4 requires waiting for the comparison between the normal address and the fuse, but the time for step 3 can be brought forward accordingly and performed during the address comparison process, thereby improving the overall timing.

[0042] Therefore, the present application provides a memory and an operating method thereof, which uses a same-segment repair judgment circuit to determine whether a failed address is repaired using redundant resources in the same storage segment. If so, the timing of the threshold voltage compensation operation of the storage segment is advanced, and the segment address information is directly obtained from the normal address pre-decoding, and the threshold voltage compensation operation of the storage segment is performed in advance, thereby improving the timing of the row redundancy circuit, reducing the minimum tRCD, and thus improving the overall timing.

[0043] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0044] Figure 1 The circuit framework diagram of part of the structure in the memory is shown. After the command address signal (CA) enters the memory through the command address input port, it is sampled and transmitted by the command address input circuit, and the command signal is transmitted to the command decoder, and the address signal is transmitted to the address decoder. The address decoder can decode the address signal received from the command address input circuit, and provide the row address signal to the row decoder, the column address signal to the column decoder, and the memory control logic. The command decoder can decode the command signal and generate various internal command signals to provide to the row decoder and the column decoder. The internal command signal may include, for example, a row activation signal for selecting a word line, a column selection signal for selecting a bit line (such as a read command or a write command), etc. The memory control logic is used to select the row decoder or column decoder corresponding to a specific memory.

[0045] For example, when the memory receives a read command, it reads data from the memory cell specified by the row and column addresses. The read data is amplified by the read / write control logic, transmitted through the input / output circuit, and output from the input / output terminals.

[0046] When redundancy technology is used, when the memory is powered on, the information of the failed address (i.e., fuse data) stored in the fuse array is read from the non-volatile fuse array (or antifuse array) and compared one-to-one with the input address information. If the input address is a failed address, the corresponding redundant resources are used to replace the failed address.

[0047] Figure 1 The memory array shown in FIG includes a plurality of memory banks, and the memory banks correspond to the row decoders and the column decoders on a one-to-one basis. Figure 2The corresponding relationship between a single memory bank and the row decoder and column decoder is shown. After the row decoder decodes the row address, it activates a single word line; after the column decoder decodes the column address, it activates a single bit line to activate the memory cell specified by the row address and column address for data transmission.

[0048] In some embodiments, a memory includes a memory array and peripheral circuits. The memory array includes multiple memory banks, each memory bank includes multiple memory segments and multiple sense amplifier arrays, and the memory segments and sense amplifier arrays are alternately arranged along a first direction. For sense amplifier arrays located outside of an edge position, sense amplification is performed on the memory segments adjacent to each other along the first direction; for sense amplifier arrays located at an edge position, sense amplification is performed on the memory segments adjacent to each other along the first direction. Each sense amplifier array includes multiple sense amplifiers arranged along a second direction, and each sense amplifier is connected to two bit lines in an adjacent memory segment for sense amplification. The first direction and the second direction are perpendicular to each other.

[0049] Figure 3 The arrangement of some memory segments and sense amplifier arrays in the memory array is shown. Figure 3 A memory bank includes multiple memory segments, each memory segment includes multiple rows (each row is represented by a word line WL), and each memory segment includes multiple columns (each column is represented by a bit line BL). Using open bit lines as an example, a sense amplifier array is used to read half of the memory cells in two adjacent memory segments.

[0050] Repair is accomplished by remapping the addresses of failed rows or columns (or defective rows or columns) to redundant rows or columns. Existing redundancy repair technologies include same-segment repair and cross-segment repair. For same-segment repair, redundant resources are distributed across each storage segment, and the failed address is repaired using redundant resources within the same storage segment as the failed address. For example, a redundant row within the same storage segment as the failed row is used to repair the failed row. For cross-segment repair, redundant resources can be centrally located in one or several storage segments, and the redundant resources in one storage segment can be used to replace the failed address in another storage segment.

[0051] Due to factors such as manufacturing processes, voltage variations, and temperature changes, sense amplifier transistor pairs may be mismatched. Therefore, the sense amplifier's operation involves offset compensation (also known as threshold voltage compensation) for these mismatched transistors. Row activation is therefore divided into two phases. The first phase involves only the sense amplifiers, requiring only the location information corresponding to the memory segment to locate the required sense amplifier. The second phase requires locating the specific word line within the specific memory segment to activate that word line for data reading and writing.

[0052] Based on this, the present application provides a memory that uses a same-segment repair judgment circuit to determine whether a failed address is repaired using redundant resources in the same storage segment. If so, the timing of the threshold voltage compensation operation of the storage segment is advanced, and the segment address information is directly obtained from the normal address pre-decoding, and the threshold voltage compensation operation of the storage segment is performed in advance, thereby improving the timing of the row redundancy circuit, reducing the minimum tRCD, and thus improving the overall timing.

[0053] Specifically, in some embodiments, Figure 4 As shown, a memory includes:

[0054] A row address pre-decoding circuit is configured to receive an input row address and pre-decode the input row address;

[0055] a same-segment repair determination circuit configured to determine whether a failed address and a redundant address replacing the failed address are in the same storage segment;

[0056] a first output circuit connected to the same-segment repair judgment circuit and the row address pre-decoding circuit, and configured to receive, based on a judgment result of the same-segment repair judgment circuit, a segment address obtained by pre-decoding the input row address from the row address pre-decoding circuit when the failed address and the redundant address replacing the failed address are in the same storage segment, and output the segment address;

[0057] Sense Amplifier ( Figure 4 Not shown, reference Figure 3 ), configured to perform a threshold voltage compensation operation on the storage segment pointed to by the segment address in response to the segment address.

[0058] In some embodiments, the row decoder includes a pre-decoder Pre-DEC and a post-decoder XDEC. The pre-decoder includes the aforementioned row address pre-decoding circuit, which takes as input a row address (e.g., 16 bits) and pre-decodes a portion of the high-order address (e.g., bits 11-16) to obtain the corresponding segment address. The segment address obtained by the row address pre-decoding circuit can be directly sent to the memory bank or decoded by the post-decoder and transmitted to the memory bank, thereby activating the sense amplifier of the memory segment corresponding to the segment address and performing threshold voltage compensation.

[0059] In some embodiments, a same-segment repair judgment circuit receives a failed address and a redundant address that replaces the failed address, and compares the segment address information of the two to determine whether the failed address and the redundant address that replaces the failed address are in the same memory segment. For example, when the failed address and the redundant address that replaces the failed address have the same corresponding bits representing the segment address information (e.g., the upper 6 bits of a 16-bit sequence), it indicates that the failed address and the redundant address that replaces the failed address are in the same memory segment, and the same-segment repair judgment circuit can output a first selection signal of a first level. When the failed address and the redundant address that replaces the failed address are not in the same memory segment, the same-segment repair judgment circuit can output a first selection signal of a second level different from the first level. In some embodiments, since only the segment address information of the failed address and the segment address information of the redundant address that replaces the failed address are compared, the same-segment repair judgment circuit can also only receive the segment address information of the failed address and the segment address information of the redundant address that replaces the failed address, thereby saving circuit area and power consumption.

[0060] The first output circuit is connected to the row address pre-decoding circuit and receives the segment address obtained by pre-decoding the input row address. The first output circuit is also connected to the same-segment repair judgment circuit and receives the first selection signal. Based on the level of the first selection signal, the first output circuit determines whether to output the segment address obtained by pre-decoding the input row address in advance. For example, when the first output circuit receives the first selection signal at a first level, the first output circuit directly outputs the segment address obtained by pre-decoding the input row address. When the first output circuit receives the first selection signal at a second level, the first output circuit waits for a comparison result between the failed address and the input address, and then determines whether to perform redundant replacement based on the comparison result. The first output circuit outputs the segment address of the row address (including the segment address and the intra-segment address) that has been or has not been redundantly replaced, activates the sense amplifier of the storage segment corresponding to the address, and simultaneously outputs the intra-segment address corresponding to the segment address, activating the word line corresponding to the address.

[0061] In some embodiments, the first output circuit can be a selection circuit, for example, a multiplexer, wherein the control end receives a first selection signal, and the two input ends respectively receive the segment address obtained by pre-decoding the input row address, and the segment address of the row address that has been redundantly replaced or not redundantly replaced determined by the comparison result.

[0062] Therefore, the same-segment repair judgment circuit is used to determine whether the failed address is repaired using redundant resources in the same storage segment. If so, the timing of the threshold voltage compensation operation of the storage segment is advanced, and the segment address information is directly obtained from the normal address pre-decoding (that is, the input row address is pre-decoded). The threshold voltage compensation operation of the storage segment is performed in advance, the timing of the row redundancy circuit is improved, the minimum tRCD is reduced, and the overall timing is improved.

[0063] Specifically, as shown in Figure 5, the row address pre-decoding circuit may include an input row address pre-decoding circuit, a failed address comparison circuit, a redundant address mapping circuit, and a second output circuit;

[0064] The input row address pre-decoding circuit is configured to receive the input row address and pre-decode the input row address;

[0065] The failed address comparison circuit is configured to receive the input row address and determine whether the input row address is a failed address;

[0066] The redundant address mapping circuit is connected to the failed address comparison circuit and is configured to output a redundant address that replaces the failed address when the input row address is a failed address;

[0067] The second output circuit is connected to the input row address pre-decoding circuit, the failed address comparison circuit and the redundant address mapping circuit, and is configured to output the redundant address that replaces the failed address as the actual activation address when the failed address comparison circuit determines that the input row address is a failed address; otherwise, output the decoded input row address output by the input row address pre-decoding circuit as the actual activation address.

[0068] In some embodiments, the input row address pre-decoding circuit can be a conventional pre-decoding circuit, such as a combinational logic circuit. The input row address pre-decoding circuit receives the input row address and pre-decodes all bits of the input row address to obtain a pre-decoded row address, including a segment address and an intra-segment address. The row decoder includes a pre-decoder and a post-decoder. The pre-decoder pre-decodes the input address into a segment address and an intra-segment address. Both of these addresses enter the post-decoder and generate a corresponding signal to drive a specific word line in the memory bank (such as a drive control signal for a main word line driver or a phase driver).

[0069] In some embodiments, the failed address comparison circuit may be an exclusive-OR logic circuit. The failed address comparison circuit receives the failed address information and input row address stored in the fuse array, and compares the input row address with the failed address one by one to determine whether the input row address is one of the failed addresses. The failed address comparison circuit includes multiple failed address comparison units, each of which corresponds to a redundant resource. If the comparison result of a failed address comparison unit is a match, the corresponding redundant resource is found through the redundant address mapping circuit to replace the failed defective address.

[0070] In some embodiments, a redundant address mapping circuit is connected to the failed address comparison circuit and is configured to output a redundant address that replaces the failed address when the input row address is a failed address. The redundant address output by the redundant address mapping circuit may be decoded into a segment address and an intra-segment address. In other embodiments, the redundant address output by the redundant address mapping circuit is decoded into a pre-decoded address that is divided into a segment address and an intra-segment address by another pre-decoding circuit.

[0071] In addition, the same-segment repair judgment circuit is connected to the redundant address mapping circuit, receives the failed address and the redundant address that replaces the failed address (or only receives its segment address information) from the redundant address mapping circuit, and compares the segment address information of the two to determine whether the failed address and the redundant address that replaces the failed address are in the same storage segment. For example, when the failed address and the redundant address that replaces the failed address have the same corresponding bits representing the segment address information (such as the upper 6 bits of 16 bits), it means that the failed address and the redundant address that replaces the failed address are in the same storage segment, and the same-segment repair judgment circuit can output a first selection signal of a first level. Conversely, when the failed address and the redundant address that replaces the failed address are not in the same storage segment, the same-segment repair judgment circuit can output a first selection signal of a second level different from the first level.

[0072] In some embodiments, the second output circuit can be a selection circuit, for example, a two-to-one multiplexer. The selection control terminal of the two-to-one multiplexer is connected to the failed address comparison circuit, receives the output signal of the failed address comparison circuit as a selection control signal, and selects a signal output between the output signal of the redundant address mapping circuit and the output signal of the input row address pre-decoding circuit based on the selection control signal. Specifically, when the signal output by the failed address comparison circuit indicates that the input row address is a failed address, the second output circuit outputs the redundant address (including the segment address and the intra-segment address) output by the redundant address mapping circuit as the actual activation address; when the signal output by the failed address comparison circuit indicates that the input row address is not a failed address, the second output circuit outputs the address (including the segment address and the intra-segment address) obtained by pre-decoding the input row address pre-decoding circuit as the actual activation address.

[0073] In some embodiments, the first output circuit is connected to the same-segment repair judgment circuit, the input row address pre-decoding circuit and the second output circuit, and based on the judgment result of the same-segment repair judgment circuit, when the failed address and the redundant address replacing the failed address are in the same storage segment, the first output circuit receives the segment address obtained by pre-decoding the input row address from the input row address pre-decoding circuit and outputs the segment address; when the failed address and the redundant address replacing the failed address are not in the same storage segment, the first output circuit receives the segment address of the actual activation address from the second output circuit and outputs the segment address.

[0074] Specifically, the first output circuit can be a selection circuit, such as a two-to-one multiplexer, wherein the selection control terminal receives a first selection signal, and the two input terminals respectively receive a segment address obtained by pre-decoding the input row address, and a segment address of a row address that has undergone redundant replacement or has not undergone redundant replacement determined by a comparison result (i.e., a segment address of an actually activated address). For example, the first level is a high level "1" and the second level is a low level "0"; the input row address pre-decoding circuit is connected to the "1" terminal of the multiplexer; and the segment address output by the second output circuit is connected to the "0" terminal of the multiplexer. When the first selection signal output by the same-segment repair judgment circuit is a first level "1", the multiplexer directly outputs the segment address obtained by pre-decoding the input row address, and performs a threshold voltage compensation operation on the sense amplifier of the memory segment corresponding to the segment address in advance. Then, after the comparison between the failed address and the input address is completed, the second output circuit outputs the segment address of the actual activation address and the intra-segment address, activating the corresponding word line. When the first selection signal output by the same-segment repair judgment circuit is a second level "0", the multiplexer selects the segment address output by the second output circuit for output. That is, the output signal of the first output circuit will wait for the comparison result between the failed address and the input address, and then decide whether to perform redundant replacement based on the comparison result. The segment address of the row address (i.e., the actual activation address) that has undergone redundant replacement or not undergone redundant replacement is output. At the same time, the intra-segment address in the actual activation address is directly output, thereby outputting the actual activation address (including the segment address and the intra-segment address) and activating the sense amplifier and word line of the memory segment corresponding to the address.

[0075] Therefore, the same-segment repair judgment circuit determines whether the failed address is repaired using the redundant resource in the same storage segment. If so, since the input row address and the redundant resource are in the same storage segment, the address of the storage segment obtained by pre-decoding the input row address can be directly outputted without waiting for the comparison result of the failed address comparison circuit. As a result, the threshold voltage compensation operation of the sense amplifier corresponding to the activated address does not need to wait for the comparison result, and the threshold voltage compensation operation time of the sense amplifier of the storage segment is advanced, thereby improving the timing of the row redundancy circuit, reducing the minimum tRCD, and thus improving the overall timing.

[0076] In some embodiments, a memory includes multiple failed addresses and multiple redundant addresses, and each failed address corresponds one-to-one with each redundant address. When all failed addresses in the memory and their corresponding redundant addresses satisfy the condition that the failed address and the redundant address replacing the failed address are in the same memory segment, the same segment repair judgment circuit outputs a first selection signal of a first level; when any redundant address in the memory is not in the same memory segment as the failed address to be replaced, the same segment repair judgment circuit outputs a first selection signal of a second level.

[0077] Specifically, the same-segment repair judgment circuit includes at least one comparison unit, each comparison unit receives and compares the failure address (that is, the address of the fuse memory) and the redundant address. In some embodiments, the comparison unit may also only receive the segment address of the failure address and the segment address of the redundant resource to save the area and power consumption of the comparison unit. In some embodiments, each comparison unit compares the failure address and the redundant address in pairs, and then summarizes all the comparison units corresponding to a storage segment. If all the comparison units corresponding to a storage segment indicate that the failure address they compare is the same as the segment address of the redundant address, then the storage segment is judged to be repaired in the same segment. Then, the comparison results within a storage body are summarized, and then the comparison results of all storage bodies are summarized. If all storage bodies meet the same-segment repair requirements, the memory chip can directly use the optimized timing before leaving the factory or when powered on, thereby using better tRCD parameters to improve the quality of the chip. Moreover, when the conditions for same-segment repair are not met, the original operation mode can be retained to ensure the normal operation of the circuit.

[0078] In other embodiments, the comparison unit may also directly compare all failed addresses and redundant addresses in a memory segment, a memory bank, or a chip, thereby omitting the step-by-step aggregation process.

[0079] In other embodiments, the same-segment repair determination circuit may also perform dynamic address same-segment repair determination based on the input row address. For example, the same-segment repair determination circuit receives the input row address and a redundant address corresponding to the input row address, and determines whether the input row address and the redundant address are in the same memory segment. If so, the circuit directly outputs the segment address obtained by pre-decoding the input row address to perform threshold voltage compensation on the sense amplifier of the corresponding memory segment.

[0080] In some embodiments, a comparison unit of the same-segment repair judgment circuit includes at least one comparison circuit, an OR logic circuit, an enable circuit, an initialization circuit, and a holding circuit, wherein:

[0081] The comparison circuit is configured to receive the segment address information of the failed address and the redundant address and perform comparison;

[0082] An input end of the OR logic circuit is connected to an output end of the at least one comparison circuit, and an output end of the OR logic circuit is connected to the enabling circuit;

[0083] The enabling circuit is connected between the control node and the OR logic circuit;

[0084] The initialization circuit is configured to initialize the control node to a preset level;

[0085] The holding circuit is connected between the power supply voltage and the control node, and maintains the voltage of the control node in response to the voltage of the control node.

[0086] Specifically, refer to Figure 6 , Figure 6 shows a circuit structure diagram of a comparison unit, Figure 6 In this example, the comparison circuit is an XOR gate, and one comparison unit includes two comparison circuits. It should be understood that logic such as an XOR gate or an AND gate can also be used as a specific implementation of the comparison circuit. Furthermore, the specific number of comparison circuits is not limited to two and can be specifically designed based on the number of addresses to be compared. When comparing all redundant addresses in a memory segment with a failed address, the number of comparison circuits can be set to the same as the number of redundant addresses.

[0087] Continue to refer Figure 6 The comparison circuit is an XOR gate. The two input terminals of the XOR gate receive the segment information of the failed address and the segment information of the redundant address respectively. When the segment information of the failed address and the segment information of the redundant address are different, the XOR gate outputs a logic level "1". The output terminal of the XOR gate is connected to the OR logic circuit. Figure 6 The example of an OR logic circuit is a parallel pair of NMOS transistors M1 and M2. Each comparator circuit corresponds to an OR logic circuit. When the XOR gate outputs a logic level of "1," the OR logic circuit connected to it is turned on, setting its output to a low level of "0."

[0088] Continue to refer Figure 6 NMOS transistors M1 and M2 are connected in parallel, with their control terminals each connected to the output of an XOR gate, their source terminals connected to ground, and their drain terminals connected to the input of an enable circuit. The enable circuit includes an enable transistor, which can be an NMOS transistor M3. Its control terminal receives an enable signal Enable, one terminal is connected to the output of the OR logic circuit, and the other terminal is connected to control node Result0. When the output of the OR logic circuit is set to a low level "0" when the enable signal is enabled, control node Result0 is also pulled down.

[0089] Continue to refer Figure 6 The comparison unit further includes an initialization circuit and a holding circuit, wherein the initialization circuit includes an initialization transistor and the holding circuit includes a holding transistor. Figure 6In the example, the initialization circuit is a PMOS transistor M4. The control terminal of the PMOS transistor M4 receives an initialization signal, one end is connected to the power supply terminal, and the other end is connected to the control node Result0. During initialization, the PMOS transistor M4 receives the power-on initialization signal Initial, causing the control node to be set to a logic level of "1." Subsequently, the initialization circuit can be closed, and the logic level of the control node is maintained by the holding circuit. That is, the power-on initialization signal Initial is initialized to "0" at power-on, then sets the control node, and then changes to "1", closing the initialization circuit. The holding circuit can be a PMOS transistor M5, which is a weak pull-up transistor. That is, the width-to-length ratio of the PMOS transistor M5 is small (for example, the width-to-length ratio of M5 is smaller than that of all other transistors M1-M4), so that the pull-up capability of M5 is smaller than the pull-down capability of M1-M3. The control terminal of M5 receives the inverted signal of the control node Result0, one end of the source / drain is connected to the power supply terminal, and the other end is connected to the control node Result0. When the control node Result0 is set to logic level “1”, the signal reaches the input terminal of the PMOS transistor M5 after being inverted, turning on M5 and maintaining the level of the control node Result0 .

[0090] After the fuse array has completely programmed the failed addresses, the enable signal "Enable" is activated. If the segment address of a failed address in the multiple comparison circuits does not match the segment address of its corresponding redundant address, the XOR gate outputs a logic level "1," activating one of the OR logic circuits. Because the enable signal is active, the level of the control node Result0 is pulled down to a logic level "0." After passing through two stages of inverters, the comparison unit outputs a logic level "0." After being aggregated through multiple stages of comparison units, memory segments, memory banks, and memory chips, a first select signal with a logic level "0" is output, causing the first output circuit to wait for the segment address information of the actual activated address to be output.

[0091] After the fuse array has completed programming of all failed addresses, the enable signal Enable is enabled. When the segment addresses of all failed addresses in the multiple comparison circuits match the segment addresses of their corresponding redundant addresses, each exclusive-OR gate outputs a logic level "0," shutting down all OR logic circuits. Since the control node Result0 is initialized to a logic level "1," the level of the control node Result0 is maintained at a logic level "1" by the holding circuit M5. After passing through two stages of inverters, the comparison unit outputs a logic level "1." After being aggregated level by level through multiple levels of comparison units, storage segments, storage bodies, and storage chips (the comparison results at each level can be aggregated through AND logic combinations), if the segment addresses of all failed addresses match the segment addresses of the redundant addresses, then after being aggregated level by level, a first selection signal of logic level "1" is output, causing the first output circuit to directly output the segment address obtained by the input row address pre-decoding circuit after pre-decoding the input row address.

[0092] Based on this, a simple circuit can be used to compare the segment addresses of multiple failed addresses and their corresponding redundant addresses, and it is convenient to store the comparison results in the segment and summarize them level by level to obtain the first selection signal to determine whether the segment address should be output in advance.

[0093] In other embodiments, the present application further provides a method for operating a memory. The memory may be the memory provided in any of the aforementioned embodiments, and its structural details are not described here. In this embodiment, the method for operating the memory includes:

[0094] Determine whether the failed address and the redundant address that replaces the failed address are in the same storage segment;

[0095] When the failed address and the redundant address that replaces the failed address are in the same memory segment, the following operations are performed:

[0096] Receive input row address;

[0097] Pre-decode the input row address to obtain the segment address of the input row address;

[0098] performing a threshold voltage compensation operation on the memory segment pointed to by the segment address;

[0099] When the failed address and the redundant address that replaces the failed address are not in the same memory segment, the following operations are performed:

[0100] Receive input row address;

[0101] Pre-decoding the input row address to obtain the segment address of the input row address; at the same time, comparing the input row address with the failed address to determine whether to replace the input row address with a redundant address;

[0102] According to the comparison result, the segment address obtained by pre-decoding the input row address or the segment address of the redundant address is output as the segment address of the actual activation address;

[0103] A threshold voltage compensation operation is performed on the storage segment pointed to by the segment address of the actual activation address.

[0104] Figure 7 The diagram below shows the timing diagram of the memory operation, where the horizontal axis Y represents time. Figure 7, first perform a conditional judgment to determine whether the failed address and the redundant address that replaces the failed address are in the same storage segment. When the condition for repairing the same segment is met, receive the input row address, perform input row address pre-decoding and address comparison synchronously, and use the segment address obtained by pre-decoding the input row address to perform a threshold voltage compensation operation on the storage segment pointed to by the segment address, and then after the address comparison and redundant address mapping are completed, open the word line that needs to be activated. When the condition for repairing the same segment is not met, receive the input row address, pre-decode the input row address, and obtain the segment address of the input row address; at the same time, compare the input row address with the failed address to determine whether to replace the input row address with the redundant address; according to the comparison result, the first output circuit selects to output the segment address obtained by pre-decoding the input row address or the segment address of the redundant address as the segment address of the actual activation address, and then perform a threshold voltage compensation operation on the storage segment pointed to by the segment address of the actual activation address, and then open the word line that needs to be activated. Reference Figure 7 ,When the conditions are met, the timing is greatly improved.

[0105] Among them, due to the row decoding operation, it is only necessary to determine whether the failed row address and the redundant row address that replaces the failed row address are in the same storage segment; when the failed address and the redundant address that replaces the failed address are in the same storage segment, it is not necessary to wait for the comparison result of the failed address comparison circuit, that is, before the comparison of the failed address comparison circuit is completed, the threshold voltage compensation operation is performed on the storage segment pointed to by the segment address.

[0106] Therefore, the memory operation method of this embodiment determines whether the failed address and the redundant address that replaces it are in the same memory segment. If so, the threshold voltage compensation operation for the memory segment is advanced, and the segment address information is directly obtained from the normal address pre-decoding. The threshold voltage compensation operation for the memory segment is performed in advance, thereby improving the timing of the row redundancy circuit, reducing the minimum tRCD, and thus improving the overall timing. If not, the existing operation method of waiting for the comparison result of the failed address comparison circuit is retained to ensure normal operation of the circuit.

[0107] In some embodiments, before the chip leaves the factory, or when the memory is powered on, an operation can be performed to determine whether the failed address and the redundant address that replaces the failed address are in the same storage segment. Since the failed address and the redundant address that repairs it are fixed, the result of this judgment is static. When the judgment is completed, the working mode of the first output circuit is fixed. When the chip is working subsequently, the first output circuit only outputs the segment address output by the input row address pre-decoding circuit, or the segment address of the actual activation address. In other words, the chip state is fixed, so the tRCD timing can be set according to the result of this judgment operation. For chips that meet the requirements of same-segment repair, the tRCD timing is compressed to screen high-quality chips.

[0108] Combined with reference Figure 5 and Figure 7 When the failed address and the redundant address that replaces the failed address are in the same memory segment, the following operations are performed: receiving an input row address; pre-decoding the input row address to obtain a segment address of the input row address; and performing a threshold voltage compensation operation on the memory segment pointed to by the segment address, specifically:

[0109] When the failed address and the redundant address that replaces the failed address are in the same memory segment, the following operations are performed:

[0110] Receive input row address;

[0111] Pre-decode the input row address to obtain the segment address of the input row address; at the same time, compare the input row address with the failed address to determine whether to replace the input row address with a redundant address;

[0112] Without waiting for the comparison result, a threshold voltage compensation operation is performed on the memory segment pointed to by the segment address obtained by pre-decoding the input row address;

[0113] According to the comparison result, the intra-segment address obtained by pre-decoding the input row address or the intra-segment address of the redundant address is output as the intra-segment address of the actual activated address;

[0114] The input row address is pre-decoded to obtain the segment address and the intra-segment address.

[0115] Among them, due to the row decoding operation, it is only necessary to determine whether the failed row address and the redundant row address that replaces the failed row address are in the same storage segment; when the failed address and the redundant address that replaces the failed address are in the same storage segment, it is not necessary to wait for the comparison result of the failed address comparison circuit, that is, before the comparison of the failed address comparison circuit is completed, the threshold voltage compensation operation is performed on the storage segment pointed to by the segment address, thereby improving the timing of the row redundancy circuit, reducing the minimum tRCD, and thus improving the overall timing.

[0116] In some embodiments, the memory includes multiple failure addresses and multiple redundant addresses, and the failure addresses and the redundant addresses correspond one-to-one. The determination of whether the failure address and the redundant address that replaces the failed address are in the same storage segment is specifically as follows: determining whether each pair of one-to-one corresponding failure addresses and redundant addresses are in the same storage segment; if there is a pair of failure addresses and redundant addresses that are not in the same storage segment, the memory performs an operation that the failure address and the redundant address that replaces the failed address are not in the same storage segment.

[0117] Specifically, the memory includes multiple failed addresses and multiple redundant addresses, and a failed address corresponds to a redundant address one by one. It is possible to determine whether a failed address corresponds to a redundant address by judging the failed address (i.e., the address of the fuse memory) and all or part of the redundant address (i.e., the address bits representing the segment address). In some embodiments, Figure 6 The comparison units compare the failed addresses and redundant addresses within the same storage segment one by one or uniformly compare them, and then summarize the storage segments, storage bodies, and storage chips step by step through the logic circuit. If all the comparison units corresponding to a storage segment indicate that the failed addresses they compare are the same as the segment addresses of the redundant addresses, then the storage segment is judged to be repaired in the same segment. The comparison results within a storage body are then summarized, and then the comparison results of all storage bodies are summarized. If all storage bodies meet the same-segment repair requirements, the memory chip can directly use the optimized timing before leaving the factory or when powered on, thereby using better tRCD parameters to improve the quality of the chip. Moreover, when the conditions for same-segment repair are not met, the original operation mode can be retained to ensure the normal operation of the circuit.

[0118] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A memory, characterized in that: include: A row address pre-decoding circuit is configured to receive an input row address and pre-decode the input row address; a same-segment repair determination circuit configured to determine whether a failed address and a redundant address replacing the failed address are in the same storage segment; a first output circuit connected to the same-segment repair judgment circuit and the row address pre-decoding circuit, and configured to receive, based on a judgment result of the same-segment repair judgment circuit, a segment address obtained by pre-decoding the input row address from the row address pre-decoding circuit when the failed address and the redundant address replacing the failed address are in the same storage segment, and output the segment address; The sense amplifier is configured to perform a threshold voltage compensation operation on the memory segment pointed to by the segment address in response to the segment address.

2. The memory according to claim 1, wherein The memory includes a memory array, the memory array includes a plurality of memory segments and a plurality of sense amplifier arrays, the memory segments and the sense amplifier arrays are alternately arranged along a first direction, and one sense amplifier array performs sense amplification on the memory segments on both sides thereof adjacent to each other along the first direction; Each sensing amplifier array includes a plurality of sensing amplifiers arranged along the second direction. The first direction and the second direction are perpendicular to each other.

3. The memory according to claim 1, wherein: The memory includes a row decoder, and the row decoder includes the row address pre-decoding circuit; wherein the row address pre-decoding circuit includes an input row address pre-decoding circuit, a failed address comparison circuit, a redundant address mapping circuit and a second output circuit; The input row address pre-decoding circuit is configured to receive the input row address and pre-decode the input row address; The failed address comparison circuit is configured to receive the input row address and determine whether the input row address is a failed address; The redundant address mapping circuit is connected to the failed address comparison circuit and is configured to output a redundant address that replaces the failed address when the input row address is a failed address; The second output circuit is connected to the input row address pre-decoding circuit, the failed address comparison circuit and the redundant address mapping circuit, and is configured to output the redundant address that replaces the failed address as the actual activation address when the failed address comparison circuit determines that the input row address is a failed address; otherwise, output the decoded input row address output by the input row address pre-decoding circuit as the actual activation address.

4. The memory according to claim 3, wherein: The first output circuit is connected to the same segment repair judgment circuit, the input row address pre-decoding circuit and the second output circuit, wherein, The first output circuit is configured to receive and output the segment address obtained by pre-decoding the input row address from the input row address pre-decoding circuit based on the judgment result of the same-segment repair judgment circuit when the failed address and the redundant address replacing the failed address are in the same storage segment; and to receive and output the segment address of the actual activation address from the second output circuit when the failed address and the redundant address replacing the failed address are not in the same storage segment.

5. The memory according to claim 1, wherein: The memory includes a plurality of failed addresses and a plurality of redundant addresses, and the plurality of failed addresses and the plurality of redundant addresses correspond to each other one by one; wherein, The same-segment repair judgment circuit is configured to output a first selection signal of a first level when all failed addresses in the memory and their corresponding redundant addresses satisfy the condition that the failed address and the redundant address replacing the failed address are in the same storage segment; and output a first selection signal of a second level when any redundant address in the memory and the failed address to be replaced are not in the same storage segment.

6. The memory according to claim 5, wherein: The same-segment repair judgment circuit includes at least one comparison circuit, at least one OR logic circuit, an enabling circuit, an initialization circuit, and a holding circuit, wherein: The comparison circuit is configured to receive the segment address information of the failed address and the segment address information of the redundant address, and perform comparison; The control end of the at least one OR logic circuit is connected to the output end of the at least one comparison circuit, and the output end of the OR logic circuit is connected to the enabling circuit; The enabling circuit is connected between the control node and the OR logic circuit; The initialization circuit is configured to initialize the control node to a preset level; The holding circuit is connected between the power supply voltage and the control node, and maintains the voltage of the control node in response to the voltage of the control node.

7. A method for operating a memory, characterized in that: include: Determine whether the failed address and the redundant address that replaces the failed address are in the same storage segment; When the failed address and the redundant address that replaces the failed address are in the same memory segment, the following operations are performed: Receive input row address; Pre-decode the input row address to obtain the segment address of the input row address; performing a threshold voltage compensation operation on the memory segment pointed to by the segment address; When the failed address and the redundant address that replaces the failed address are not in the same memory segment, the following operations are performed: Receive input row address; Pre-decoding the input row address to obtain the segment address of the input row address; at the same time, comparing the input row address with the failed address to determine whether to replace the input row address with a redundant address; According to the comparison result, the segment address obtained by pre-decoding the input row address or the segment address of the redundant address is output as the segment address of the actual activation address; A threshold voltage compensation operation is performed on the storage segment pointed to by the segment address of the actual activation address.

8. The operating method according to claim 7, characterized in that: When the memory is powered on, the operation of determining whether the failed address and the redundant address replacing the failed address are in the same memory segment is performed.

9. The operating method according to claim 7, characterized in that: When the failed address and the redundant address replacing the failed address are in the same storage segment, the following operations are performed: receiving an input row address; pre-decoding the input row address to obtain a segment address of the input row address; and performing a threshold voltage compensation operation on the storage segment pointed to by the segment address, specifically: When the failed address and the redundant address replacing the failed address are in the same storage segment, the following operations are performed: Receive input row address; Pre-decoding the input row address to obtain the segment address of the input row address; at the same time, comparing the input row address with the failed address to determine whether to replace the input row address with a redundant address; Without waiting for the comparison result, a threshold voltage compensation operation is performed on the memory segment pointed to by the segment address obtained by pre-decoding the input row address; According to the comparison result, the intra-segment address obtained by pre-decoding the input row address or the intra-segment address of the redundant address is output as the intra-segment address of the actual activated address; The input row address is pre-decoded to obtain a segment address and an intra-segment address.

10. The operating method according to claim 7, characterized in that: The memory includes a plurality of failure addresses and a plurality of redundant addresses, wherein the failure addresses correspond to the redundant addresses in a one-to-one manner. The determining whether the failed address and the redundant address replacing the failed address are in the same storage segment is specifically determining whether each pair of one-to-one corresponding failed addresses and redundant addresses are in the same storage segment; If there is a pair of failed address and redundant address that are not in the same memory segment, the memory performs the operation when the failed address and the redundant address replacing the failed address are not in the same memory segment.

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