A method for preparing a heterojunction solar cell and a heterojunction solar cell

Abstract

The present invention provides a method for preparing a heterojunction solar cell and a heterojunction solar cell, and relates to the technical field of solar cell preparation. The method for preparing a heterojunction solar cell of the present invention may include providing a substrate, preparing a first passivation layer, a first doping layer, a first transparent conductive layer, a second passivation layer, a second doping layer, and a second transparent conductive layer on both sides of the substrate, etching the second transparent conductive layer to form an isolation region, and etching the second doping layer at a position corresponding to the isolation region to isolate the first transparent conductive layer and the second transparent conductive layer to avoid battery short circuit. The width of the isolation region of the present invention is less than 0.3 mm, so that the solar cell prepared by the preparation method can avoid short circuit and reduce the etching area of ​​the battery as much as possible, make full use of the substrate area, and improve the battery efficiency under the same substrate area.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell preparation, and in particular to a preparation method of a heterojunction solar cell and a heterojunction solar cell. Background Art

[0002] In the prior art, the manufacturing process of heterojunction solar cells is simple, with only four steps: cleaning and texturing, deposition of passivation layers and doping layers on the front and back sides, deposition of transparent conductive oxide thin films (TCO), and preparation of electrodes. When preparing the doping layer and TCO layer, if a mask is not used to block it, the deposited doping layer and TCO layer materials will completely cover one side of the product. In the process of this full coverage preparation, it is inevitable that some materials will reach the side of the substrate or even be plated around the opposite side. When the two-sided materials are overlapped together on the side of the battery or the edge area of ​​the silicon wafer, it will cause conductivity between the front and back of the battery cell, thereby causing a short circuit in the solar cell. In the prior art, such as patent CN114990514B, in order to prevent the solar cell from short-circuiting, in the process of preparing the transparent conductive layer (TCO), a carrier is used as a mask to achieve the purpose of isolating the front and back TCOs from being connected. The heterojunction solar cell prepared by this method has an edge area with a width of about 1-2 mm around the back. Specifically, such as Figure 1 , Figure 2 and Figure 3 As shown, the carrier has a support surface 103 and an inclined surface 104. During the preparation process, the silicon wafer is placed on the support surface 103. Since this part of the area is not deposited with the TCO film, it cannot absorb and utilize sunlight, which affects the efficiency improvement of the battery. If a maskless carrier is used for coating to increase the use area of ​​the battery cell, it is necessary to add at least one edge etching process to electrically isolate the front and back of the battery. However, in current technology, both dry etching and wet etching have certain technical problems. For example, laser etching in dry etching has a poor effect on microcrystalline doping etching, and when wet etching is used for edge etching, considering the tolerance problem of silicon wafer size in the photovoltaic industry, both the mask plate and the screen printing screen selected for wet etching cannot fully utilize the silicon wafer area during mass production, resulting in the problem that the final battery efficiency cannot be fully reflected. Summary of the invention

[0003] An object of the first aspect of the present invention is to provide a method for preparing a heterojunction solar cell to solve the problem in the prior art that the substrate area cannot be fully utilized.

[0004] In particular, the present invention also provides a method for preparing a heterojunction solar cell, comprising:

[0005] providing a substrate;

[0006] forming a first passivation layer covering the front surface of the substrate and a first doping layer covering the first passivation layer on the front surface of the substrate, and forming a second passivation layer covering the substrate and a second doping layer covering the second passivation layer on the back surface of the substrate;

[0007] forming a first transparent conductive layer covering the first doping layer and a second transparent conductive layer covering the second doping layer on the first doping layer and the second doping layer;

[0008] An isolation region is formed on the second transparent conductive layer and the second doping layer by an etching process.

[0009] Optionally, the etching process includes a first etching process and a second etching process, and the second transparent conductive layer is etched by the first etching process to form a first isolation region, and the second doped layer is etched at a position corresponding to the first isolation region by the second etching process to form a second isolation region; wherein the first isolation region and the second isolation region form the isolation region.

[0010] Optionally, the first etching process includes coating an etching slurry on the second transparent conductive layer by roller coating, and etching the second transparent conductive layer by using the etching slurry to form the first isolation region;

[0011] The step of coating the etching slurry by roller coating comprises:

[0012] Using two sets of two rollers arranged opposite to each other to simultaneously coat the surroundings of the second transparent conductive layer; or

[0013] A set of two rollers arranged opposite to each other are used to first coat a set of opposite edges of the second transparent conductive layer, and then the other set of opposite edges of the second transparent conductive layer is coated after the cell is horizontally rotated 90°.

[0014] Optionally, before the roller coats the cell with etching slurry, the method further comprises:

[0015] The scraper is used to control the amount of etching slurry on the surface of the roller, thereby controlling the width of the etching slurry coated on the second transparent conductive layer.

[0016] Optionally, the axis of the roller is biased toward a side of the plane where the battery cell is located and where the etching slurry needs to be coated.

[0017] Optionally, the dimensions of both ends of the roller are larger than the dimension of the middle area.

[0018] Optionally, the first etching process includes printing etching slurry on the second transparent conductive layer by screen printing, and the printing etching slurry specifically includes:

[0019] The etching slurry is printed on the surface of the second transparent conductive layer for multiple times by screen printing, and the second transparent conductive layer is etched by the etching slurry to form the first isolation region.

[0020] Optionally, the first isolation region is a square closed region extending parallel to the periphery of the substrate;

[0021] Printing the etching slurry four times on the surface of the second transparent conductive layer by screen printing, each printing area corresponds to the area where one of the edges of the closed area is located; or

[0022] The etching slurry is printed twice on the surface of the second transparent conductive layer by screen printing, the first printing area corresponds to the area where two adjacent edges of the closed area are located, and the second printing area corresponds to the area where the remaining two adjacent edges are located.

[0023] Optionally, before printing the etching slurry on the second transparent conductive layer by screen printing, the method further includes: when forming the second transparent conductive layer, using the supporting portion of the supporting board as a mask to form a non-coated area on which the second transparent conductive layer is not coated; wherein the non-coated area at least partially overlaps with the area to be screen-printed.

[0024] Optionally, the number of the non-coated areas is four, which are respectively located at four corner areas of the substrate;

[0025] Optionally, the size of each of the non-coated areas in a direction parallel to the side of the closed area is a, a is greater than or equal to 0.25 mm, and a is less than half of the side length of the substrate;

[0026] Optionally, the shape of each of the non-coating areas includes L-shape, fan-shape, triangle or quadrilateral.

[0027] Optionally, the first etching process includes using laser etching to scan at least once a position of the second transparent conductive layer corresponding to the first isolation region to form the first isolation region.

[0028] Optionally, the first etching process includes spraying etching slurry on a position of the second transparent conductive layer corresponding to the first isolation region by inkjet printing, and etching the second transparent conductive layer by using the etching slurry to form the first isolation region.

[0029] Optionally, the second etching process includes adopting one of wet etching, ICP etching or CCP etching, using the second transparent conductive layer as a mask, and etching the second doped layer at a position corresponding to the first isolation region to form the second isolation region.

[0030] Optionally, the etching process is a one-step etching process, and the second transparent conductive layer and the second doped layer are etched by the one-step etching process to form the isolation region.

[0031] Optionally, the one-step etching process includes coating an etching slurry on the second transparent conductive layer by roller coating, and etching the second transparent conductive layer and the second doped layer by using the etching slurry to form the isolation region;

[0032] The step of coating the etching slurry by roller coating specifically includes:

[0033] Using two sets of two rollers arranged opposite to each other to simultaneously coat the surroundings of the second transparent conductive layer; or

[0034] A set of two rollers arranged opposite to each other are used to first coat a set of opposite edges of the second transparent conductive layer, and then the other set of opposite edges of the second transparent conductive layer is coated after the cell is horizontally rotated 90°.

[0035] Optionally, before the roller coats the cell with etching slurry, the method further comprises:

[0036] The scraper is used to control the amount of etching slurry on the surface of the roller, thereby controlling the width of the etching slurry coated on the second transparent conductive layer.

[0037] Optionally, the axis of the roller is biased toward a side of the plane where the battery cell is located and where the etching slurry needs to be coated.

[0038] Optionally, the dimensions of both ends of the roller are larger than the dimension of the middle area.

[0039] Optionally, the isolation area comprises a square closed area formed along the periphery of the substrate;

[0040] The one-step etching process includes printing etching slurry on the surface of the second transparent conductive layer multiple times by screen printing, and etching the second transparent conductive layer and the second doping layer by using the etching slurry to form the isolation region.

[0041] Optionally, the etching slurry is printed four times on the surface of the second transparent conductive layer by screen printing, and each printing area corresponds to an area where one of the edges of the closed area is located; or

[0042] The etching slurry is printed twice on the surface of the second transparent conductive layer by screen printing, the first printing area corresponds to two adjacent sides of the closed area, and the second printing area corresponds to the remaining two adjacent sides.

[0043] Optionally, before etching by screen printing, the method further includes: when forming the second transparent conductive layer, using the supporting portion of the supporting board as a mask to form a non-coated area, and the non-coated area at least partially overlaps with the area to be screen printed.

[0044] Optionally, the number of the non-coated areas is four, which are respectively located at four corner areas of the substrate;

[0045] Optionally, the size of each of the non-coated areas in a direction parallel to the side of the closed area is a, a is greater than or equal to 0.25 mm, and a is less than half of the side length of the substrate;

[0046] Optionally, the shape of each of the non-coating areas includes L-shape, fan-shape, triangle or quadrilateral.

[0047] Optionally, the width b of the isolation region is less than 0.3 mm.

[0048] Optionally, a distance c between the isolation region and the edge of the substrate is less than 0.1 mm.

[0049] In particular, the present invention also provides a heterojunction solar cell, which is prepared using the above-mentioned preparation method.

[0050] The preparation method of this scheme etches the second transparent conductive layer and the second doped layer of the heterojunction battery through an etching process to form an isolation area, and isolates the first transparent conductive layer and the second transparent conductive layer located on the front and back of the substrate to avoid short circuit of the battery. When etching the second transparent conductive layer to form the isolation area, the width b of the isolation area is less than 0.3mm, so that the solar cell can avoid short circuit and reduce the etching area of ​​the battery as much as possible, making full use of the substrate area and improving the efficiency of the battery under the same substrate area.

[0051] This solution etches at the position corresponding to the isolation area of ​​the second doped layer. Since the second doped layer is located below the second transparent conductive layer, an isolation area is formed after the second transparent conductive layer is etched, so that when etching the second doped layer, the second transparent conductive layer can be directly used as a mask plate for etching, without the need for an additional mask plate for masking, thereby reducing the mask process and improving production efficiency. In addition, since the second transparent conductive layer is used as a mask, etching is performed at the position corresponding to the isolation area through the second doped layer, and the etching size of the second doped layer is less than or equal to the size of the isolation area, making the etching area of ​​the second doped layer smaller, thereby improving battery efficiency.

[0052] In this solution, due to the tolerance of the substrate during the preparation process, specifically, the tolerance range is generally around 0.25mm. The size of the non-coated area in the direction parallel to the edge of the closed area is designed to be greater than or equal to 0.25mm, but less than half the length of the closed area, which not only satisfies the formation of an etched closed area through the wind-coated area during screen printing, but also reduces the area of ​​the non-enclosed area, thereby maximizing the efficiency of the battery.

[0053] In this solution, the surface of the second doped layer is processed during the etching of the second transparent conductive layer, which is equivalent to pre-processing the surface of the second doped layer before etching, making it more conducive to etching the second doped layer.

[0054] Based on the following detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings, those skilled in the art will become more aware of the above and other objects, advantages and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0056] Figure 1 is a schematic structural diagram of a carrier board in the prior art;

[0057] Figure 2 It is a partial enlarged schematic diagram of a carrier board in the prior art;

[0058] Figure 3 It is a partial cross-sectional view of a carrier plate in the prior art;

[0059] Figure 4 is a schematic flow chart of a method for preparing a heterojunction solar cell according to a specific embodiment of the present invention;

[0060] Figure 5 is a schematic structural diagram of a heterojunction solar cell before being etched according to a specific embodiment of the present invention;

[0061] Figure 6 is a cross-sectional view of a heterojunction solar cell after the second transparent conductive layer and the second doping layer are etched according to a specific embodiment of the present invention;

[0062] Figure 7 (a) is a bottom view of a heterojunction solar cell after the second transparent conductive layer and the second doped layer are etched according to a specific embodiment of the present invention;

[0063] Figure 7 (b) Yes Figure 7(a) A partial schematic diagram;

[0064] Figure 8 (a) is a bottom view of a heterojunction solar cell after the second transparent conductive layer and the second doped layer are etched according to another specific embodiment of the present invention;

[0065] Figure 8 (b) Yes Figure 8 (a) A partial schematic diagram;

[0066] Fig. 9 is a cross-sectional view of a heterojunction solar cell after the second transparent conductive layer is etched according to a specific embodiment of the present invention;

[0067] Fig.10 is a schematic structural diagram of a roller and a scraper used for roller coating etching slurry according to a specific embodiment of the present invention;

[0068] Fig.11 is a schematic structural diagram of a roller and a battery cell for roller coating etching slurry according to a specific embodiment of the present invention;

[0069] Fig.12 (a) is a schematic structural diagram of a cell in which a roller is used to apply etching slurry and the second transparent conductive layer is etched to form a first isolation region according to a specific embodiment of the present invention;

[0070] Fig.12 (b) Yes Fig.12 (a) A partial schematic diagram;

[0071] Fig.13 is a schematic structural diagram of a carrier used for forming a non-coating area according to a specific embodiment of the present invention;

[0072] Fig.14 is a partial enlarged schematic diagram of a carrier used to form a non-coating area according to a specific embodiment of the present invention;

[0073] Fig.15 is a schematic structural diagram of a second transparent conductive layer having a non-coating area according to a specific embodiment of the present invention;

[0074] Fig.16 (a) is a schematic structural diagram of a bearing portion according to a specific embodiment of the present invention;

[0075] Fig.16 (b) is a schematic structural diagram of a bearing portion according to another specific embodiment of the present invention;

[0076] Fig.16 (c) is a schematic structural diagram of a bearing portion according to another specific embodiment of the present invention;

[0077] Fig.16 (d) is a schematic structural diagram of a bearing portion according to another specific embodiment of the present invention;

[0078] Fig.17 (a) is a schematic structural diagram after printing etching paste on the second transparent conductive layer having a non-coated area according to another specific embodiment of the present invention;

[0079] Fig.17 (b) Yes Fig.17 (a) is a partial enlarged schematic diagram.

[0080] Description of reference numerals:

[0081] Substrate-100; second passivation layer-200; first passivation layer-300; first doping layer-400; second doping layer-500; first transparent conductive layer-600; second transparent conductive layer-700; isolation region-710; first isolation region-711; second isolation region-712; non-coating region-720; roller-810; middle region-811; end-812; scraper-820; etching slurry-830; battery cell-900; chamfer-910;

[0082] Carrier plate 1000; carrying area 1100; carrying portion 1110. DETAILED DESCRIPTION

[0083] In the description of this embodiment, it should be understood that the terms "length", "width", "height", "up", "down", "left", "right", "vertical", "horizontal", "bottom", "inside" and "outside" etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0084] As a specific embodiment of the present invention, Figure 4 As shown, this embodiment discloses a method for preparing a heterojunction solar cell, which may include:

[0085] Step S100, providing a substrate 100;

[0086] Step S200, forming a first passivation layer 300 covering the front surface of the substrate 100 and a first doping layer 400 covering the first passivation layer 300 on the front surface of the substrate 100, and forming a second passivation layer 200 covering the substrate 100 and a second doping layer 500 covering the second passivation layer 200 on the back surface of the substrate 100;

[0087] Step S300 , forming a first transparent conductive layer 600 covering the first doping layer 400 and a second transparent conductive layer 700 covering the second doping layer 500 on the first doping layer 400 and the second doping layer 500 ;

[0088] Step S400 , forming an isolation region 710 on the second transparent conductive layer 700 and the second doping layer 500 by an etching process.

[0089] In step S200 , the first passivation layer 300 may be a single-layer structure or a multi-layer structure; similarly, the second passivation layer 200 may be a single-layer structure or a multi-layer structure, which is not further limited herein.

[0090] In step S200 , the first doping layer 400 may be a single-layer structure or a multi-layer structure; similarly, the second doping layer 500 may be a single-layer structure or a multi-layer structure, which is not further limited herein.

[0091] In step S300, the first transparent conductive layer 600 can be a single-layer structure or a multi-layer structure; similarly, the second transparent conductive layer 700 can be a single-layer structure or a multi-layer structure, which is not further limited here. In addition, it can adopt a double-sided coating process to simultaneously form a first transparent conductive layer 600 covering the first doping layer 400 and a second transparent conductive layer 700 covering the second doping layer 500 on the first doping layer 400 and the second doping layer 500. This process does not require flipping the substrate, which simplifies the process. Of course, a single-sided coating method can also be adopted to form a first transparent conductive layer 600 covering the first doping layer 400 and a second transparent conductive layer 700 covering the second doping layer 500 on the first doping layer 400 and the second doping layer 500, respectively. It should be noted that when a single-sided coating process is adopted, the substrate 100 needs to be flipped between the two transparent conductive layer coating processes. The above is a conventional process and is not further limited here.

[0092] Specifically, the structure after the preparation in step S300 in this embodiment is as follows Figure 5 The structure after step S400 is completed is as shown Figure 6 and Figure 7 shown.

[0093] Specifically, in this embodiment Figure 5 and Figure 6 The lower middle side is the back side. Figure 5 and Figure 6 The upper side in the figure is the front side.

[0094] In addition, it should be noted that before step S400, a first electrode (not shown in the figure) may be formed on the first transparent conductive layer 600, and a second electrode (not shown in the figure) may be formed on the second transparent conductive layer 700, and then step S400 may be performed to form an isolation region 710 on the second transparent conductive layer 700 and the second doping layer 500 through an etching process, which will not be further explained.

[0095] The preparation method of this embodiment etches the second transparent conductive layer 700 and the second doping layer 500 of the heterojunction battery through an etching process to form an isolation region 710, which isolates the transparent conductive film on the front and back of the battery to prevent the battery from short-circuiting. When etching the second transparent conductive layer 700, the width b of the isolation region is less than 0.3 mm, so that the battery can avoid short-circuiting and reduce the etching area as much as possible, making full use of the light-emitting area of ​​the battery and improving the efficiency of the battery under the same area.

[0096] Specifically, Figure 7 As shown in (a) and 7(b), in this embodiment, since the width b of the partition area is less than 0.3 mm, of course, the width b is greater than 0. Preferably, the width b of the partition area can be designed to be less than 0.1 mm, so that the area of ​​the partition area 710 can be further reduced and the efficiency of the battery can be improved. In one embodiment, as Figure 7 As shown in FIGS. 7(a) and 7(b), the isolation region 710 is still a certain distance away from the side of the substrate 100, and the isolation region 710 is formed into a square. Figure 8 As shown in FIGS. 8(a) and 8(b), the isolation region 710 is at a certain distance from the side of the substrate 100. The isolation region 710 extends directly along the side of the edge region of the substrate 100. When the corner of the substrate 100 is chamfered, the isolation region also extends along the chamfer accordingly. In other embodiments, the isolation region 710 may also be at a distance of 0 from the side of the substrate 100 (see Fig.12 When the first isolation region 711 is formed at the second transparent conductive layer 700, since the width of the first isolation region 711 is relatively small (less than 0.3 mm, preferably, less than 0.1 mm), in order to achieve a better isolation effect of the battery, after the first isolation region 711 is formed at the second transparent conductive layer 700, the second doping layer 500 at the same position needs to be etched to form a second isolation region 712.

[0097] As a specific embodiment of the present invention, the etching process of this embodiment includes a first etching process and a second etching process. The second transparent conductive layer 700 is etched by the first etching process to form a first isolation region 711 (such as Fig. 9), the second doping layer 500 is etched at a position corresponding to the first isolation region 711 by a second etching process to form a second isolation region 712 (as shown in FIG. Figure 6 As shown); wherein, the first isolation region 711 and the second isolation region 712 form an isolation region 710.

[0098] Specifically, in this embodiment, a first etching process is used to etch the second transparent conductive layer 700 to obtain a first isolation region 711, and then a second etching process is used to etch the second doping layer 500 to obtain a second isolation region 712. The first isolation region 711 and the second isolation region 712 together constitute an isolation region 710. Such an operation allows the preparation method of this embodiment to select the same or different processes according to the material properties of the second transparent conductive layer 700 and the second doping layer 500, thereby facilitating the smooth progress of etching.

[0099] As a specific embodiment of the present invention, Fig.10 As shown, the first etching process may include coating the etching slurry 830 on the second transparent conductive layer 700 by means of a roller 810 , and etching the second transparent conductive layer 700 by means of the etching slurry 830 to form the first isolation region 711 .

[0100] In the prior art, a roller coating is usually used to coat the double sides of the cell, while in the present invention, a roller is used to coat one side of the cell with etching slurry, and the cell is etched on one side, that is, only the back side of the cell is etched, so as to further ensure the utilization rate of the light-receiving surface of the cell. Specifically, in this embodiment, since a layer of etching slurry 830 needs to be coated on the roller 810 when coating, and then the roller 810 is contacted with the cell 900, so that the etching slurry 830 is transferred to the edge position of one side of the cell 900, and then the etching slurry 830 is used to etch the second transparent conductive layer 700 to form a first isolation area. Specifically, in this embodiment, since the etching slurry 830 is directly coated on the edge of the cell 900, the distance between the formed isolation area and the edge of the cell 900 is 0.

[0101] As one of the specific embodiments of the present invention, the step of coating the etching slurry 830 by using the roller 810 in this embodiment may include:

[0102] Two sets of two rollers 810 disposed opposite to each other are used to coat the surroundings of the second transparent conductive layer 700 at the same time.

[0103] Specifically, rollers 810 are disposed around the silicon wafer, and the four rollers 810 simultaneously coat the etching slurry 830 around the silicon wafer.

[0104] As a specific embodiment of the present invention, the step of coating the etching slurry 830 by using the roller 810 in this embodiment may include:

[0105] A set of two rollers 810 arranged opposite to each other are used to first coat a set of opposite sides of the second transparent conductive layer 700 . After heat treatment, the cell 900 is horizontally rotated 90° and then another set of opposite sides of the second transparent conductive layer 700 is coated.

[0106] In both groups of embodiments, the etching slurry 830 will eventually be coated around the battery cell 900, and the etching slurry 830 around the battery cell 900 will be interconnected to form a closed shape, so that the first transparent conductive layer and the second transparent conductive layer will be separated after the second transparent conductive layer is etched.

[0107] As a specific embodiment of the present invention, before the roller 810 coats the etching slurry 830 on the cell 900, the present embodiment further includes:

[0108] The scraper 820 is used to control the amount of the etching slurry 830 on the surface of the roller 810 , thereby controlling the width of the etching slurry 830 coated on the second transparent conductive layer 700 .

[0109] Specifically, before the etching slurry 830 is applied, the etching slurry 830 is applied on the roller 810. During the continuous rotation of the roller 810, the thickness of the etching slurry 830 on the roller 810 is controlled by a scraper 820 disposed on one side of the roller 810. Since the roller 810 and the battery cell 900 are in contact with each other, the etching slurry 830 on the roller 810 will be applied to the periphery of the battery cell 900. Therefore, the thickness of the etching slurry 830 on the roller 810 will affect the width of the etching slurry 830 applied at the periphery of the battery cell 900. Specifically, the thickness of the etching slurry 830 on the roller 810 of this embodiment is linearly related to the width of the etching slurry 830 applied at the battery cell 900. Generally speaking, the greater the thickness of the etching slurry 830 on the roller 810, the wider the width of the etching slurry 830 applied at the battery cell 900. Therefore, the thickness of the etching slurry 830 on the roller 810 can be controlled by the scraper 820 , thereby controlling the width of the etching slurry 830 coated on the battery cell 900 .

[0110] As a specific embodiment of the present invention, the axis of the roller 810 of this embodiment is biased toward the side of the plane where the battery cell 900 is located and where the etching slurry 830 needs to be coated.

[0111] Specifically, if the upper side of the cell 900 needs to be coated with etching slurry 830, the axis of the roller 810 is located above the plane where the cell 900 is located. If the lower side of the cell 900 needs to be coated with etching slurry 830, the axis of the roller 810 is located below the plane where the cell 900 is located. That is, there is a certain distance between the plane where the axis of the roller 810 is located and the plane where the cell 900 is located, and the front and back sides of the cell 900 are selected for coating by controlling the plane where the axis of the roller 810 is located. Of course, the position where the cell 900 contacts the roller 810 will also affect the thickness of the slurry coated on the cell 900.

[0112] More specifically, in this embodiment, the amount of etching slurry coated on one side and the side edge of the cell 900 by the roller 810 is controlled by controlling the angle between the line connecting the contact point between the cell 900 and the roller 810 and the axis of the roller 810 and the horizontal plane, for example, the angle is between 20-70 degrees. Preferably, the angle between the line connecting the contact point between the cell 900 and the roller 810 and the axis of the roller 810 and the horizontal plane is preferably 45 degrees, and then the etching slurry is coated on the back and side edge of the cell 900, and the transparent conductive layer of the coated area is etched to form electrical isolation, further improving the electrical isolation effect of the first transparent conductive layer 600 and the second transparent conductive layer 700 on the front and back of the cell 900, and improving the cell light conversion efficiency.

[0113] Specifically, in this embodiment, the axis of the roller 810 is biased toward one side of the battery cell 900, so that the etching slurry 830 on the roller 810 is only coated on the side of the battery cell 900 that needs to be coated (preferably, the etching slurry is coated on the back of the battery cell), ensuring that the other side (the front of the battery cell) is not coated with the etching slurry 830, further ensuring the light-receiving area of ​​the front side of the solar cell, and improving the photoelectric conversion efficiency of the battery cell.

[0114] As a specific embodiment of the present invention, Fig.11 As shown, the battery cell 900 of this embodiment is provided with a chamfer 910 , and both ends of the roller 810 are provided with shapes matching the shape of the chamfer 910 .

[0115] Specifically, in this embodiment, the chamfers 910 are arranged around the cell 900 mainly to eliminate the sharp edges and corners of the silicon wafer edge, reduce stress concentration and dislocation, and thus reduce the risk of mechanical damage and cracking of the silicon wafer. However, due to the existence of the chamfer 910, the roller 810 may not be coated at the chamfer 910 when coating the etching slurry 830. Therefore, in this embodiment, the two ends of the roller 810 are arranged to match the shape of the chamfer 910, so that the etching slurry 830 can also be coated at the chamfer 910, and then the etching slurry 830 can be coated around the entire cell 900, and a closed isolation area is subsequently formed.

[0116] Specifically, the dimensions of the two ends of the roller 810 are larger than the dimension of the middle area 811 , and the dimension gradually increases from the middle area 811 to the end 812 .

[0117] Specifically, since the battery cell 900 of this embodiment is provided with chamfers 910 on all four sides, and the chamfers 910 can be an inclined surface or a curved surface, no matter which form, the size of the chamfer 910 is smaller than the size of other parts. Therefore, in this embodiment, the size of the two tons of the roller 810 is larger than the size of the middle area 811, and the size gradually increases from the middle area 811 to the end 812, thereby ensuring that the etching slurry 830 can also be coated on the chamfer 910 of the battery cell 900. Finally, the battery cell 900 coated with the etching slurry is dried and fully reacted to remove the TCO in the area covered by the etching slurry 830, exposing the second doping layer 500. The schematic diagram of the bottom view of the battery cell after the second transparent conductive layer 700 is etched is shown in FIG. Fig.12 (a) and Fig.12 (b) as shown.

[0118] In addition, the structural shape of the roller can be processed according to the shape of the silicon wafer. The roller structure corresponding to the side of the silicon wafer without chamfer can be straight, and the roller structure corresponding to the silicon wafer with chamfer can have a roller size in the chamfered area larger than that in other areas. Therefore, the structures of a group of symmetrically arranged rollers can be the same or different.

[0119] As a specific embodiment of the present invention, the first etching process includes printing etching paste at the second transparent conductive layer 700 by screen printing, and the printing etching paste specifically includes:

[0120] The etching slurry is printed multiple times on the surface of the second transparent conductive layer 700 by screen printing, and the second transparent conductive layer 700 is etched by the etching slurry to form the first isolation region 711 .

[0121] In this embodiment, screen printing is used to form the isolation region 710 at the second transparent conductive layer 700, without masking the edges around the battery cell, and a smaller size (width b less than 0.3 mm) isolation region 710 can be formed, thereby maximizing the efficiency of the battery.

[0122] Specifically, the specific steps of etching by screen printing in this embodiment may be to place the cell on the printing table, fix the silicon wafer with a vacuum suction cup, take a picture with a digital camera, determine the actual edge position of the cell, convert the signal into a digital signal, and then adjust the screen position and angle so that the longest distance between the printed glue and the edge of the cell is less than 0.1 mm. Finally, the distance c between the edge of the isolation area 710 and the edge of the entire battery is less than 0.1 mm.

[0123] Specifically, since the isolation area 710 of this embodiment can be located on the front side of the battery or on the back side of the battery cell, the first transparent conductive layer 600 located on the front side of the battery is electrically isolated from the second transparent conductive layer 700 located on the back side of the battery to prevent the battery from short-circuiting. Therefore, there are many forms of the isolation area 710. In this embodiment, the isolation area 710 is preferably set at the second transparent conductive layer 700 and the second doping layer 500, and is located at a distance c less than 0.1 mm from the edge of the battery to improve the battery efficiency as much as possible.

[0124] More specifically, the first isolation region 711 of the present embodiment is a square closed region extending parallel to the outer circumference of the substrate 100 .

[0125] As one of the embodiments, the step of printing the second transparent conductive layer 700 multiple times by screen printing may be: printing etching slurry four times on the surface of the second transparent conductive layer 700 by screen printing, and each printing area corresponds to the area where one edge of the closed area is located.

[0126] When the first isolation region 711 is formed by printing four times, one side of the closed region is printed each time. In this embodiment, the printing is more accurate by printing four times, but the printing takes a long time.

[0127] As another specific embodiment, the step of printing the second transparent conductive layer 700 multiple times by screen printing may be: printing the etching slurry twice on the surface of the second transparent conductive layer 700 by screen printing, the first printing area corresponds to the area where two adjacent edges of the closed area are located, and the second printing area corresponds to the area where the remaining two adjacent edges are located.

[0128] In this embodiment, the etching slurry is printed twice on the back side of the second transparent conductive layer 700 by screen printing. First, two adjacent sides of the closed area are printed, and then the remaining two adjacent sides are printed. This can reduce the printing time while ensuring the printing accuracy.

[0129] In this embodiment, in order to accurately print the area during screen printing, the silicon wafer needs to be calibrated, and during the calibration process, only two adjacent sides of the silicon wafer can be calibrated at most once. Therefore, in this embodiment, only two adjacent sides can be printed at most once. Therefore, when the second transparent conductive layer 700 is etched by screen printing, at least two printings are required to complete the entire process.

[0130] In the above embodiment, the closed area of ​​the first isolation region 711 is entirely formed by etching the second transparent conductive layer 700.

[0131] In the above embodiment, ideally, during the screen printing of the etching paste, the ends of the etching paste printed on the edge of the cell overlap with each other, thereby forming a closed area (such as Figure 7 However, due to the tolerance problem of silicon wafer size in the photovoltaic industry, although the screen printing is calibrated by taking a photo with a camera before printing to make the printing position more accurate, there may still be printing deviations, which makes it impossible for the etching slurry printed on the edge of the cell to form a closed area, resulting in the TCO layer on the back side not being completely cut off.

[0132] Based on the above situation, preferably, as a specific embodiment of the present invention, this embodiment further includes, before printing the etching slurry on the second transparent conductive layer 700 by screen printing: when forming the second transparent conductive layer 700, using the supporting portion of the supporting board 1000 as a mask to form a non-coated area 720 where the second transparent conductive layer 700 is not coated; wherein the non-coated area 720 at least partially overlaps with the area to be printed with the etching slurry.

[0133] Specifically, the step of forming the non-coated area 720 may be to use the carrier 1000 to regionally mask the back of the product after preparing the second doping layer 500, and then prepare the first transparent conductive layer 600 and the second transparent conductive layer 700, and then form the non-coated area 720 at the second transparent conductive layer 700. The shape of the contact surface of the mask carrier 1000 with the product matches the shape of the non-coated area 720. Specifically, as Fig.13 and Fig.14 As shown, the carrier 1000 of this embodiment may include a plurality of carrier areas 1100 for placing substrates. In this embodiment, one carrier 1000 includes 24 carrier areas 1100. The four corners of each carrier area 1100 are formed with a carrier portion 1110. The four corners of the substrate 100 are placed at the carrier portion 1110. The first transparent conductive layer 600 and the second transparent conductive layer 700 are then deposited on the product. Finally, the first transparent conductive layer 600 is formed on the front side, and a product having a non-coated area 720 is formed on the back side (such as Fig.15 Generally speaking, the four corners of the silicon wafer are all provided with chamfers 910, and the size of the supporting portion 1110 in this embodiment is larger than the chamfer, so that the four corners of the silicon wafer can be placed at the supporting portion 1110, and the size of the non-coating area 720 formed is also larger than the chamfer, and the chamfer can be basically ignored. The following is a specific description using the example of no chamfers on the four sides of the silicon wafer.

[0134] Specifically, the dimension of the non-coated area 720 in the present embodiment in a direction parallel to the side of the closed area is a, wherein a is greater than or equal to 0.25 mm, and a is less than half of the side length of the substrate 100 .

[0135] Specifically, in this embodiment, due to the tolerance problem of silicon wafer size in the photovoltaic industry, specifically, the tolerance range is generally about 0.25mm. The size of the non-coated area 720 in the direction parallel to the edge of the closed area is designed to be greater than or equal to 0.25mm, but less than half of the side length of the closed area, which not only satisfies the formation of an etched closed area through the wind-coated area during screen printing, but also reduces the area of ​​the non-enclosed area, thereby maximizing the efficiency of the battery.

[0136] Preferably, in this embodiment, the dimension a of the non-coated area 720 in the direction parallel to the side length of the enclosed area is designed to be 0.25 mm. This can reduce the area of ​​the non-enclosed area as much as possible, so that the efficiency of the battery is higher while meeting the etching requirements.

[0137] As a specific embodiment of the present invention, corresponding to each corner of the battery cell, the shape of the supporting portion 1110 may include a triangle (eg Fig.16 (a)), L-shaped (as shown Fig.16 (b)), quadrilateral (as shown Fig.16 (c)) or fan-shaped (as shown Fig.16 (d)).

[0138] Specifically, since the substrate 100 is generally a whole piece or a half piece, the number of the non-coated areas 720 is generally four, and the shape of each non-coated area 720 can be the same or different. Specifically, the shape of each non-coated area 720 can be L-shaped, fan-shaped, triangular or quadrilateral.

[0139] When the four non-coating areas 720 are all quadrilaterals, the shape of the non-coating area 720 may be a square, such as Fig.16 As shown in (c), the side length of each non-coated area 720 can be 0.25 mm. Of course, when the non-coated area 720 is L-shaped, such as Fig.16 (b) Its dimension in the direction parallel to the side length of the closed area may be 0.25 mm. In addition, its width L may be greater than or equal to 0.1 mm and less than 0.25 mm. In this way, the L-shaped non-coated area 720 is smaller than the square non-coated area 720, so that the area of ​​the final isolation area 710 is correspondingly smaller, so that the efficiency of the final battery is also higher.

[0140] Optionally, the shape of the non-coating area 720 of this embodiment can also be selected from a fan shape or a triangle, such as Fig.16 (a) Fig.16 (d). Of course, any other shape that meets the requirements can also be selected. However, no matter what the shape of the non-coated area 720 is, its dimension a in the direction parallel to the side of the isolation area 710 must be greater than or equal to 0.25 mm.

[0141] More specifically, after the non-plating area is formed on the second transparent conductive layer 700, an etching paste (such as Fig.17 As shown in FIG. 1 ). Due to the existence of the non-coated area 720, the etching paste is printed according to the minimum value. Considering the maximum tolerance of the silicon wafer, the etching paste can always pass through the non-coated area 720, and then the first isolation area 711 formed in the second transparent conductive layer 700 can electrically isolate the first transparent conductive layer 600 and the second transparent conductive layer 700. Specifically, the etching paste is printed at the second transparent conductive layer 700 where the non-coated area 720 is formed. Fig.17 shown.

[0142] In this embodiment, when the etching paste is printed on the second transparent conductive layer 700 by screen printing, the printing width can be 10 to 300 μm, preferably less than 0.1 mm. The printing length can be the side length of the substrate 100 minus 0.25 mm, so that after the etching paste etches the second transparent conductive layer 700, the area etched by the etching paste is connected to the non-plating area 720, so that a closed isolation area 710 is formed.

[0143] In the above embodiment, the closed area of ​​the first isolation region 711 is composed of the area formed by etching the second transparent conductive layer 700 and the non-plating area 720 .

[0144] Compared with the mask carrier in the prior art, the above carrier is used to deposit transparent conductive layers on both sides of the cell at the same time, and an isolation area is formed by etching process to achieve the effect of electrical isolation between the front and back sides, which reduces the area blocked by the mask, that is, the light conversion area of ​​the cell is fully used. In addition, compared with the prior art of forming a full-area cell by depositing a transparent conductive layer on one side, the present invention forms an isolation area by a single-sided etching process, which achieves the effect of electrical isolation between the front and back sides, while reducing the number of flipping and shortening the process cycle.

[0145] As another specific embodiment of the present invention, the step of etching the second transparent conductive layer 700 to form the first isolation region 711 in this embodiment may further include:

[0146] By laser etching, the position of the second transparent conductive layer 700 corresponding to the isolation region 710 is scanned at least once to form a first isolation region 711 (eg, Figure 8 shown).

[0147] Generally, when laser etching is used, the excessive laser energy will damage the silicon-based film layer of the solar cell, reducing the efficiency of the solar cell. In this embodiment, laser etching is performed by multiple scanning etching, which can achieve the purpose of etching while avoiding damage to the silicon-based film layer.

[0148] As another specific embodiment of the present invention, the step of etching the second transparent conductive layer 700 to form the first isolation region 711 may include:

[0149] By inkjet printing, etching slurry is sprayed on the position of the second transparent conductive layer 700 corresponding to the isolation area 710 , and the second transparent conductive layer 700 is etched by the etching slurry to form the first isolation area 711 .

[0150] The above three etching methods for the second transparent conductive layer 700 will all completely etch the second transparent conductive layer 700 in the area to be etched, and at the same time, the surface of the second doped layer 500 will be processed, for example, the second doped layer 500 will be pre-treated during the etching slurry heat treatment or laser etching process, which is equivalent to the surface of the second doped layer 500 being pre-treated before etching, so that in the second etching process, it is more conducive to the etching of the second doped layer 500.

[0151] As another specific embodiment of the present invention, in step S400 of this embodiment, the step of etching the second doping layer 500 at a position corresponding to the isolation region 710 may include:

[0152] The second doping layer 500 is etched at a position corresponding to the isolation region 710 by using one of acid etching, alkaline etching, ICP etching or CCP etching.

[0153] In this embodiment, etching is performed at the position corresponding to the second doping layer 500 and the first isolation region 711. Since the second doping layer 500 is located below the second transparent conductive layer 700, the second transparent conductive layer 700 forms the first isolation region 711 after etching, so that when etching the second doping layer 500, the second transparent conductive layer 700 can be directly used as a mask plate for etching, without the need for an additional mask plate for masking, thereby reducing the mask process and improving production efficiency. In addition, since the second transparent conductive layer 700 is used as a mask plate, etching is performed at the position corresponding to the isolation region 710 through the second doping layer 500, and the etching size of the second doping layer 500 is less than or equal to the size of the first isolation region 711, so that the etching area of ​​the second doping layer 500 is smaller, thereby improving the battery efficiency.

[0154] As another specific embodiment of the present invention, the etching process in this embodiment is a one-step etching process, and the second transparent conductive layer 700 and the second doping layer 500 are etched through the one-step etching process to form the isolation region 710 .

[0155] Specifically, in this embodiment, a one-step etching process is directly used to etch the second transparent conductive layer 700 and the second doping layer 500 to obtain the isolation region 710, thereby isolating the motors on both sides of the battery to prevent the battery from short circuiting.

[0156] In this embodiment, the one-step etching process uses a screen printing method to directly etch the second transparent conductive layer 700 and the second doping layer 500 to form an isolation area 710. Compared with using a two-step etching process to form the isolation area 710, the one-step etching process to form the isolation area 710 reduces the process steps, reduces the contamination and damage to the product during the transfer process, and thus improves the quality.

[0157] Specifically, the one-step etching process used in this embodiment includes coating the etching slurry 830 on the second transparent conductive layer 700 by means of a roller 810 , and etching the second transparent conductive layer 700 and the second doping layer 500 by means of the etching slurry 830 to form the isolation region 710 .

[0158] Specifically, the steps of the coating method using the roller 810 in the one-step etching process are consistent with the steps of the coating method using the roller 810 in the first etching process, except that the etching slurry 830 coated on the second transparent conductive layer of the cell 900 by the coating method using the roller 810 in the one-step etching process can etch both the second transparent conductive layer 700 and the second doping layer 500. However, the etching slurry 830 coated on the second transparent conductive layer 700 by the coating method using the roller 810 in the first etching process can only etch the second transparent conductive layer 700, and cannot etch the second doping layer 500. The specific steps of the coating method using the roller 810 refer to the above description, which will not be repeated here.

[0159] As another specific embodiment of the present invention, the one-step etching process of this embodiment may also include printing etching paste on the surface of the second transparent conductive layer 700 multiple times by screen printing, and etching the second transparent conductive layer 700 and the second doping layer 500 by etching the etching paste to form the isolation region 710. The difference between the step of using the screen printing method of the one-step etching process and the step of etching the second transparent conductive layer 700 by screen printing in the first etching process is that: in the one-step etching process, the screen-printed etching paste can not only etch the second transparent conductive layer 700, but also etch the second doping layer 500. When etching is performed by screen printing in the first etching process, the amount and parameters of the printed etching paste can be set so that the etching paste can only etch the second transparent conductive layer 700, and cannot etch the second doping layer 500.

[0160] Specifically, the present invention also provides a heterojunction solar cell, which can be prepared by the above preparation method, so that the utilization rate of the silicon wafer area in the solar cell is increased and the photoelectric conversion efficiency is improved.

[0161] Example 1

[0162] The steps for preparing a solar cell without etching include:

[0163] Step S210, provide an n-type single crystal silicon wafer, place the n-type single crystal silicon wafer with its back side facing upward, into a PECVD carrier, and then the PECVD carrier carries the silicon wafer into a PECVD chamber, and a second intrinsic amorphous or microcrystalline silicon passivation layer (second passivation layer 200) is deposited on the back side of the n-type single crystal silicon wafer by chemical vapor deposition. Due to the wrap-around plating phenomenon during chemical vapor deposition, a second intrinsic amorphous or microcrystalline silicon passivation layer (second passivation layer 200) is also deposited on the side of the silicon wafer.

[0164] Step S220, the sample obtained in step S210 is turned over so that the front side of the sample faces upward, and is placed on a PECVD carrier. The PECVD carrier then carries the sample into a PECVD chamber to deposit a first intrinsic amorphous or microcrystalline silicon passivation layer (first passivation layer 300) and an n-type amorphous or microcrystalline layer (first doping layer 400) on the front side of the n-type single crystal silicon wafer. Similarly, in this process, a first intrinsic amorphous or microcrystalline silicon passivation layer (first passivation layer 300) and an n-type amorphous or microcrystalline layer (first doping layer 400) are also deposited on the side of the silicon wafer.

[0165] In step S230, the sample obtained in step S220 is turned over so that the back side of the sample faces upward, and is placed on a PECVD carrier. The PECVD carrier then carries the sample into a PECVD chamber to deposit a p-type amorphous or microcrystalline layer (second doped layer 500) on the first passivation layer 300 on the back side of the n-type single crystal silicon wafer. Similarly, in this process, a p-type amorphous or microcrystalline layer is also deposited on the side of the first passivation layer 300.

[0166] Among them, in the coating process, since the diffusion coefficient of boron is higher than that of phosphorus, considering the pollution problem caused by doping in the coating process of n-type amorphous or microcrystalline layer and p-type amorphous or microcrystalline layer, as well as factors such as the number of coating flips, the p-type amorphous or microcrystalline layer process is set to the last in the present invention, thereby improving the light conversion efficiency of the battery cell.

[0167] Among them, the deposition conditions of the first intrinsic amorphous or microcrystalline silicon passivation layer (first passivation layer 300) and the second intrinsic amorphous or microcrystalline silicon passivation layer (second passivation layer 200) are: power supply power is 550W, the gas flow ratio of hydrogen to silane (hydrogen dilution ratio) is 12:1, the pressure is 70pa, and the substrate temperature during deposition is 220°C.

[0168] Among them, the deposition conditions of the n-type amorphous or microcrystalline layer (first doped layer 400) are: power supply power is 400W, hydrogen and silane gas flow ratio (hydrogen dilution ratio) is 4:1, phosphine and silane gas flow ratio (phosphorus to silicon ratio) is 1:100, pressure is 40Pa, and substrate temperature during deposition is 210°C.

[0169] Among them, the deposition conditions of the p-type amorphous or microcrystalline silicon layer (second doped layer 500) are: power supply power is 500W, the gas flow ratio of hydrogen to silane (hydrogen dilution ratio) is 5:1, the gas flow ratio of TMB to silane is 3:97, the pressure is 30Pa, and the temperature of the substrate during deposition is 180°C.

[0170] Step S240, the sample obtained in step S230 is placed with the front side facing upwards, and the carrier carries the sample into the PVD magnetron coating equipment to perform TCO (transparent conductive layer) deposition. The first transparent conductive layer 600 is deposited on the n-type amorphous or microcrystalline layer (the first doped layer 400), and the second transparent conductive layer 700 is deposited on the p-type amorphous or microcrystalline silicon layer (the second doped layer 500). Similarly, the first transparent conductive layer 600 and the second transparent conductive layer 700 are also deposited on the side of the sample at this time.

[0171] The conditions for depositing TCO are: room temperature, introduction of argon and oxygen, the gas flow ratio of argon to oxygen is set at 50:1, the chamber pressure is maintained at 0.7 Pa, and the transparent conductive material is ITO material or other non-indium-based TCO materials, such as tin oxide-based TCO.

[0172] Specifically, the substrate 100 of the solar cell prepared by the above preparation method can be an n-type single crystal silicon wafer, and the thickness of the silicon wafer can be 110 to 180 μm. The first passivation layer 300 and the second passivation layer 200 can be intrinsic amorphous or microcrystalline silicon passivation layers. And the thickness of the first passivation layer 300 and the second passivation layer 200 can both be 7 nm. The first doped layer 400 can be an n-type amorphous or microcrystalline layer, and the thickness of the first doped layer 400 can be 30 nm. The second doped layer 500 can be a p-type amorphous or microcrystalline layer, and the thickness can be 35 nm. The thickness of the first transparent conductive layer 600 and the second transparent conductive layer 700 can both be 80 nm.

[0173] During this process, as each film layer is deposited, the corresponding material is deposited on the side, so conductivity will appear between the front and back of the silicon wafer.

[0174] Then, the second transparent conductive layer 700 and the second doping layer 500 are etched by an etching process to form an isolation region 710 on the back side of the cell to electrically isolate the first transparent conductive layer 600 and the second transparent conductive layer 700 .

[0175] Example 2

[0176] Steps S210 to S240 in this embodiment are consistent with those in Embodiment 1, and after step S240, the following steps are further included:

[0177] The cell 900 prepared in step S240 is positioned and transported to the coating station of the roller 810. The roller 810 is controlled to move until the roller 810 contacts the periphery of the cell 900, and then the etching slurry 830 is coated on the periphery of the cell 900.

[0178] Specifically, two sets of two rollers 810 disposed opposite to each other are used to simultaneously coat the surroundings of the second transparent conductive layer 700, and the specific steps include:

[0179] Four rollers 810 are respectively arranged around the rolling station, and each roller 810 is matched with a scraper 820, and the etching slurry 830 at the corresponding roller 810 is controlled to be at a suitable thickness by the scraper 820. The positioned battery cell 900 is transported to the rolling station, and the four rollers 810 are controlled to move around the battery cell 900 to be close to the battery cell 900, so as to coat the etching slurry 830 at the edge of the battery cell 900. After the coating is completed, it is dried and fully reacted to remove the TCO in the area covered by the etching slurry 830, exposing the p-type amorphous or microcrystalline silicon layer (the second doping layer 500).

[0180] Alternatively, specifically, a group of two rollers 810 disposed opposite to each other are used to coat the second transparent conductive layer 700, and the specific steps include:

[0181] First, the etching slurry 830 at the corresponding roller 810 is controlled to a suitable thickness by using a scraper 820, and the positioned cell 900 is transported to the roller coating station, and the two rollers 810 are controlled to move to contact a pair of oppositely disposed side edges of the cell 900, and first a group of opposite sides of the second transparent conductive layer 700 are coated. After heat treatment, the cell 900 is horizontally rotated 90°, and then another group of opposite sides of the second transparent conductive layer 700 are coated. After coating, drying and sufficient reaction are performed to remove the TCO in the area covered by the etching slurry 830, exposing the p-type amorphous or microcrystalline silicon layer (second doped layer 500).

[0182] In this embodiment, the carrier board involved in the present invention can also be used to deposit a transparent conductive layer on both sides simultaneously. The surface of the cell to be coated with the etching slurry is on the same side as the supporting surface of the carrier board, that is, only the back side of the cell is etched to form an isolation area, thereby ensuring the use area of ​​the light-receiving surface of the front side of the cell and improving the photoelectric conversion efficiency.

[0183] Example 3

[0184] Due to the tolerance problem of silicon wafer size in the photovoltaic industry, the size of the screen printing stencil can only be set according to the minimum size during screen printing. This will result in large silicon wafers not forming a closed etching area after printing the etching slurry, and thus cannot electrically isolate the front and back sides of the battery.

[0185] In this embodiment, before etching the second transparent conductive layer 700 by screen printing, it is necessary to first form a non-coated area 720. In the steps of preparing the solar cell in this embodiment, steps S210, S220 and S230 are consistent with those in Embodiment 1, and after step S230, the following steps are further included:

[0186] The sample prepared in step S230 is placed with the front side facing upwards on the carrier 1000, and the four corners of the sample are supported by the supporting part 1110 of the carrier 1000. The mask width (i.e., the dimension parallel to the edge of the sample) is 0.25 mm. The carrier 1000 carries the sample into the PVD magnetron coating equipment for TCO deposition. The first transparent conductive layer 600 is deposited on the n-type amorphous or microcrystalline layer (the first doped layer 400) and the side of the silicon wafer, and the second transparent conductive layer 700 is deposited on the p-type amorphous or microcrystalline silicon layer (the second doped layer 500) and the side of the silicon wafer. The conditions for depositing TCO are: room temperature, argon and oxygen are introduced, the gas flow ratio of argon to oxygen is set at 50:1, the chamber pressure is maintained at 0.7 Pa, and the transparent conductive material is ITO material or other non-indium-based TCO materials, such as tin oxide-based TCO.

[0187] The steps of etching the second transparent conductive layer 700 by four-step screen printing include:

[0188] Place the sample with the back side facing up after the non-coating area mask is formed into the non-coating area 720, put it into the sample conveyor belt of the screen printing equipment, place the sample on the first sample stage of the screen printing, and after taking pictures with the camera, adjust the screen printing screen to print the etching paste for etching TCO on the second transparent conductive layer 700 on the back of the sample. For example, the etching paste printing pattern is a rectangle with a length of the standard length of the side of silicon wafer A minus 0.25mm and a width of 10 microns to 300 microns. Then repeat the above steps to complete the printing on the BCD side in turn. After the printing is completed, dry and react fully to remove the TCO in the area covered by the paste, exposing the p-type amorphous or microcrystalline silicon layer (the second doped layer 500).

[0189] The steps of etching the second transparent conductive layer 700 by two-step screen printing include:

[0190] Place the back of the battery facing upwards on the sample conveyor belt of the screen printing equipment, place the sample on the first sample stage of the screen printing, take a picture with the camera, adjust the screen printing screen, and print the etching paste for etching TCO on the second transparent conductive layer 700 on the back of the battery, such as Fig.15 As shown, the etching paste printing pattern is an L square (printed simultaneously on the AB side), where the length of the A side of the cell is the standard length minus 0.25mm. The width b is 10μm to 300μm. The length of the B side of the cell is the standard length minus 0.25mm. The width b is 10μm to 300μm. Then repeat the above steps to print the etching paste on the CD side at the same time. After printing the etching paste, dry and fully react to remove the TCO in the area covered by the etching paste, exposing the p-type amorphous or microcrystalline silicon layer (the second doping layer 500).

[0191] Based on the above scheme, it can be known that due to the existence of the non-coated area 720, no matter how many times the etching slurry is printed, the size of the isolation area 710 can be supplemented by the non-coated area 720, ensuring that after the etching slurry is etched, the first transparent conductive layer 600 on the front and the second transparent conductive layer 700 on the back are completely electrically isolated.

[0192] Example 4

[0193] The first few steps of the steps for preparing the solar cell are consistent with those of Example 1, but in this embodiment, the second transparent conductive layer 700 is etched by laser. In this embodiment, the second transparent conductive layer 700 can be etched to form an isolation region, and then electrodes are formed on the first transparent conductive layer 600 and the second transparent conductive layer 700. Alternatively, electrodes are formed on the first transparent conductive layer 600 and the second transparent conductive layer 700, and then the second transparent conductive layer 700 is etched to form an isolation region. The specific process can be adjusted according to requirements and will not be further described here.

[0194] Specifically, in this embodiment, the steps of etching the second transparent conductive layer 700 by laser include:

[0195] Pre-cleaning: The incoming sheet is firstly transported in CV and cleaned by a brush to clean the sample prepared in Example 1;

[0196] Visual positioning: The CV conveyor performs rough positioning of the clamping piece, and then the product is transferred to the marking area through a swing arm or linear motor, and multiple cameras perform precise positioning;

[0197] Laser etching: The ion air knife blows air at the same time, and the dust generated by laser etching is taken away by vacuuming;

[0198] Post-cleaning: After etching is completed, the swing arm or linear motor transfers the sample to the CV, and then it is cleaned by the ultrasonic dust removal device during the CV transmission process;

[0199] Defect detection: After cleaning, the chip source undergoes IV test efficiency and IR test for leakage detection.

[0200] The laser wavelength used in this embodiment can be 193nm~355nm. The power can be 0.5W~30W. The size and shape of the light plate can be 20μm~100μm round or square. The frequency can be 500KHZ~20MHZ. The scanning speed is 2000㎜ / s~60000㎜ / s. The pulse width is femtosecond or picosecond level. The laser etching in this embodiment involves DOE shaping, the spot size and shape can be customized, and the spot uniformity is ≥95%. High-precision visual positioning system, laser scanning accuracy ±15μm, edge engraving line width ≤100μm.

[0201] Example 5

[0202] The first few steps in the steps of preparing the solar cell are consistent with those in Example 1, and inkjet printing is used when etching the second transparent conductive layer 700. The etching slurry is printed on the second transparent conductive layer 700 by inkjet printing, and then dried and fully reacted to remove the TCO in the area covered by the etching slurry, exposing the p-type amorphous or microcrystalline silicon layer (the second doped layer 500).

[0203] Example 6

[0204] After etching the second transparent conductive layer 700 using the methods in Embodiment 2, Embodiment 3, Embodiment 4 and Embodiment 5, the second doping layer 500 is etched using acid etching or alkaline etching. The specific steps may include:

[0205] The samples in which the second transparent conductive layer 700 is etched and the p-type amorphous or microcrystalline silicon layer (the second doped layer 500) is exposed in Example 2, Example 3, Example 4 and Example 5 are placed in an alkaline etching solution, wherein the alkaline etching solution contains potassium hydroxide or sodium hydroxide, and the mass fraction of the solution is 1% to 20%. The solution temperature is room temperature to 80° C., the reaction time is 1s to 5min, and the etching speed is controlled to be 1 to 30nm / s.

[0206] In another embodiment, the sample with the edge TCO removed and the p-type amorphous or microcrystalline silicon layer (the second doped layer 500) exposed is subjected to an acid pickling etchant, wherein the acid pickling etchant contains hydrofluoric acid and a deboronizing additive, the solution temperature is room temperature to 60°C, the reaction time is 1s to 5min; and the etching speed is controlled to be 1 to 30nm / s.

[0207] In the above acid etching or alkaline etching step, the process parameters need to be precisely controlled to ensure that the exposed second doped layer 500 is etched cleanly, while retaining the second doped layer 500 in other areas and without damaging the second passivation layer 200 .

[0208] In the present embodiment, after etching the second first isolation region 711 of the second transparent conductive layer 700 in Embodiment 2, 3, 4 or 5, the surface of the second doped layer 500 is pretreated during the steps of Embodiment 2, 3 or 4, thereby improving the etching efficiency of the second doped layer 500 in the second etching process.

[0209] Example 7

[0210] After the second transparent conductive layer 700 is etched by the method in Embodiment 2, Embodiment 3, Embodiment 4 or Embodiment 5, and the second transparent conductive layer 700 is used as a mask, the p-type amorphous or microcrystalline silicon layer (second doped layer 500) is etched by ICP or CCP process, the specific steps include:

[0211] The sample after etching of the second transparent conductive layer 700 obtained by the steps of Example 2, Example 3, Example 4 or Example 5 is placed in a carrier and introduced into a chamber with the carrier, and one or more reaction gases of SF6, NF3, CF4 are introduced, and argon is introduced to maintain the chamber pressure, and the chamber pressure is maintained at 0.01-1T, the power is 100W-2000W, and the etching thickness of the p-type amorphous or microcrystalline silicon layer (the second doped layer 500) is precisely controlled by different time. After the etching process is completed, the film is collected and screen printed.

[0212] The above-mentioned ICP or CCP process to remove the second doped layer 500 requires precise control of process parameters to ensure that the exposed p-type amorphous or microcrystalline silicon layer (second doped layer 500) is etched cleanly, while retaining the second doped layer 500 in other areas and without damaging the second passivation layer 200.

[0213] In the present embodiment, after etching the second first isolation region 711 of the second transparent conductive layer 700 in Embodiment 2, 3, 4 or 5, the surface of the second doped layer 500 is pretreated during the steps of Embodiment 2, 3, 4 or 5, thereby improving the etching efficiency of the second doped layer 500 in the second etching process.

[0214] Example 8

[0215] The steps in this embodiment are consistent with those in Embodiment 2, except that, in this embodiment, after the etching slurry is coated on the second transparent conductive layer 700 by a roll coating process, the etching slurry etches both the second transparent conductive layer 700 and the second doping layer 500 to form an isolation region 710. There is no need to etch the second doping layer 500 later. By etching the second transparent conductive layer 700 and the second doping layer 500 in one step by a one-step etching method to obtain the isolation region 710, the etching process steps can be reduced, the damage and contamination to the product during the transfer of the product can be reduced, and the quality can be improved.

[0216] Example 9

[0217] The steps in this embodiment are consistent with those in Embodiment 3, except that, in this embodiment, after screen printing the etching slurry on the second transparent conductive layer 700 by screen printing through a one-step etching process, the etching slurry etches both the second transparent conductive layer 700 and the second doping layer 500 to form the isolation region 710. There is no need to etch the second doping layer 500 later. By etching the second transparent conductive layer 700 and the second doping layer 500 in one step to obtain the isolation region 710, the etching process steps can be reduced, the damage and contamination to the product during the transfer of the product can be reduced, and the quality can be improved.

[0218] At this point, those skilled in the art should recognize that, although multiple exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications that conform to the principles of the present invention can still be directly determined or derived based on the content disclosed in the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and recognized as covering all these other variations or modifications.

Claims

1. A method for preparing a heterojunction solar cell, characterized in that: include: providing a substrate; forming a first passivation layer covering the front surface of the substrate and a first doping layer covering the first passivation layer on the front surface of the substrate, and forming a second passivation layer covering the substrate and a second doping layer covering the second passivation layer on the back surface of the substrate; forming a first transparent conductive layer covering the first doping layer and a second transparent conductive layer covering the second doping layer on the first doping layer and the second doping layer; forming an isolation region on the second transparent conductive layer and the second doped layer by an etching process; The etching process includes coating the etching slurry on the second transparent conductive layer by roller coating, and etching by using the etching slurry; The axis of the roller is biased toward the side of the plane where the substrate is located and where the etching slurry needs to be coated; The substrate has a chamfer, and the two ends of the roller are set to a shape matching the chamfer shape, and an etching slurry is coated on the edges and chamfers of the substrate, and the second transparent conductive layer is etched by the etching slurry to form a closed isolation area, thereby isolating the first transparent conductive layer and the second transparent conductive layer; or The etching process includes printing etching slurry on the second transparent conductive layer by screen printing, and etching by using the etching slurry; Before printing the etching slurry on the second transparent conductive layer by screen printing, the method further includes: when forming the second transparent conductive layer, using the supporting portion of the supporting board as a mask to form a non-coated area where the second transparent conductive layer is not coated; wherein the non-coated area at least partially overlaps with the area to be screen-printed; and etching the second transparent conductive layer by the etching slurry to form a closed isolation area, thereby isolating the first transparent conductive layer and the second transparent conductive layer.

2. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The etching process includes a first etching process and a second etching process. The second transparent conductive layer is etched by the first etching process to form a first isolation region. The second doping layer is etched at a position corresponding to the first isolation region by the second etching process to form a second isolation region. The first isolation region and the second isolation region form the isolation region.

3. The method for preparing a heterojunction solar cell according to claim 2, characterized in that: The first etching process includes coating an etching slurry on the second transparent conductive layer by roller coating, and etching the second transparent conductive layer by using the etching slurry to form the first isolation region; The step of coating the etching slurry by roller coating comprises: Using two sets of two rollers arranged opposite to each other to simultaneously coat the surroundings of the second transparent conductive layer; or A set of two rollers arranged opposite to each other are used to first coat a set of opposite edges of the second transparent conductive layer, and then the other set of opposite edges of the second transparent conductive layer is coated after the cell is horizontally rotated 90°.

4. The method for preparing a heterojunction solar cell according to claim 2, characterized in that: The first etching process includes printing etching slurry on the second transparent conductive layer by screen printing, and the printing etching slurry specifically includes: The etching slurry is printed on the surface of the second transparent conductive layer for multiple times by screen printing, and the second transparent conductive layer is etched by the etching slurry to form the first isolation region.

5. The method for preparing a heterojunction solar cell according to claim 4, characterized in that: The first isolation region is a square closed region extending parallel to the periphery of the substrate; Printing the etching slurry four times on the surface of the second transparent conductive layer by screen printing, wherein each printing area corresponds to an area where one of the edges of the closed area is located; or The etching slurry is printed twice on the surface of the second transparent conductive layer by screen printing, the first printing area corresponds to the area where two adjacent edges of the closed area are located, and the second printing area corresponds to the area where the remaining two adjacent edges are located.

6. The method for preparing a heterojunction solar cell according to claim 2, characterized in that: The second etching process includes adopting one of wet etching, ICP etching or CCP etching, using the second transparent conductive layer as a mask, and etching the second doped layer at a position corresponding to the first isolation region to form the second isolation region.

7. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The etching process is a one-step etching process, and the second transparent conductive layer and the second doping layer are etched by the one-step etching process to form the isolation region.

8. The method for preparing a heterojunction solar cell according to claim 7, characterized in that: The one-step etching process includes coating an etching slurry on the second transparent conductive layer by roller coating, and etching the second transparent conductive layer and the second doping layer by using the etching slurry to form the isolation region; The step of coating the etching slurry by roller coating specifically includes: Using two sets of two rollers arranged opposite to each other to simultaneously coat the surroundings of the second transparent conductive layer; or A set of two rollers arranged opposite to each other are used to first coat a set of opposite edges of the second transparent conductive layer, and then the other set of opposite edges of the second transparent conductive layer is coated after the cell is horizontally rotated 90°.

9. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: Before the roller coats the cell with etching slurry, the method further includes: The scraper is used to control the amount of etching slurry on the surface of the roller, thereby controlling the width of the etching slurry coated on the second transparent conductive layer.

10. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The dimensions of the two ends of the roller are larger than the dimension of the middle area.

11. The method for preparing a heterojunction solar cell according to claim 7, characterized in that: The isolation area includes a square closed area formed along the periphery of the substrate; The one-step etching process includes printing etching slurry on the surface of the second transparent conductive layer multiple times by screen printing, and etching the second transparent conductive layer and the second doping layer by using the etching slurry to form the isolation region.

12. The method for preparing a heterojunction solar cell according to claim 11, characterized in that: Printing the etching slurry four times on the surface of the second transparent conductive layer by screen printing, wherein each printing area corresponds to an area where one of the edges of the closed area is located; or The etching slurry is printed twice on the surface of the second transparent conductive layer by screen printing, the first printing area corresponds to two adjacent sides of the closed area, and the second printing area corresponds to the remaining two adjacent sides.

13. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The number of the non-coating areas is four, which are respectively located at four corner areas of the substrate.

14. The method for preparing a heterojunction solar cell according to claim 5 or 11, characterized in that: The dimension of each of the non-coated areas in a direction parallel to the side of the closed area is a, a is greater than or equal to 0.25 mm, and a is less than half of the side length of the substrate.

15. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The shape of each of the supporting parts includes L-shape, fan-shape, triangle or quadrilateral.

16. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The width b of the isolation region is less than 0.3 mm.

17. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The distance c between the isolation region and the edge of the substrate is less than 0.1 mm.

18. A heterojunction solar cell, characterized in that: The method is prepared by the method described in any one of claims 1 to 17.

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