A dual communication multi-node transceiver system

Abstract

The invention discloses a dual communication multi-node transceiver system, which uses RS485 to realize a communication system of one host and multiple slaves, saves design costs, and the system can realize the execution of various types of instructions and information interaction. A dual communication system that realizes two-way RS485 communication in both the host and the slave improves the communication risk resistance and ensures that the host and the slave can communicate normally in a complex environment. Based on the Manchester protocol, there is no information such as a start bit and a check bit, and multiple bytes of data can be transmitted, with high transmission efficiency. The communication rate is high, and the baud rate is 20Mbps.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a multi-node, multi-functional, high-efficiency dual-communication multi-node transceiver system based on FPGA and Manchester protocol. Background Art

[0002] At present, the communication between avionics products basically uses RS485 chips to implement UART protocol data transmission.

[0003] The advantages of this method are: 1. Half-duplex working mode, strong anti-interference ability; 2. Only two data lines are needed to transmit data, saving the number of communication lines; 3. No clock signal is required; 4. There is a parity bit to facilitate communication error checking; 5. Only the receiving end and the sending end need to set the data packet structure to achieve stable communication.

[0004] The disadvantages of this method are: 1. The data frame supports a maximum of 9 bits of data, and the data transmission efficiency is low; 2. The data transmission baud rate is low; 3. It does not support the master-slave system with multiple hosts or multiple slaves. Summary of the invention

[0005] In view of the above problems, the present invention provides a dual-communication multi-node transceiver system for overcoming the above problems or at least partially solving the above problems.

[0006] The present invention provides the following scheme:

[0007] A dual-communication multi-node transceiver system, comprising:

[0008] An FPGA device, wherein the FPGA device comprises a functional logic module, a first interface IP core and a second interface IP core, wherein the first interface IP core and the second interface IP core are independent of each other and are both connected to the functional logic module;

[0009] A first RS485 chip and a second RS485 chip, wherein the first RS485 chip is connected to the first interface IP core, and the second RS485 chip is connected to the second interface IP core; the first RS485 chip is connected to a first bus, and the second RS485 chip is connected to a second bus;

[0010] an external connector, the first bus and the second bus are both connected to the external connector; the external connector is used to be connected to a host and a plurality of slaves; the host is used to form a transmitting end, and the slaves are used to form a receiving end;

[0011] The functional logic module is used to generate a plurality of communication instructions, each of which is issued at an interval of 10 milliseconds, and each 10 milliseconds is divided into 10 time slices of 1 millisecond, so that each receiving end is assigned a time slice with its own address attribute when sending and receiving data;

[0012] The first bus and the second bus are used to output the communication instructions to the multiple slaves at the same time, and each of the multiple slaves determines the target bus for receiving data according to the data update identification decision receiving logic fed back by the first interface IP core and the second interface IP core; the first interface IP core and the second interface IP core are also used to send return status data to the host through the first bus and the second bus at the same time.

[0013] Preferably: the communication instructions include a handshake message instruction, a request to receive data message instruction, and a request to send message instruction;

[0014] The handshake message instruction is used by the sending end to send a handshake message to each node. When each node receives a correct handshake message, it returns a handshake success message; otherwise, it returns a handshake failure message;

[0015] After receiving the request to receive data message instruction, each node enters the data receiving state;

[0016] After receiving the message sending request instruction, each node returns status information to the sending end.

[0017] Preferably: the decision receiving logic includes preferentially receiving the data transmitted by the first bus, and receiving the second bus data when the first bus data update flag is invalid.

[0018] Preferably: the first interface IP core and the second interface IP core are both used for encoding and decoding according to the Manchester protocol;

[0019] The decoded data is parsed into various instruction types according to the communication protocol; and the data valid flag is identified.

[0020] Preferably: it also includes a time signal output circuit, which is connected to the first interface IP core and the second interface IP core; the time signal output circuit is used to provide the same clock signal and / or reset signal to each node.

[0021] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0022] A dual-communication multi-node transceiver system provided in an embodiment of the present application utilizes RS485 to implement a communication system of one host and multiple slaves, saving design costs, and the system can realize the execution of various types of instructions and information interaction. A dual communication system that implements two-way RS485 communication in both the host and the slave improves the communication risk resistance and ensures that the host and the slave can communicate normally in a complex environment. Based on the Manchester protocol, there is no start bit, check bit and other information, and multiple bytes of data can be transmitted, with high transmission efficiency. A high communication rate is used, and the baud rate is 20Mbps.

[0023] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 It is a framework diagram of a dual-communication multi-node transceiver system provided by an embodiment of the present invention;

[0026] Figure 2 is a bus message timing diagram provided by an embodiment of the present invention;

[0027] Figure 3 This is a bus message time slot diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0029] See also Figure 1 , is a dual communication multi-node transceiver system provided by an embodiment of the present invention, such as Figure 1 As shown, the system may include:

[0030] An FPGA device, wherein the FPGA device comprises a functional logic module, a first interface IP core and a second interface IP core, wherein the first interface IP core and the second interface IP core are independent of each other and are both connected to the functional logic module;

[0031] A first RS485 chip and a second RS485 chip, wherein the first RS485 chip is connected to the first interface IP core, and the second RS485 chip is connected to the second interface IP core; the first RS485 chip is connected to a first bus, and the second RS485 chip is connected to a second bus;

[0032] an external connector, the first bus and the second bus are both connected to the external connector; the external connector is used to be connected to a host and a plurality of slaves; the host is used to form a transmitting end, and the slaves are used to form a receiving end;

[0033] The functional logic module is used to generate a plurality of communication instructions, each of which is issued at an interval of 10 milliseconds, and each 10 milliseconds is divided into 10 time slices of 1 millisecond, so that each receiving end is assigned a time slice with its own address attribute when sending and receiving data;

[0034] The first bus and the second bus are used to output the communication instructions to the multiple slaves at the same time, and each of the multiple slaves determines the target bus for receiving data according to the data update identification decision receiving logic fed back by the first interface IP core and the second interface IP core; the first interface IP core and the second interface IP core are also used to send return status data to the host through the first bus and the second bus at the same time.

[0035] The dual-communication multi-node transceiver system provided in the embodiment of the present application can realize communication between one host and multiple slaves, and the system can realize the execution of various types of instructions and information interaction; at the same time, it realizes dual-channel communication with one backup channel in both the host and the slave.

[0036] In specific implementation, the embodiment of the present application may provide that the communication instruction includes a handshake message instruction, a request to receive data message instruction, and a request to send message instruction;

[0037] The handshake message instruction is used by the sending end to send a handshake message to each node. When each node receives a correct handshake message, it returns a handshake success message; otherwise, it returns a handshake failure message;

[0038] After receiving the request to receive data message instruction, each node enters the data receiving state;

[0039] After receiving the message sending request instruction, each node returns status information to the sending end.

[0040] The first bus and the second bus provided in the embodiment of the present application can simultaneously transmit and receive data. When each slave receives a communication instruction, it can select to receive the communication instruction of one of the channels according to the decision receiving logic. In a specific implementation, the decision receiving logic includes preferentially receiving the data transmitted by the first bus, and receiving the data of the second bus when the data update flag of the first bus is invalid.

[0041] In a specific implementation, the embodiment of the present application may provide that the first interface IP core and the second interface IP core are both used for encoding and decoding according to the Manchester protocol;

[0042] The decoded data is parsed into various instruction types according to the communication protocol; and the data valid flag is identified.

[0043] It also includes a time signal output circuit, which is connected to the first interface IP core and the second interface IP core; the time signal output circuit is used to provide the same clock signal and / or reset signal to each node.

[0044] The system provided in the embodiments of the present application is described in detail below.

[0045] The system provided in the embodiment of the present application is based on FPGA to implement a Manchester protocol communication system with one host and multiple slaves at a high speed and dual communication.

[0046] Manchester protocol transceiver communication is implemented based on FPGA, thus realizing a high-speed, multi-instruction type, multi-node two-way communication system.

[0047] Specific implementations include:

[0048] 1. A multi-node communication transceiver system with one host sending and multiple slaves.

[0049] The system provided in the embodiment of the present application uses FPGA to realize high-speed, multi-instruction type, multi-node RS485 transceiver communication. The specific implementation process is as follows:

[0050] Multi-node communication protocol: This system slices the data on the communication bus. Each instruction is sent at an interval of 10ms, and each 10ms is divided into 10 1ms time slices. Each receiving end will be assigned a time slice with its own address attribute when sending and receiving data, ensuring that each receiving end communicates normally and does not affect each other. Thus, multi-node sending and receiving communication is realized. The bus message timing diagram is shown in the figure below. Figure 2 As shown, the bus message time slot diagram is as follows Figure 3 shown.

[0051] Communication instruction type: The system uses different types of instructions to implement various instructions and data interactions between the sender and the receiver. Communication instruction types can be divided into three categories: handshake messages, request to receive data messages, and request to send messages:

[0052] ①Handshake message: used by the sender to send handshake messages to each node. When each node receives the correct handshake message, it returns a handshake success message. Otherwise, it returns a handshake failure message.

[0053] ② Request to receive data message: After receiving the message instruction, each node enters the data receiving state;

[0054] ③ Request to send message: After receiving the message instruction, each node returns various status information to the sender.

[0055] 2. Dual communication mechanism In order to improve the anti-risk capability of communication, the system realizes the independent operation of dual redundant control buses A and B. The FPGA of each terminal uses an independent IP core to control the message sending and receiving. Figure 1 shown.

[0056] (1) Data transmission and reception logic:

[0057] During operation, the A and B buses output valid data at the same time. The receiving end decides the receiving logic based on the "data update flag" fed back by the two IP cores, and receives the A bus data first. When the A bus data update flag is invalid, the B bus data is used.

[0058] (2) Data sending logic:

[0059] Independent IPs return status data to the sender through A and B buses at the same time, and IP cores run independently and have independent caches;

[0060] (3) Data synchronization:

[0061] Each node uses the same time signal (clock signal, reset signal) to send and receive data to ensure bus data synchronization;

[0062] (4) IP core logic:

[0063] The main functions of the IP core include:

[0064] ①Encode and decode according to the Manchester protocol;

[0065] ② The decoded data is parsed into various instruction types according to the communication protocol;

[0066] ③ Identify the data valid flag.

[0067] In summary, the dual-communication multi-node transceiver system provided by the present application uses RS485 to implement a communication system of one host and multiple slaves, saving design costs, and the system can realize the execution of various types of instructions and information interaction. A dual communication system that implements two-way RS485 communication in both the host and the slave improves the communication risk resistance and ensures that the host and the slave can communicate normally in a complex environment. Based on the Manchester protocol, there is no start bit, check bit and other information, and multiple bytes of data can be transmitted, with high transmission efficiency. Use a high communication rate, with a baud rate of 20Mbps.

[0068] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0069] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0070] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work.

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A dual-communication multi-node transceiver system, characterized in that: include: An FPGA device, the FPGA device comprising a functional logic module, a first interface IP core and a second interface IP core, the first interface IP core and the second interface IP core are independent of each other and are both connected to the functional logic module; the first interface IP core and the second interface IP core are both used for encoding and decoding according to the Manchester protocol; the decoded data is parsed into various instruction types according to the communication protocol; and the data valid flag is identified; A first RS485 chip and a second RS485 chip, wherein the first RS485 chip is connected to the first interface IP core, and the second RS485 chip is connected to the second interface IP core; the first RS485 chip is connected to a first bus, and the second RS485 chip is connected to a second bus; an external connector, the first bus and the second bus are both connected to the external connector; the external connector is used to be connected to a host and a plurality of slaves; the host is used to form a transmitting end, and the slaves are used to form a receiving end; The functional logic module is used to generate a number of communication instructions, each of which is issued at an interval of 10 milliseconds, and each 10 milliseconds is divided into 10 time slices of 1 millisecond, so that each receiving end will be assigned a time slice with its own address attribute when sending and receiving data; the communication instructions include a handshake message instruction, a request to receive data message instruction, and a request to send message instruction; the handshake message instruction is used by the sending end to send a handshake message to each node, and when each node receives the correct handshake message, it returns a handshake success message; Otherwise, a handshake failure message is returned; After receiving the request to receive data message instruction, each node enters the data receiving state; after receiving the request to send message instruction, each node returns the state information to the sending end; The first bus and the second bus are used to output the communication instruction to the plurality of slaves at the same time, and the plurality of slaves each update the identification decision receiving logic according to the data feedback from the first interface IP core and the second interface IP core to determine the target bus for receiving data; The decision receiving logic includes preferentially receiving data transmitted by the first bus, and receiving data transmitted by the second bus when the first bus data update flag is invalid; the first interface IP core and the second interface IP core are also used to send return status data to the host through the first bus and the second bus at the same time.

2. The dual communication multi-node transceiver system according to claim 1, characterized in that: It also includes a time signal output circuit, which is connected to the first interface IP core and the second interface IP core; the time signal output circuit is used to provide the same clock signal and / or reset signal to each node.

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