A processor lockstep apparatus and related components

Abstract

The application discloses a processor lockstep device and related components, and relates to the field of processors, comprising a lockstep module and an abstract generation module corresponding to each processor. Each abstract generation module generates abstract data according to the running data of each processor. The lockstep module compares whether the abstract data is consistent to determine whether each processor is working normally. The abstract generation module extracts abstract data from the running data of each processor, and the lockstep is completed based on the abstract data. On the basis of realizing the judgment of whether each processor is working normally, the amount of data to be compared in the lockstep process is reduced, and the integrity of the running data of each processor to be transmitted is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processors, in particular to a processor lockstep device and related components. BACKGROUND

[0002] In systems such as aircraft and automobiles which have high safety requirements, multiple processors running the same application program are usually provided, that is, processor redundancy technology is used to improve the reliability of the system. In the related art, lockstep technology is often used to determine whether each processor in the system is reliably running, which is achieved by comparing all the data output by each processor in real time to determine whether they are consistent. With the advancement of semiconductor technology, the frequency and bus bandwidth of the processor are also increasing, resulting in an increasing amount of data output by the processor, making it more and more difficult to determine whether each processor in the system is reliably running using the lockstep technology in the related art. SUMMARY

[0003] The purpose of the present application is to provide a processor lockstep device and related components that reduce the amount of data that needs to be compared during the lockstep process while ensuring the integrity of the running data of each processor being transmitted, based on the determination of whether each processor is working normally.

[0004] To solve the above technical problems, the present application provides a processor lockstep device, comprising a lockstep module and a digest generation module corresponding to each processor;

[0005] Each digest generation module is electrically connected to each processor, and the lockstep module is electrically connected to each digest generation module;

[0006] The digest generation module is configured to generate digest data based on the running data of each processor;

[0007] The lockstep module is configured to compare each digest data to determine whether each processor is working normally.

[0008] Optionally, the number of lockstep modules is consistent with the number of processors;

[0009] Each lockstep module is configured to compare each digest data to determine whether each processor is working normally.

[0010] Optionally, each digest generation module is electrically connected to each processor through a bus; wherein the data transmitted by the bus is the running data of each processor electrically connected to each digest generation module.

[0011] Optionally, the summary generation module is specifically configured to acquire bus transmission data connected to itself, perform padding processing on the bus transmission data to obtain padded bus transmission data, perform grouping processing on the padded bus transmission data to obtain grouped bus transmission data, perform data expansion on the grouped bus transmission data to obtain expanded bus transmission data, and perform compression processing on the expanded bus transmission data by using a compression function to extract the summary data from the bus transmission data; wherein the bus transmission data is running data of each processor connected to an input end of each summary generation module.

[0012] Optionally, the summary generation module is specifically configured to acquire advanced extensible bus transmission data connected to itself, and extract write address channel data, write data channel data, write response channel data, read address channel data and read data channel data from the data as the summary data by using a preset summary extraction algorithm.

[0013] Optionally, the summary generation module is specifically configured to acquire bus transmission data connected to itself in real time, and extract the summary data from the data transmitted by the bus within a preset time period in parallel by using a preset summary extraction algorithm.

[0014] Optionally, the lockstep module comprises a comparison module and a buffer corresponding to each summary generation module.

[0015] The buffer is configured to store summary data output by a summary generation module connected to itself.

[0016] The comparison module is configured to acquire the summary data stored in each buffer, and compare whether the summary data in each buffer is consistent; when the summary data in each buffer is consistent, output a first signal indicating that each processor is working normally; when the summary data in each buffer is inconsistent, output a second signal indicating a processor with working abnormality in each processor; and the first signal is different from the second signal.

[0017] Optionally, the lockstep module further comprises a register connected to the comparison module.

[0018] The comparison module is further configured to output the summary data in each buffer to the register when the summary data in each buffer is inconsistent, so that the register stores the summary data in each buffer.

[0019] Optionally, the lockstep module further comprises:

[0020] An abnormality prompting module is configured to generate prompt information of the lockstep abnormality when the second signal indicating that there is an abnormal processor in the processors is detected by the comparison module.

[0021] To solve the above technical problems, the application further provides an inter-chip lockstep system comprising at least two chips, and the processor lockstep device.

[0022] Each of the summary generation modules in the processor lockstep device corresponds to a processor in each of the chips.

[0023] To solve the above technical problems, the application further provides an intra-chip lockstep system comprising a chip, and the processor lockstep device.

[0024] Each of the summary generation modules in the processor lockstep device corresponds to a processor in the chip.

[0025] The application provides a processor lockstep device and related components, which comprise a lockstep module and a summary generation module corresponding to each processor. The summary generation module generates summary data according to the running data of each processor. The lockstep module compares the summary data to determine whether each processor is working normally. The summary generation module extracts summary data from the running data of each processor, and the lockstep is completed based on the summary data. The amount of data to be compared in the lockstep process is reduced based on the judgment of whether each processor is working normally, and the integrity of the running data of each processor is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0026] To make the technical solutions in the embodiments of the application clearer, the following briefly introduces the drawings needed in the prior art and the embodiments. Obviously, the drawings in the following description only show some embodiments of the application, and for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0027] Figure 1 A structural schematic diagram of a processor lockstep device provided by the application;

[0028] Figure 2 A structural schematic diagram of an inter-chip lockstep system provided by the application;

[0029] Figure 3 A structural schematic diagram of an intra-chip lockstep system provided by the application. DETAILED DESCRIPTION

[0030] The core of the present application is to provide a processor lockstep device and related components, which reduces the amount of data to be compared in the lockstep process on the basis of judging whether each processor is working normally.

[0031] To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0032] It is worth noting that the processor lockstep device provided by the present application can realize the lockstep of processors between multiple chips and the lockstep of multiple processor cores inside a chip, and the two kinds of locksteps can be realized simultaneously or individually.

[0033] Please refer to Figure 1 , Figure 1 The processor lockstep device provided by the present application has a structure diagram, which includes a lockstep module 1 and an abstract generation module 2 corresponding to each processor;

[0034] Each abstract generation module 2 is electrically connected to each processor one by one, and the lockstep module 1 is electrically connected to each abstract generation module 2.

[0035] The abstract generation module 2 is used for generating abstract data according to the running data of each processor.

[0036] The lockstep module 1 compares whether each abstract data is consistent to determine whether each processor is working normally.

[0037] In the related art, when the lockstep technology is applied to judge whether each processor in a system is reliably running, all the data output by each processor needs to be compared in real time. With the gradual increase of the amount of data output by the processor (the bus of a modern processor can transmit several thousand bits of information in parallel), the process of judging whether each processor in the system is reliably running becomes more and more complex. To solve the above technical problem, the present application provides a processor lockstep device, which includes a lockstep module 1 and an abstract generation module 2. The abstract generation module 2 is used for generating abstract data from the running data of the processor, thereby reducing the amount of data and the comparison frequency involved in the comparison process of the lockstep module 1, so as to reduce the difficulty of the lockstep process on the basis of judging whether each processor is working normally.

[0038] First of all, it needs to be pointed out that the application in each processor executes the same application, one of which is the main processor, and the others are redundant processors. In the system, each processor works simultaneously, and the instructions output by the peripheral device are sent to the main processor and the redundant processor at the same time. The main processor generates output data based on the instructions and feeds back to the peripheral device, so that the system completes the normal function. The redundant processor also generates output data based on the instructions, but does not need to be fed back to the peripheral device. The output data generated by the main processor and the redundant processor is transmitted to the digest generation module 2 through the bus of each processor, so as to be compared by the lockstep module 1 subsequently.

[0039] On this basis, the processor lockstep device provided by the application comprises a lockstep module 1 and a digest generation module 2 corresponding to each processor. Each digest generation module 2 is electrically connected to each processor through a bus, so as to obtain the data output by each processor through the bus, that is, the data transmitted through the bus is the running data of each processor electrically connected to each digest generation module. After obtaining the data transmitted through the bus connected to itself, the digest generation module 2 extracts the digest data from the data transmitted through the bus by using a preset digest extraction algorithm for integrity measurement, so as to be compared by the lockstep module 1 subsequently. Specifically, the digest generation module 2 is specifically used to obtain the data transmitted through the bus connected to itself, perform padding processing on the data transmitted through the bus to obtain padded data transmitted through the bus (wherein the length of the padding is not limited, such as the length of the padded data transmitted through the bus being a multiple of 512 bits), perform grouping processing on the padded data transmitted through the bus to obtain grouped data transmitted through the bus (wherein the grouping condition is not limited, such as the length of each group of data transmitted through the bus after grouping being 512 bits), perform data expansion on the grouped data transmitted through the bus to obtain expanded data transmitted through the bus (such as 132 words being generated after expansion), and compress the expanded data transmitted through the bus by using a compression function to extract the digest data from the data transmitted through the bus (such as 256-bit digest data being finally extracted from the data transmitted through the bus).

[0040] It needs to be pointed out that in the mode that each digest generation module 2 is electrically connected to each processor through a bus, the input end of each digest generation module 2 can be electrically connected to the output end of each processor through the bus, wherein whether the input end of the digest generation module 2 is electrically connected to the output end of each processor through a single pin of both or all pins of both is not limited in this embodiment, as long as the communication between each digest generation module 2 and each processor can be realized.

[0041] It should be noted that, compared with the previous direct comparison of bus data of all processors (i.e., comparison of raw data), in which the comparison data contains data bus and interface input and output information, the number of buses to be compared is about several hundred or several thousand, and in the method provided by the present application, the comparison is of abstract information, which greatly reduces the amount of data to be compared compared with the comparison of raw data, and is more adaptable and not limited by the type of bus.

[0042] In order to further reduce the comparison frequency and data amount of each two processors, in the present application, after collecting the output data of each processor within a period of time (which can be determined according to the current lockstep safety level requirement), the abstract information is continuously extracted and processed for comparison. Compared with the method of setting the comparison frequency to be compared every cycle, the present application continuously extracts the abstract information of the bus transmission information and compares it once, which can greatly reduce the data amount and frequency of comparison.

[0043] In addition, the present application provides a one-to-one correspondence between the abstract generation module 2 and each processor in the processor lockstep device, which can reduce the amount of data to be processed by each abstract generation module 2 and reduce the complexity of lockstep processing to a certain extent. It should be noted that, when the preset abstract extraction algorithm is used to extract abstract data from the bus transmission data, not only the data amount required for lockstep comparison can be reduced, but also the integrity of the processor execution transaction can be ensured. The preset abstract extraction algorithm in the present application includes but is not limited to cryptographic hash algorithms such as SM3 algorithm, Sha1, Sha256, Sha512, etc. Among them, the cryptographic hash algorithm can ensure that when the data output by the processor through the bus changes slightly, the abstract data extracted from the data output by the bus by the abstract generation module 2 will also change, so using the cryptographic hash algorithm as the preset abstract extraction algorithm can improve the reliability of lockstep comparison to a certain extent. For example, the SM3 algorithm as the preset abstract extraction algorithm can reduce the number of interconnect lines for lockstep comparison (from several thousand to 256), and the algorithm also ensures that any 1 of the several thousand will cause the output of the 256 to be different, i.e., a slight change in input information will inevitably cause a change in output abstract, ensuring the integrity and security of data in the lockstep process.

[0044] Further, the lockstep module 1 in the processor lockstep device compares whether the summary data is consistent, so as to determine whether the processors in the system are working normally. It should be noted that the lockstep module 1 obtains the summary data output by the summary generation module 2, and then compares whether the summary data is consistent, and the number of the lockstep module 1 in the processor lockstep device can be one or multiple. In particular, the number of the lockstep module 1 can be consistent with the number of the processors, and each lockstep module 1 is used to obtain the summary data output by the summary generation module 2, and compare whether the summary data is consistent to determine whether the processors are working normally. By setting the redundant lockstep module 1, the problem that the single lockstep module 1 cannot detect whether the processors are working normally when the lockstep module 1 fails can be avoided, and the reliability of the processor lockstep device is improved.

[0045] In summary, the present application provides a processor lockstep device, which comprises a lockstep module 1 and a summary generation module 2 corresponding to each processor. The summary generation module 2 generates summary data according to the running data of each processor. The lockstep module 1 compares whether the summary data is consistent to determine whether the processors are working normally. The summary generation module 2 extracts the summary data from the running data of each processor, and completes the lockstep of the processors based on the summary data. On the basis of judging whether the processors are working normally, the amount of data to be compared in the lockstep process is reduced, and the integrity of the running data of the processors transmitted is ensured.

[0046] On the basis of the above embodiment:

[0047] As an optional embodiment, the summary generation module 2 is specifically used to obtain the data of the advanced extensible bus transmission connected with itself, and extract the write address channel data, the write data channel data, the write response channel data, the read address channel data and the read data channel data from the data as the summary data through a preset summary extraction algorithm. In addition, the summary generation module 2 can also be specifically used to obtain the data of the advanced extensible bus transmission connected with itself, and selectively extract the data from the data of the advanced extensible bus transmission connected with itself as the summary data.

[0048] In consideration of the fact that the external interface of a modern processor is usually a high-concurrency bus such as an AXI (Advanced eXtensible Interface) bus, the embodiment provides the type of the digest data extracted by the digest generation module 2 when the processor transmits data through the AXI bus. Specifically, the AXI bus includes five channels: a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel. The bus information of the AW channel (i.e., the write address channel) includes AWID, AWADDR, AWLEN, AWSIZE, AWBURST, AWLOCK, AWCACHE, AWPROT, AWUSER, AWVALID, AWREADY, etc. The bus information of the AR channel (i.e., the read address channel) includes ARID, ARADDR, ARLEN, ARSIZE, ARBURST, ARLOCK, ARCACHE, ARPROT, ARUSER, ARVALID, ARREADY, etc. The specific information of the write data channel data, the write response channel data, and the read data channel data is not described herein. The total number of signal lines of the AXI bus is about 2000, and the extraction method in the embodiment can be to perform parallel digest extraction on the 2000 signal lines to obtain 256-bit digest data.

[0049] In summary, by arranging the digest generation module 2 in the processor lockstep device, the embodiment can extract the write address channel data, the write data channel data, the write response channel data, the read address channel data, and the read data channel data from the AXI bus as digest data, greatly reducing the amount of data that needs to be compared by the lockstep module 1, reducing the complexity of the lockstep comparison, and improving the efficiency of judging whether each processor is working normally.

[0050] As an optional embodiment, the digest generation module 2 is specifically configured to acquire data transmitted by a bus connected thereto in real time, and extract digest data from the data transmitted by the bus within a preset time period in parallel through a preset digest extraction algorithm.

[0051] In the embodiment, the digest generation module 2 acquires data transmitted by the bus in real time, and extracts digest data from multiple shots of data (i.e., data transmitted by the bus within a preset time period) continuously. Then, the lockstep module 1 performs a lockstep comparison between the digest data and the digest data output by the other digest generation modules 2 in a time sequence corresponding to each other, which can greatly reduce the amount of data involved in the lockstep comparison.

[0052] As an optional embodiment, the lockstep module 1 includes a comparison module 12 and a buffer 11 corresponding to each digest generation module 2;

[0053] The cache 11 is used for storing the digest data output by the digest generation module 2 connected therewith;

[0054] The comparison module 12 is used for obtaining the digest data stored in each cache 11 and comparing whether the digest data in each cache 11 is consistent; when the digest data in each cache 11 is consistent, a first signal used for indicating that each processor is working normally is output; when the digest data in each cache 11 is inconsistent, a second signal used for indicating that there is a processor working abnormally in each processor is output, and the first signal is different from the second signal.

[0055] Please refer to Figure 1 The lockstep module 1 in the processor lockstep device comprises the comparison module 12 and the cache 11 corresponding to each digest generation module 2. The cache 11 stores the digest data output by the digest generation module 2 corresponding thereto, which can prevent the abnormality caused by the loss of the digest data and reduce the pressure of data storage to a certain extent. The cache 11 stores the digest data output by the digest generation module 2, and the comparison module 12 obtains the digest data stored in each cache 11. When the digest data in each cache 11 is consistent, the comparison module 12 outputs the first signal used for indicating that each processor is working normally; when the digest data in each cache 11 is inconsistent, the comparison module 12 outputs the second signal used for indicating that there is a processor working abnormally in each processor. For example, when the processor is two, the comparison module 12 is a double-input comparator, the comparison module 12 outputs a high level when the digest data corresponding to the two processors is consistent, and the comparison module 12 outputs a low level when the digest data corresponding to the two processors is inconsistent.

[0056] In addition, the register 13 can also be arranged in the lockstep module 1. The register 13 is connected with the comparison module 12, and the comparison module 12 outputs the digest data in each cache 11 to the register 13 when the digest data in each cache 11 is inconsistent, so that the register 13 stores the digest data in each cache 11, which is convenient for locking the processor appearing abnormally based on the data in the register 13 subsequently. On this basis, the abnormality prompting module can also be arranged in the lockstep module 1; the abnormality prompting module is used for generating the prompt information of the lockstep abnormality when the second signal used for indicating that there is a processor working abnormally in each processor is output by the comparison module 12, so that the maintenance personnel receives the prompt information and processes the abnormality in time, thereby ensuring the reliable operation of the system.

[0057] Please refer to Figure 2 , Figure 2 The structure schematic diagram of the inter-chip lockstep system provided by the application. The inter-chip lockstep system comprises at least two chips and further comprises the processor lockstep device in any one of the above aspects;

[0058] Each of the digest generation modules 2 in the processor lockstep device corresponds to a processor in each chip.

[0059] The inter-chip lockstep system provided by the embodiment comprises at least two chips Figure 2 Taking the inter-chip lockstep system comprising chip one and chip two as an example, each chip is provided with a processor, and each processor in each chip corresponds to a digest generation module 2 in the processor lockstep device.

[0060] Figure 2 The inter-chip lockstep system shown comprises three parts:

[0061] 1) Chip one: a complete one-way chip for executing a lockstep application, which internally comprises a processor, a bus, and a digest generation module 2 for extracting information on the processor bus and sending out the information through a lockstep IO;

[0062] 2) Chip two: a complete another-way chip for executing a lockstep application, which internally comprises a processor, a bus, and a digest generation module 2 for extracting information on the processor bus and sending out the information through a lockstep IO;

[0063] 3) Lockstep module 1: receiving bus digest information extracted by the two lockstep chips executing the same application through the respective digest generation modules 2, and comparing the two-way information to determine whether the system is normally working in lockstep. By using the digest generation module 2 in the processor lockstep device, the amount of data and the comparison frequency during lockstep comparison can be reduced.

[0064] For a detailed introduction of the inter-chip lockstep system provided by the embodiment, please refer to the above-mentioned embodiment of the processor lockstep device, which will not be described herein again.

[0065] Please refer to Figure 3 , Figure 3 The structure diagram of the intra-chip lockstep system provided by the embodiment, which comprises a chip, further comprises any one of the above-mentioned processor lockstep devices.

[0066] Each of the digest generation modules 2 in the processor lockstep device corresponds to a processor in each chip.

[0067] The intra-chip lockstep system provided by the embodiment comprises a chip with multiple processors Figure 3 Taking the chip comprising processor one and processor two as an example, each processor in the chip corresponds to a digest generation module 2 in the processor lockstep device.

[0068] Specifically, Figure 3 The structure of the intra-chip lockstep system comprises six parts:

[0069] 1) Processor one + bus one: a complete one-way function for executing a lockstep application;

[0070] 2) The summary generation module 2 connected with the bus 1: extracting summaries of the information sent by the processor 1 to the bus 1;

[0071] 3) The processor 2 + the bus 2: performing the complete function of the lockstep application;

[0072] 4) The summary generation module 2 connected with the bus 2: extracting summaries of the information sent by the processor 2 to the bus 2;

[0073] 5) The lockstep module 1: comparing the bus 1 summary information extracted by the summary generation module 2 of the processor 1 performing the lockstep application and the bus 2 summary information extracted by the summary generation module 2 of the processor 2, to determine whether the system works normally in lockstep;

[0074] 6) The lockstep module 2: comparing the bus 2 summary information extracted by the summary generation module 2 of the processor 2 performing the lockstep application and the bus 1 summary information extracted by the summary generation module 2 of the processor 1, to determine whether the system works normally in lockstep.

[0075] By using the summary generation module 2 in the processor lockstep device, the connection lines between the processors in the chip during the lockstep comparison can be reduced, the difficulty of back-end wiring is reduced, and the frequency bottleneck problem of the on-chip lockstep system is solved to a certain extent.

[0076] It is worth noting that, due to the current status of chip packaging technology, the number of inter-chip lockstep interconnection lines that can be supported is limited, and the inter-chip lockstep currently seen is generally about several hundred. If the summary extraction method proposed in the present application is not used, and the several thousand inter-chip bus lines are directly compared for lockstep, it may be difficult to implement lockstep between chips, and only the lockstep between two channels in the chip (the number of inter-chip interconnection lines is relatively not limited) can be used. The inter-chip lockstep adopted in the present application uses the summary algorithm for extraction, and the number of bus lines required for the inter-chip lockstep is fixed to 256, which can realize the inter-chip lockstep from the perspective of chip packaging.

[0077] In addition, when the inter-chip lockstep scheme is used, the signals need to be transmitted on a printed circuit board (PCB), and due to the difference in performance between the PCB process and the chip internal silicon process, the data line frequency on the PCB is lower than the data line frequency inside the chip.

[0078] For detailed introduction of the on-chip lockstep system provided by the present application, please refer to the above-mentioned embodiments of the processor lockstep device, which will not be repeated here.

[0079] It can be seen that the present application uses the digest algorithm commonly used in cryptography to extract the message of the execution transaction of two processors in the inter-chip or intra-chip, measures the information of the lockstep with a small amount of message digest data, directly compares the digest when the lockstep is performed to complete the lockstep, can reduce the lockstep comparison information to an acceptable range, guarantees the integrity of the data, and thus realizes the real-time comparison of the system lockstep.

[0080] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. It should be noted that in the specification, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0081] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A processor lockstep device, characterized in that, This includes a lockstep module and a summary generation module that corresponds to each processor. Each of the above-described summary generation modules is electrically connected to each of the above-described processors, and the lockstep module is electrically connected to each of the above-described summary generation modules; The summary generation module is used to generate summary data based on the operating data of each processor; The lockstep module is used to compare whether the summaries are consistent to determine whether each processor is working properly. Specifically, each of the summary generation modules and each of the processors are electrically connected in a one-to-one correspondence via a bus; wherein, the data transmitted on the bus is the operating data of each of the processors electrically connected to each of the summary generation modules; After acquiring the data transmitted on the bus connected to it, the summary generation module extracts summary data from the data transmitted on the bus using a preset summary extraction algorithm for integrity measurement, so that the lockstep module can perform lockstep comparison later.

2. The processor lockstep device as described in claim 1, characterized in that, The number of lockstep modules is the same as the number of processors; Each lockstep module is used to compare whether the summary data is consistent to determine whether each processor is working properly.

3. The processor lockstep device as described in claim 1, characterized in that, The summary generation module is specifically used to acquire data transmitted by the bus connected to itself, fill the data transmitted by the bus to obtain filled data, group the filled data to obtain grouped data, expand the grouped data to obtain expanded data, and compress the expanded data using a compression function to extract the summary data from the data transmitted by the bus.

4. The processor lockstep device as described in claim 1, characterized in that, The digest generation module is specifically used to acquire data transmitted by the Advanced Scalable Bus connected to itself, and extract write address channel data, write data channel data, write response channel data, read address channel data, and read data channel data from the data using a preset digest extraction algorithm as the digest data.

5. The processor lockstep device as described in claim 1, characterized in that, The summary generation module is specifically used to acquire data transmitted by the bus connected to it in real time, and extract the summary data in parallel from the data transmitted by the bus within a preset time period using a preset summary extraction algorithm.

6. The processor lockstep device according to any one of claims 1 to 5, characterized in that, The lockstep module includes a comparison module and a buffer corresponding to each of the summary generation modules; The buffer is used to store the summary data output by the summary generation module connected to it; The comparison module is used to obtain the summary data stored in each of the caches and compare whether the summary data in each cache is consistent; when the summary data in each cache is consistent, a first signal is output to indicate that each processor is working normally; when the summary data in each cache is inconsistent, a second signal is output to indicate that there is a processor with abnormal operation in each processor, and the first signal is different from the second signal.

7. The processor lockstep device as described in claim 6, characterized in that, The lockstep module also includes a register connected to the comparison module; The comparison module is further configured to output the summary data of each of the buffers to the register when the summary data in each of the buffers is inconsistent, so that the register stores the summary data in each of the buffers.

8. The processor lockstep device as described in claim 6, characterized in that, The lockstep module also includes: An error message module is used to generate a lockstep error message when the comparison module outputs a second signal indicating that there is a malfunction in one of the processors.

9. An inter-chip lockstep system, characterized in that, It includes at least two chips, and also includes a processor lockstep device as described in any one of claims 1 to 8; Each summary generation module in the processor lockstep device corresponds one-to-one with the processor in each of the chips.

10. An in-chip lockstep system, characterized in that, Includes a chip, and also includes a processor lockstep device as described in any one of claims 1 to 8; Each of the summary generation modules in the processor lockstep device corresponds one-to-one with each processor in the chip.

Images