Semiconductor device and method for manufacturing the same

Abstract

The present application provides a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: an anode metal layer; an active layer located on one side of the anode metal layer, including an anode region, a first base region, a second base region, a third base region, and a cathode region that are sequentially stacked along the thickness direction. The third base region includes a plurality of first doping regions, and different first doping regions have different sizes in the thickness direction of the semiconductor device; a plurality of cathode structures located on the side of the cathode sub-region away from the anode metal layer; a gate metal layer including a gate contact structure, located on the side of the third base region away from the second base region and on the same side of the cathode sub-region; one gate contact structure is used to control the turn-off of at least two first doping regions, and the turn-off time of the first sub-doping region is prior to that of the second sub-doping region. In the thickness direction of the semiconductor device, the size of the first sub-doping region is smaller than that of the second sub-doping region. The safety, stability, and reliability of the semiconductor device can be enhanced.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of semiconductor devices, and in particular, to semiconductor devices and a method for manufacturing semiconductor devices. Background Art

[0002] With the development and progress of semiconductor device manufacturing technology, the requirements for the safety, stability, and reliability of semiconductor devices have gradually increased. The IGCT (Integrated Gate Commutated Thyristor) chip, as a semiconductor switching device, is composed of multiple GCT (Gate Commutated Thyristor) units connected in parallel. It is usually a whole-wafer structure, and the wafer includes a terminal region, an active region, and a gate contact region. When an external gate drive signal is received, the drive signal needs to be transmitted to the gate metal corresponding to each GCT unit through the gate contact region to control the turn-off of the active region corresponding to the gate metal.

[0003] In traditional IGCT devices, the active regions corresponding to different gate metals have different response speeds to the turn-off signal, which will cause the phenomenon of current redistribution in the later-turning-off active region, increasing the risk of dynamic avalanche in the active region, causing the failure of semiconductor devices, and further affecting the safety, stability, and reliability of semiconductor devices, and reducing the service life of semiconductor devices. Summary of the Invention

[0004] Based on this, the semiconductor device and the method for manufacturing a semiconductor device provided by the embodiments of the present application can improve the ability of the active region to resist avalanche risk in the case of current redistribution in the active region, further enhance the safety, stability, and reliability of the semiconductor device, and extend the service life of the semiconductor device.

[0005] In a first aspect of the embodiments of the present application, a semiconductor device is provided, including:

[0006] An anode metal layer;

[0007] An active layer, the active layer is located on one side of the anode metal layer, the active layer includes an anode region, a first base region, a second base region, a third base region, and a cathode region that are sequentially stacked along the thickness direction of the semiconductor device, the anode region is in contact with the anode metal layer, the third base region includes a plurality of first doping regions, and the sizes of different first doping regions in the thickness direction of the semiconductor device are different, and the cathode region includes a plurality of cathode sub-regions;

[0008] A plurality of cathode structures, each cathode structure is located on the side of the cathode sub-region away from the anode metal layer;

[0009] The gate metal layer includes a gate contact structure, and the gate contact structure is located on the side of the third base region away from the second base region and on the same side as the cathode sub-region;

[0010] Wherein, one of the gate contact structures is used to control the turn-off of at least two of the first doped regions. The first doped region includes a first sub-doped region and a second sub-doped region. When the turn-off of the first sub-doped region and the second sub-doped region is controlled by the gate contact structure, the turn-off time of the first sub-doped region is prior to that of the second sub-doped region, and the unit current densities of the first sub-doped region and the second sub-doped region at the turn-off moment are both within a preset range.

[0011] In one embodiment, the sizes of different first doped regions corresponding to the same gate contact structure in the thickness direction of the semiconductor device are positively correlated with the magnitude of the instantaneous current of the first doped region at the turn-off moment.

[0012] In one embodiment, the distance between the first doped region and the corresponding gate contact structure is a first distance, and the sizes of different first doped regions corresponding to the same gate contact structure in the thickness direction of the semiconductor device are positively correlated with the first distance.

[0013] In one embodiment, the second base region includes a plurality of second doped regions, and the second doped regions correspond to the first doped regions one by one;

[0014] In the thickness direction of the semiconductor device, the sum of the sizes of the first doped region and the corresponding second doped region is equal.

[0015] In one embodiment, within a preset range on the surface of the first doped region near the anode metal layer side, the doping concentrations of different first doped regions corresponding to the same gate contact structure are the same.

[0016] In one embodiment, the gate contact structure includes a plurality of;

[0017] The gate metal layer further includes a plurality of gate metal structures, and the gate metal structures are located between two adjacent cathode sub-regions and on the side of the third base region away from the second base region;

[0018] The semiconductor device further includes:

[0019] A passivation layer, and the passivation layer is located between the gate metal structure and the cathode structure.

[0020] In one embodiment, the positive projection of the first doping region onto the anode metal layer covers the positive projections of at least two of the cathode sub-regions onto the anode metal layer.

[0021] In one embodiment, the anode region, the first base region, and the third base region include P-type doping regions;

[0022] The second base region and the cathode region include N-type doping regions.

[0023] In a second aspect of the embodiments of the present application, a method for manufacturing a semiconductor device is provided, including:

[0024] Providing an active layer, the active layer including an anode region, a first base region, a second base region, a third base region, and a cathode region that are sequentially stacked along the thickness direction of the semiconductor device, the third base region including a plurality of first doping regions, different ones of the first doping regions having different sizes in the thickness direction of the semiconductor device, the cathode region including a plurality of cathode sub-regions;

[0025] Forming a plurality of cathode structures on one side of the cathode sub-regions;

[0026] Forming a gate metal layer on the side of the third base region away from the second base region, including a gate contact structure, the gate contact structure being located on the side of the third base region away from the second base region and on the same side as the cathode sub-regions, wherein one gate contact structure is used to control the turn-off of at least two of the first doping regions, the first doping regions including a first sub-doping region and a second sub-doping region, and in the case of controlling the turn-off of the first sub-doping region and the second sub-doping region through the gate contact structure, the turn-off time of the first sub-doping region is earlier than that of the second sub-doping region, and the unit current densities of the first sub-doping region and the second sub-doping region at the turn-off moment are both within a preset range;

[0027] Forming an anode metal layer on the side of the active layer away from the cathode structures, the anode region being in contact with the anode metal layer.

[0028] In one embodiment, the providing the active layer includes:

[0029] Providing a substrate, the substrate including a first doping region and a second doping region, and in the thickness direction of the substrate, the size of the first sub-doping region in the first doping region is larger than the size of the second sub-doping region in the second doping region;

[0030] Performing a doping process on one side of the substrate to obtain a first doping structure, the first doping structure being located in the first doping region;

[0031] Dope one side of the substrate to obtain a second doped structure, and the first doped structure is located between the second doped structure and the undoped substrate;

[0032] Dope the side of the substrate away from the first doped structure to obtain a third doped structure;

[0033] Dope the second doped structure to obtain a fourth doped structure;

[0034] Perform pre-diffusion treatment on the fourth doped structure to obtain a cathode emission layer and the third base region;

[0035] Remove a part of the cathode emission layer to obtain a plurality of the cathode sub-regions;

[0036] Dope the third doped structure to obtain the anode region, the first base region, and the second base region.

[0037] The semiconductor device and the method for manufacturing the semiconductor device provided by the embodiments of the present application can determine the current redistribution flow direction of different first doped regions corresponding to the same gate contact structure under the control of a turn-off signal according to the turn-off sequence of different first doped regions controlled by the same gate contact structure, that is, the residual current in the first sub-doped region that is turned off first will flow into the second sub-doped region that is turned off later, resulting in an increase in the current intensity in the second sub-doped region. By setting the size of the second sub-doped region in the thickness direction of the semiconductor device to be different from the size of the first sub-doped region in the thickness direction of the semiconductor device, the current density in the second sub-doped region after redistribution can be adjusted, so that the unit current density of different first doped regions in the semiconductor device at the turn-off moment is within a preset range, avoiding the occurrence of dynamic avalanche phenomena when the semiconductor device is turned off instantaneously, improving the avalanche risk resistance ability of the active region, further enhancing the safety, stability, and reliability of the semiconductor device, extending the service life of the semiconductor device, and improving the yield of the semiconductor device. At the same time, by making the unit current density in the second sub-doped region within a preset range, the phenomenon of re-triggering of the cathode structure corresponding to the second sub-doped region at high current density can also be avoided, thereby improving the response quality and turn-off performance of the semiconductor device and improving the robustness of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0039] Figure 1 Schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

[0040] Figure 2 Schematic structural diagram of a traditional semiconductor device provided by an embodiment of the present application;

[0041] Figure 3 Schematic top view of a semiconductor device provided by an embodiment of the present application;

[0042] Figure 4 Schematic top view of the cathode structure of a semiconductor device provided by an embodiment of the present application;

[0043] Figure 5 Schematic diagram of the doping concentration gradient of the third base region of a semiconductor device provided by an embodiment of the present application;

[0044] Figure 6 Schematic structural diagram of another semiconductor device provided by an embodiment of the present application;

[0045] Figure 7 Schematic flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0046] Figure 8 Schematic structural diagram of the third structure obtained by the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0047] Figure 9 Schematic structural diagram of the fourth structure obtained by the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0048] Figure 10 Schematic structural diagram of the cathode emission layer obtained by the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0049] Figure 11 Schematic structural diagram of the structure obtained by the method for manufacturing a semiconductor device provided by an embodiment of the present application.

[0050] Description of reference numerals:

[0051] 100 - Anode metal layer, 200 - Active layer, 210 - Anode region, 220 - First base region, 230 - Second base region, 231 - Second doping region, 240 - Third base region, 241 - First doping region, 242 - First sub - doping region, 243 - Second sub - doping region, 250 - Cathode sub - region, 300 - Cathode structure, 301 - Cathode comb - bar structure, 400 - Gate metal layer, 410 - Gate contact structure, 420 - Gate metal structure, 500 - Substrate, 501 - First doping structure, 502 - Second doping structure, 503 - Third doping structure, 504 - Fourth doping structure, 505 - Cathode emission layer, H1 - Dimension of the first doping region in the thickness direction of the semiconductor device, H2 - Dimension of the second doping region in the thickness direction of the semiconductor device, L1 - First distance, S1 - First doping region, S2 - Second doping region. Detailed implementation manners

[0052] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0054] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0055] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. Additionally, the device may also include other orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0056] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0057] As shown Figure 1 in the figure, an embodiment of the present application provides a semiconductor device. The semiconductor device includes: an anode metal layer 100, an active layer 200, a plurality of cathode structures 300, and a gate metal layer 400. The active layer 200 is located on one side of the anode metal layer 100. The active layer 200 includes an anode region 210, a first base region 220, a second base region 230, a third base region 240, and a cathode region that are sequentially stacked in the thickness direction of the semiconductor device. The anode region 210 is in contact with the anode metal layer 100. The third base region 240 includes a plurality of first doping regions 241, and different first doping regions 241 have different dimensions in the thickness direction of the semiconductor device. The cathode region includes a plurality of cathode sub-regions 250; each cathode structure 300 is located on the side of the cathode sub-region 250 away from the anode metal layer 100; the gate metal layer 400 includes a gate contact structure 410, and the gate contact structure 410 is located on the side of the third base region 240 away from the second base region 230 and on the same side as the cathode sub-region 250; wherein, one gate contact structure 410 is used to control the turn-off of at least two first doping regions 241. The first doping region 241 includes a first sub-doping region 242 and a second sub-doping region 243. When the first sub-doping region 242 and the second sub-doping region 243 are controlled to turn off by the gate contact structure 410, the turn-off time of the first sub-doping region 242 is prior to that of the second sub-doping region 243, and the unit current densities of the first sub-doping region 242 and the second sub-doping region 243 at the turn-off moment are both within a preset range.

[0058] Exemplarily, the unit current density is the ratio of the current intensity in the first doping region 241 to the spatial volume of the corresponding first doping region 241. The preset range is the maximum current density at which the semiconductor device undergoes an avalanche phenomenon, and the unit current densities of the first sub-doping region 242 and the second sub-doping region 243 at the turn-off moment are both less than the above maximum current density.

[0059] It should be noted that the first sub-doping region 242 and the second sub-doping region 243 are first doping regions 241 with different dimensions in the thickness direction of the semiconductor device.

[0060] As shown Figure 2 in the figure, for a traditional IGCT device, in the thickness direction of the semiconductor device, the dimensions of the first sub-doping region 242 and the second sub-doping region 243 controlled by the same gate contact structure 410 are equal.

[0061] It should be noted that in a traditional IGCT device, after the gate contact structure 410 receives a gate drive signal, it transmits the gate drive signal to each gate metal structure 420. One gate metal structure 420 corresponds to a cathode structure 300 and a partially doped region within the third base region 240. Among them, the cathode structures 300 and the partially doped regions are in one-to-one correspondence. The gate metal structure 420 controls the corresponding partial third base region 240 to turn off according to the gate drive signal.

[0062] However, for at least two gate metal structures 420 at different distances from the gate contact structure 410, the reception times of the gate drive signal transmitted by the gate contact structure 410 are different, resulting in different turn-off sequences of the corresponding partial third base regions 240 of the gate metal structures 420. The partial third base region 240 closer to the gate contact structure 410 will turn off earlier than the partial third base region 240 farther from the gate contact structure 410. As a result, the residual partial current in the first sub-doped region 242 that turns off first will flow to the second sub-doped region 243 that turns off later, increasing the current in the second sub-doped region 243. When the sizes of the first sub-doped region 242 and the second sub-doped region 243 are equal, it will cause an increase in the current density in the second sub-doped region 243, triggering a dynamic avalanche phenomenon in the second sub-doped region, resulting in a reduction in the reliability, stability, and safety of the semiconductor device, further leading to a reduction in the service life and yield rate of the semiconductor device. In addition, as the current density in the second sub-doped region 243 increases, the turn-off of the second sub-doped region 243 is easily affected, causing secondary re-triggering of the cathode structure 300 corresponding to the second sub-doped region 243, resulting in poor turn-off effect of the semiconductor device, affecting the turn-off performance and response quality of the semiconductor device, and leading to a reduction in the accuracy of the semiconductor device.

[0063] For the semiconductor device provided by the embodiment of the present application, according to the turn-off sequence of different first doped regions 241 controlled by the same gate contact structure 410, the current redistribution flow direction of different first doped regions 241 corresponding to the same gate contact structure 410 under the control of the turn-off signal can be determined, that is, the residual current in the first sub-doped region 242 that is turned off first will flow into the second sub-doped region 243 that is turned off later, resulting in an increase in the current intensity in the second sub-doped region 243. By setting the size of the second sub-doped region 243 in the thickness direction of the semiconductor device to be different from the size of the first sub-doped region 242 in the thickness direction of the semiconductor device, the current density in the second sub-doped region 243 after redistribution can be regulated, so that the unit current density of different first doped regions 241 in the semiconductor device at the turn-off moment is within a preset range, avoiding the occurrence of dynamic avalanche phenomenon when the semiconductor device is turned off, improving the anti-avalanche risk ability of the active region, further enhancing the safety, stability and reliability of the semiconductor device, prolonging the service life of the semiconductor device, and improving the yield rate of the semiconductor device. At the same time, by making the unit current density in the second sub-doped region 243 within a preset range, the re-triggering phenomenon of the cathode structure 300 corresponding to the second sub-doped region 243 at high current density can also be avoided, thereby improving the response quality and turn-off performance of the semiconductor device and improving the robustness of the semiconductor device.

[0064] In some feasible embodiments, the size H1 of different first doped regions 241 corresponding to the same gate contact structure 410 in the thickness direction of the semiconductor device is positively correlated with the magnitude of the instantaneous current of the first doped region 241 at the turn-off moment.

[0065] It should be noted that for the first doped region 241 with a large instantaneous current at the turn-off moment, it is easy to generate dynamic avalanche phenomenon, and at the same time, it is easy to cause secondary re-triggering of the cathode structure 300 corresponding to the first doped region 241.

[0066] For the semiconductor device provided by the embodiment of the present application, by increasing the size H1 of the first doped region 241 with a large instantaneous current at the turn-off moment in the thickness direction of the semiconductor device, the instantaneous current density of the first doped region 241 can be reduced, the dynamic avalanche risk of the semiconductor device can be lowered, the anti-avalanche ability of the semiconductor device can be improved, the turn-off performance and response quality of the semiconductor device can be improved, thereby enhancing the safety, stability and reliability of the semiconductor device, prolonging the service life of the semiconductor device, improving the response quality and turn-off performance of the semiconductor device, improving the accuracy of the semiconductor device, and further improving the yield rate of the semiconductor device.

[0067] In some feasible embodiments, the distance between the first doping region 241 and the corresponding gate contact structure 410 is the first distance L1, and the size of different first doping regions 241 corresponding to the same gate contact structure 410 in the thickness direction of the semiconductor device is positively correlated with the first distance.

[0068] As Figure 3 shown, the cathode structure 300 may include an annular structure, and multiple cathode structures 300 within the same semiconductor device may be arranged in a concentric circle manner. The gate contact structure 410 may be located on a side of the cathode structure 300 away from the center of the concentric circle, and the cathode structures 300 are insulated from each other.

[0069] Exemplarily, the gate contact structure 410 may be located on a side of the cathode structure 300 close to the center of the concentric circle. The gate contact structure 410 may include multiple ones for respectively driving different cathode structures 300.

[0070] As Figure 4 shown, when the cathode structure 300 is an annular structure, the cathode structure 300 may include multiple cathode comb structures 301, and the cathode comb structures 301 are insulated from each other.

[0071] It should be noted that for at least two first doping regions 241 controlled by the gate contact structure 410, the larger the first distance L1 between the first doping region 241 and the corresponding gate contact structure 410, the longer the conduction path between the gate contact structure 410 and the gate metal structure 420 corresponding to the first doping region 241, and the longer the transmission time of the driving signal. As a result, the first doping region 241 with a smaller first distance L1 will respond to the driving signal first. Therefore, when the driving signal is a turn-off signal, the turn-off order of the first doping region 241 with a smaller first distance L1 is prior to that of the first doping region 241 with a larger first distance L1, causing redistribution of the residual current.

[0072] For the semiconductor device provided by the embodiment of the present application, according to the different first distances L1 between different first doped regions 241 controlled by the same gate contact structure 410 and the gate contact structure 410, the current redistribution flow direction of different first doped regions 241 corresponding to the same gate contact structure 410 under the control of the turn-off signal can be determined, that is, the current intensity in the first doped region 241 with a larger first distance L1 will instantaneously increase. By increasing the size H1 of the first doped region 241 with a larger first distance L1 in the thickness direction of the semiconductor device, the instantaneous increase amplitude of the current density in the first doped region 241 with a larger first distance L1 can be reduced, avoiding the occurrence of dynamic avalanche phenomenon when the semiconductor device is turned off, improving the avalanche risk resistance ability of the active region, further enhancing the safety, stability and reliability of the semiconductor device, prolonging the service life of the semiconductor device, and improving the yield rate of the semiconductor device. At the same time, the cathode structure 300 corresponding to the first doped region 241 with a larger first distance L1 can be prevented from experiencing a re-triggering phenomenon under a high current density, thereby improving the response quality and turn-off performance of the semiconductor device and enhancing the accuracy of the semiconductor device.

[0073] As Figure 1 shown, in some feasible embodiments, the second base region 230 includes a plurality of second doped regions 231, and the second doped regions 231 correspond to the first doped regions 241 one by one; in the thickness direction of the semiconductor device, the sum of the sizes of the first doped region 241 and the corresponding second doped region 231 is equal.

[0074] For the semiconductor device provided by the embodiment of the present application, by setting the sizes of the second base region 230 and the third base region 240 to be equal everywhere in the thickness direction of the semiconductor device, the flatness and uniformity of the semiconductor device surface can be improved, and the manufacturing difficulty of the semiconductor device can be reduced.

[0075] In some feasible embodiments, within a preset range on the surface of the first doped region 241 close to the anode metal layer 100, the doping concentrations of different first doped regions 241 corresponding to the same gate contact structure 410 are the same.

[0076] Exemplarily, within a preset range on the surface of the first doped region 241 close to the anode metal layer 100, the doping concentrations of the first doped regions 241 with different sizes in the thickness direction of the semiconductor device are basically consistent and the concentration gradient is small.

[0077] Exemplarily, the third base region 240 includes a first sub-base region and a second sub-base region. Among them, the first sub-base region is located between the second sub-base region and the second base region 230. The first sub-base region is located within a preset range on the surface of the first doping region 241 closer to the anode metal layer 100. The interface between the first sub-base region and the second base region 230 is the first surface, and the interface between the first sub-base region and the second sub-base region is the second surface.

[0078] As Figure 5 shown, the horizontal axis of the image represents the doping depth of the first doping region 241, and the vertical axis represents the doping concentration of the first doping region 241. The solid line represents the concentration gradient curve A of the first doping region 241 with a larger size in the thickness direction of the semiconductor device, and the dashed line represents the concentration gradient curve B of the first doping region 241 with a smaller size in the thickness direction of the semiconductor device. α is the doping depth of the second surface, and x j1 is the doping depth of the first surface of the first doping region 241 with a smaller size in the thickness direction of the semiconductor device, and x j2 is the doping depth of the first surface of the first doping region 241 with a larger size in the thickness direction of the semiconductor device. It can be seen that within the depth range of 0 to α of the doping depth, the doping concentrations of the first doping regions 241 with different sizes are the same. Within the depth range of α to x j , the change trends of curve A and curve B are the same, indicating that the doping concentration gradients of the first doping regions 241 with different sizes in the thickness direction of the semiconductor device corresponding to the same gate contact structure 410 are similar.

[0079] For the semiconductor device provided by the embodiment of the present application, by setting the same doping concentration for the first doping regions 241 with different sizes in the thickness direction of the semiconductor device corresponding to the same gate contact structure 410, the carrier migration rates of different first doping regions 241 can be made similar, so as to improve the consistency of the turn-off speed of the first doping regions 241, thereby reducing the overall dynamic avalanche risk of the semiconductor device after the anode voltage increases during the current turn-off process, further enhancing the safety, stability and reliability of the semiconductor device, prolonging the service life of the semiconductor device, and improving the yield rate of the semiconductor device.

[0080] As Figure 1 shown, in some feasible embodiments, the gate contact structure 410 includes multiple ones; the gate metal layer 400 further includes multiple gate metal structures 420. The gate metal structure 420 is located between two adjacent cathode sub-regions 250 and on the side of the third base region 240 away from the second base region 230; the semiconductor device further includes: a passivation layer, and the passivation layer is located between the gate metal structure 420 and the cathode structure 300.

[0081] Exemplarily, a gate metal structure 420 corresponds to a cathode structure 300. The gate metal structure 420 is electrically connected to the gate contact structure 410, and the gate metal structures 420 are connected in parallel with each other.

[0082] The semiconductor device provided by the embodiment of the present application can receive the driving signal of the gate contact structure 410 through the gate metal structure 420, and control the conduction or cutoff of a part of the third base region 240 between the corresponding cathode structure 300 and the anode metal layer 100 according to the driving signal, thereby improving the control ability of the semiconductor device.

[0083] As Figure 1 shown, in some feasible embodiments, the positive projection of the first doped region 241 towards the anode metal layer 100 covers the positive projection of at least two cathode sub-regions 250 towards the anode metal layer 100.

[0084] As Figure 6 shown, the third base region 240 may include a plurality of first doped regions 241 with different sizes in the thickness direction of the semiconductor device. Among them, the positive projection of the first doped region 241 towards the anode metal layer 100 covers the positive projection of a cathode sub-region 250 towards the anode metal layer 100. By corresponding one first doped region 241 to one gate metal structure 420 and one cathode structure 300, the ability of the first doped region 241 to cope with current redistribution during the cutoff process can be enhanced, and the reliability, safety and stability of the semiconductor device can be further improved.

[0085] The semiconductor device provided by the embodiment of the present application, by setting one first doped region 241 as the active region corresponding to at least two cathode structures 300, can reduce the number of first doped regions 241 with different sizes in the thickness direction of the semiconductor device, thereby reducing the manufacturing difficulty of the semiconductor device, reducing the doping difficulty of the third base region 240, and improving the manufacturing efficiency of the semiconductor device.

[0086] In some feasible embodiments, the anode region 210, the first base region 220 and the third base region 240 include P-type doped regions; the second base region 230 and the cathode region include N-type doped regions.

[0087] Exemplarily, the doping concentration of the anode region 210 is less than the doping concentration of the first base region 220.

[0088] The semiconductor device provided by the embodiment of the present application can form a first PN junction at the interface between the first base region 220 and the second base region 230, a second PN junction at the interface between the second base region 230 and the third base region 240, and a third PN junction at the interface between the third base region 240 and the cathode region. Thus, when a driving signal is applied to the gate metal structure 420, the active layer 200 can form a carrier channel between the cathode structure 300 and the anode metal layer 100, and the on / off state of the semiconductor device can be controlled through the gate contact structure 410.

[0089] As Figure 7 shown, the embodiment of the present application further provides a method for manufacturing a semiconductor device, including:

[0090] Step S110: Provide an active layer 200, which includes an anode region 210, a first base region 220, a second base region 230, a third base region 240, and a cathode region that are sequentially stacked along the thickness direction of the semiconductor device. The third base region 240 includes a plurality of first doping regions 241, and the sizes of different first doping regions 241 in the thickness direction of the semiconductor device are different. The cathode region includes a plurality of cathode sub-regions 250.

[0091] Exemplarily, a substrate can be provided, and doping is performed on one side in the thickness direction of the substrate to obtain the anode region 210 and the first base region 220. Then, doping is performed on the other side in the thickness direction of the substrate to obtain the third base region 240 and the cathode region, and the undoped substrate is used to form the second base region 230.

[0092] Step S120: Form a plurality of cathode structures 300 on one side of the cathode sub-region 250.

[0093] Exemplarily, evaporation or sputtering can be used to deposit the anode metal, and photolithography is performed on the anode metal thin film to form the cathode structure 300. The material of the cathode structure 300 can include aluminum, and the cathode structure 300 can be a composite metal layer.

[0094] Step S130: A gate metal layer 400 is formed on the side of the third base region 240 away from the second base region 230, including a gate contact structure 410. The gate contact structure 410 is located on the side of the third base region 240 away from the second base region 230 and on the same side as the cathode sub-region 250. Among them, one gate contact structure 410 is used to control the turn-off of at least two first doping regions 241. The turn-off time of the first sub-doping region 242 is prior to that of the second sub-doping region 243. In the thickness direction of the semiconductor device, the size of the first sub-doping region 242 is smaller than that of the second sub-doping region 243. Among them, one gate contact structure 410 is used to control the turn-off of at least two first doping regions 241. The first doping region 241 includes the first sub-doping region 242 and the second sub-doping region 243. When controlling the turn-off of the first sub-doping region 242 and the second sub-doping region 243 through the gate contact structure 410, the turn-off time of the first sub-doping region 242 is prior to that of the second sub-doping region 243. The unit current density of the first sub-doping region 242 and the second sub-doping region 243 at the turn-off moment is within a preset range.

[0095] Exemplarily, the first sub-doping region 242 and the second sub-doping region 243 can be directly doped with different doping concentrations in different regions of the substrate. The deposition of the metal film layer can be carried out by evaporation or sputtering, and the metal film layer is lithographed to form the gate contact structure 410. Among them, the material of the gate contact structure 410 can include aluminum, and the gate contact structure 410 can be a composite metal layer.

[0096] Step S140: An anode metal layer 100 is formed on the side of the active layer 200 away from the cathode structure 300, and the anode region 210 is in contact with the anode metal layer 100.

[0097] Exemplarily, the deposition of the anode metal can be carried out by evaporation or sputtering, and the anode metal thin film is lithographed to form the anode metal layer 100. Among them, the material of the anode metal layer 100 can include aluminum, and the anode metal layer 100 can be a composite metal layer.

[0098] In the manufacturing method of the semiconductor device provided by the embodiment of the present application, according to the turn-off sequence of different first doping regions 241 controlled by the same gate contact structure 410, the current redistribution flow direction of different first doping regions 241 corresponding to the same gate contact structure 410 under the control of the turn-off signal can be determined, that is, the residual current in the first sub-doping region 242 that is turned off first will flow into the second sub-doping region 243 that is turned off later, resulting in an increase in the current intensity in the second sub-doping region 243. By setting the size of the second sub-doping region 243 in the thickness direction of the semiconductor device to be different from the size of the first sub-doping region 242 in the thickness direction of the semiconductor device, the current density in the second sub-doping region 243 after redistribution can be adjusted, so that the unit current density of different first doping regions 241 in the semiconductor device at the turn-off moment is within a preset range, avoiding the occurrence of dynamic avalanche phenomenon when the semiconductor device is turned off, improving the avalanche risk resistance ability of the active region, further enhancing the safety, stability and reliability of the semiconductor device, prolonging the service life of the semiconductor device, and improving the yield rate of the semiconductor device. At the same time, by making the unit current density in the second sub-doping region 243 within a preset range, the re-triggering phenomenon of the cathode structure 300 corresponding to the second sub-doping region 243 at high current density can also be avoided, thereby improving the response quality and turn-off performance of the semiconductor device and enhancing the robustness of the semiconductor device.

[0099] In some feasible embodiments, the active layer 200 is provided, including:

[0100] Step S210: Provide a substrate 500, the substrate includes a first doping region S1 and a second doping region S2, and in the thickness direction of the substrate, the size of the first sub-doping region 242 in the first doping region S1 is larger than the size of the second sub-doping region 243 in the second doping region S2.

[0101] Exemplarily, the substrate 500 may be an N-type substrate, and the substrate 500 can be determined according to the voltage level of the semiconductor device. The value of the ion doping concentration in the substrate 500 is 5×10 11 / cm -3 to 1×10 14 / cm -3 , and the value of the thickness of the substrate 500 is 200 μm to 1400 μm. The surface of the substrate 500 can be chemically cleaned to preprocess the substrate 500 and improve the doping efficiency of the substrate 500.

[0102] As Figure 8 shown, step S220: Perform a doping process on one side of the substrate 500 to obtain a first doping structure 501, and the first doping structure 501 is located in the first doping region S1.

[0103] Exemplarily, a first doping structure 501 can be formed in the first doping region S1 by ion implantation plus diffusion. Among them, the ion implantation dose in the first doping structure 501 is 5×10 11 / cm -2 to 5×10 13 / cm -2 , the diffusion junction depth ranges from 20 μm to 30 μm, and the implanted ions can be aluminum or gallium.

[0104] As Figure 8 shown, in step S230, one side of the substrate 500 is doped to obtain a second doping structure 502, and the first doping structure 501 is located between the second doping structure 502 and the undoped substrate 500.

[0105] Exemplarily, a second doping structure 502 can be formed layer by layer on the side of the first doping structure 501 away from the substrate 500 by ion implantation plus diffusion. Among them, the second doping structure 502 is located in the first doping region S1 and the second doping region S2. The ion implantation dose in the second doping structure 502 is 5×10 11 / cm -2 to 5×10 13 / cm -2 , the diffusion junction depth ranges from 90 μm to 150 μm, and the implanted ions can be aluminum or gallium.

[0106] As Figure 8 shown, in step S240, the side of the substrate 500 away from the first doping structure 501 is doped to obtain a third doping structure 503.

[0107] Exemplarily, a third doping structure 503 can be doped on the side of the substrate 500 away from the first doping structure 501 by ion implantation plus diffusion. Among them, the ion implantation dose in the third doping structure 503 is 5×10 11 / cm -2 to 5×10 13 / cm -2 , the diffusion junction depth ranges from 90 μm to 150 μm, and the implanted ions can be aluminum or gallium.

[0108] As Figure 9 shown, in step S250, the second doping structure 502 is doped to obtain a fourth doping structure 504.

[0109] Exemplarily, the fourth doping structure 504 can be doped on the side of the second doping structure 502 far from the first doping structure 501 by ion implantation plus diffusion. Among them, the doping concentration of the fourth doping structure 504 is higher than that of the second doping structure 502, and the ion types implanted and doped in the fourth doping structure 504 and the second doping structure 502 are the same. The range of the doping concentration of the fourth doping structure 504 is 1×10 16 / cm -3 to 1×10 20 / cm -3 , the value of the diffusion junction depth is 10 μm to 50 μm, and the implanted ion can be boron.

[0110] As Figure 10 shown, in step S260, the fourth doping structure 504 is pre-diffused to obtain the cathode emission layer 505 and the third base region 240.

[0111] Exemplarily, the cathode emission layer 505 can be formed on the side of the fourth doping structure 504 far from the second doping structure 502 by a pre-diffusion process. Among them, the value of the junction depth of the cathode emission layer 505 is 5 μm to 10 μm, and the diffused ion can be phosphorus. After doping in this step, the first doping structure 501, the second doping structure 502 and the fourth doping structure 504 together form the third base region 240. Among them, the first doping structure 501, the second doping structure 502 and the fourth doping structure 504 in the first doping region S1 together form the second sub-doping region 243, and the first doping structure 501 and the second doping structure 502 in the second doping region S2 together form the first sub-doping region 242.

[0112] As Figure 11 shown, in step S270, part of the cathode emission layer 505 is removed to obtain a plurality of cathode sub-regions 250.

[0113] Exemplarily, part of the cathode emission layer 505 can be removed by a lithography process to obtain a plurality of hollowed-out areas, and a pre-structure is formed between adjacent hollowed-out areas. The pre-structure can be etched by at least one of a wet etching process and a dry etching process, and ion implantation plus diffusion is performed on the etched pre-structure to obtain the cathode sub-regions 250. Among them, the value of the diffusion concentration of the cathode sub-regions 250 is 1×10 18 / cm -3 to 1×10 21 / cm -3 , and the value of the diffusion junction depth is 10 μm to 30 μm.

[0114] As Figure 11 shown, in step S280, the third doping structure 503 is doped to obtain the anode region 210, the first base region 220 and the second base region 230.

[0115] Exemplarily, an anode region 210 may be formed on a side of the third doping structure 503 away from the substrate 500 by ion implantation plus diffusion. The doped third doping structure 503 is used to form a first base region 220, and the doped substrate 500 is used to form a second base region 230. Among them, the doping concentration of the anode region 210 ranges from 5×10 16 / cm -3 to 1×10 20 / cm -3 , the diffusion junction depth ranges from 1 μm to 20 μm, and the implanted ions may include boron.

[0116] Exemplarily, an oxide layer may be formed on a side of the cathode sub-region 250 and the third base region 240 away from the anode region 210. Among them, the oxide layer may be formed by a chemical vapor deposition process. The oxide layer may be etched by a photolithography process to obtain a contact opening for the cathode structure 300 and the gate metal layer 400.

[0117] Exemplarily, a metal film layer may be formed in the contact opening by processes such as evaporation or magnetron sputtering, and the metal film layer may be lithographed to obtain the cathode structure 300 and the gate metal layer 400. Among them, the materials of the cathode structure 300 and the gate metal layer 400 may include aluminum, and the cathode structure 300 and the gate metal layer 400 may be composite metal layers.

[0118] Exemplarily, a metal film layer may be formed on a side of the anode region 210 away from the third base region 240 by processes such as evaporation or magnetron sputtering, and the metal film layer may be lithographed to obtain the anode metal layer 100. Among them, the material of the anode metal layer 100 may include aluminum, and the cathode structure 300 and the gate metal layer 400 may be composite metal layers.

[0119] Exemplarily, a passivation layer may be formed between the cathode structure 300 and the gate metal structure 420 by at least one of the group consisting of polyimide, amorphous hydrogenated carbon, inorganic-organic composite material, parylene, and phenolic resin containing polymer particles.

[0120] Exemplarily, processes such as chamfering, cleaning, passivation, and rounding may be performed on the terminal region of the semiconductor device to complete the shaping and passivation protection of the terminal region of the semiconductor device.

[0121] The method for manufacturing a semiconductor device provided by the embodiments of the present application can improve the manufacturing quality of the third base region 240, reduce the manufacturing difficulty of the semiconductor device, improve the manufacturing efficiency, and thus can improve the yield rate of the semiconductor device.

[0122] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0123] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0124] The above-described embodiments merely represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A semiconductor device, characterized in that include: Anode metal layer; an active layer, the active layer being located on one side of the anode metal layer, the active layer comprising an anode region, a first base region, a second base region, a third base region and a cathode region stacked in sequence along a thickness direction of the semiconductor device, the anode region being in contact with the anode metal layer, the third base region comprising a plurality of first doped regions, different first doped regions having different sizes in the thickness direction of the semiconductor device, and the cathode region comprising a plurality of cathode sub-regions; A plurality of cathode structures, each of the cathode structures being located on a side of the cathode sub-region away from the anode metal layer; a gate metal layer, comprising a gate contact structure, wherein the gate contact structure is located on a side of the third base region away from the second base region and on the same side of the cathode sub-region; Among them, one of the gate contact structures is used to control the shutdown of at least two of the first doping regions, and the first doping region includes a first sub-doping region and a second sub-doping region. When the first sub-doping region and the second sub-doping region are controlled to be shut down by the gate contact structure, the shutdown time of the first sub-doping region is earlier than that of the second sub-doping region, and the unit current density of the first sub-doping region and the second sub-doping region at the shutdown moment are both within a preset range.

2. The semiconductor device according to claim 1, wherein: The sizes of different first doped regions corresponding to the same gate contact structure in the thickness direction of the semiconductor device are positively correlated with the magnitude of the instantaneous current of the first doped region at the turn-off moment.

3. The semiconductor device according to claim 1, wherein: The distance between the first doped region and the corresponding gate contact structure is a first distance, and the sizes of different first doped regions corresponding to the same gate contact structure in the thickness direction of the semiconductor device are positively correlated with the first distance.

4. The semiconductor device according to claim 1, wherein: The second base region includes a plurality of second doping regions, and the second doping regions correspond to the first doping regions one by one; In a thickness direction of the semiconductor device, a sum of sizes of the first doping region and a corresponding second doping region are equal.

5. The semiconductor device according to claim 1, wherein: Within a preset range of a surface of the first doping region on one side close to the anode metal layer, the doping concentrations of different first doping regions corresponding to the same gate contact structure are the same.

6. The semiconductor device according to claim 1, wherein: The gate contact structure includes a plurality of; The gate metal layer further comprises a plurality of gate metal structures, wherein the gate metal structure is located between two adjacent cathode sub-regions and located on a side of the third base region away from the second base region; The semiconductor device further comprises: A passivation layer is located between the gate metal structure and the cathode structure.

7. The semiconductor device according to claim 1, wherein: The orthographic projection of the first doped region toward the anode metal layer covers the orthographic projections of at least two cathode sub-regions toward the anode metal layer.

8. The semiconductor device according to claim 1, wherein: The anode region, the first base region and the third base region include P-type doped regions; The second base region and the cathode region include N-type doped regions.

9. A method for preparing a semiconductor device, characterized in that: include: Providing an active layer, the active layer comprising an anode region, a first base region, a second base region, a third base region and a cathode region stacked in sequence along a thickness direction of the semiconductor device, the third base region comprising a plurality of first doped regions, different first doped regions having different sizes in the thickness direction of the semiconductor device, and the cathode region comprising a plurality of cathode sub-regions; forming a plurality of cathode structures on one side of the cathode sub-region; A gate metal layer is formed on a side of the third base region away from the second base region, comprising a gate contact structure, the gate contact structure is located on a side of the third base region away from the second base region and on the same side of the cathode sub-region, wherein one gate contact structure is used to control the turn-off of at least two of the first doping regions, the first doping region comprises a first sub-doping region and a second sub-doping region, and when the first sub-doping region and the second sub-doping region are turned off by controlling the turn-off of the first sub-doping region and the second sub-doping region by the gate contact structure, the turn-off time of the first sub-doping region is earlier than that of the second sub-doping region, and the unit current density of the first sub-doping region and the second sub-doping region at the turn-off time is both within a preset range; An anode metal layer is formed on a side of the active layer away from the cathode structure, and the anode region is in contact with the anode metal layer.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The providing of the active layer comprises: Providing a substrate, the substrate comprising a first doping region and a second doping region, wherein in a thickness direction of the substrate, a size of the first sub-doping region in the first doping region is greater than a size of the second sub-doping region in the second doping region; Performing a doping process on one side of the substrate to obtain a first doping structure, wherein the first doping structure is located in the first doping region; Performing a doping process on one side of the substrate to obtain a second doping structure, wherein the first doping structure is located between the second doping structure and the undoped substrate; Performing a doping process on a side of the substrate away from the first doping structure to obtain a third doping structure; performing a doping process on the second doping structure to obtain a fourth doping structure; Performing a pre-diffusion treatment on the fourth doping structure to obtain a cathode emission layer and the third base region; removing part of the cathode emission layer to obtain a plurality of cathode sub-regions; The third doping structure is doped to obtain the anode region, the first base region and the second base region.

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