Method and device for implementing data flow conversion finite state machine based on security protocol

Abstract

The application discloses a data flow conversion finite state machine implementation method and device based on a security protocol, and the method steps comprise: acquiring a stage judgment signal and a server control register verification signal to determine a current processing stage; and sequentially entering a registration stage, a first authentication stage and a second authentication stage. In the registration stage, data flow is circulated through a PUF module, a Hash module and a Flash module to realize registration of user information of a protocol to a server end; in the first authentication stage, data flow is circulated through a Hash module, a pseudo-random number generator module, a clock module and a Flash module to realize user end identity verification of the protocol; and in the second authentication stage, identity verification or session key negotiation is realized through a PUF module, a Hash module, a clock module and a Hash module. The application realizes accurate data result acquisition and control of data flow conversion, optimizes the use of hardware resources, and ensures the safety and high efficiency of data flow conversion.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of network data security authentication, and particularly relates to a data flow conversion finite state machine implementation method and device based on a security protocol. BACKGROUND

[0002] A security authentication protocol is a mechanism for verifying the identity of both parties in communication, and the purpose is to ensure the trustworthiness of both parties in communication. A key agreement protocol allows two or more participants to jointly establish a session key without relying on a trusted third party. In wireless security communication, it is usually necessary to combine the two protocols: first, the identity of both parties is verified through the authentication protocol before establishing secure communication; then, a shared key is generated through the key agreement protocol, which is used for subsequent encryption and decryption of communication.

[0003] In the hardware implementation of security authentication and key agreement protocols, a state machine is needed to control the execution flow of the protocol. A finite state machine is a tool for describing the transition and behavior of a system between different states, which usually has an initial state representing the initial state of system startup, and can define one or more termination states representing that the system has completed a specific task. For the hardware implementation of security authentication and key agreement protocols, the existing state machine technology often has the following problems:

[0004] (1) Complex states and unclear data flow conversion: the state of the security protocol is too complex, and the lack of transparency leads to unclear data flow conversion and difficult tracking of state transitions. This problem also makes it difficult for developers to understand and verify the behavior of the protocol, thereby increasing the risk of errors and reducing the reliability and security of the system.

[0005] (2) Large consumption of hardware resources: in the hardware implementation process, due to the large number of states and complex data flow conversion, the hardware resources and states required in each stage are more, which will cause the entire state machine to occupy a large amount of hardware resources, resulting in waste of resources and low efficiency. SUMMARY

[0006] The technical problem to be solved by the application: in view of the problems existing in the prior art, the application provides a data flow conversion finite state machine implementation method and device based on a security protocol, which realizes the optimization of hardware resource use by accurately obtaining data results and controlling data flow conversion, and at the same time improves the efficiency and security and reliability of the system.

[0007] In order to solve the problems existing in the prior art, the technical scheme adopted by the application is as follows: a data flow conversion finite state machine implementation method based on a security protocol, the implementation steps of which include the following:

[0008] (1) In the idle state, obtain the stage judgment signal and the server control register verification signal to judge the current stage;

[0009] (2) According to the state of the stage judgment signal and the server control register verification signal, respectively entering the registration stage, the first authentication stage and the second authentication stage;

[0010] (3) In the registration stage, data flow is carried out through the PUF module, the Hash module and the Flash module, and user information is registered on the server end through the protocol;

[0011] (4) In the first authentication stage, data flow is carried out through the Hash module, the pseudo-random number generator module, the clock module and the Flash module, and the user end identity authentication is realized through the protocol;

[0012] (5) In the second authentication stage, identity authentication or session key negotiation is realized through the PUF module, the Hash module, the clock module and the Hash module.

[0013] Further, in the registration stage, the data flow includes in turn: the start PUF operation state, the end PUF operation state, the FID storage state, the start Hash_ID operation state, the end Hash_ID operation state, the end Ve storage state, the start Hash_PW operation state, the end Hash_PW operation state and the end PK storage state.

[0014] Further, the process of data flow in the registration stage includes:

[0015] (1) In the start PUF operation state, the i-th challenge Ci is sent to the PUF module for operation, and in the end PUF operation state, the PUF operation is waited to end, so as to obtain the result Ri;

[0016] (2) In the FID storage state, the FID is stored in the Flash, and the storage is waited to be completed;

[0017] (3) In the start Hash_ID operation state, the username IDe and the password data PWe are combined and sent to the Hash module for calculation;

[0018] (4) In the end Hash_ID operation state, the Hash operation is waited to end, and the authentication verification value Ve obtained by the Hash operation result is stored in the Flash;

[0019] (5) In the end Ve storage state, the authentication verification value Ve is waited to be stored;

[0020] (6) In the start Hash_PW operation state, the password data PWe is sent to the Hash module for operation, the next state judgment signal stage_h is written into the Flash module, and the storage is waited for completion; in the end Hash_PW operation state, the Hash operation is waited for completion and confusion, and the confusion result PK is stored into the Flash module;

[0021] (7) In the end PK storage state, the confusion result PK storage is waited for completion.

[0022] Further, in the first authentication stage, the data flow conversion includes in turn: start Hash_ID operation state, end Hash_ID operation state, end Ve reading state, compare Ve state, start random number generation state, end random number generation state, start reading PK state, end reading PK state, start Hash_PW operation state, end Hash_PW operation state, start reading FID state, and end reading FID state.

[0023] Further, the process of the data flow conversion in the first authentication stage includes:

[0024] (1) In the start Hash_ID operation state, the username IDe and the password data PWe are sent to the Hash module for calculation after being combined; in the end Hash_ID operation state, the Hash operation is waited for completion, so as to obtain the second authentication check value Ve*, and the registration stage is read from the Flash module, so as to obtain the value of the first authentication check value Ve;

[0025] (2) In the end Ve reading state, the first authentication check value Ve reading is waited for completion; in the compare Ve state, the values of the first authentication check value Ve and the second authentication check value Ve* are compared, if not equal, the authentication fails, and if equal, the next state is entered;

[0026] (3) In the start random number generation state, the time stamp TS1 is obtained, and the time stamp TS1 is sent to the pseudo-random number generator module as a seed; in the end random number generation state, the pseudo-random number generator module is waited for generating the random number R1;

[0027] (4) In the start reading PK state, the PK is read from the Flash module; in the end reading PK state, the PK reading from the Flash module is completed;

[0028] (5) In the start Hash_PW operation state, the data PWe data is sent to the Hash module for calculation after being combined; in the end Hash_PW operation state, the Hash operation is waited for completion and confusion, so as to obtain the result PUK;

[0029] (6) In the start read FID state, the specified FID is read from the Flash module; in the end read FID state, the katakana FID stored in the registration stage is read from the Flash, and the stage judgment signal stage_l is set to 1, i.e. the second authentication stage is entered.

[0030] Further, in the second authentication stage, the data flow conversion includes in turn: the compare TS2 state, the end TS2 state, the start PUF operation state, the end PUF operation state, the start Hash_TS2 operation state, the end Hash_TS2 operation state, the compare V1 state, the calculate R2 state, the start Hash_R1R2 operation state, the end Hash_R1R2 operation state, the start Hash_FID operation state, the end Hash_FID operation state, the end FID1 storage state, the start PUF_CIP1 operation state, the end PUF_CIP1 operation state, the start Hash_TS3 operation state, the end Hash_TS3 operation state, the start Hash_SK operation state, and the end Hash_SK operation state.

[0031] Further, in the second authentication stage, the authentication check value V1, the confusion information DCi, DRi, DCi+1, and the time stamp TS2 are inputted from outside, and the process of the data flow conversion includes:

[0032] (1) In the compare TS2 state, the TS3 time stamp is generated, and the TS3 time stamp generation is waited; in the end TS2 state, whether the difference between TS3 and TS2 is less than |Δ| is compared, if the authentication fails if it does not meet, if it meets, the next state is entered;

[0033] (2) In the start PUF operation state, the i-th challenge data Ci is sent to the PUF module for operation; in the end PUF operation state, the PUF operation is waited to end, and the result is written into the register;

[0034] (3) In the start Hash_TS2 operation state, the data R1, Ri, TS2 is sent to the Hash module for calculation after being merged, wherein R1 represents the random number generated in the first authentication stage, and Ri is generated by the PUF given to the challenge Ci; in the end Hash_TS2 operation state, the Hash operation is waited to end to obtain the result V1*; in the compare V1 state, whether the values of V1 and V1* are equal is compared, if not equal, the authentication fails, and if equal, the next state is entered;

[0035] (4) in the computing R2 state, XORing DRi and Ri to obtain R2; in the starting Hash_R1R2 operation state, sending the combined data R1, Ri and R2 to the Hash module for computation; in the ending Hash_R1R2 operation state, waiting for the Hash computation to end, thereby obtaining the result SK;

[0036] (5) in the starting Hash_FID operation state, sending the combined data FID and R2 to the Hash module for computation; in the ending Hash_FID operation state, waiting for the Hash computation to end and to be obfuscated, thereby obtaining the result FID1 and writing it into the Flash module; in the ending FID1 storage state, waiting for the FID1 storage to be completed;

[0037] (6) in the starting PUF_CIP1 operation state, sending the data Ci1 to the PUF module for computation; in the ending PUF_CIP1 operation state, waiting for the PUF computation to end, thereby obtaining the result Ri1; in the starting Hash_TS3 operation state, sending the combined data Ri, R2 and TS3 to the Hash module for computation; in the ending Hash_TS3 operation state, waiting for the Hash computation to end, thereby obtaining the result V2;

[0038] (7) in the starting Hash_SK operation state, sending the combined data SK and TS3 to the Hash module for computation; in the ending Hash_SK operation state, waiting for the Hash computation to end and to be obfuscated, thereby obtaining the result PRi.

[0039] Further, according to the stage judgment signal and the state of the server control register verification signal, the registration stage, the first authentication stage and the second authentication stage are entered respectively, and the judgment conditions are as follows:

[0040] (1) if the stage judgment signal stage_h is 0 and the server control register verification signal server_ctrl_rig_vld is 1, the registration stage is entered;

[0041] (2) if the stage judgment signal stage_h is not 0, stage_l is 0 and the server control register verification signal server_ctrl_auth_1_vld is 1, the first authentication stage is entered;

[0042] (3) if the stage judgment signal stage_h is not 0, stage_l is 1 and the server control register verification signal server_ctrl_auth_2_vld is 1, the second authentication stage is entered.

[0043] The device for the above-mentioned security protocol-based data flow conversion finite state machine implementation method comprises a control module and its connected Flash module, Hash module, clock module, pseudo-random number generator module, PUF module and interface module.

[0044] A computer readable storage medium storing a computer program, the computer program being executed by a processor to implement the above-mentioned method.

[0045] Compared with the prior art, the present application has the following advantages:

[0046] 1. The present application integrates the state changes and data flow conversion of each stage of the security protocol operation process, combines the data flow of the PUF module, Hash module, Flash module, clock module and pseudo-random number generator module, forms a security protocol-based data flow conversion finite state machine, can improve the clarity of the security protocol state and the intuitiveness of the data flow conversion, ensures that information data can be converted between modules under the control of the state machine, and realizes accurate data result acquisition and data control conversion.

[0047] 2. The present application simplifies and combines the states of the finite state machine, optimizes the use of hardware resources, effectively reduces the demand for hardware resources, thereby solving the problem of excessive hardware resource occupation in traditional security protocol implementation, greatly improving the system operation efficiency and response speed. While reducing the cost, the reliability and security of the system are also enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 is a structural schematic diagram of the device for implementing the security protocol-based data flow conversion finite state machine of the present embodiment.

[0049] Figure 2 is a schematic diagram of the implementation principle of the security protocol-based data flow conversion finite state machine of the present embodiment.

[0050] Figure 3 is a schematic diagram of the data state conversion in the registration stage of the present embodiment.

[0051] Figure 4 is a schematic diagram of the data state conversion in the first authentication stage of the present embodiment.

[0052] Figure 5 is a schematic diagram of the data state conversion in the second authentication stage of the present embodiment. Detailed Implementation

[0053] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0054] like Figure 1 As shown, for the hardware implementation of the security authentication and key negotiation protocol, this embodiment integrates and constructs a device consisting of seven modules: a Control module, a Flash module, a Hash module, a Time module, an AXI (Advanced eXtensible Interface) module, a Pseudo-Random Number Generator (PRNG) module, and a PUF (Physical Unclonable Function). This device forms a finite state machine for the hardware implementation of the security authentication and key negotiation protocol. The Control module is at the core of this finite state machine, regulating the data flow between each module of the protocol and the state changes between each stage. The AXI module enables data interaction between devices. This finite state machine data flow architecture optimizes hardware resource utilization, reduces hardware overhead, and improves the operating efficiency and security reliability of the hardware implementation system.

[0055] Based on the above architecture, this embodiment utilizes the data flow process in the protocol flow to define the responses of different steps corresponding to each state in the protocol, making the protocol data flow and state design more intuitive. It can support data conversion between six different modules, including Flash, Hash, Time, AXI, PRNG, and PU F. At the same time, the Control module implements state machine control to control the data communication between these modules, thereby making the system highly adaptable to external inputs and ensuring accurate and clear control of the data flow. It also simplifies the merging of states, supports data conversion and communication between multiple modules, optimizes the use of hardware resources, reduces hardware overhead, and, combined with the efficient management of the Control module, improves the system's operating efficiency and response speed while reducing hardware resource consumption.

[0056] like Figure 2 As shown, the steps of the data flow finite state machine implementation method based on the security protocol in this embodiment include:

[0057] (1) In the idle state, the current stage is determined by acquiring the stage judgment signal and the server control register verification signal;

[0058] (2) According to the state of the stage judgment signal and the server control register verification signal, respectively enter the registration stage, the first authentication stage and the second authentication stage;

[0059] (3) In the registration stage, the data flow is circulated through the PUF module, the Hash module and the Flash module, and the user information of the protocol is registered to the server end; in the first authentication stage, the data flow is circulated through the Hash module, the pseudo-random number generator module, the clock module and the Flash module, and the identity authentication of the user end of the protocol is realized; in the second authentication stage, the identity authentication or the negotiation of the session key is realized through the PUF module, the Hash module, the clock module and the Hash module.

[0060] Through the above method, the embodiment can solve the hardware implementation problem of the security authentication and key negotiation protocol, combine the data flow of the PUF module, the Hash module, the Flash module, the clock module and the pseudo-random number generator module, construct the data flow conversion finite state machine based on the security protocol, so that the protocol data flow conversion path can be clearly determined, the hardware resource occupation is reduced, and the efficiency and reliability of the hardware implementation are improved.

[0061] Referring to Figure 2 , the embodiment integrates the above architecture to form a finite state machine state, and supports the operation of the following three stages of the security protocol:

[0062] 1) Registration stage: the data flow is circulated by the PUF module, the Hash module and the Flash module, and the user information of the protocol is registered to the server end;

[0063] Considering the mutual authentication of the user end and the server end, the authentication is divided into the first authentication stage and the second authentication stage:

[0064] 2) First authentication stage: the data flow is circulated by the Hash module, the PRNG module, the Time module and the Flash module, and the identity authentication of the user end of the protocol is supported;

[0065] 3) Second authentication stage: use PUF, Hash, Time and Flash modules, the protocol in this stage needs to perform identity authentication, negotiate session keys and other processes.

[0066] In this embodiment, considering the security protocol and the number of operation steps, nine operation states are abstracted in the general classical operation, i.e. nine states are designed for the data flow in the registration stage, including: start PUF operation state, end PUF operation state, store FID state, start Hash_ID operation state, end Hash_ID operation state, end Ve storage state, start Hash_PW operation state, end Hash_PW operation state and end PK storage state. The process of the data flow in the registration stage is as follows:

[0067] (1) In the start PUF operation state, the i-th challenge Ci is sent to the PUF module for operation;

[0068] (2) In the end PUF operation state, the PUF operation is waited to end, so as to obtain the result Ri;

[0069] (3) In the FID storage state, the FID is stored in the Flash module, and the storage is waited to be completed;

[0070] (4) In the start Hash_ID operation state, the username (IDe) and the password (PWe) data are merged and sent to the Hash module for calculation;

[0071] (5) In the end Hash_ID operation state, the Hash operation is waited to end, and the first authentication check value Ve obtained by the Hash operation result is stored in the Flash module;

[0072] (6) In the end Ve storage state, the first authentication check value Ve is waited to be stored completely;

[0073] (7) In the start Hash_PW operation state, the password data PWe is sent to the Hash module for operation, the next state judgment signal stage_h is written into the Flash module, and the storage is waited to be completed, stage_h represents the high bit of the stage signal, and is used for judging whether it is in the authentication stage or the registration stage;

[0074] (8) In the end Hash_PW operation state, the Hash operation is waited to end, and the confusion result PK is stored in the Flash module;

[0075] (9) In the end PK storage state, the confusion result PK is waited to be stored completely.

[0076] In the embodiment, considering the general security protocol in the security protocol, the general security protocol in the authentication first part is generally 6-10 operation parameters, and the data flow of the first authentication stage is designed with 12 states, which include: start Hash_ID operation state, end Hash_ID operation state, end Ve reading state, compare Ve state, start random number generation state, end random number generation state, start reading PK state, end reading PK state, start Hash_PW operation state, end Hash_PW operation state, start reading FID state, and end reading FID state.

[0077] Specifically, the process of the data flow of the first authentication stage is specifically:

[0078] (1) In the start Hash_ID operation state, the username IDe and the password data PWe are combined and sent to the Hash module for calculation;

[0079] (2) In the end Hash_ID operation state, the second authentication check value Ve* obtained after the Hash operation is ended is waited, and the value of the first authentication check value Ve obtained in the registration stage is read from the Flash module;

[0080] (3) In the end first authentication check value Ve reading state, the first authentication check value Ve reading is waited to end;

[0081] (4) In the compare first authentication check value Ve state, the values of the first authentication check value Ve and the second authentication check value Ve* are compared, if they are not equal, the authentication fails, and if they are equal, the next state is entered;

[0082] (5) In the start random number generation state, the timestamp TS1 is obtained, and the timestamp TS1 is sent to the pseudo-random number generator module as a seed;

[0083] (6) In the end random number generation state, the pseudo-random number generator module is waited to generate the random number R1;

[0084] (7) In the start entering PK state, the PK is read from the Flash module;

[0085] (8) In the end reading PK state, the PK reading from the Flash module is completed;

[0086] (9) In the start Hash_PW operation state, the data PWe data is combined and sent to the Hash module for calculation;

[0087] (10) In the end Hash_PW operation state, the Hash operation is waited to end and is confused, so as to obtain the result PUK;

[0088] (11) In the beginning of reading FID state, reading the katakana FID stored in the designated registration stage from the Flash module;

[0089] (12) In the end of reading FID state, reading the katakana FID from the Flash is completed, and the stage judgment signal stage_l is set to 1, that is, the second authentication stage will be entered, wherein Stage_l represents the low bit of stage signal, and is used to judge which specific stage the authentication stage is in.

[0090] In the embodiment, considering that the general security protocol in the security protocol is generally 15-19 in the second part of mutual authentication Operation number, considering the number of long and short period operations, 19 states are designed for data flow in the second authentication stage, which include in turn: comparison TS2 state, end TS2 state, start PUF operation state, end PUF operation state, start Hash_TS2 operation state, end Hash_TS2 operation state, comparison V1 state, calculation R2 state, start Hash_R1R2 operation state, end Hash_R1R2 operation state, start Hash_FID operation state, end Hash_FID operation state, end FID1 storage state, start PUF_CIP1 operation state, end PUF_CIP1 operation state, start Hash_TS3 operation state, end Hash_TS3 operation state, start Hash_SK operation state, and end Hash_SK operation state.

[0091] Specifically, in the second authentication stage, the authentication check value V1, the confusion information DCi, DRi, DCi+1, the timestamp TS2, and five data are input from the outside, and the process of data flow is as follows:

[0092] (1) In the comparison TS2, generate TS3 timestamp, and wait for TS3 timestamp generation;

[0093] (2) In the end TS2 state, compare whether the difference between TS3 and TS2 is less than |Δ|, if not, authentication fails, if yes, enter the next state;

[0094] (3) In the start PUF operation state, send the data Ci to the PUF module for operation;

[0095] (4) In the end PUF operation state, wait for the end of PUF operation, and write the result into the register;

[0096] (5) In the start Hash_TS2 operation state, send the data R1, Ri, TS2 to the Hash module for calculation after merging, wherein R1 represents the random number generated in the first authentication stage, and Ri is generated by the PUF input excitation Ci;

[0097] (6) In the end Hash_TS2 operation state, wait for the Hash operation to end to get the result V1*;

[0098] (7) Compare V1 state, compare the values of V1 and V1* whether equal, if not equal, the authentication fails, equal to enter the next state;

[0099] (8) In the state of calculating R2, XOR DRi and Ri inputted from outside to get R2;

[0100] (9) In the start Hash_R1R2 operation state, send the data R1, Ri, R2 to the Hash module after merging to calculate;

[0101] (10) In the end Hash_R1R2 operation state, wait for the Hash operation to end to get the result SK;

[0102] (11) In the start Hash_FID operation state, send the Katakana data FID, R2 to the Hash module after merging to calculate;

[0103] (12) In the end Hash_FID operation state, wait for the Hash operation to end and mix, thereby getting the result FID1, and write into the Flash module;

[0104] (13) In the end FID1 storage state, wait for FID1 to be stored completely;

[0105] (14) In the start PUF_CIP1 operation state, send the i+1th challenge Ci+1 to the PUF module to operate;

[0106] (15) In the end PUF_CIP1 operation state, wait for the PUF operation to end, get the i+1th response Ri1;

[0107] (16) In the start Hash_TS3 operation state, send the data Ri, R2, TS3 to the Hash module after merging to calculate;

[0108] (17) In the end Hash_TS3 operation state, wait for the Hash operation to end to get the result V2;

[0109] (18) In the start Hash_SK operation state, send the data SK, TS3 to the Hash module after merging to calculate;

[0110] (19) In the end Hash_SK operation state, wait for the Hash operation to end and mix, thereby getting the result PRi.

[0111] Considering that the flow between each stage needs transition, the embodiment sets an idle state IDLE to connect the transition and flow between each state. In the IDLE state, the following three steps are included:

[0112] (1) If the judgment signal stage_h is 0 and server_ctrl_rig_vld is 1, enter the registration stage, and the data flow of 9 states is performed in the registration stage.

[0113] (2) If the judgment signal stage_h is not 0, stage_l is 0, and server_ctrl_auth_1_vld is 1, enter the first authentication stage, and the flow of 12 states is performed in the first authentication stage.

[0114] (3) If the judgment signal stage_h is not 0, stage_l is 1, and server_ctrl_auth_2_vld is 1, enter the second authentication stage, and the data flow of 19 states is performed in the stage.

[0115] The embodiment decomposes the complex logical relationship in the security protocol data flow into a series of finite and well-defined states to accurately map various security situations of the security protocol, each state is represented by a node in the state diagram, thereby enhancing the transparency and understandability of the overall design. Considering that the security protocol usually needs to communicate with different modules, the Control module ensures that the state machine can effectively and clearly manage the data transmission between different modules, and at the same time, by integrating and explicitly representing the state in the security protocol running process, the intuitiveness of the protocol data flow and state transition can be significantly improved, making the whole process easier to monitor and analyze.

[0116] Specifically, the embodiment constructs a finite state machine to perform the detailed steps of data flow:

[0117] Step 1: If the judgment signal stage_h is 0 and server_ctrl_rig_vld is 1, enter the registration stage. As shown in the registration stage, the data flow has 9 states in total, which are specifically: Figure 3

[0118] 1. RIG_PUF_CI_START (start PUF operation state): send data Ci to the PUF module for operation

[0119] 2. RIG_PUF_RI_WAIT_END (end PUF operation state): wait for the PUF operation to end, thereby obtaining the result Ri;

[0120] ​3. RIG_FLASH_FID_WRITE_WAIT_END (FID storage to Flash and wait for completion) ;

[0121] 4. RIG_HASH_ID_START (start Hash_ID operation state) : merge data IDe and PWe data and send to Hash module for calculation;

[0122] 5. RIG_HASH_ID_WAIT_END (end Hash_ID operation state) : wait for Hash operation to end and store result Ve in Flash;

[0123] 6. RIG_FLASH_VE_WRITE_WAIT_END (end Ve storage state) : wait for Ve storage to complete;

[0124] 7. RIG_HASH_PW_START (start Hash_PW operation state) : send data PWe to Hash module for operation, write next state judgment signal stage_h into Flash (prepare for entering authentication phase), and wait for storage to complete;

[0125] 8. RIG_HASH_PW_WAIT_END (end Hash_PW operation state) : wait for Hash operation to end and mix, and store result PK in Flash;

[0126] 9. RIG_FLASH_PK_WRITE_WAIT_END (end PK storage state) : wait for PK storage to complete.

[0127] Second step: if judgment signal stage_h is not 0, stage_l is 0 and server_ctrl_auth_1_vld is 1, then enter authentication phase 1. As shown in FIG. 2, the data flow of the first authentication phase has 12 states in total, which are as follows: Figure 4

[0128] 1. AUTH1_HASH_ID_START (start Hash_ID operation state) : merge data IDe and PWe data and send to Hash module for calculation;

[0129] 2. AUTH1_HASH_ID_WAIT_END (end Hash_ID operation state) : wait for Hash operation to end and obtain Ve*, read Ve value from Flash;

[0130] ​3. AUTH1_FLASH_VE_READ_WAIT_END (End Ve Read State): Wait for the end of Ve read;

[0131] 4. AUTH1_COMPARE_VE (Compare Ve State): Compare the value of Ve and Ve* to determine if they are equal. If not, authentication fails. If equal, enter the next state;

[0132] 5. AUTH1_PRNG_R1_START (Start Random Number Generation State): Obtain a timestamp TS1 and send TS1 to the PRNG module as a seed;

[0133] 6. AUTH1_PRNG_R1_WAIT_END (End Random Number Generation State): Wait for the PRNG module to generate a random number R1;

[0134] 7. AUTH1_FLASH_PK_READ (Start Read PK State): Read PK from Flash;

[0135] 8. AUTH1_FLASH_PK_WAIT_END (End Read PK State): Finish reading PK from Flash;

[0136] 9. AUTH1_HASH_PW_START (Start Hash_PW Operation State): Merge data PWe and send to the Hash module for calculation;

[0137] 10. AUTH1_HASH_PW_WAIT_END (End Hash_PW Operation State): Wait for the end of Hash operation and obfuscation, thereby obtaining the result PUK;

[0138] 11. AUTH1_FLASH_FID_READ (Start Read FID State): Read a specified FID from Flash;

[0139] 12. AUTH1_FLASH_FID_READ_WAIT_END (End Read FID State): Finish reading FID from Flash and set stage_l to 1, i.e., enter authentication phase 2.

[0140] Third step: If the judgment signal stage_h is not 0, stage_l is 1, and server_ctrl_auth_2_vld is 1, enter the second authentication phase. As shown in Figure 5 the data flow of the second authentication phase has a total of 19 states, as follows:

[0141] 1. AUTH2_COMPARE_TS2_START (compare TS2 state): generate TS3 timestamp; and wait for TS3 timestamp generation;

[0142] 2. AUTH2_COMPARE_TS2_WAIT_END (end TS2 state): compare whether the difference between TS3 and TS2 is less than |Δ|, if not, authentication fails, if yes, enter next state;

[0143] 3. AUTH2_PUF_CI_START (start PUF operation state): send data Ci to PUF module for operation;

[0144] 4. AUTH2_PUF_CI_WAIT_END (end PUF operation state): wait for PUF operation to end, and write the result into a register;

[0145] 5. AUTH2_HASH_TS2_START (start Hash_TS2 operation state): send the combined data R1, Ri, TS2 to Hash module for calculation;

[0146] 6. AUTH2_HASH_TS2_WAIT_END (end Hash_TS2 operation state): wait for Hash operation to end to obtain result V1*;

[0147] 7. AUTH2_COMPARE_V1 (compare V1 state): compare whether the values of V1 and V1* are equal, if not, authentication fails, if yes, enter next state;

[0148] 8. AUTH2_R2_STATE (calculate R2 state): XOR DRi and Ri to obtain R2;

[0149] 9. AUTH2_HASH_R1R2_START (start Hash_R1R2 operation state): send the combined data R1, Ri, R2 to Hash module for calculation;

[0150] 10. AUTH2_HASH_RIR2_WAIT_END (end Hash_R1R2 operation state): wait for Hash operation to end to obtain result SK;

[0151] 11. AUTH2_HASH_FID_START (start Hash_FID operation state): send the combined data FID, R2 to Hash module for calculation;

[0152] 12. AUTH2_HASH_FID_WAIT_END (End Hash_FID operation state): waiting for the end of Hash operation and confusion, thus obtaining the result FID1 and writing into the Flash module;

[0153] 13. AUTH2_FLASH_FID_WRITE (End FID1 storage state): waiting for the end of FID1 storage;

[0154] 14. AUTH2-PUF_CIP1_START (Start PUF_CIP1 operation state): sending data Ci1 to the PUF module for operation;

[0155] 15. AUTH2-PUF_CIP1-WAIT_END (End PUF_CIP1 operation state): waiting for the end of PUF operation, thus obtaining the result Ri1;

[0156] 16. AUTH2-HASH_TS3-START (Start Hash_TS3 operation state): sending the combined data Ri, R2, TS3 to the Hash module for calculation;

[0157] 17. AUTH2-HASH_TS3-WAIT_END (End Hash_TS3 operation state): waiting for the end of Hash operation to obtain the result V2;

[0158] 18. AUTH2-HASH_SK_START (Start Hash_SK operation state): sending the combined data SK, TS3 to the Hash module for calculation;

[0159] 19. AUTH2-HASH_SK_WAIT_END (End Hash_SK operation state): waiting for the end of Hash operation and confusion, thus obtaining the result PRi.

[0160] This embodiment, by designing the aforementioned 41 states according to the security protocol, clearly defines the correspondence between the state machine and the security protocol states. With this clear correspondence, data flow is effectively completed, realizing a finite state machine for data flow based on the security protocol. This method significantly improves the clarity of the security protocol states and the intuitiveness of data flow, ensuring that information data, under the control of the state machine, can flow rationally to the target module, making data flow between modules more explicit and clear. Therefore, by achieving precise data result acquisition and data control flow, the problems of unclear states, ambiguous data flow, and unintuitive flow processes during data flow can be directly solved. Simultaneously, through in-depth analysis and optimization of the protocol flow, and the simplification and merging of states in the finite state machine, the demand for hardware resources is effectively reduced, and the use of hardware resources is optimized, thus solving the problem of excessive hardware resource consumption in traditional security protocol implementations. The finite state machine also effectively avoids the repeated instantiation of algorithm modules, avoiding increased power consumption and layout / routing difficulties caused by increased resource usage, while also increasing maintainability and scalability. Furthermore, by rationally arranging data flow and intelligently managing control modules, the system's operational efficiency and response speed can be significantly improved. This ensures overall system security while reducing costs, achieving high efficiency and economy in resource utilization. These improvements also contribute to enhancing protocol transparency and verifiability, thereby increasing system reliability and security.

[0161] This embodiment also provides an apparatus for implementing the above-described data flow finite state machine implementation method based on a security protocol, such as... Figure 1 As shown, its modules include: a control module and a Flash module, a Hash module, a clock module, a pseudo-random number generator module, a PUF module, and an interface module, which are respectively connected to the control module. The Hash module is used to perform Hash calculations, the pseudo-random number generator module is used to generate pseudo-random numbers, and the PUF module is used to generate identity identifiers or security keys. The control module controls the data communication between the above modules, and the implementation process of each module is as described above.

[0162] The application realizes a high-efficiency state machine by using the above method, each state of which corresponds to a calculation process in the security protocol. According to the different calculation time, 1 to 2 states are set according to the length of the running period of each module. For the module with long calculation period, two states of "start" and "wait for end" are set, and for the module with short calculation period, only one state is set. Further, in order to effectively shorten the number of states, two steps are simultaneously performed in the same state, for example, for two long-period calculations, the start of the next state is entered while the end of the previous state is entered. The above design not only can clearly indicate the corresponding security protocol step of each state, but also can simplify the state as much as possible, so that the correctness of data flow is ensured while the simplicity and clarity of the process are maintained.

[0163] The embodiment further provides a computer readable storage medium storing a computer program, which is executed by a processor to realize the method.

[0164] Those skilled in the art should understand that the above-mentioned embodiments of the application can be provided as a method, a system or a computer program product. Therefore, the application can adopt a completely hardware embodiment, a completely software embodiment or an embodiment combining software and hardware aspects. Moreover, the application can adopt a computer program product in the form of one or more computer readable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer usable program codes. The application is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to the embodiments of the application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams and the combination of the flows and / or blocks can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The functions specified in one or more flows and / or blocks These computer program instructions can also be stored in a computer readable memory capable of causing the computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including instruction devices, which realize the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks Figure 1the functions specified in the flow or flows and / or blocks of the flow or flows. Such computer program instructions can also be loaded into a computer or other programmable data processing devices, so that a series of operational steps are generated to realize the computer-implemented processing, and the instructions executed on the computer or other programmable devices provide a process for implementing the functions specified in the flow or flows and / or blocks of the flow or flows. Figure 1 the functions specified in the flow or flows and / or blocks of the flow or flows. Such computer program instructions can also be loaded into a computer or other programmable data processing devices, so that a series of operational steps are generated to realize the computer-implemented processing, and the instructions executed on the computer or other programmable devices provide a process for implementing the functions specified in the flow or flows and / or blocks of the flow or flows. ​ the functions specified in the flow or flows and / or blocks of the flow or flows. Such computer program instructions can also be loaded into a computer or other programmable data processing devices, so that a series of operational steps are generated to realize the computer-implemented processing, and the instructions executed on the computer or other programmable devices provide a process for implementing the functions specified in the flow or flows and / or blocks of the flow or flows.

[0165] The above description is only the preferred embodiments of the present application, and the protection scope of the present application is not limited to the above-mentioned embodiments. Any technical solutions falling within the concept of the present application shall be deemed to fall within the protection scope of the present application. It should be noted that, for ordinary skilled in the art, some improvements and refinements without departing from the principles of the present application shall also be deemed to fall within the protection scope of the present application.

Claims

1. A method for implementing a finite state machine for data flow based on a security protocol, characterized in that, The steps in implementing the method are as follows: (1) In the idle state, acquire the stage judgment signal and the server control register verification signal to determine the current stage; (2) Based on the status of the stage judgment signal and the server control register verification signal, enter the registration stage, the first authentication stage and the second authentication stage respectively; (3) During the registration phase, data is circulated through the PUF module, Hash module and Flash module to realize the protocol to register user information with the server; (4) In the first authentication phase, data flow is achieved through the Hash module, pseudo-random number generator module, clock module and Flash module to realize the authentication of the protocol user terminal; (5) In the second authentication phase, authentication or session key negotiation is performed through the PUF module, Hash module, clock module and Hash module; During the registration phase, the data flow sequentially includes: start PUF operation state, end PUF operation state, store FID state, start Hash_ID operation state, end Hash_ID operation state, end Ve storage state, start Hash_PW operation state, end Hash_PW operation state, and end PK storage state; during the first authentication phase, the data flow sequentially includes: start Hash_ID operation state, end Hash_ID operation state, end Ve read state, compare Ve state, start random number generation state, end random number generation state, start PK read state, end PK read state, start Hash_PW operation state, end Hash_PW operation state, start FID read state, and end FID read state. In the second authentication phase, the data flow sequentially includes: comparing TS2 states, ending TS2 states, starting PUF operation states, ending PUF operation states, starting Hash_TS2 operation states, ending Hash_TS2 operation states, comparing V1 states, calculating R2 states, starting Hash_R1R2 operation states, ending Hash_R1R2 operation states, starting Hash_FID operation states, ending Hash_FID operation states, ending FID1 storage states, starting PUF_CIP1 operation states, ending PUF_CIP1 operation states, starting Hash_TS3 operation states, ending Hash_TS3 operation states, starting Hash_SK operation states, and ending Hash_SK operation states.

2. The data flow finite state machine implementation method based on security protocols according to claim 1, characterized in that, The data flow process during the registration phase includes: (1) In the start PUF operation state, the i-th challenge Ci is sent to the PUF module for operation, and when the PUF operation state ends, the PUF operation is waited for to end, so as to obtain the result Ri; (2) In the FID state of the storage fragment kana, store the FID in the Flash and wait for the storage to complete; (3) In the state of starting Hash_ID operation, the username IDe and password data PWe are merged and sent to the Hash module for calculation; (4) In the state of ending Hash_ID operation, wait for the Hash operation to end, and store the authentication verification value Ve obtained by the Hash operation result into Flash; (5) In the state of ending Ve storage, wait for the authentication verification value Ve to be stored. (6) In the start Hash_PW operation state, the password data PWe is sent to the Hash module for operation, the next state judgment signal stage_h is written into the Flash module, and the storage is waited for to be completed; in the end Hash_PW operation state, the Hash operation is waited for to be completed and obfuscated, and the obfuscated result PK is stored into the Flash module. (7) In the state of ending PK storage, wait for the obfuscation result PK storage to be completed.

3. The data flow finite state machine implementation method based on security protocol according to claim 1, characterized in that, The data flow process in the first authentication phase includes: (1) In the state of starting Hash_ID operation, the username IDe and password data PWe are merged and sent to the Hash module for calculation; in the state of ending Hash_ID operation, wait for the Hash operation to end, and thus obtain the second authentication verification value Ve*. Read the value of the first authentication verification value Ve obtained in the registration stage from the Flash module. (2) In the state of ending Ve reading, wait for the first authentication verification value Ve to finish reading; in the state of comparing Ve, compare whether the values ​​of the first authentication verification value Ve and the second authentication verification value Ve* are equal. If they are not equal, authentication fails; if they are equal, proceed to the next state. (3) In the state of starting random number generation, obtain the timestamp TS1 and send the timestamp TS1 as a seed to the pseudo-random number generator module; in the state of ending random number generation, wait for the pseudo-random number generator module to generate a random number R1. (4) When the PK reading starts, the PK is read from the Flash module; when the PK reading ends, the PK reading from the Flash module is complete. (5) In the start Hash_PW operation state, the data PWe is merged and sent to the Hash module for calculation; in the end Hash_PW operation state, the Hash operation is waited for to end and the data is obfuscated to obtain the result PUK. (6) In the state of starting to read FID, the specified FID is read from the Flash module; in the state of ending to read FID, the katakana FID stored in the registration stage is read from the Flash, the stage judgment signal stage_l is set to 1, and the second authentication stage is about to begin.

4. The data flow finite state machine implementation method based on security protocol according to claim 1, characterized in that, In the second authentication phase, the data flow process, which involves externally inputting the authentication verification value V1, obfuscation information DCi, DRi, DCi+1, and timestamp TS2, includes: (1) In the TS2 comparison state, generate the TS3 timestamp and wait for the TS3 timestamp to be generated; when the TS2 state ends, compare whether the difference between TS3 and TS2 is less than |△|. If it does not meet the requirements, the authentication fails; if it does meet the requirements, proceed to the next state. (2) In the start PUF operation state, the i-th challenge data Ci is sent to the PUF module for operation; in the end PUF operation state, wait for the PUF operation to end and write the result to the register; (3) In the state of starting Hash_TS2 operation, the data R1, Ri and TS2 are merged and sent to the Hash module for calculation, where R1 represents the random number generated in the first authentication stage and Ri is generated by the stimulus Ci given by PUF; in the state of ending Hash_TS2 operation, wait for the Hash operation to end and get the result V1*; in the state of comparing V1, compare whether the values ​​of V1 and V1* are equal. If they are not equal, the authentication fails. If they are equal, proceed to the next state. (4) In the R2 calculation state, DRi and Ri are XORed to obtain R2; in the Hash_R1R2 operation state, the data R1, Ri and R2 are merged and sent to the Hash module for calculation; in the Hash_R1R2 operation state, the Hash operation is waited for to end, and the result SK is obtained. (5) In the state of starting Hash_FID operation, the data FID and R2 are merged and sent to the Hash module for calculation; in the state of ending Hash_FID operation, wait for the Hash operation to end and obfuscate, so as to obtain the result FID1 and write it to the Flash module; in the state of ending FID1 storage, wait for FID1 to be stored. (6) In the PUF_CIP1 start operation state, the data Ci1 is sent to the PUF module for operation; in the PUF_CIP1 end operation state, wait for the PUF operation to end, and thus obtain the result Ri1; in the Hash_TS3 start operation state, the data Ri, R2, and TS3 are merged and sent to the Hash module for calculation; in the Hash_TS3 end operation state, wait for the Hash operation to end, and thus obtain the result V2; (7) In the initial Hash_SK operation state, the data SK and TS3 are merged and sent to the Hash module for calculation; in the final Hash_SK operation state, the Hash operation is waited for to end and the result PRi is obtained.

5. The data flow finite state machine implementation method based on security protocols according to any one of claims 1 to 4, characterized in that, Based on the status of the stage judgment signal and the server control register verification signal, the system enters the registration stage, the first authentication stage, and the second authentication stage, respectively. The specific judgment conditions are as follows: (1) If the stage judgment signal stage_h is 0 and the server control register verification signal server_ctrl_rig_vld is 1, then the registration stage is entered; (2) If the stage judgment signal stage_h is not 0, stage_l is 0 and the server control register verification signal server_ctrl_auth_1_vld is 1, then the first authentication stage is entered; (3) If the stage judgment signal stage_h is not 0, stage_l is 1 and the server control register verification signal server_ctrl_auth_2_vld is 1, then the second authentication stage is entered.

6. An apparatus for implementing the data flow finite state machine method based on a security protocol as described in any one of claims 1 to 4, the apparatus comprising: The system includes a control module and several modules connected to it, including a Flash module, a Hash module, a clock module, a pseudo-random number generator module, a PUF module, and an interface module. The Hash module is used for hash calculations, the random number generator module is used for generating pseudo-random numbers, and the PUF module is used for generating identity identifiers or security keys. The control module controls the data communication between the other modules.

7. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the method as described in any one of claims 1 to 4.

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