Multifunctional vehicle bus communication network card based on FPGA and RISC-V

Abstract

The present invention relates to a multifunctional vehicle bus communication network card based on FPGA and RISC-V, comprising a user interface, an FPGA chip, and a transceiver circuit. The user interface is a PC104 interface, which connects the FPGA chip to a host computer bus; the FPGA chip comprises an FPGA logic module, an AXI-to-EMIF bus module, and a RISC-V processor. The FPGA logic module receives and processes host computer instructions and MVB bus signals, packages them into MVB frames for transmission; the RISC-V processor processes the instructions and data of the FPGA logic module; the AXI-to-EMIF bus module implements interface conversion; and the transceiver circuit processes MVB frame signals. The FPGA logic module also controls the transmission and reception of MVB links and frames. The present invention solves the problems of high complexity, cost, and large size of existing MVB communication equipment.

Description

Technical Field

[0001] The present invention belongs to the field of rail transportation technology, and in particular relates to a multifunctional vehicle bus communication network card based on FPGA and RISC-V. Background Art

[0002] The Multifunction Vehicle Bus (MVB) is a communication bus used for railway vehicle control and monitoring. Due to its high reliability and real-time performance, the MVB bus is widely used in railway vehicle control and monitoring systems. According to IEC-61375, devices connected to the MVB can be divided into five functional categories. Category 1-3 devices possess device status, process data, or message data capabilities and can serve as MVB slaves. Category 4 and 5 devices also possess bus management capabilities, allowing them to function as both slaves and masters. Traditional Category 4 or 5 MVB devices utilize an MCU + FPGA standalone chip architecture, with the MCU handling the communication protocol and data logic, and the FPGA (Field-Programmable Gate Array) implementing the communication interface and protocol control. However, this standalone chip architecture increases board complexity, cost, and size.

[0003] RISC-V is an open standard instruction set architecture (ISA), its full name is Reduced Instruction Set Computer V. It is based on the mature reduced instruction set computer (RISC) design principles. It is an open, flexible and scalable computer architecture with broad application prospects in the processor field.

[0004] Therefore, it is of great significance to design an integrated solution based on domestic FPGA and RISC-V to meet the requirements of railway vehicle control and monitoring systems for high reliability, low cost and small size, and to realize independent and controllable cost-effective Category 4 or Category 5 MVB communication network cards. Summary of the Invention

[0005] Aiming at the shortcomings in the related art and solving the problems of high complexity, cost and large size of existing MVB communication equipment in the prior art, the present invention provides a multifunctional vehicle bus communication network card based on FPGA and RISC-V.

[0006] In one possible implementation, a multifunctional vehicle bus communication network card based on FPGA and RISC-V is provided, comprising: a user interface, an FPGA chip and a transceiver circuit; wherein the user interface is a PC104 interface, connecting the FPGA chip to the bus of the host computer; the FPGA chip comprises: an FPGA logic module, an AXI to EMIF bus module and a RISC-V processor; wherein the FPGA logic module is configured to: receive instructions and / or data from the host computer, send the received instructions and / or data to the RISC-V processor; receive processing results sent by the RISC-V processor and send them to the host computer; receive signals transmitted from the MVB bus via the transceiver circuit, and perform one or more of the following operations: frame parsing, data processing and status monitoring; and package the processed data into MV B frame is sent to the MVB bus through the transceiver circuit; the RISC-V processor is configured to receive and process instructions and / or data sent by the FPGA logic module, and send the processing results to the FPGA logic module; the AXI to EMIF bus module, whose AXI bus is connected to the RISC-V processor and whose EMIF bus is connected to the FPGA logic module, is configured for interface conversion between the AXI bus and the EMIF bus; the transceiver circuit connects the FPGA chip and the MVB bus, and is configured to: receive the MVB frame sent from the FPGA logic module, and transmit the converted signal to the MVB bus; and receive the signal transmitted from the MVB bus, convert it into a standard signal and send it to the FPGA logic module; wherein the FPGA logic module is also configured to perform MVB link control and MVB frame transmission and reception control.

[0007] In one possible implementation, the FPGA logic module includes a PC104 protocol module, an MVB bus transceiver module, a RISC-V processor interface module, an MVB link layer control module, and a memory management module; wherein the PC104 protocol module communicates with the host computer and can access the memory management module and write to the memory management module; the MVB bus transceiver module communicates with the MVB bus and can access the memory management module and write to the memory management module; the RISC-V processor interface module communicates with the RISC-V processor and can access the memory management module and write to the memory management module; the MVB link layer control module is configured to perform MVB link control; the memory management module is used to store data, including one or more of the following: MVB configuration data, communication data.

[0008] In one possible implementation, the PC104 protocol module includes: a PC104 receiving module, a PC104 sending module and a PC104 control module; the PC104 receiving module receives commands and parameters from the host computer through a parallel bus, and sends a command reception completion pulse to the PC104 control module; the PC104 sending module receives command return data processed by the PC104 control module, and sends it to the host computer through the parallel bus; the PC104 control module processes the received command and sends the result to the PC104 sending module.

[0009] In one possible implementation, the MVB bus transceiver module includes: an MVB sending module, an MVB-A path receiving module, an MVB-B path receiving module, and an AB path selection control module; the MVB sending module is configured to send master-slave frames according to the MVB standard; the MVB-A path receiving module and the MVB-B path receiving module are configured to receive data frames transmitted on the MVB bus; the AB path selection control module is configured to perform AB path redundancy switching of the MVB bus, process the redundant switching, and forward the data set as the trust line in the AB path upward.

[0010] In a possible implementation, the MVB link layer control module is configured to perform one or more of the following operations: process data master frame transmission, process data slave frame processing, monitoring data slave frame processing, and message data slave frame processing.

[0011] In one possible implementation, the RISC-V processor adopts a three-stage pipeline processor architecture, including an instruction fetch unit, a decoding unit, and an execution unit connected in sequence, a pipeline buffer I is set between the instruction fetch unit and the decoding unit, and a pipeline buffer II is set between the decoding unit and the execution unit, and also includes a pipeline controller connected to the instruction fetch unit, the decoding unit, and the execution unit; wherein the instruction fetch unit is configured to be controlled by the pipeline controller to obtain instructions and pre-process the instructions via the AXI bus, and send the processed instructions to the pipeline memory I and / or store them in the memory via the AXI bus; the pipeline buffer I is configured to store the instruction fetch unit. The preprocessed instructions and / or the instructions output by the memory are sent to the decoding unit after being synchronized; the decoding unit is configured to decode according to the instructions sent by the pipeline buffer I module, and after decoding the specific instructions, it generates a signal whether to read or write the register; when the decoding unit sends a read register signal, the register module immediately sends the data of the read register module, and the data of the register module and the write register signal are sent to the pipeline buffer II together; the pipeline buffer II is configured to synchronize the signal whether to write the register and the data of the register module and send them to the execution unit; the execution unit is a combinational logic circuit, which performs corresponding operations according to the specific instructions.

[0012] In one possible embodiment, the pipeline controller is further configured to: be connected to the decoding unit and / or the execution unit, and be used to send one or more of the following instructions: pipeline pause, jump; the instruction fetch unit, decoding unit and / or execution unit are controlled by the instructions of the pipeline controller to perform corresponding pipeline pause and / or jump operations.

[0013] In one possible embodiment, the transceiver circuit includes an RS485 chip, an ESD protection circuit, an isolation transformer, and an AC decoupling circuit connected in sequence; wherein, the RS485 chip is used to convert the single-ended signal of the FPGA chip into an RS485 level standard signal, which is output to the MVB bus after passing through the ESD protection circuit, the isolation transformer, and the AC decoupling circuit.

[0014] Based on the above technical solution, in the multifunctional vehicle bus communication network card based on FPGA and RISC-V of the present invention, the user interface connects the FPGA chip to the host computer bus, the logic module of the FPGA chip receives the instructions and data of the host computer, and passes them to the RISC-V processor for processing; the processed results are returned to the host computer through the FPGA logic module; at the same time, the FPGA logic module communicates with the MVB bus through the transceiver circuit, receives the signal transmitted by the MVB bus, performs frame parsing, data processing and status monitoring, and packages the processed data into MVB frames and sends them back to the MVB bus; the AXI to EMIF bus module is used for interface conversion between the RISC-V processor and the FPGA logic module, ensuring efficient transmission and processing of data, realizing reliable communication and efficient processing of the vehicle bus communication network card, and solving the problems of high complexity, cost and large size of existing MVB communication equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0016] Figure 1 This is a logical architecture diagram of a multi-function vehicle bus communication network card based on FPGA and RISC-V according to an embodiment of the present invention;

[0017] Figure 2 A circuit block diagram of a transceiver circuit according to an embodiment of the present invention;

[0018] Figure 3 This is the logical architecture diagram of the FPGA logic module;

[0019] Figure 4 This is the overall architecture diagram of the RISC-V processor. DETAILED DESCRIPTION

[0020] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0021] In the description of the present invention, it should be understood that the terms "center", "transverse", "longitudinal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0022] The terms "first," "second," and "third" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or to implicitly specify the quantity of the technical features indicated. Therefore, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of such features.

[0023] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0024] In order to solve the problems of high complexity, cost and large size of existing MVB communication equipment in the prior art.

[0025] This application provides a multifunctional vehicle bus communication network card based on FPGA and RISC-V, see Figure 1, including: user interface, FPGA chip and transceiver circuit; wherein, the user interface is a PC104 interface, which connects the FPGA chip to the bus of the host computer; the FPGA chip includes: FPGA logic module, AXI to EMIF bus module and RISC-V processor; wherein, the FPGA logic module is configured to: receive instructions and / or data from the host computer, send the received instructions and / or data to the RISC-V processor; receive the processing results sent by the RISC-V processor and send them to the host computer; receive the signal transmitted from the MVB bus through the transceiver circuit, and perform one or more of the following operations: frame parsing, data processing and status monitoring; pack the processed data into MVB frames, and send them to the MVB bus through the transceiver circuit; The C-V processor is configured to receive and process instructions and / or data sent by the FPGA logic module and send the processing results to the FPGA logic module; the AXI to EMIF bus module, whose AXI bus is connected to the RISC-V processor and whose EMIF bus is connected to the FPGA logic module, is configured for interface conversion between the AXI bus and the EMIF bus; the transceiver circuit is connected to the FPGA chip and the MVB bus and is configured to: receive the MVB frame sent from the FPGA logic module and transmit the converted signal to the MVB bus; and receive the signal transmitted from the MVB bus and convert it into a standard signal before sending it to the FPGA logic module; wherein the FPGA logic module is also configured to perform MVB link control and MVB frame transmission and reception control.

[0026] In the above solution, the synergy between FPGA and RISC-V processor is utilized to realize the communication between the host computer and the MVB bus. The logic module in the FPGA chip is responsible for receiving instructions or data from the host computer and sending them to the RISC-V processor through the AXI to EMIF bus module. After processing, the RISC-V processor returns the results to the FPGA logic module. The FPGA logic module also receives the signal of the MVB bus through the transceiver circuit, and performs data analysis, data processing and status monitoring. The processed data is then packaged into MVB frames and sent back to the MVB bus to realize complete two-way communication.

[0027] By leveraging the high parallel processing capabilities of the FPGA and the flexibility of the RISC-V processor, complex bus communication tasks can be efficiently handled. The adoption of the PC104 interface enables the network card to be easily connected to various host computers. Through the precise control of the FPGA logic module, the transmission and reception of MVB frames and link control are realized, ensuring the accuracy and real-time performance of data transmission. In addition, the modular design makes the system highly scalable and easy to maintain.

[0028] See also Figure 3In one possible implementation, the FPGA logic module includes a PC104 protocol module, an MVB bus transceiver module, a RISC-V processor interface module, an MVB link layer control module, and a memory management module; wherein the PC104 protocol module communicates with a host computer and can access the memory management module and write to the memory management module; the MVB bus transceiver module communicates with the MVB bus and can access the memory management module and write to the memory management module; the RISC-V processor interface module communicates with the RISC-V processor and can access the memory management module and write to the memory management module; the MVB link layer control module is configured to perform MVB link control; and the memory management module is used to store data, including one or more of the following: MVB configuration data and communication data.

[0029] The FPGA logic module realizes the communication between the host computer and the MVB bus and RISC-V processor through different sub-modules; the PC104 protocol module exchanges data with the host computer and stores the received data in the memory management module; the MVB bus transceiver module is responsible for communicating with the MVB bus and also stores the data in the memory management module; the RISC-V processor interface module is responsible for communicating with the RISC-V processor and transmitting processing instructions and data; the MVB link layer control module is used to control the MVB link to ensure the stability and reliability of data transmission.

[0030] Through modular design, each functional module operates independently, improving the stability and scalability of the system; the use of the memory management module ensures efficient storage and access of data, improving communication efficiency; the flexible configuration of the FPGA logic module enables the system to adapt to different application requirements, with high adaptability and scalability.

[0031] In the above implementation, the PC104 protocol module can be replaced with other protocol modules, such as a PCIe protocol module, to adapt to different host computer interfaces; the memory management module can use different types of memory, such as SRAM or DDR memory, to improve system performance.

[0032] In one possible implementation, the PC104 protocol module includes: a PC104 receiving module, a PC104 sending module and a PC104 control module; the PC104 receiving module receives commands and parameters from the host computer through a parallel bus, and sends a command reception completion pulse to the PC104 control module; the PC104 sending module receives command return data processed by the PC104 control module, and sends it to the host computer through the parallel bus; the PC104 control module processes the received command and sends the result to the PC104 sending module.

[0033] In the above scheme, the PC104 protocol module realizes communication with the host computer through the coordinated work of the PC104 receiving module, the PC104 sending module and the PC104 control module; the receiving module receives the commands and parameters of the host computer and sends them to the PC104 control module; the PC104 control module processes these commands and sends the processing results to the PC104 sending module, and the PC104 sending module then returns the processing results to the host computer; the entire process uses a parallel bus for data transmission, ensuring efficient communication.

[0034] The modular setup simplifies communication with the host computer and improves data transmission efficiency and reliability. The clear division of labor among the PC104 receiving module, PC104 transmitting module, and PC104 control module allows each module to focus on its specific function, improving system stability and maintainability.

[0035] See also Figure 3 In one possible implementation, the MVB bus transceiver module includes: an MVB sending module, an MVB-A receiving module, an MVB-B receiving module, and an AB path selection control module; the MVB sending module is configured to send master-slave frames according to the MVB standard; the MVB-A receiving module and the MVB-B receiving module are configured to receive data frames transmitted on the MVB bus; the AB path selection control module is configured to perform AB path redundancy switching of the MVB bus, process the redundancy switching, and forward the data set as the trust line in the AB path upward; because the MVB bus reception is mutually redundant in AB, at a certain moment one line is a trust line and the other is a redundant line; the AB path selection control module is responsible for processing the redundancy switching and forwarding the trust line data upward.

[0036] For example, by default, path A is the trusted line and path B is the redundant line. This module is responsible for switching when the following conditions occur: 1) no frames arrive for a long time; 2) the trusted line is disturbed, such as a CRC check error; 3) the redundant line receives a valid frame, but the trusted line does not.

[0037] The MVB bus transceiver module realizes communication with the MVB bus through the sending module, MVB-A receiving module, MVB-B receiving module and AB selection control module; the sending module sends master-slave frames according to the MVB standard; the MVB-A receiving module and MVB-B receiving module respectively receive data frames transmitted on the MVB bus; the AB selection control module is responsible for redundant switching of the AB channels to ensure the reliability and stability of data transmission and forward the trust line data upward.

[0038] The adoption of AB redundant design improves the reliability and anti-interference capability of data transmission; the independent design of the sending module and the receiving module enables the system to efficiently send and receive data; the setting of the AB selection control module realizes automatic redundant switching, which improves the stability and reliability of the system.

[0039] In a possible implementation, the MVB link layer control module is configured to perform one or more of the following operations: process data master frame transmission, process data slave frame processing, monitoring data slave frame processing, and message data slave frame processing.

[0040] The MVB link layer control module controls the MVB link layer by processing the sending of process data master frames, processing process data slave frames, processing monitoring data slave frames, and processing message data slave frames. The module uses corresponding processing methods according to different data types to ensure the correctness and reliability of data transmission.

[0041] By classifying and processing different types of data frames, the efficiency and accuracy of data transmission are improved. The setting of the MVB link layer control module enables the system to better manage and control data transmission, improving the overall performance of the system.

[0042] See also Figure 4 In one possible implementation, the RISC-V processor adopts a three-stage pipeline processor architecture, including an instruction fetch unit, a decoding unit, and an execution unit connected in sequence, a pipeline buffer I is set between the instruction fetch unit and the decoding unit, and a pipeline buffer II is set between the decoding unit and the execution unit, and further includes a pipeline controller connected to the instruction fetch unit, the decoding unit, and the execution unit; wherein the instruction fetch unit is configured to be controlled by the pipeline controller to obtain instructions and pre-process the instructions via an AXI bus, and send the processed instructions to the pipeline memory I and / or store them in the storage unit via the AXI bus; the pipeline buffer I is configured to store the instruction fetch unit. The preprocessed instructions and / or the instructions output by the storage unit are sent to the decoding unit after being synchronized; the decoding unit is configured to decode according to the instructions sent by the pipeline buffer I module, and after decoding the specific instructions, it generates a signal whether to read or write the register; when the decoding unit sends a read register signal, the register module immediately sends the data of the read register module, and the data of the register module and the write register signal are sent to the pipeline buffer II together; the pipeline buffer II is configured to synchronize the signal whether to write the register and the data of the register module and send them to the execution unit; the execution unit is a combinational logic circuit, which performs corresponding operations according to the specific instructions.

[0043] The RISC-V processor adopts a three-stage pipeline processor architecture, which achieves efficient instruction processing through the collaborative work of the instruction fetch unit, decoding unit and execution unit; the instruction fetch unit is controlled by the pipeline controller, obtains and preprocesses instructions through the AXI bus, and sends the preprocessed instructions to the pipeline memory I or storage unit; the decoding unit decodes the instructions sent by the pipeline buffer I, generates a signal whether to read or write the register, and sends the data to the pipeline buffer II; the execution unit operates according to the specific instructions to complete the instruction execution.

[0044] The three-stage pipeline architecture improves instruction processing efficiency and parallel processing capabilities. The introduction of pipeline buffers I and II reduces data transmission latency and improves overall system performance. Through the control of the pipeline controller, instruction processing is optimized and scheduled, improving system stability and reliability.

[0045] See also Figure 4 In one possible embodiment, the pipeline controller is further configured to: be connected to the decoding unit and / or the execution unit, and be used to send one or more of the following instructions: pipeline pause, jump; the instruction fetch unit, the decoding unit and / or the execution unit are controlled by the instructions of the pipeline controller to perform corresponding pipeline pause and / or jump operations.

[0046] The pipeline controller sends pipeline pause and jump instructions by connecting to the decoding unit and execution unit to control the operations of the instruction fetch unit, decoding unit and execution unit; the instruction fetch unit pauses or continues to fetch instructions according to the controller instructions, the decoding unit pauses or continues decoding according to the controller instructions, and the execution unit pauses or continues execution operations according to the controller instructions.

[0047] By setting up a pipeline controller, precise control of pipeline operations is achieved, improving the stability and flexibility of the system; the use of pipeline pause and jump instructions optimizes the instruction processing flow, reduces pipeline pauses and delays, and improves the overall performance of the system.

[0048] See also Figure 2 In one possible implementation, the transceiver circuit includes an RS485 chip, an ESD protection circuit, an isolation transformer, and an AC decoupling circuit connected in sequence; wherein the RS485 chip is used to convert the single-ended signal of the FPGA chip into an RS485 level standard signal, which is then output to the MVB bus after passing through the ESD protection circuit, the isolation transformer, and the AC decoupling circuit.

[0049] The transceiver circuit converts the single-ended signal of the FPGA chip into an RS485 level standard signal through the RS485 chip, and then passes through the ESD protection circuit, isolation transformer and AC decoupling circuit, and finally outputs it to the MVB bus; the ESD protection circuit protects the circuit from the influence of electrostatic discharge, the isolation transformer provides electrical isolation, and the AC decoupling circuit eliminates the coupling interference of the AC signal.

[0050] By introducing the RS485 chip, standardized signal conversion is achieved, ensuring the reliability of signal transmission; the use of ESD protection circuits, isolation transformers and AC decoupling circuits improves the system's stability and anti-interference capabilities, ensuring the security of data transmission.

[0051] The multifunctional vehicle bus communication network card based on FPGA and RISC-V according to one embodiment of the present invention is specifically described as follows:

[0052] A design scheme for four types of MVB communication network cards based on domestic FPGA and RISC-V is provided. According to the system configuration requirements, the query, management and arbitration of devices on the MVB are organized, and the following functions need to be completed: (1) MVB process data communication function; (2) MVB message data communication function; (3) MVB bus master function; (4) MVB device status function; (5) user programmable function; (6) accepting host computer commands to realize dynamic configuration; (7) providing slave frame data according to the master frame requirements when the own data is the source data; (8) MVB bus data complies with the IEC 61375-1 standard definition, and the transmission and reception have two-way redundancy, can be switched according to the interference situation, and send interference status reports; (9) the mechanical structure meets the PC104 standard; (10) the MVB interface uses EMD medium, that is, transformer isolation.

[0053] The RISC-V SoC is implemented using an FPGA, with the RISC-V processor core and FPGA logic working in tandem, replacing the original MCU + FPGA standalone chip architecture. In this new design, the MCU is responsible for running message data, device status, and sovereignty transfer link control logic, while the FPGA is responsible for the user interface, remaining MVB link control, and MVB frame transmission and reception. This integrated solution achieves complete autonomy and control of the MVB product while simultaneously reducing board area, lowering costs, and improving product competitiveness.

[0054] To achieve the above objectives, the technical solutions of the present invention are as follows.

[0055] This design of MVB network card is mainly based on FPGA. Figure 1 As shown in the figure, it includes user interface, transceiver circuit, FPGA logic module and RISC-V processor.

[0056] (1) User interface

[0057] The user interface in this embodiment uses the PC104 interface, an industrial control bus specifically defined for embedded systems. The 8-bit version of PC104 has 64 bus pins, with single-row and double-row pins and sockets. When the MVB network card device is actually used, if the host computer platform containing the CPU board needs to control the MVB network card, the PC104 interface can be used to connect the MVB network card to the host computer's bus.

[0058] (2) Transceiver circuit

[0059] The transceiver circuit uses an RS485 transceiver. The single-ended signal is converted to an RS485 level standard signal, then passes through a TVS tube protection / ESD protection circuit and transformer isolation, and is finally output to the MVB bus. Figure 2 .

[0060] In this circuit, a full-duplex RS485 chip is used, enabling the MVB board to transmit and receive simultaneously. ESD protection primarily protects the circuit from damage caused by external pulses and surges. An isolation transformer completely isolates our circuit from external communication lines, resulting in lower insertion loss and improved signal integrity. AC isolation capacitors block DC signal components on the MVB bus to prevent damage to the isolation transformer.

[0061] (3) FPGA logic module

[0062] The FPGA logic module is at the core of the MVB network card, responsible for MVB link control and MVB frame transmission and reception. It interfaces with the RISC-V processor, user interface, and transceiver circuits, completing message data scheduling, sovereignty transfer, and device status scanning through communication with the RISC-V. It provides MVB link layer services through the user interface and completes MVB frame transmission and reception by connecting to the transceiver circuits.

[0063] The FPGA logic module in the MVB network card interacts directly with the user interface, RISC-V processor, and transceiver circuits. The FPGA logic plays a dominant role in the MVB network card, implementing all core functions. These include providing parallel bus access services to users, parsing the PC104 protocol and executing commands based on the parallel bus, MVB frame transmission and reception, MVB process data master frame polling, slave frame processing, MVB message data slave frame processing, MVB monitoring data slave frame processing, and interaction with the RISC-V processor.

[0064] FPGA logic module function detailed division see Figure 3 .

[0065] The FPGA logic module is divided into five functional components: PC104 protocol, MVB bus transceiver, RISC-V processor interface, MVB link control, and memory management. The PC104 protocol consists of three submodules: PC104 receive, PC104 transmit, and PC104 control. The MVB bus transceiver consists of four submodules: MVB transmit, MVB A-channel receive, MVB B-channel receive, and AB-channel selection control. The RISC-V processor interface, MVB link control, and memory management modules each contain one submodule.

[0066] 1) PC104 protocol module

[0067] The PC104 receiving module receives the PC104 command word and command parameters sent by the host computer through the parallel bus, determines the parameter length based on the command word, buffers the command word and parameters, and sends a command reception completion pulse to the PC104 control module after receiving all the commands.

[0068] The PC104 sending module receives the command word return data sent by the PC104 control module, caches it, and sends the command word return data to the host computer through the parallel bus.

[0069] The PC104 control module receives the command buffered by the PC104 receiving module, processes the command, and sends the return result to the PC104 sending module.

[0070] 2) MVB bus transceiver module

[0071] The MVB sending module provides MVB master-slave frame sending services to other modules according to the MVB standard's provisions on frame formats.

[0072] The MVB A-channel receiving module and the MVB B-channel receiving module implement the receiving service of the data frames on the MVB bus according to the frame format provisions of the MVB standard.

[0073] The AB route selection control module is responsible for controlling the AB route redundancy switching of the MVB bus. At a certain moment, one line is the trusted line and the other is the redundant line. This module is responsible for handling the redundancy switching and forwarding the trusted line data upward.

[0074] 3) RISC-V processor interface

[0075] The FPGA logic module interacts with the RISC-V processor, notifying the RISC-V processor when it enters the sporadic phase, receives a slave frame indicating device status, or receives a master frame operation, and waits for action commands from the RISC-V processor. The FPGA logic module is externally mounted on the AXI bus as a general-purpose peripheral of the RISC-V processor. The FPGA logic module's general-purpose interface is the EMIF interface, so an AXI-to-EMIF bus module is added between the RISC-V processor and the FPGA logic module to implement interface conversion.

[0076] 4) MVB link control module

[0077] The main module of MVB link control mainly completes the transmission of process data master frame, processing of process data slave frame, processing of monitoring data slave frame, and processing of message data slave frame.

[0078] 5) Memory management module

[0079] The FPGA utilizes internal block RAM resources to instantiate an SRAM memory block for storing MVB configuration and communication data. This SRAM can be randomly accessed by multiple modules to prevent access conflicts. This makes continuous SRAM access atomic, abstracting the memory management module. Each use requires a query (ask) before access, and access is allowed only after receiving an acknowledgment (ack). The SRAM is released after the access is complete.

[0080] (4)RISC-V processor design and logic

[0081] This invention provides a processor design based on the RISC-V open source instruction set, the overall architecture of which is as follows: Figure 4 shown.

[0082] The processor adopts a three-stage pipeline architecture, and two sets of pipeline buffers are used between the three pipelines to store the data sent from the previous pipeline to the next stage. The three-stage pipeline is divided as follows:

[0083] The first pipeline stage is the instruction fetch unit, which performs instruction fetching and instruction preprocessing. This module generates the value of the program counter (PC) register, which is used as the address signal for the instruction memory. Pipeline buffer I is the module between the instruction fetch unit and the decoder unit, which is used to pulse instructions output from the instruction memory and send them to the decoder unit.

[0084] The second pipeline stage is the decoder unit, which decodes instructions sent from pipeline buffer I. Once the specific instruction is decoded, it generates a register read / write signal. Because registers use asynchronous reads, the corresponding register data is immediately available upon sending the register read signal. This data is then sent to pipeline buffer II along with the register write signal. Pipeline buffer II is the module between decoding and execution, combining the register write signal and register data before sending them to the execution unit.

[0085] The third pipeline stage is the execution unit, a purely combinatorial logic circuit that performs operations based on specific instructions. It includes a set of control and status registers, an energy accumulator, a multiplier, a divider, an arithmetic logic unit (ALU), and a memory access instruction manager. Depending on the opcode, a different execution module is selected. Each execution module outputs a result, which is also written back to a general register during the execution phase. For memory access instructions, memory access is achieved through the memory access manager.

[0086] The system also includes a pipeline controller, interrupt module, debug unit, memory, and general-purpose peripherals. The pipeline controller generates control signals such as pipeline pause and jump. The interrupt module processes incoming interrupt request signals and generates the final interrupt signal. The debug unit implements the JTAG debug interface. The memory unit is divided into ROM and RAM. ROM serves as the program memory module for storing program configuration files, while RAM serves as the data storage module for data generated during program execution. General-purpose peripherals include UART, SPI, timers, and GPIO, which can be flexibly configured according to needs. The processor core communicates with the memory and general-purpose peripherals via the AXI bus.

[0087] The RISC-V processor is designed and implemented based on the internal resources of the FPGA and is an on-chip processor within the FPGA. In the MVB network interface card, the RISC-V processor serves as an auxiliary FPGA, primarily handling relatively complex logic scenarios and guiding the FPGA through interaction and link control. The RISC-V processor performs tasks such as device status polling, message data polling, and sovereignty transfer.

[0088] Compared with the existing technology, the technical innovations of the present invention include the following points:

[0089] 1. This paper proposes an integrated solution combining domestic FPGAs and RISC-V. This solution integrates the RISC-V processor within the FPGA chip. Using a single FPGA chip, the team designed a Class 4 MVB network card that can function as both an MVB slave and an MVB master. This integrated design simplifies the system architecture, reduces the number of chips and board area, and improves system stability and reliability. This solution meets the high reliability, low cost, compact size, and autonomous control requirements of railway vehicle control and monitoring systems.

[0090] 2. The four-category MVB network card solution proposed in this invention not only meets all the functions required by the MVB standard, but also uses ESD protection circuits, isolation transformers, and AC decoupling circuits in the design of the transceiver circuits to improve the integrity and anti-interference capabilities of the MVB signal.

[0091] 3. This invention proposes a RISC-V processor design based on FPGA, achieving a high-performance, flexible, and reconfigurable processor core. This processor core supports a variety of peripheral expansions and can be flexibly configured and customized according to specific application requirements. It can perform device status polling, message data polling, and sovereignty transfer functions in MVB network cards. It can also serve as a general-purpose processor architecture design, replacing existing standalone MCU chips in other systems.

[0092] In summary, the FPGA- and RISC-V-based MVB communication network card design proposed in this application achieves a self-sustainable, cost-effective solution. Through an integrated design, the RISC-V processor core and FPGA logic components work together, replacing the traditional MCU+FPGA standalone chip architecture. This achieves complete self-sustainability and controllability for MVB products, reduces costs, reduces board size, and enhances product competitiveness. This design solution offers significant technical advantages and inventive benefits, and will have a positive impact on the development of the MVB communication field.

[0093] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the same. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the specific implementation methods of the present invention may still be modified or some technical features may be replaced by equivalents without departing from the spirit of the technical solutions of the present invention, and all of these should be included in the scope of the technical solutions claimed for protection by the present invention.

Claims

1. A multifunctional vehicle bus communication network card based on FPGA and RISC-V, characterized in that: include: User interface, FPGA chip and transceiver circuit; Among them, The user interface is a PC104 interface, which connects the FPGA chip to the bus of the host computer; The FPGA chip includes: FPGA logic module, AXI to EMIF bus module and RISC-V processor; among them, The FPGA logic module is configured to: receive instructions and / or data from a host computer and send the received instructions and / or data to the RISC-V processor; receive processing results sent by the RISC-V processor and send them to the host computer; receive signals transmitted from the MVB bus via the transceiver circuit and perform one or more of the following operations: frame parsing, data processing, and status monitoring; package the processed data into MVB frames and send them to the MVB bus via the transceiver circuit; The RISC-V processor is configured to receive and process instructions and / or data sent by the FPGA logic module, and send processing results to the FPGA logic module; An AXI to EMIF bus module, whose AXI bus is connected to the RISC-V processor and whose EMIF bus is connected to the FPGA logic module, is configured for interface conversion between the AXI bus and the EMIF bus; The transceiver circuit is connected to the FPGA chip and the MVB bus and is configured to: receive the MVB frame sent from the FPGA logic module and transmit the converted signal to the MVB bus; and receive the signal transmitted from the MVB bus and convert it into a standard signal before sending it to the FPGA logic module; The FPGA logic module is further configured to perform MVB link control and MVB frame transmission and reception control.

2. The multifunctional vehicle bus communication network card based on FPGA and RISC-V according to claim 1, characterized in that: The FPGA logic module includes PC104 protocol module, MVB bus transceiver module, RISC-V processor interface module, MVB link layer control module and memory management module; among them, PC104 protocol module, which communicates with the host computer and can access and write to the memory management module; MVB bus transceiver module, which communicates with the MVB bus and can access and write to the memory management module; RISC-V processor interface module, which communicates with the RISC-V processor and can access and write to the memory management module; An MVB link layer control module configured to perform MVB link control; The memory management module is used to store data, including one or more of the following: MVB configuration data and communication data.

3. The multifunctional vehicle bus communication network card based on FPGA and RISC-V according to claim 2, characterized in that: PC104 protocol module, including: PC104 receiving module, PC104 sending module and PC104 control module; The PC104 receiving module receives commands and parameters from the host computer through the parallel bus and sends a command reception completion pulse to the PC104 control module; The PC104 sending module receives the command return data processed by the PC104 control module and sends it to the host computer through the parallel bus; The PC 104 control module processes the received command and sends the result to the PC 104 sending module.

4. The multifunctional vehicle bus communication network card based on FPGA and RISC-V according to claim 3, characterized in that: MVB bus transceiver module, including: MVB sending module, MVB-A receiving module, MVB-B receiving module and AB selecting control module; The MVB sending module is configured to send master-slave frames according to the MVB standard; The MVB-A receiving module and the MVB-B receiving module are configured to receive data frames transmitted on the MVB bus; The AB path selection control module is configured to perform AB path redundancy switching of the MVB bus, process the redundancy switching, and forward the data set as the trust line in the AB path upward.

5. The multifunctional vehicle bus communication network card based on FPGA and RISC-V according to claim 2, characterized in that: The MVB link layer control module is configured to perform one or more of the following operations: process data master frame transmission, process data slave frame processing, monitoring data slave frame processing, and message data slave frame processing.

6. The multifunctional vehicle bus communication network card based on FPGA and RISC-V according to claim 3, characterized in that: The RISC-V processor adopts a three-stage pipeline processor architecture, including an instruction fetch unit, a decoding unit, and an execution unit connected in sequence, a pipeline buffer I is set between the instruction fetch unit and the decoding unit, a pipeline buffer II is set between the decoding unit and the execution unit, and also includes a pipeline controller connecting the instruction fetch unit, the decoding unit, and the execution unit; wherein, An instruction fetch unit is configured to be controlled by the pipeline controller to fetch instructions via the AXI bus and pre-process the instructions, and send the processed instructions to the pipeline memory I and / or store them in the memory via the AXI bus; The pipeline buffer I is configured to store instructions pre-processed by the instruction fetch unit and / or to send the instructions output by the memory to the decoding unit after a beat; The decoding unit is configured to decode the instruction sent by the pipeline buffer I. After decoding the specific instruction, it generates a signal whether to read or write the register. When the decoding unit sends the read register signal, the register module immediately sends the data of the register module to be read. The data of the register module and the write register signal are sent to the pipeline buffer II. The pipeline buffer II is configured to transmit the register write signal and the register module data to the execution unit after a beat; The execution unit is a combinational logic circuit that performs corresponding operations according to specific instructions.

7. The multifunctional vehicle bus communication network card based on FPGA and RISC-V according to claim 6, characterized in that: The pipeline controller is further configured to: connect to the decoding unit and / or the execution unit, and send one or more of the following instructions: pipeline pause, jump; The instruction fetch unit, the decoding unit and / or the execution unit are controlled by the instructions of the pipeline controller and perform corresponding pipeline pause and / or jump operations.

8. The multifunctional vehicle bus communication network card based on FPGA and RISC-V according to claim 7, characterized in that: The transceiver circuit includes an RS485 chip, an ESD protection circuit, an isolation transformer and an AC decoupling circuit connected in sequence; among them, the RS485 chip is used to convert the single-ended signal of the FPGA chip into an RS485 level standard signal, which is then output to the MVB bus after passing through the ESD protection circuit, the isolation transformer and the AC decoupling circuit.

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