Task-based heterogeneous CPU-GPU on-chip network routing method, device, system, and media

Abstract

This application relates to the field of chip design technology, and discloses a task-based heterogeneous CPU-GPU on-chip network routing method, apparatus, system, and medium. First, path selection rules for the routing method are defined, including minimizing the number of hops for each task, minimizing the number of high-traffic paths allocated, quickly leaving hotspot areas, and balancing the workload within the network as much as possible. Then, the corresponding routing method is determined according to the path selection rules. For tasks involving cache access requests and GPU request-response tasks, the XY routing method is used; for tasks involving CPU request-response tasks, the YX routing method is used. This invention solves the blocking problem in the central layout mode of existing CPU-GPU heterogeneous on-chip network architectures.

Description

Technical Field

[0001] This application relates to the field of chip design technology, such as a task-based heterogeneous CPU-GPU on-chip network routing method, apparatus, system, and medium. Background Technology

[0002] Currently, with the increasing computing demands of various tasks in production and daily life, heterogeneous multi-core chips have emerged to address the insufficient computing power of traditional homogeneous multi-core CPUs. Among them, the heterogeneous combination of CPU and GPU is the most common. The CPU and GPU reduce communication overhead and improve system performance by sharing the final cache (LLC), memory controller (MC), and other on-chip resources.

[0003] However, resource sharing inevitably leads to resource contention issues. While the multi-threaded architecture of GPUs is not sensitive to latency, their high throughput significantly exacerbates the problems caused by resource sharing. Against this backdrop, using on-chip networks (NoCs) to connect various modules and separate different traffic flows within the network becomes a crucial solution for achieving the rational allocation of shared resources.

[0004] The CPU-GPU LLC / MC comprises four types of nodes: CPU, GPU, LLC, and MC. Various topology models have emerged based on different layout positions. Figure 1 This paper illustrates the central layout pattern addressed in this application, where nodes of the same type are relatively clustered. This model prioritizes CPU and GPU memory access tasks, with LLCs and MCs located in the central region of the topology, surrounded by CPUs and GPUs. MCs are surrounded by LLCs and communicate only with them to reduce hop count. This design minimizes the routing hop count when CPUs and GPUs frequently access LLCs. However, this layout can lead to significant data load pressure on some paths, resulting in congested paths, as shown by the bolded data paths in the diagram. Furthermore, frequent communication between LLCs and MCs can create information hotspots in the central region, as indicated by the dashed box in the diagram. These hotspots are more prone to information congestion. Within these hotspots, there is no direct communication between LLCs and MCs; therefore, the traffic on vertical paths within these hotspots is less than the traffic on horizontal paths. Additionally, the traffic on the loops around the CPU and GPUs in the outer regions is also relatively low. Summary of the Invention

[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0006] This disclosure provides a task-based heterogeneous CPU-GPU on-chip network routing method, apparatus, system, and medium to solve the blocking problem in the central layout mode of existing CPU-GPU heterogeneous on-chip network architectures.

[0007] In some embodiments, the method includes:

[0008] S01) Set the path selection rules for the routing method, with the priority of the path selection rules decreasing from A to D:

[0009] A. Minimize the number of hops when executing a task;

[0010] B. Assign as few high-traffic paths as possible;

[0011] C. Leave the hotspot area as soon as possible;

[0012] D. Balance the workload within the network as much as possible;

[0013] S02) When executing a cache access request task, i.e. when the CPU / GPU accesses the LLC, according to rule B, the XY routing method is adopted, prioritizing the outer loop path and the vertical path of the hot spot area;

[0014] S03) When executing the CPU request response task, that is, when LLC responds to the CPU, according to rule B, the YX routing method is adopted to prioritize leaving the hotspot area through the vertical path;

[0015] S04) When executing the GPU request response task, that is, when LLC responds to the GPU, according to rule D, the XY routing method is adopted to leave the hotspot area and enter the low-traffic pressure loop area as soon as possible.

[0016] Furthermore, let src be the source node and dst be the destination node, with src.x and dst.x being the horizontal coordinates of the source and destination nodes, respectively, and src.y and dst.y being the vertical coordinates of the source and destination nodes, respectively. The XY routing method is as follows: First, compare the values ​​of src.x and dst.x. If src.x > dst.x, then proceed straight to the left; otherwise, proceed straight to the right, until src.x = dst.x. Then, determine the relationship between src.y and dst.y. If src.y > dst.y, then proceed straight down; otherwise, proceed straight up, until the destination node is reached.

[0017] Furthermore, let src be the source node and dst be the destination node, src.x and dst.x be the horizontal coordinates of the source and destination nodes respectively, and src.y and dst.y be the vertical coordinates of the source and destination nodes respectively. The YX routing method is as follows: First, compare the values ​​of src.y and dst.y. If src.y > dst.y, then proceed downwards and straight ahead; otherwise, proceed upwards and straight ahead until src.y = dst.y. Then, determine the relationship between src.x and dst.x. If src.x > dst.x, then proceed left and straight ahead; otherwise, proceed right and straight ahead until the destination node is reached.

[0018] Furthermore, this method provides two virtual channels, VC1 and VC2, at each router input port. Virtual channel VC1 is used for all task-based XY routing paths, and virtual channel VC2 is used for all task-based YX routing paths. The router output port is equipped with a crossbar switch, and the virtual channels at each router input port are connected to the crossbar switch, which generates an output to avoid deadlock.

[0019] Furthermore, the router output end is also equipped with a routing calculation module, a virtual channel arbitrator, and a cross switch arbitrator. The routing calculation module schedules the selection of the data output port, that is, confirms the port used for output data. The virtual channel arbitrator determines the virtual channel data that leaves the virtual channel and is transmitted to the cross switch. The cross switch arbitrator manages the matching of the cross switch input and output. Different outputs generated by the cross switch have different physical data links.

[0020] In some embodiments, the apparatus includes: a routing path selection rule determination module, configured to determine the following four path selection rules, wherein the priority of the path selection rules decreases progressively from A to D:

[0021] A. Minimize the number of hops when executing a task;

[0022] B. Assign as few high-traffic paths as possible;

[0023] C. Leave the hotspot area as soon as possible;

[0024] D. Balance the workload within the network as much as possible;

[0025] When the cache access request task routing path determination module executes the cache access request task, that is, when the CPU / GPU accesses the LLC, it adopts the XY routing method according to rule B, giving priority to the outer loop path and the vertical path of the hot spot area.

[0026] When the CPU request and response task routing path determination module executes the CPU request and response task, that is, when LLC responds to the CPU, it adopts the YX routing method according to rule B.

[0027] When the GPU request and response task routing path determination module executes the GPU request and response task, i.e. when LLC responds to the GPU, it adopts the XY routing method according to rule D.

[0028] Furthermore, each router input port is equipped with two virtual channels, VC1 and VC2. Virtual channel VC1 is used for all task-based XY routing paths, and virtual channel VC2 is used for all task-based YX routing paths. The router output port is equipped with a crossbar switch, and the end of the virtual channel at each router input port is connected to the crossbar switch, which generates an output to avoid deadlock.

[0029] Furthermore, the router output end is also equipped with a routing calculation module, a virtual channel arbitrator, and a cross switch arbitrator. The routing calculation module schedules the selection of the data output port, that is, confirms the port used for outputting data. The virtual channel arbitrator determines the virtual channel data that leaves the virtual channel and is transmitted to the cross switch. The cross switch arbitrator manages the matching of the cross switch input and output.

[0030] In some embodiments, the system includes a processor and a memory storing program instructions, the processor being configured to execute, when running the program instructions, the task-based heterogeneous CPU-GPU on-chip network routing method as described above.

[0031] In some embodiments, the storage medium stores program instructions that, when executed, perform the task-based heterogeneous CPU-GPU on-chip network routing method as described above.

[0032] The beneficial effects of this invention are as follows: This solution addresses the data hotspots and network congestion problems inherent in heterogeneous on-chip networks and centrally located LLC / MC topologies. Compared to traditional routing algorithms, this solution offers lower network latency and higher overall performance. Furthermore, task-based virtual channels prevent deadlock, further improving network performance.

[0033] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0034] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0035] Figure 1 This is a schematic diagram of the topology model of the central layout pattern;

[0036] Figure 2This is a schematic diagram of the XY routing method;

[0037] Figure 3 This is a schematic diagram of the YX routing method;

[0038] Figure 4 This is a schematic diagram of a virtual channel. Detailed Implementation

[0039] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. When writing effect descriptions in other cases, the analytical derivation process from the solution to the effect should be given. To simplify the drawings, well-known structures and devices can be simplified in their depiction.

[0040] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0041] Unless otherwise stated, the term "multiple" means two or more.

[0042] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0043] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0044] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0045] Example 1

[0046] This embodiment discloses a task-based CPU-GPU on-chip network routing method. This method is based on... Figure 1The illustrated central layout topology pattern, the heterogeneous CPU-GPU on-chip network includes four types of nodes: CPU, GPU, LLC, and MC. These four nodes form a central layout topology model, where LLC and MC nodes are distributed in the central region of the topology and surrounded by CPU and GPU nodes, and MC nodes are surrounded by LLC nodes. This method includes the following steps:

[0047] S01) Set the path selection rules for the routing method, with the priority of the path selection rules decreasing from A to D:

[0048] A. Minimize the number of hops when executing a task;

[0049] B. Assign as few high-traffic paths as possible;

[0050] C. Leave the hotspot area as soon as possible;

[0051] D. Balance the workload within the network as much as possible;

[0052] S02) When executing a cache access request task, i.e. when the CPU / GPU accesses the LLC, according to rule B, the XY routing method is adopted, prioritizing the outer loop path and the vertical path of the hot spot area;

[0053] S03) When executing the CPU request response task, that is, when LLC responds to the CPU, since the vertical traffic in the hot spot area is low, according to rule B, the YX routing method is adopted to prioritize leaving the hot spot area through the vertical path;

[0054] (S04) When executing a GPU request response task, i.e., when LLC responds to the GPU, the XY routing method is adopted according to rule D. The purpose is to make it leave the hotspot area as soon as possible and enter the loop area with less traffic, in accordance with rule D, so as to leave the hotspot area and enter the loop area with low traffic pressure as soon as possible.

[0055] Let src be the source node and dst be the destination node. Let src.x and dst.x be the horizontal coordinates of the source node and the destination node, respectively, and let src.y and dst.y be the vertical coordinates of the source node and the destination node, respectively.

[0056] like Figure 2 As shown, the XY routing method works as follows: First, compare the values ​​of src.x and dst.x. If src.x > dst.x, proceed straight to the left; otherwise, proceed straight to the right, until src.x = dst.x. Then, determine the relationship between src.y and dst.y. If src.y > dst.y, proceed straight down; otherwise, proceed straight up, until the destination node is reached. The XY routing method is used for CPU request tasks, GPU request tasks, and GPU response tasks.

[0057] Let src be the source node and dst be the destination node. Let src.x and dst.x be the horizontal coordinates of the source node and the destination node, respectively, and let src.y and dst.y be the vertical coordinates of the source node and the destination node, respectively.

[0058] like Figure 3 As shown, the YX routing method is as follows: First, compare the values ​​of src.y and dst.y. If src.y > dst.y, proceed downwards along the straight path; otherwise, proceed upwards along the straight path, until src.y = dst.y. Then, determine the relationship between src.x and dst.x. If src.x > dst.x, proceed left along the straight path; otherwise, proceed right along the straight path, until the destination node is reached. The YX routing method is used for CPU response tasks.

[0059] like Figure 4 As shown, this method provides two virtual channels VC1 and VC2 at each router input port. Virtual channel VC1 is used for all task-based XY routing paths, and virtual channel VC2 is used for all task-based YX routing paths. The router output port is equipped with a crossbar switch, and the virtual channels at each router input port are connected to the crossbar switch. The crossbar switch generates an output to avoid deadlock.

[0060] The router output also includes a routing calculation module, a virtual channel arbitrator, and a crossbar arbitrator. The routing calculation module schedules the selection of the data output port, i.e., confirms the port used for output data. The virtual channel arbitrator determines the virtual channel data that leaves the virtual channel and is transmitted to the crossbar. The crossbar arbitrator manages the matching of the crossbar input and output. Different outputs generated by the crossbar have different physical data links.

[0061] Virtual channels are used to resolve the deadlock problem that may arise from the mixed use of XY and YX routing methods in this routing algorithm. Specifically, VC1 handles all XY routing tasks of the task-based routing algorithm, while VC2 handles the relevant tasks for the YX portion. Thus, although the routing algorithm itself places the XY and YX algorithms on the same dimension, the virtual channels separate their actual physical data links, thereby avoiding deadlock.

[0062] Example 2

[0063] This embodiment discloses a task-based heterogeneous CPU-GPU on-chip network routing device. The heterogeneous CPU-GPU on-chip network includes four types of nodes: CPU, GPU, LLC and MC. The four types of nodes form a central layout topology model, wherein the LLC and MC nodes are distributed in the central region of the topology and are surrounded by the CPU and GPU nodes, and the MC node is surrounded by the LLC node.

[0064] The device described in this embodiment includes: a routing path selection rule determination module, used to determine the following four path selection rules, wherein the priority of the path selection rules decreases progressively from A to D:

[0065] A. Minimize the number of hops when executing a task;

[0066] B. Assign as few high-traffic paths as possible;

[0067] C. Leave the hotspot area as soon as possible;

[0068] D. Balance the workload within the network as much as possible;

[0069] When the cache access request task routing path determination module executes the cache access request task, that is, when the CPU / GPU accesses the LLC, it adopts the XY routing method according to rule B, giving priority to the outer loop path and the vertical path of the hot spot area.

[0070] When the CPU request and response task routing path determination module executes the CPU request and response task, that is, when LLC responds to the CPU, the YX routing method is adopted according to rule B because the vertical traffic in the hot spot area is low.

[0071] When the GPU request / response task routing path determination module executes the GPU request / response task, i.e., when LLC responds to the GPU, it uses the XY routing method according to rule D. The purpose is to guide the GPU out of the hotspot area as quickly as possible and into a less congested loop area to comply with rule D.

[0072] Let src be the source node and dst be the destination node. Let src.x and dst.x be the horizontal coordinates of the source node and the destination node, respectively, and let src.y and dst.y be the vertical coordinates of the source node and the destination node, respectively.

[0073] like Figure 2 As shown, the XY routing method works as follows: First, compare the values ​​of src.x and dst.x. If src.x > dst.x, proceed straight to the left; otherwise, proceed straight to the right, until src.x = dst.x. Then, determine the relationship between src.y and dst.y. If src.y > dst.y, proceed straight down; otherwise, proceed straight up, until the destination node is reached. The XY routing method is used for CPU request tasks, GPU request tasks, and GPU response tasks.

[0074] Let src be the source node and dst be the destination node. Let src.x and dst.x be the horizontal coordinates of the source node and the destination node, respectively, and let src.y and dst.y be the vertical coordinates of the source node and the destination node, respectively.

[0075] like Figure 3As shown, the YX routing method is as follows: First, compare the values ​​of src.y and dst.y. If src.y > dst.y, proceed downwards along the straight path; otherwise, proceed upwards along the straight path, until src.y = dst.y. Then, determine the relationship between src.x and dst.x. If src.x > dst.x, proceed left along the straight path; otherwise, proceed right along the straight path, until the destination node is reached. The YX routing method is used for CPU response tasks.

[0076] like Figure 4 As shown, this method provides two virtual channels VC1 and VC2 at each router input port. Virtual channel VC1 is used for all task-based XY routing paths, and virtual channel VC2 is used for all task-based YX routing paths. The router output port is equipped with a crossbar switch, and the virtual channels at each router input port are connected to the crossbar switch. The crossbar switch generates an output to avoid deadlock.

[0077] The router output also includes a routing calculation module, a virtual channel arbitrator, and a crossbar arbitrator. The routing calculation module schedules the selection of the data output port, i.e., confirms the port used for output data. The virtual channel arbitrator determines the virtual channel data that leaves the virtual channel and is transmitted to the crossbar. The crossbar arbitrator manages the matching of the crossbar input and output. Different outputs generated by the crossbar have different physical data links.

[0078] Virtual channels are used to resolve the deadlock problem that may arise from the mixed use of XY and YX routing methods in this routing algorithm. Specifically, VC1 handles all XY routing tasks of the task-based routing algorithm, while VC2 handles the relevant tasks for the YX portion. Thus, although the routing algorithm itself places the XY and YX algorithms on the same dimension, the virtual channels separate their actual physical data links, thereby avoiding deadlock.

[0079] Example 3

[0080] This embodiment discloses a task-based heterogeneous CPU-GPU on-chip network routing system, including a processor and a memory storing program instructions. The processor is configured to execute the task-based heterogeneous CPU-GPU on-chip network routing method as described in Embodiment 1 when running the program instructions.

[0081] Example 4

[0082] This embodiment discloses a storage medium storing program instructions, which, when executed, perform the task-based heterogeneous CPU-GPU on-chip network routing method as described in Embodiment 1.

[0083] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0084] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0085] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0086] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0087] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection shown or discussed between each other may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0088] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A task-based routing method for heterogeneous CPU-GPU on-chip networks, wherein the heterogeneous CPU-GPU on-chip network includes four types of nodes: CPU, GPU, LLC, and MC, which form a central layout topology model, wherein LLC and MC are distributed in the central region of the topology and surrounded by CPU and GPU nodes, and MC is surrounded by LLC nodes, characterized in that: Includes the following steps: S01) Set the path selection rules for the routing method, with the priority of the path selection rules decreasing from A to D: Minimize the number of hops when executing a task; Assign as few high-traffic paths as possible; Leave the hotspot area as soon as possible; Balance the workload within the network as much as possible; S02) When executing a cache access request task, i.e. when the CPU / GPU accesses the LLC, according to rule B, the XY routing method is adopted, prioritizing the outer loop path and the vertical path of the hot spot area; S03) When executing the CPU request response task, that is, when LLC responds to the CPU, the YX routing method is adopted according to rule B; S04) When executing the GPU request response task, that is, when LLC responds to the GPU, the XY routing method is adopted according to rule D.

2. The task-based heterogeneous CPU-GPU on-chip network routing method according to claim 1, characterized in that: [The following is a partial translation of the original text, which is not possible without further context.] src is the source node, dst is the destination node, src.x and dst.x are the horizontal coordinates of the source and destination nodes, respectively, and src.y and dst.y are the vertical coordinates of the source and destination nodes, respectively. The XY routing method is as follows: First, compare the values ​​of src.x and dst.x. If src.x > dst.x, then proceed straight to the left; otherwise, proceed straight to the right, until src.x = dst.x. Then, determine the relationship between src.y and dst.y. If src.y > dst.y, then proceed straight down; otherwise, proceed straight up, until the destination node is reached.

3. The task-based heterogeneous CPU-GPU on-chip network routing method according to claim 1, characterized in that: [The following is a partial translation of the original text, which is not possible without further context.] src is the source node, dst is the destination node, src.x and dst.x are the horizontal coordinates of the source and destination nodes respectively, and src.y and dst.y are the vertical coordinates of the source and destination nodes respectively. The YX routing method is as follows: First, compare the values ​​of src.y and dst.y. If src.y > dst.y, then proceed downwards and forwards; otherwise, proceed upwards and forwards until src.y = dst.y. Then, determine the relationship between src.x and dst.x. If src.x > dst.x, then proceed left and forwards; otherwise, proceed right and forwards until the destination node is reached.

4. The task-based heterogeneous CPU-GPU on-chip network routing method according to claim 1, characterized in that: This method provides two virtual channels, VC1 and VC2, at each router input port. Virtual channel VC1 is used for all task-based XY routing paths, and virtual channel VC2 is used for all task-based YX routing paths. The router output port is equipped with a crossbar switch, and the virtual channels at each router input port are connected to the crossbar switch. The crossbar switch generates an output to avoid deadlock.

5. The task-based heterogeneous CPU-GPU on-chip network routing method according to claim 4, characterized in that: The router output also includes a routing calculation module, a virtual channel arbitrator, and a crossbar arbitrator. The routing calculation module schedules the selection of the data output port, i.e., confirms the port used for output data. The virtual channel arbitrator determines the virtual channel data that leaves the virtual channel and is transmitted to the crossbar. The crossbar arbitrator manages the matching of the crossbar input and output. Different outputs generated by the crossbar have different physical data links.

6. A task-based heterogeneous CPU-GPU on-chip network routing device, wherein the heterogeneous CPU-GPU on-chip network includes four types of nodes: CPU, GPU, LLC, and MC, which form a central layout topology model, wherein the LLC and MC nodes are distributed in the central region of the topology and are surrounded by the CPU and GPU nodes, and the MC node is surrounded by the LLC node, characterized in that: include: The routing path selection rule determination module is used to determine the following four path selection rules, with the priority of the path selection rules decreasing from A to D: A. Minimize the number of hops when executing a task; B. As few high-traffic paths as possible; C. Leave the hotspot area as soon as possible; D. Balance the workload within the network as much as possible; When the cache access request task routing path determination module executes the cache access request task, that is, when the CPU / GPU accesses the LLC, it adopts the XY routing method according to rule B, giving priority to the outer loop path and the vertical path of the hot spot area. When the CPU request and response task routing path determination module executes the CPU request and response task, that is, when LLC responds to the CPU, it adopts the YX routing method according to rule B. When the GPU request and response task routing path determination module executes the GPU request and response task, i.e. when LLC responds to the GPU, it adopts the XY routing method according to rule D.

7. The task-based heterogeneous CPU-GPU on-chip network routing device according to claim 6, characterized in that: Each router input port has two virtual channels, VC1 and VC2. Virtual channel VC1 is used for all task-based XY routing paths, and virtual channel VC2 is used for all task-based YX routing paths. The router output port is equipped with a crossbar switch. The end of the virtual channel of each router input port is connected to the crossbar switch, which generates an output to avoid deadlock.

8. The task-based heterogeneous CPU-GPU on-chip network routing device according to claim 7, characterized in that: The router output also includes a routing calculation module, a virtual channel arbitrator, and a cross switch arbitrator. The routing calculation module schedules the selection of the data output port, that is, confirms the port used for outputting data. The virtual channel arbitrator determines the virtual channel data that leaves the virtual channel and is transmitted to the cross switch. The cross switch arbitrator manages the matching of the cross switch input and output.

9. A task-based heterogeneous CPU-GPU on-chip network routing system, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute, when running the program instructions, the task-based heterogeneous CPU-GPU on-chip network routing method as described in any one of claims 1 to 5.

10. A storage medium storing program instructions, characterized in that, When the program instructions are executed, they perform the task-based heterogeneous CPU-GPU on-chip network routing method as described in any one of claims 1 to 5.

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