A pnCCD background data on-board processing system

Abstract

The application discloses a pnCCD background data on-orbit processing system, which is characterized by comprising an FPGA, a FLASH and an SRAM; the FLASH is used for storing offset noise data of each pixel of the pnCCD calculated during ground calibration; the SRAM is used for reading and caching the offset noise data from the FLASH; the FPGA is used for processing the offset noise according to received instructions, and comprises an offset noise shift and calculation module, an offset noise correction module, an instruction modified offset noise module and an updated static offset noise module; the offset noise shift and calculation module is used for calculating the offset noise on orbit; the offset noise correction module is used for correcting the offset noise of each pixel of the pnCCD on orbit according to the offset noise calculated on orbit; and the updated static offset noise module is used for updating the offset noise data stored in the FLASH according to the offset noise corrected on orbit.

Description

Technical Field

[0001] This invention belongs to the field of spaceborne X-ray detection technology in astronomy, and relates to a pnCCD background noise calculation and elimination system. Background Technology

[0002] By using telescope satellites orbiting in space, we can observe X-rays from different celestial bodies, which is of great significance for understanding the universe.

[0003] Among existing technologies, pnCCD has advantages in energy spectrum measurement, imaging, and strong radiation resistance, giving it an edge in the field of spaceborne low-energy X-ray detection.

[0004] pn-CCD is a back-illuminated three-phase CCD on a fully depleted silicon substrate. Its function is based on the lateral depletion principle. Unlike commonly used MOS-CCDs, the transfer register of a pn-CCD is formed by a pn junction. This achieves high radiation hardness, fast transfer mode, and high full-well capacitance. Ultra-thin and unstructured radiation entrance windows enable high quantum efficiency from near-infrared and visible light to X-ray systems. The latest aerospace-grade pn-CCDs add a memory to the original exposure area; the image from the exposure area is rapidly transferred to the memory, which shields against X-rays, significantly reducing the occurrence of timeout events.

[0005] CAMEX (CMOS Analog Multiplexer) ASICs are used for reading out pnCCD signals. A single 384x384 pixel spaceborne pnCCD requires three CAMEX ASICs, each responsible for reading out 128 columns × 384 rows of pixels.

[0006] pnCCD data processing involves many steps: offset correction, common-mode noise correction, bad pixel removal, physical event filtering and reconstruction, gain correction, and CTE (charge transfer efficiency) correction. The computational load exceeds the satellite's hardware capabilities. Furthermore, the raw data acquired by the ADC contains offset noise and common-mode noise, which must be corrected before transmission. Therefore, on-board preprocessing is necessary, including offset and common-mode noise correction, followed by thresholding to ensure only data exceeding the threshold is transmitted. This approach achieves accurate signal amplitude while significantly reducing data volume.

[0007] For pnCCDs, due to dark current and readout noise, each pixel has a baseline corresponding to the zero energy point; this baseline is often referred to as the offset (offset noise). The offset table is obtained by averaging the dark field samples of each pixel. Offset measurements may be affected by charged particle background (such as cosmic rays). To remove the influence of cosmic rays from the data, for each pixel, the largest values ​​are discarded, and for symmetry, the same number of the smallest values ​​are also discarded. For example, for a set of 200 frames of dark field data, typically the five largest and five smallest values ​​are discarded.

[0008] Therefore, in the EP satellite FXT payload subsystem, simply discarding pixel values ​​has a significant impact on image quality, thus a pnCCD background noise calculation and elimination system is urgently needed. Summary of the Invention

[0009] To address the problems existing in the prior art, the purpose of this invention is to provide a pnCCD background data onboard processing system. This invention utilizes the limited hardware resources onboard and combines them with FPGA software functions for noise cancellation, enabling the storage, calculation, modification, and updating of offset noise required for various modes, including windowed mode, time-varying mode, full-frame mode, and energy-saving mode.

[0010] The technical solution of this invention is as follows:

[0011] A pnCCD background data onboard processing system, characterized in that it includes FPGA, FLASH, and SRAM;

[0012] The FLASH is used to store the offset noise data of each pixel of the pnCCD calculated during ground calibration;

[0013] The SRAM is used to read and cache the offset noise data of each pixel of the pnCCD from the FLASH.

[0014] The FPGA is used to process offset noise according to received instructions, including an offset noise transfer and calculation module, an offset noise correction module, an instruction-modified offset noise module, and a static offset noise update module; wherein...

[0015] The offset noise transfer and calculation module is used to calculate offset noise in orbit;

[0016] The offset noise correction module is used to correct the offset noise of each pixel of the pnCCD in orbit based on the offset noise calculated in orbit.

[0017] The instruction to modify offset noise module is used to modify the offset noise value of a specified pixel in the SRAM on track according to the received instruction, or to modify the range of offset noise calculated by the FPGA, or to move the calculated offset noise to a specified area.

[0018] The static offset noise update module is used to update the offset noise data stored in the FLASH according to the offset noise corrected on track.

[0019] Furthermore, the method for the offset noise transfer and calculation module to calculate the offset noise on orbit is as follows:

[0020] 21) Offset noise removal process: Read the offset noise data stored in the FLASH and write it into the SRAM;

[0021] 22) Offset noise calculation process: Compare whether the value of each pixel in the image data detected by the pnCCD is within the baseline data range. If it is within the baseline data range, add the pixel value to the accumulated value of the current pixel, increment the pixel count by one, and enter the SRAM write state.

[0022] In the SRAM write state, the data obtained in the comparison state is written into the address of the corresponding pixel in the SRAM used to calculate the offset noise, and then the process waits for the falling edge of the SRAM write signal to enter the judgment state.

[0023] In the judgment state, the current operating mode of the FPGA is determined, whether the division operation has started, and the number of image frames read. If it is in full-frame mode, division has not started, and the number of image frames read is less than 3, then return to the comparison state. If the number of image frames read is greater than or equal to 3, then enter the SRAM read state. If it is in non-full-frame mode, division has not started, and the number of image frames read is 0, then enter the SRAM read state. If division has started and the maximum address has been reached, then return to the idle state. Otherwise, enter the SRAM read state.

[0024] The SRAM read state reads the data stored in the SRAM and waits for the falling edge of the SRAM read signal. If division has not started, it returns to the comparison state; if division has started, it enters the calculation state.

[0025] In the calculation state, the accumulated value of each pixel stored in SRAM is divided by the corresponding pixel count value to complete the division operation and obtain the offset noise. Then, the process enters the SRAM write state.

[0026] Furthermore, it also includes an RS422 receiver chip, used to receive instructions sent by the satellite through the electrical control box and send them to the FPGA; the instructions include instructions to calculate offset noise, instructions to modify offset noise, and instructions to update static offset noise.

[0027] Furthermore, the address of the FLASH is divided into two functional areas: Area A is used to store the offset noise data of each pixel of the pnCCD calculated during ground calibration; Area B is used to store the offset noise data calculated by the satellite in orbit.

[0028] Furthermore, the FLASH address is 16 bits wide; wherein, FLASH addresses 0x0 to 0x23FFF store offset noise data of the full-frame mode storage area; FLASH addresses 0x24000 to 0x47FFF store offset noise data of each pixel of the pnCCD calculated during ground calibration; FLASH addresses 0x48000 to 0x53FFF store offset noise data of the time-varying mode exposure area during ground calibration; FLASH addresses 0x54000 to 0x55E7F store offset noise data of the windowed mode or energy-saving mode exposure area during ground calibration; and area B stores offset noise data calculated on-orbit by satellites of the same type as area A, with an offset address of 0x80000.

[0029] Furthermore, the instruction modifies the offset noise module to move the calculated offset noise to the specified area. The instruction content includes the areas that need to be updated: the full-frame mode storage area cache address 0x56000~0x79FFF is updated to 0x0~0x23FFF; the full-frame mode exposure area cache address 0x56000~0x79FFF is updated to 0x24000~0x47FFF; the time-varying mode exposure area cache address 0x56000~0x61FFF is updated to 0x48000~0x53FFF; and the windowed mode or power-saving mode exposure area cache address 0x56000~0x57E7F is updated to 0x54000~0x55E7F.

[0030] Furthermore, the SRAM address is 32 bits wide; wherein, SRAM addresses 0x0 to 0x55E7F store offset noise data; and SRAM addresses 0x56000 to 0x79FFF cache the offset noise data calculated by the satellite in orbit.

[0031] Furthermore, the SRAM cache size used varies depending on the observation mode: full-frame mode storage area cache address 0x56000~0x79FFF; full-frame mode exposure area cache address 0x56000~0x79FFF; time-varying mode exposure area cache address 0x56000~0x61FFF; windowed mode or power-saving mode exposure area cache address 0x56000~0x57E7F.

[0032] Furthermore, the FPGA is Fudan Microelectronics' NOR FLASH JFM29LV641RH.

[0033] The advantages of this invention are as follows:

[0034] It features high integration, high flexibility, complex functions, low cost, high reliability, and all chips are domestically produced. Attached Figure Description

[0035] Figure 1 This is a block diagram illustrating the principle of the present invention.

[0036] Figure 2 This is a system block diagram of the present invention.

[0037] Figure 3 This is a flowchart of the noise removal process. Detailed Implementation

[0038] The present invention will now be described in further detail with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0039] The system's hardware resources mainly include an FPGA, FLASH, SRAM, and an RS422 receiver chip. The offset of each pixel (i.e., background noise or offset noise) is pre-calculated on the ground and stored in the onboard FLASH memory. FLASH is non-volatile, ensuring data reliability in the complex space environment. However, FLASH readout is slow and cannot be used as a high-speed cache for FPGA data processing in this system. Therefore, after power-on, the FPGA needs to transfer the offset table from the FLASH to the SRAM. The main functions of this system include: correcting offset noise, calculating offset noise, modifying offset noise via instructions, and updating static offset noise.

[0040] The principle block diagram of the present invention is as follows: Figure 1 As shown, the pnCCD detector assembly includes one pnCCD and three CAMEXs; the CAMEX (CMOS analog multiplexer) ASIC is used for pnCCD signal readout. A state-of-the-art 384x384 pixel spaceborne pnCCD requires three CAMEXs, each responsible for readout of 128 columns × 384 rows of pixels. The detector chassis is responsible for signal processing of the detector assembly; each CAMEX corresponds to one operational amplifier and one analog-to-digital converter. The FPGA receives the signals from the analog-to-digital converter and processes the data using FLASH and SRAM.

[0041] The system block diagram is as follows: Figure 2As shown, the FPGA controls the power supply board and pnCCD driver board to power the pnCCD detector assembly. The FPGA sends drive signals to the pnCCD driver board and CAMEX readout timing signals to the differential signal conversion chip to read image data from the pnCCD detector assembly. The data reaches the FPGA via the differential operational amplifier chip and the analog-to-digital converter chip. The FPGA processes the acquired data. The FPGA communicates with the electrical control box through an interface chip, receiving instructions from the electrical control box and sending engineering parameters and scientific data of the detector chassis to the electrical control box.

[0042] This system includes an FPGA, SRAM, and FLASH. FLASH is responsible for static data storage, SRAM is responsible for high-speed data caching, and the FPGA is responsible for data processing.

[0043] The pnCCD image data acquired by the analog-to-digital converter chip is corrected for offset noise to obtain the original pixel values. When offset noise needs to be calculated, the satellite sends a command to this system via the electronic control box to calculate the offset noise. When the offset noise value of a certain pixel needs to be changed, the satellite sends a command to this system via the electronic control box to modify the offset noise. When it is necessary to transfer the offset noise in SRAM to FLASH, the satellite sends a command to this system via the electronic control box to update the static offset noise. After being stored in FLASH, the latest offset noise can be used the next time the system is powered on.

[0044] This system employs a JFM4VSX55RT SRAM-type FPGA from Fudan Microelectronics, with a total dose (TID) ≥ 1000 Gy (Si) and single-event immunity (SEL) ≥ 75 MeV·cm² / mg. It also utilizes a high-capacity SRAM from the Beijing Institute of Microelectronics, specifically model B8CR512k32RH, with a TID ≥ 100 Krad (Si) and SEL ≥ 75 MeV·cm² / mg, and a single-event upset error rate (SEE) of less than 1E-10 errors / day·bit (GEO orbit, equivalent AL3mm). Finally, it employs Fudan Microelectronics' NORFLASH JFM29LV641RH, with a TID ≥ 100 Krad (Si) and SEE ≥ 99.8 MeV·cm² / mg, and a SEE error rate (SEE) of less than 1.41E-12 errors / day·bit (GEO orbit, equivalent AL3mm). The total dose and single-event lockout protection of FPGA, FLASH, and SRAM meet engineering requirements and do not require special protection design.

[0045] The SRAM space is 512K x 32 bits, or 16,777,216 bits. The probability of a single-event upset (SOME) error occurring daily across all storage bits of a single SRAM is less than 0.0016,777,216 (GEO orbit, equivalent to Al3 mm), meaning an SOME occurs once every 596 days. Based on this analysis, this design does not include a checksum for the SRAM. Instead, the data within the SRAM is periodically transmitted to the ground-based scientific satellite support system, allowing the ground to determine whether an SOME has occurred.

[0046] FLASH Address Division Introduction: The FLASH memory is 16 bits wide, with the lower 12 bits storing offset noise data. The FLASH address is divided into two functional areas: Area A (FLASH address 0x0~0x55E7F) stores offset noise data calculated during ground calibration; Area B (FLASH address 0x80000~0xD5E7F) stores offset noise data calculated by the satellite in orbit. FLASH address 0x0~0x23FFF stores offset noise data for the full-frame mode storage area; FLASH address 0x24000~0x47FFF stores offset noise data for the full-frame mode exposure area during ground calibration; FLASH address 0x48000~0x53FFF stores offset noise data for the time-varying mode exposure area during ground calibration; FLASH address 0x54000~0x55E7F stores offset noise data for the windowed mode or energy-saving mode exposure area during ground calibration; Area B stores offset noise data calculated by the satellite in orbit of the same type as Area A, with an offset address of 0x80000.

[0047] SRAM Address Division Introduction: The SRAM is 32 bits wide, with the lower 12 bits storing offset noise data. SRAM addresses 0x0 to 0x55E7F store offset noise data. After the FPGA powers on, ground commands specify whether the offset noise data is moved from area A or area B of the FLASH memory to the SRAM. SRAM addresses 0x56000 to 0x79FFF cache the offset noise data calculated by the satellite in orbit. The SRAM cache size used varies depending on the observation mode: Full-frame mode storage area cache address 0x56000 to 0x79FFF; Full-frame mode exposure area cache address 0x56000 to 0x79FFF; Time-varying mode exposure area cache address 0x56000 to 0x61FFF; Windowing mode or energy-saving mode exposure area cache address 0x56000 to 0x57E7F.

[0048] The FPGA is divided into four modules according to its functions: offset noise transfer and calculation module, offset noise correction module, instruction-modified offset noise module, and static offset noise update module.

[0049] Offset noise transfer and calculation module

[0050] The original data acquired by the ADC (i.e., the image data detected by the pnCCD) is averaged to update the offset of each pixel, and then written to the corresponding pixel offset storage location in the SRAM. The SRAM has a total of 32 bits, with the first 10 bits used for counting and the last 22 bits storing the accumulated value.

[0051] The offset noise shifting function moves offset noise data stored in FLASH memory from area A (FLASH address 0x0~0x55E7F) or area B (FLASH address 0x80000~0xD5E7F) to SRAM address 0x0~0x55E7F. Area A or area B is selected by the ground command; after selection, the ground sends a command to begin the shifting process.

[0052] The offset noise calculation function uses SRAM addresses 0x56000 to 0x79FFF. It utilizes the 32-bit width of SRAM, with the first 10 bits used for counting and the last 22 bits storing the accumulated value. The latest offset noise is obtained by averaging 1000 frames of original pixels in different working modes.

[0053] The offset noise shifting and offset noise calculation functions are combined into a single FPGA functional module, as shown in the flowchart below. Figure 3 As shown. Offset noise removal process:

[0054] In idle state, the FPGA waits for instructions from the control box. Upon receiving a relocation instruction while idle, it enters the FLASH read state.

[0055] In the FLASH read state, data at a specific address in the FLASH memory is read. In the FLASH read state, after waiting 200ns for the FLASH output data to be valid, the system enters the SRAM write state.

[0056] In SRAM write mode, data read from a specific address in FLASH is written to the same address in SRAM. In SRAM write mode, the system waits for the falling edge of the SRAM write signal before entering the address increment state.

[0057] In the address increment state, both the FLASH address and SRAM address are incremented by one. While in the address increment state, it checks if the address is the maximum. If it is, it returns to the idle state, and the offset noise relocation is complete. If it is not the maximum address, it enters the FLASH read state and continues the offset noise relocation process.

[0058] Offset noise calculation process:

[0059] In idle state, the FPGA waits for instructions from the control box. Upon receiving a command to calculate offset noise in idle state, it enters the comparison state.

[0060] In comparison mode, the system compares the value of each pixel in the raw image data acquired by the analog-to-digital converter chip with the baseline data range (between channels 300 and 900). If the pixel value is within the range, it adds the pixel value to the accumulated value of that pixel, and increments the pixel count by one. For example, if the value of the i-th pixel in a frame of image data detected by the pnCCD is 600, then in SRAM address 0x56000+i-1, the first 10 bits are incremented by one, and the last 22 bits store the accumulated value incremented by 600. In comparison mode, the system directly enters the SRAM write mode.

[0061] In SRAM write mode, the data obtained in the comparison state is written to the address in the SRAM corresponding to the pixel used to calculate the offset noise. In SRAM write mode, the system waits for the falling edge of the SRAM write signal before entering the judgment state.

[0062] The system determines the FPGA's current operating mode (full-frame mode, time-varying mode, or other modes), whether division has started, and the number of image frames read. If, under the determination state, division has not started, it is in full-frame mode, and the number of frames is less than 3, it returns directly to the comparison state; if the number of frames is greater than or equal to 3, it enters the SRAM read state. If, under the determination state, division has not started, it is not in full-frame mode, and the number of frames is 0, it enters the SRAM read state. If, under the determination state, division starts and reaches the maximum address, it returns to the idle state; otherwise, it enters the SRAM read state. Specifically, under the determination state, if division starts and it is in full-frame mode, it performs 384×384 divisions until the maximum address is reached and returns to the idle state. If, under the determination state, division starts and it is in time-varying mode, it performs 384×128 divisions until the maximum address is reached and returns to the idle state. If, under the determination state, division starts and it is in other modes, it performs 128×61 divisions until the maximum address is reached and returns to the idle state.

[0063] In SRAM read mode, data is read from an address stored in the SRAM (each address in the SRAM range 0x56000 to 0x79FFF corresponds to one pixel; the SRAM has a 32-bit width, with the first 10 bits used for counting and the last 22 bits storing the accumulated value). In SRAM read mode, if the SRAM read signal has not yet started and the division has not begun, the system returns to the compare mode; if division begins, the system enters the calculation mode.

[0064] In the calculation state, the offset noise is obtained by dividing the accumulated value of each pixel stored in the last 22 bits of SRAM by the corresponding pixel count value stored in the first 10 bits. In the calculation state, after waiting 300ns, the divider output is valid, and the process enters the SRAM write state.

[0065] Offset noise correction module

[0066] After the offset noise removal process is completed, the FPGA receives the instruction from the control box to start reading and reads the detector component data. After the FPGA reads the pnCCD pixel, it reads the offset noise corresponding to that pixel from SRAM addresses 0x0 to 0x55E7F, subtracts the two, and completes the offset noise correction for the pixel.

[0067] Instructions modify offset noise module

[0068] The main functions include: modifying the offset noise value of a pixel in SRAM, modifying the offset noise range calculated by the FPGA, and moving the calculated offset noise to a specified area.

[0069] The instruction modifies the offset noise value of a pixel in SRAM. The instruction content includes the address to be modified and the offset noise value.

[0070] Modify the FPGA's offset noise calculation range. The instruction includes the maximum and minimum values ​​of the calculation range.

[0071] The calculated offset noise is moved to the specified area. The instruction includes the areas that need to be updated: the full-frame mode storage area cache address 0x56000~0x79FFF is updated to 0x0~0x23FFF; the full-frame mode exposure area cache address 0x56000~0x79FFF is updated to 0x24000~0x47FFF; the time-varying mode exposure area cache address 0x56000~0x61FFF is updated to 0x48000~0x53FFF; and the windowed mode or power-saving mode exposure area cache address 0x56000~0x57E7F is updated to 0x54000~0x55E7F.

[0072] Update static offset noise module

[0073] The update of offset noise data stored in SRAM addresses 0x0 to 0x55E7F to FLASH B area (FLASH addresses 0x80000 to 0xD5E7F) is defined as updating static offset noise.

[0074] Upon receiving the update static offset noise command, the data in the corresponding sector of FLASH area B is erased first, that is, sectors 16 to 27 are erased sequentially. Each sector erased requires a 1.5-second wait. After all sectors in area B are erased, data is written to the FLASH. The update offset noise value is stored at addresses 0x80000 to 0xD5E7F, totaling 351,872 words. 128 words are programmed per frame, requiring 2,749 frames. The FLASH word programming time is 11µs, and programming 128 words takes 1.408ms. All modes guarantee that FLASH programming of 128 data points can be completed within one cycle.

[0075] The full-frame mode cycle is 50ms, and FLASH updates take approximately 138 seconds.

[0076] The time-varying mode has a cycle of 9.2352ms, and the FLASH update takes about 26 seconds.

[0077] The windowed mode has a cycle of 2ms, sends 128 SRAM data in 16 frames, and takes about 88 seconds to update the FLASH.

[0078] The power-saving mode cycle is 50ms, and FLASH updates take approximately 138 seconds.

[0079] Although specific embodiments of the invention have been disclosed for illustrative purposes to aid in understanding and implementing the invention, those skilled in the art will understand that various substitutions, variations, and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the content disclosed in the preferred embodiments, and the scope of protection claimed by the invention is defined by the claims.

Claims

1. A pnCCD background data spaceborne processing system, characterized in that, Including FPGA, FLASH, and SRAM; The FLASH is used to store the offset noise data of each pixel of the pnCCD calculated during ground calibration; The SRAM is used to read and cache the offset noise data of each pixel of the pnCCD from the FLASH. The FPGA is used to process offset noise according to received instructions, including an offset noise transfer and calculation module, an offset noise correction module, an instruction-modified offset noise module, and a static offset noise update module; wherein... The offset noise transfer and calculation module is used to calculate offset noise in orbit; The offset noise correction module is used to correct the offset noise of each pixel of the pnCCD in orbit based on the offset noise calculated in orbit. The instruction to modify offset noise module is used to modify the offset noise value of a specified pixel in the SRAM on track according to the received instruction, or to modify the range of offset noise calculated by the FPGA, or to move the calculated offset noise to a specified area. The static offset noise update module is used to update the offset noise data stored in the FLASH according to the offset noise corrected on track. The method for calculating offset noise on-orbit by the offset noise transfer and calculation module is as follows: 21) Offset noise removal process: Read the offset noise data stored in the FLASH and write it into the SRAM; 22) Offset noise calculation process: Compare whether the value of each pixel in the image data detected by the pnCCD is within the baseline data range. If it is within the baseline data range, add the pixel value to the accumulated value of the current pixel, increment the pixel count by one, and enter the SRAM write state. In the SRAM write state, the data obtained in the comparison state is written into the address of the corresponding pixel in the SRAM used to calculate the offset noise, and then the process waits for the falling edge of the SRAM write signal to enter the judgment state. In the judgment state, the current operating mode of the FPGA is determined, whether the division operation has started, and the number of image frames read. If it is in full-frame mode, division has not started, and the number of image frames read is less than 3, then return to the comparison state. If the number of image frames read is greater than or equal to 3, then enter the SRAM read state. If it is in non-full-frame mode, division has not started, and the number of image frames read is 0, then enter the SRAM read state. If division has started and the maximum address has been reached, then return to the idle state. Otherwise, enter the SRAM read state. The SRAM read state reads the data stored in the SRAM and waits for the falling edge of the SRAM read signal. If division has not started, it returns to the comparison state; if division has started, it enters the calculation state. In the calculation state, the accumulated value of each pixel stored in SRAM is divided by the corresponding pixel count value to complete the division operation and obtain the offset noise. Then, the process enters the SRAM write state.

2. The system according to claim 1, characterized in that, It also includes an RS422 receiver chip, used to receive instructions sent by the satellite through the electrical control box and send them to the FPGA; the instructions include instructions to calculate offset noise, instructions to modify offset noise, and instructions to update static offset noise.

3. The system according to claim 1, characterized in that, The FLASH address is divided into two functional areas: Area A is used to store the offset noise data of each pixel of the pnCCD calculated during ground calibration; Area B is used to store the offset noise data calculated by the satellite in orbit.

4. The system according to claim 3, characterized in that, The FLASH address is 16 bits wide; among them, FLASH addresses 0x0 to 0x23FFF store offset noise data of the full-frame mode storage area; FLASH addresses 0x24000 to 0x47FFF store offset noise data of each pixel of the pnCCD calculated during ground calibration; FLASH addresses 0x48000 to 0x53FFF store offset noise data of the time-varying mode exposure area during ground calibration; FLASH addresses 0x54000 to 0x55E7F store offset noise data of the windowed mode or energy-saving mode exposure area during ground calibration; area B stores offset noise data calculated on-orbit by satellites of the same type as area A, with an offset address of 0x80000.

5. The system according to claim 4, characterized in that, The instruction modifies the offset noise module to move the calculated offset noise to the specified area. The instruction includes the areas that need to be updated: full-frame mode storage area cache address 0x56000~0x79FFF updated to 0x0~0x23FFF; full-frame mode exposure area cache address 0x56000~0x79FFF updated to 0x24000~0x47FFF; time-varying mode exposure area cache address 0x56000~0x61FFF updated to 0x48000~0x53FFF; windowed mode or power saving mode exposure area cache address 0x56000~0x57E7F updated to 0x54000~0x55E7F.

6. The system according to claim 1, characterized in that, The SRAM address is 32 bits wide; among them, SRAM addresses 0x0 to 0x55E7F store offset noise data; SRAM addresses 0x56000 to 0x79FFF cache the offset noise data calculated by the satellite in orbit.

7. The system according to claim 6, characterized in that, The SRAM cache size used varies depending on the observation mode: full frame mode storage area cache address 0x56000~0x79FFF; full frame mode exposure area cache address 0x56000~0x79FFF; time-varying mode exposure area cache address 0x56000~0x61FFF; windowed mode or power saving mode exposure area cache address 0x56000~0x57E7F.

8. The system according to claim 1, characterized in that, The FPGA is Fudan Microelectronics' NORFLASHJFM29LV641RH.

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