Display device and electronic terminal

Abstract

The present invention provides a display device and an electronic terminal. For a shift register module of a gate driving unit in the display device, an inverting submodule is electrically connected between a third node and a second node to achieve its isolation between a first transistor loaded with a clock signal and a second node electrically connected to a self-stabilizing module, thereby reducing the influence of the clock signal jump on the potential of the second node.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device and an electronic terminal. Background Art

[0002] Each self-stabilizing module in the gate drive circuit controls the potential of the control terminal of the corresponding gate output unit, thereby indirectly controlling the output of the corresponding gate signal to achieve the scanning of the sub-pixels in the plane. Therefore, the stability of the potential of the internal node of the self-stabilizing module is particularly important. Summary of the invention

[0003] Embodiments of the present invention provide a display device and an electronic terminal for improving the stability of the potential of an internal node of a self-stabilizing module.

[0004] An embodiment of the present invention provides a display device, comprising a plurality of sub-pixels, a plurality of gate lines and a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded gate driving units, the gate lines are electrically connected between corresponding gate driving units and corresponding plurality of sub-pixels, and the gate driving unit comprises:

[0005] A shift register module, wherein an input end of the shift register module is electrically connected to a frame start line or a first node of the gate driving unit of a previous stage, a control end of the shift register module is electrically connected to a clock line, and the shift register module is used to control the frame start signal transmitted by the frame start line or the signal of the first node of the gate driving unit of the previous stage to act on the second node in response to a first potential of a clock signal transmitted by the clock line;

[0006] A self-stabilizing module, electrically connected to the shift register module via the second node;

[0007] a gate output module, electrically connected to the corresponding gate line, connected to the self-stabilizing module through the second node, and used for generating a gate signal transmitted to the corresponding gate line in response to a signal of the second node;

[0008] Wherein, the shift register module comprises:

[0009] a first transistor, one of a source and a drain of the first transistor being electrically connected to an input terminal of the shift register module, the other of a source and a drain of the first transistor being electrically connected to a third node, a gate of the first transistor being electrically connected to a control terminal of the shift register module, and the first transistor being used to control the frame start signal or the signal of the first node of the gate driving unit of the previous stage to be transmitted to the third node in response to a first potential of the clock signal;

[0010] An inverting submodule is electrically connected between the third node and the second node, an input end of the inverting submodule is electrically connected to the voltage line, and the inverting submodule is used to respond to the signal of the third node to control the voltage signal transmitted by the voltage line to be transmitted to the second node.

[0011] An embodiment of the present invention also provides an electronic terminal, including:

[0012] A display device as described in any one of the above;

[0013] A driving chip, electrically connected to the display device, for generating the frame start signal and the clock signal;

[0014] A power management chip is electrically connected to the display device and the driving chip, and is used to generate the voltage signal and a power signal transmitted to the driving chip, wherein the power signal is used to generate the frame start signal and the clock signal.

[0015] The display device and electronic terminal provided by the embodiments of the present invention, with respect to the shift register module of the gate driving unit in the display device, electrically connect the inverting submodule between the third node and the second node to achieve its isolation between the first transistor loaded with the clock signal and the second node electrically connected to the self-stabilizing module, thereby reducing the influence of the clock signal jump on the potential of the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the structure of a display device provided by an embodiment of the present invention.

[0017] Figure 2 It is a module diagram of a gate driving unit provided in an embodiment of the present invention.

[0018] Figure 3 and Figure 4 is a circuit diagram of a gate driving unit provided in an embodiment of the present invention.

[0019] Figure 5 and Figure 6 It is a waveform diagram of some external signals and node signals in the gate driving unit provided by the embodiment of the present invention.

[0020] Figure 7 It is a module diagram of an electronic terminal provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0022] An embodiment of the present invention provides a display device, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0023] In one embodiment, if Figure 1 As shown, the display device 100 includes a plurality of sub-pixels P, a plurality of gate lines 10 and a gate driving circuit 20, wherein the gate driving circuit 20 includes a plurality of cascaded gate driving units 201, and the gate lines 10 are electrically connected between the corresponding gate driving units 201 and the corresponding plurality of sub-pixels P. Figures 2 to 4 As shown, the gate driving unit 201 includes: a shift register module 301, the input end of the shift register module 301 is electrically connected to the frame start line or the first node P of the gate driving unit 201 of the previous stage, the control end of the shift register module 301 is electrically connected to the clock line (including at least one of the first clock line and the second clock line), and the shift register module 301 is used to respond to the first potential of the clock signal transmitted by the clock line (the first clock signal XCK transmitted by the first clock line or the second clock signal CK transmitted by the second clock line, here taking the former as an example), control the frame start signal STV transmitted by the frame start line or the signal P(n-1) of the first node P of the gate driving unit 201 of the previous stage to act on the second node K; a self-stabilizing module 302, electrically connected to the shift register module 301 through the second node K; a gate output module 303 (including at least one of the first gate output module 3031 and the second gate output module 3032), electrically connected to Figure 1 The gate line 10 corresponding to the gate line 10 is connected to the self-stabilizing module 302 through the second node K, and is used to generate a gate signal (including at least one of the first gate signal Nout and the second gate signal Pout) transmitted to the corresponding gate line 10 in response to the signal of the second node K; wherein, Figure 2 and Figure 3As shown, the shift register module 301 includes: a first transistor T2, one of the source and the drain of the first transistor T2 is electrically connected to the input end of the shift register module 301, the other of the source and the drain of the first transistor T2 is electrically connected to the third node O, the gate of the first transistor T2 is electrically connected to the control end of the shift register module 301, and the first transistor T2 is used to respond to the first potential of the clock signal (here, the first clock signal XCK is used as an example to control the frame start signal STV or the gate of the previous stage The signal P(n-1) of the first node P of the driving unit 201 is transmitted to the third node O; the inverting sub-module 3011 is electrically connected between the third node O and the second node K, and the input end of the inverting sub-module 3011 is electrically connected to the voltage line. The inverting sub-module 3011 is used to respond to the second potential of the signal of the third node O (for example, the signal O(n) of the nth level third node O), and control the voltage signal (including the first voltage signal NVGL and the second voltage signal PVGH) transmitted by the voltage line to be transmitted to the second node K.

[0024] Among them, in this embodiment, the input end of the shift register module 301 of the first-stage gate driving unit 201 is electrically connected to the frame start line, and the input end of the shift register module 301 of the gate driving unit 201 of the remaining stages is electrically connected to the first node P of the gate driving unit 201 of the previous stage. The multi-stage gate driving unit 201 works in sequence so that the multiple gate pulses in the output multiple gate signals are arranged in sequence on the time axis, thereby controlling multiple rows of sub-pixels P to turn on in sequence, so as to load the corresponding data voltages in sequence, and realize sequential light emission or global simultaneous light emission.

[0025] Specifically, the shift register module 301 of the gate driving unit 201 transmits the frame start signal STV or the signal P(n-1) of the first node P of the gate driving unit 201 of the previous stage to the second node K under the first potential of the clock signal, and the self-stabilizing module 302 electrically connected to the second node K also controls the potential of the second node K. Finally, the potential of the second node K is used to control the gate signal at the output end of the gate output module 303, thereby controlling the opening of multiple sub-pixels P in the surface. However, the clock signal acting on the shift register module 301 will jump. If it is not interfered, the jump of the clock signal will affect the potential of the second node K connected to the shift register module 301 through the coupling effect of the parasitic capacitance between the lines, thereby reducing the reliability of the operation of the gate driving unit 201.

[0026] It can be understood that in this embodiment, the inverting submodule 3011 in the shift register module 301 is set to be electrically connected between the third node O and the second node K, that is, the first transistor T2 is connected between the input end of the shift register module 301 and the third node O. Since the inverting submodule 3011 is set between the first transistor T2 and the second node K, the jump of the clock signal loaded on the gate of the first transistor T2 is only transmitted to the third node O, but cannot be transmitted to the second node K. In this embodiment, while the inverting submodule 3011 and the first transistor T2 are still provided to realize the shift register and signal reversal functions of the shift register module 301, by appropriately setting the connection relationship between the inverting submodule 3011 and the first transistor T2, the stability of the potential of the second node K can also be improved, so as to improve the reliability of the operation of the gate driving unit 201.

[0027] In some embodiments, in combination Figures 2 to 4 As shown, the control end of the inverting sub-module 3011 is electrically connected to the third node O, the first input end of the inverting sub-module 3011 is electrically connected to the first voltage line, the second input end of the inverting sub-module 3011 is electrically connected to the second voltage line, and the output end of the inverting sub-module is electrically connected to the second node K; wherein, the inverting sub-module 3011 is used to respond to the potential of the third node O to control the first voltage signal NVGL transmitted by the first voltage line or the second voltage signal PVGH transmitted by the second voltage line to be transmitted to the second node K.

[0028] In combination with the above discussion, by acting on the first transistor T2 with a clock signal (here taking the first clock signal XCK as an example), a shift registration effect of the frame start signal STV or the signal P(n-1) of the first node P of the previous gate driving unit 201 can be realized. In this embodiment, the first input terminal and the second input terminal of the inverting submodule 3011 are respectively loaded with the first voltage signal NVGL and the second voltage signal PVGH with different amplitudes, so that the above-mentioned potential stored in the third node O is transmitted to the second node K by acting on the inverting submodule 3011 to realize the first voltage signal NVGL or the second voltage signal PVGH. By reasonably setting the amplitude of the first voltage signal NVGL or the amplitude of the second voltage signal PVGH, the signal of the second node K and the signal of the third node O can be reversed.

[0029] In some embodiments, Figure 3 and Figure 4As shown, the inverting submodule 3011 includes: a second transistor T13, one of the source and the drain of the second transistor T13 is electrically connected to the first input terminal of the inverting submodule 3011; a third transistor T12, one of the source and the drain of the third transistor T12 is electrically connected to the second input terminal of the inverting submodule 3011, and the other of the source and the drain of the second transistor and the other of the source and the drain of the third transistor T12 are electrically connected to the second node K; wherein, at least the gate of the third transistor T12 is electrically connected to the control terminal of the inverting submodule 3011, and the amplitude of the second voltage signal PVGH is greater than the amplitude of the first voltage signal NVGL.

[0030] Among them, the conduction and cutoff of at least the third transistor T12 in the inverting submodule 3011 in this embodiment are controlled by the potential of the control end of the inverting submodule 3011 (i.e., the potential of the third node O), and the gate of the second transistor T13 can also be controlled by a signal related to the frame start signal STV or the signal P(n-1) of the first node P of the previous gate driving unit 201. Based on this, the types of the two transistors can be set to be different, and the types need to be set in combination with the amplitude of the first voltage signal NVGL and the amplitude of the second voltage signal PVGH, so that the potential of the second node K is close to the amplitude of the first voltage signal NVGL or the amplitude of the second voltage signal PVGH in each time period, thereby realizing the inversion of the signal of the second node K and the signal of the third node O.

[0031] In particular, in this embodiment, for the third transistor T12 loaded with the second voltage signal PVGH with a larger amplitude, its gate is electrically connected to the control end of the inverting sub-module 3011, so that its conduction and cutoff are simultaneously controlled by the frame start signal STV, one of the signals P(n-1) of the first node P of the previous gate driving unit 201, and the clock signal, so as to avoid the jump of the former signal directly causing the third transistor T12 to be mistakenly turned on, thereby transmitting the second voltage signal PVGH with a larger amplitude to the second node K to affect its potential.

[0032] Specifically, Figure 3As shown, the gate of the second transistor T13 is electrically connected to the control terminal 3011 (i.e., the third node O) of the inverting submodule. At this time, the conduction and cutoff of the second transistor T13 and the third transistor T12 are both controlled by the potential of the control terminal of the inverting submodule 3011 (i.e., the potential of the third node O), that is, the conduction and cutoff of the two are simultaneously controlled by the frame start signal STV, one of the signals P(n-1) of the first node P of the previous gate driving unit 201, and the clock signal, so that in each time period, one of the two transistors is cut off and the other is turned on, so as to transmit the first voltage signal NVGL or the second voltage signal PVGH loaded by one of the source and the drain of the turned-on transistor to the second node K, thereby realizing the reversal of the signal of the second node K and the signal of the third node O.

[0033] Or, if Figure 4 As shown, the gate of the second transistor T13 is electrically connected to the input end of the shift register module 301. That is, the conduction and cutoff of the second transistor T13 are only controlled by one of the frame start signal STV and the signal P(n-1) of the first node P of the previous gate driving unit 201. Since the second transistor T13 is loaded with the first voltage signal NVGL with a smaller amplitude, even if the second transistor T13 and the third transistor T12 are turned on at the same time, the potential of the second node K will still be closer to the amplitude of the larger second voltage signal PVGH, and the signal of the second node K and the signal of the third node O can still be reversed.

[0034] Understandably, no matter what Figure 3 or Figure 4 In the configuration of the shift register module 301 shown, since the second transistor T13 and the third transistor T12 are provided at the second node K and the third node O, the second transistor T13 and the third transistor T12 will isolate the jump of the clock signal, and isolate the influence of the coupling effect caused by the jump of the clock signal before the gate of the third transistor T12.

[0035] In some embodiments, Figure 5 and Figure 6 As shown, the two are Figure 3 and Figure 4The waveform diagram of some signals in the gate driving unit 201 is shown in FIG. 1 , the potential VK1 of the signal K(n) of the second node K in the first time period (including but not limited to the time period t1 and the time period t9) is greater than the potential VK2 in the second time period (including the time period t2 to the time period t8), and the absolute value of the difference between the maximum value and the minimum value of the potential VK1 and the stable value is less than 0.001 volt. The stable value can be understood as the value of the potential VK1 that maintains the longest time, and the degree of up and down fluctuation relative to the stable value can be understood as the degree of instability. Due to the setting method of the above-mentioned shift register module 301, the absolute value of the difference between the maximum value and the minimum value of the potential VK1 in the first time period and the stable value is less than 0.001 volt, that is, the absolute value of the up and down fluctuation of the potential VK1 relative to the above-mentioned stable value is less than 0.001 volt, and the potential VK1 presents a relatively stable state.

[0036] Similarly, by adopting the above-mentioned configuration of the shift register module 301, as Figure 5 and Figure 6 As shown, the potential VK1 of the signal K(n) of the second node K in the first time period is greater than the potential VK2 in the second time period, and the absolute value of the difference between the maximum value and the minimum value of the potential VK2 in the second time period is less than or equal to 3.4 V. Wherein, based on the fact that the potential VK2 is less than the potential VK1, the value of the potential VK2 is less than 0 as an example, then the maximum value of the potential VK2 in the second time period is closer to 0 than the minimum value, for example, when the minimum value is the stable value of the potential VK2, then the “absolute value of the difference between the maximum value and the minimum value” can represent the degree of floating of the potential VK2, for example Figure 5 The maximum floating degree of the middle potential VK2 can be a momentary floating of 3.3V from a stable value (eg, a minimum value) of -8V to a maximum value of -4.7V, for example Figure 6 The maximum floating degree of the middle potential VK2 can be an instantaneous floating degree of 3.4V from a stable value (eg, the minimum value) -8V to reach a maximum value of -4.6V.

[0037] In some embodiments, in combination Figures 2 to 4As shown, the gate driving unit 201 also includes: a gate frequency division module 304 (which may include at least one of a first gate frequency division submodule 3041 and a second gate frequency division submodule 3042), the control end of the gate frequency division module 304 is electrically connected to the frequency division control line, the input end of the gate frequency division module is electrically connected to the second node K, and the output end of the gate frequency division module 304 is electrically connected to the gate output module 303 through a fourth node (which may include at least one of a first subnode W and a second subnode M); wherein the gate frequency division module 304 is used to control the fourth node to be electrically connected to the second node K in response to a third potential of the frequency division control signal (at least one of the first frequency division control signal NLF and the second frequency division control signal PLF) transmitted by the frequency division control line.

[0038] It can be understood that in this embodiment, by setting a gate frequency division module 304 controlled by a frequency division control signal, it can control whether the fourth node is electrically connected to the second node K at the current moment according to at least the frequency division control signal, thereby controlling whether the signal of the second node K can be transmitted and act on the gate frequency division module 304, thereby controlling whether the waveform of the above-mentioned gate signal generated by the gate frequency division module 304 includes a gate pulse. If it does, the sub-pixels P of the corresponding row can be controlled to be turned on, otherwise the sub-pixels P of the corresponding row are turned off. Further, through the current amplitude of the frequency division control signal corresponding to the gate driving unit 201 corresponding to each row of sub-pixels P in the working period, it can be controlled whether the waveform of the above-mentioned gate signal generated by the gate driving unit 201 includes a gate pulse, and then it can be controlled whether each of the multiple gate signals includes a gate pulse. Further, it is understood in the same way in each frame. By setting the amplitude of the frequency division control signal in different time periods in multiple frames, the partitioned frequency division setting in the display area of ​​the display device 100 can be realized.

[0039] In some embodiments, Figure 3 and Figure 4As shown, the frequency division control line includes a first frequency division control line and a second frequency division control line, and the fourth node includes the first sub-node W and the second sub-node M; wherein the gate frequency division module 304 includes: the first gate frequency division module 3041, electrically connected between the second node K and the first sub-node W, for responding to the first sub-potential of the first frequency division control signal NLF transmitted by the first frequency division control line to control the second node K to be electrically connected to the first sub-node W; the second gate frequency division module 3042, electrically connected between the second node K and the second sub-node M, for responding to the second sub-potential of the second frequency division control signal PLF transmitted by the second frequency division control line potential to control the electrical connection between the second node K and the second sub-node M; the gate output module 303 includes: the above-mentioned first gate output module 3031, electrically connected between the first sub-node W and the corresponding first sub-gate line in the gate line, for responding to the third sub-potential of the first sub-node W to generate the corresponding first gate signal Nout transmitted to the corresponding first sub-gate line; the above-mentioned second gate output module 3032, electrically connected between the second sub-node M and the corresponding second sub-gate line in the gate line, for responding to the fourth sub-potential of the second sub-node M to generate the corresponding second gate signal Pout transmitted to the corresponding second sub-gate line.

[0040] For ease of description, Figure 3 and Figure 4 Only the n-th gate driving unit 201 is taken as an example, where n is a positive integer greater than or equal to 1. If n is greater than or equal to 3, the signal P(n-2) of the first node P of the (n-2)-th gate driving unit 201 and the signal P(n-1) of the first node P of the (n-1)-th gate driving unit 201 required in the n-th gate driving unit 201 can be directly provided by the (n-2)-th gate driving unit 201 and the (n-1)-th gate driving unit 201 respectively. If n is less than 3, the above signals can be provided by a virtual gate driving unit (which does not output gate signals into the plane).

[0041] It can be understood that in this embodiment, based on the gate output module 303 including the first gate output module 3031 and the second gate output module 3032, the gate frequency division module 304 includes the first gate frequency division module 3041 and the second gate frequency division module 3042. For the n-th level gate driving unit 201, the first gate frequency division module 3041 controls whether the first gate signal Nout(n) output by the first gate output module 3031 includes the corresponding gate pulse at least according to the first frequency division control signal NLF, and the second gate frequency division module 3042 controls whether the second gate signal Pout(n) output by the second gate output module 3032 includes the corresponding gate pulse at least according to the second frequency division control signal PLF. Further, it can be controlled whether the multiple first gate signals Nout and the multiple second gate signals Pout output by the multi-level gate driving unit 201 in multiple frames include the corresponding gate pulses, thereby realizing the zoned frequency division setting within the display area of ​​the display device 100.

[0042] In some embodiments, Figure 3 and Figure 4 As shown, the first control end of the control end of the gate frequency division module 304 is electrically connected to the frequency division control line, and the second control end of the control end of the gate frequency division module is electrically connected to the first node P; wherein the gate frequency division module 304 is used to respond to the fourth potential of the signal of the first node P to control the frequency division control signal to be transmitted to the fifth node J, and is also used to respond to the fifth potential of the signal of the fifth node J to control the fourth node (at least one of the first sub-node W and the second sub-node M) to be electrically connected to the second node K.

[0043] Among them, when the gate frequency division module 304 includes one of the first gate frequency division module 3041 and the second gate frequency division module 3042, the above-mentioned first control end, the second control end and the fifth node J can be the corresponding terminals and nodes in the first gate frequency division module 3041 or the second gate frequency division module 3042. When the gate frequency division module 304 includes both the first gate frequency division module 3041 and the second gate frequency division module 3042, both of them can include the above-mentioned first control end, the second control end and the fifth node J, and the fifth node J can include the third sub-node J1 and the fourth sub-node J2 corresponding to the first gate frequency division module 3041 and the second gate frequency division module 3042 respectively.

[0044] It can be understood that, taking the nth level as an example, the second control end in this embodiment is controlled by the signal P(n) of the first node P of the nth level, and controls whether the frequency division control signal (at least one of the first frequency division control signal NLF and the second frequency division control signal PLF) is transmitted to the fifth node J, and the first control end is controlled by the signal of the fifth node J to control the electrical connection between the fourth node (at least one of the first sub-node W and the second sub-node M) and the second node K, that is, the electrical connection between the fourth node and the second node K is jointly controlled by the signal of the first node P(n) of the nth level and the frequency division control signal.

[0045] Specifically, Figure 3 and Figure 4 As shown, the gate frequency division module 304 (including at least one of the first gate frequency division module 3041 and the second gate frequency division module 3042) includes: a first gate frequency division submodule 01, the input end of the first gate frequency division submodule 01 is electrically connected to the first control end of the gate frequency division module 304, the output end of the first gate frequency division submodule 01 is electrically connected to the fifth node J, and the control end of the first gate frequency division submodule 01 is electrically connected to the first node P; a second gate frequency division submodule 02, the input end of the second gate frequency division submodule 02 is electrically connected to the second node K, the output end of the second gate frequency division submodule 02 is electrically connected to the fourth node (which may include at least one of the first subnode W and the second subnode M), and the control end of the second gate frequency division submodule 02 is electrically connected to the fifth node J.

[0046] Here, the gate frequency division module 304 includes a first gate frequency division module 3041 and a second gate frequency division module 3042 as an example, that is, both include a first gate frequency division submodule 01 and a second gate frequency division submodule 02, the first gate frequency division submodule 01 of the former and the latter include a fourth transistor T16 and a fifth transistor T20, respectively, the second gate frequency division submodule 02 of the former and the latter include a sixth transistor T11 and a seventh transistor T19, respectively, and also include a first capacitor C2 and a second capacitor C3, respectively, the connection relationship of the above-mentioned components can refer to but is not limited to Figure 3 and Figure 4 shown.

[0047] It can be understood that when the signal P(n) of the first node P of the nth level is the third potential, the fourth transistor T16 transmits the frequency division control signal to the fifth node J, otherwise it is not transmitted to the fifth node J; when the frequency division control signal is transmitted to the fifth node J, if the frequency division control signal makes the signal of the fifth node J the fifth potential, the first sub-node W is electrically connected to the second node K, and if the frequency division control signal makes the signal of the fifth node J jump from the fifth potential to other potentials, it can be considered that the first sub-node W is electrically disconnected from the second node K, and through the coupling effect of the first capacitor C2, the potential of the first sub-node W also changes with the potential of the fifth node J, thereby changing the working condition of the first gate output module 3031. Similarly, the working principles of the fifth transistor T20, the seventh transistor T19 and the second capacitor C3 can also refer to the above discussion.

[0048] Specifically, the self-stabilizing module 302 may include an eighth transistor T1, a ninth transistor T3, a tenth transistor T4, an eleventh transistor T5 and a twelfth transistor T14, the first gate output module 3031 may include a thirteenth transistor T9, a fourteenth transistor T10, a fifteenth transistor T17 and a sixteenth transistor T18, the second gate output module 3032 may include a seventeenth transistor T6, an eighteenth transistor T7, a nineteenth transistor T21, a twentieth transistor T22 and a third capacitor C1, the second gate frequency division module 3042 may further include a twenty-first transistor T8, and the self-stabilizing module 302 may further include a twenty-second transistor T15.

[0049] Among them, taking the nth stage as an example, the gate of the twenty-second transistor T15 can be electrically connected to the control line to load the control signal Control transmitted by the control line, the gate of the twenty-first transistor T8 is electrically connected to the first node P of the (n-2)th stage gate driving unit 201 to receive its signal P(n-2), one of the source and the drain of the twenty-first transistor T8 is electrically connected to the second sub-node M, and the other is electrically connected to the gate of the seventeenth transistor T6 through the sixth node Q, and one of the source and the drain of the seventeenth transistor T6 is electrically connected to the second clock line to load the second clock signal CK transmitted by the second clock line.

[0050] The types of the above-mentioned multiple transistors, the signals loaded by the multiple transistors and capacitors, and the connection relationship can refer to but are not limited to Figure 3 and Figure 4 As shown, based on Figure 3 and Figure 4The types of the multiple transistors listed (only the eighth transistor T1, the tenth transistor T4, the fourteenth transistor T10, the second transistor T13, the twelfth transistor T14, the fifteenth transistor T17, the nineteenth transistor T21, are N-type transistors, and the first transistor T2, the ninth transistor T3, the eleventh transistor T5, the seventeenth transistor T6, the eighteenth transistor T7, the twenty-first transistor T8, the thirteenth transistor T9, the sixth transistor T11, the third transistor T12, the twenty-second transistor T15, the fourth transistor T16, the sixteenth transistor T18, the seventh transistor T19, the fifth transistor T20, and the twentieth transistor T22 are P-type transistors as an example), the corresponding waveform diagrams of the multiple signals and nodes can be respectively referred to Figure 5 and Figure 6 Of course, if the transistor type is different Figure 3 and Figure 4 As shown, the corresponding signals and node waveforms also need to be changed accordingly.

[0051] In order to better explain the working principle of the gate driving circuit 20 in the display device 100 of the present invention, Figure 3 and Figure 4 The gate drive unit 201 structure shown in FIG. Figure 5 and Figure 6 The waveform diagram shown takes the n-th gate driving unit 201 as an example to explain the working process as follows.

[0052] After power-on, the control signal Control is used to control the twenty-second transistor T15 to be turned on to transmit the second voltage signal PVGH with a higher amplitude to the second node K, the ninth transistor T3 is turned off, the eighth transistor T1 is turned on, and the third voltage signal PVGL with a lower amplitude is transmitted to the first node P, so that the fourth transistor T16 and the fifth transistor T20 are turned on. If the first frequency division control signal NLF and the second frequency division control signal PLF are both at corresponding low potentials, the sixth transistor T11 and the seventh transistor T19 are turned on, and the signal W(n) of the first sub-node W and the signal M(n) of the second sub-node M are also at high potentials, so that the thirteenth transistor T16 and the fifth transistor T20 are turned on. The body transistor T9 is turned off and the fourteenth transistor T10 is turned on, so as to output the low potential (for example, a constant voltage signal) of the first voltage signal NVGL as the first gate signal Nout(n). At this time, it can be considered that the signal P(n-2) of the first node P of the (n-2)-th level gate driving unit 201 is also at a corresponding low potential, so that the twenty-first transistor T8 is turned on, the sixth node Q is at a high potential, so that the seventeenth transistor T6 is turned off, and at the same time, the low potential of the signal P(n) of the first node P turns on the eighteenth transistor T7, so as to output the high potential (for example, a constant voltage signal) of the second voltage signal PVGH as the second gate signal Pout(n);

[0053] In time period t1, the first clock signal XCK is at a corresponding high potential, the second clock signal CK is at a corresponding low potential, and the frame start signal STV or the signal P(n-1) of the first node P of the (n-1)th level gate driving unit 201 is at a corresponding high potential, then the first transistor T2 is turned off, the signal O(n) of the third node O is maintained at the previous low potential, the working state of the inverting submodule 3011 remains unchanged, the signal K(n) of the second node K is maintained at the previous high potential so that the signal P(n) of the first node P is maintained at a low potential. If the first frequency division control signal NLF and the second frequency division control signal PLF are both at corresponding low potentials, the signal W(n) of the first subnode W and the signal M(n) of the second subnode M are also at a high potential. Similarly, the low potential output of the first voltage signal NVGL is used as the first gate signal signal Nout(n), at this time, the signal P(n-2) of the first node P of the (n-2)-th stage gate driving unit 201 is also at a corresponding high potential, the twenty-first transistor T8 is turned off, the sixth node Q is maintained at a high potential, so that the seventeenth transistor T6 is turned off, and the eighteenth transistor T7 is turned on, so as to output the high potential (for example, a constant voltage signal) of the second voltage signal PVGH as the second gate signal Pout(n), and at the same time, the eleventh transistor T5, the sixteenth transistor T18, and the twentieth transistor T22 are all turned on, and the tenth transistor T4, the fifteenth transistor T17, and the nineteenth transistor T21 are all controlled by the first clock signal XCK and turned on, so as to transmit the high potential of the second voltage signal PVGH to the second node K, the first sub-node W, and the second sub-node M so that they maintain a stable high potential;

[0054] In time period t2, the first clock signal XCK is at a corresponding low potential (i.e., the first potential), the second clock signal CK is at a corresponding high potential, and the frame start signal STV or the signal P(n-1) of the first node P of the (n-1)th gate driving unit 201 is at a corresponding high potential, then the first transistor T2 is turned on, and the high potential is transmitted to the third node O to turn on the second transistor T13 and turn off the third transistor T12, so as to transmit the low potential first voltage signal NVGL to the second node K, so that the ninth transistor T3 is turned on, the eighth transistor T1 is turned off, and the second voltage signal PVGH with a higher amplitude is transmitted to the first node P, so that the fourth transistor T16 and the fifth transistor T20 are turned off, and the sixth transistor T11 and the seventh transistor T19 are all kept turned on, so the signal of the first subnode W is The signal W(n) and the signal M(n) of the second sub-node M are also at a low potential, so the fourteenth transistor T10 is turned off and the thirteenth transistor T9 is turned on, and the high potential (for example, a constant voltage signal) of the fourth voltage signal NVGH is output as the first gate signal Nout(n), and at the same time the eighteenth transistor T7 is turned off, and the seventeenth transistor T6 is kept turned off, so the second gate signal Pout(n) is maintained at a high potential, and at the same time the eleventh transistor T5, the sixteenth transistor T18, and the twentieth transistor T22 are all turned off, and the tenth transistor T4, the fifteenth transistor T17, and the nineteenth transistor T21 are all controlled by the first clock signal XCK and turned off, so as to avoid transmitting the high potential of the second voltage signal PVGH to the second node K, the first sub-node W, and the second sub-node M to affect their low potentials;

[0055] In period t3, the first clock signal XCK is at a corresponding high potential, the second clock signal CK is at a corresponding high potential, and the frame start signal STV or the signal P(n-1) of the first node P of the (n-1)th gate driving unit 201 is at a corresponding high potential, then the first transistor T2 is turned off, so the third node O and the second node K are respectively maintained at the previous high potential and low potential, so the first node P is maintained at the previous high potential, so the first subnode W and the second subnode M are maintained at the previous low potential, so the working states of other transistors and the potentials of the nodes can be the same as those in period t2;

[0056] In time period t4, the first clock signal XCK is at a corresponding high potential, the second clock signal CK is at a corresponding low potential, and the frame start signal STV or the signal P(n-1) of the first node P of the (n-1)th gate driving unit 201 is at a corresponding high potential, then the first transistor T2 is turned off, and the rest can be analyzed similarly to that of time period t3;

[0057] In the period t5, the first clock signal XCK is at a corresponding low potential (i.e., the first potential), the second clock signal CK is at a corresponding high potential, and the frame start signal STV or the signal P(n-1) of the first node P of the (n-1)th gate driving unit 201 is at a corresponding high potential, then the first transistor T2 is turned on, and the rest can be similarly analyzed with reference to the period t2;

[0058] For period t6, the analysis of period t3 can be referred to in the same way;

[0059] The time period t7 is different from the time period t3 and the time period t6 in that the frame start signal STV or the signal P(n-1) of the first node P of the (n-1)th gate driving unit 201 is a corresponding high potential, and the signal P(n-2) of the first node P is a corresponding low potential, so that the twenty-first transistor T8 is turned on, the sixth node Q is a low potential, so that the seventeenth transistor T6 is turned on, and the eighteenth transistor T7 is kept off, so the high potential of the second clock signal CK is output as the second gate signal Pout(n), and the first gate signal Nout(n) is kept high.

[0060] The difference between the period t8 and the period t7 is that the second clock signal CK is at a corresponding low potential, so the low potential of the second clock signal CK is output as the second gate signal Pout(n), and the first gate signal Nout(n) maintains a high potential;

[0061] In the time period t9, the first clock signal XCK is at the corresponding low potential (i.e., the first potential), the second clock signal CK is at the corresponding high potential, and the frame start signal STV or the signal P(n-1) of the first node P of the (n-1)th gate driving unit 201 is at the corresponding low potential, then the first transistor T2 is turned on, and the low potential is transmitted to the third node O to turn off the second transistor T13 and turn on the third transistor T12 to transmit the high potential second voltage signal PVGH to the second node K. Referring to the above discussion on “after power-on”, it can be seen that the ninth transistor T3 is turned off, the eighth transistor T1 is turned on, the fourth transistor T16 and the third transistor T17 are turned on, and the eighth transistor T20 is turned on. The fifth transistor T20 is turned on. If the first frequency-division control signal NLF and the second frequency-division control signal PLF are both corresponding low potentials, the sixth transistor T11 and the seventh transistor T19 are turned on. Then the signal W(n) of the first sub-node W and the signal M(n) of the second sub-node M are also high potentials. The low potential (for example, a constant voltage signal) of the first voltage signal NVGL is output as the first gate signal Nout(n). The twenty-first transistor T8 is turned on, the seventeenth transistor T6 is turned off, and the eighteenth transistor T7 is turned on. The high potential (for example, a constant voltage signal) of the second voltage signal PVGH is output as the second gate signal Pout(n).

[0062] It should be noted that the above analysis is based on the analysis that "the first frequency-division control signal NLF and the second frequency-division control signal PLF are both corresponding low potentials", that is, the frequencies of all regions can be equal; but if at least one of the first frequency-division control signal NLF and the second frequency-division control signal PLF is a corresponding high potential, it can be considered that even if at least one of the fourth transistor T16 and the fifth transistor T20 is turned on, at least one of the corresponding first sub-node W and the second sub-node M is still electrically disconnected from the second node K, resulting in the gate frequency-division module 304 in the gate driving unit being unable to be controlled by the second node K in real time to achieve the output of the gate pulse, thereby achieving the zoned frequency-division setting within the display area of ​​the display device 100.

[0063] The embodiment of the present invention also provides an electronic terminal, such as Figure 7 As shown, the electronic terminal 200 includes: the display device 100 as described above; a driving chip 201, electrically connected to the display device 100, for generating the frame start signal STV and the clock signal (including at least one of the first clock signal XCK and the second clock signal CK); a power management chip 202, electrically connected to the display device 100 and the driving chip 201, for generating the voltage signal (including the first voltage signal NVGL and the second voltage signal PVGH) and the power signal transmitted to the driving chip 201, and the power signal is used to generate the frame start signal STV and the clock signal.

[0064] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A display device, characterized in that: The invention comprises a plurality of sub-pixels, a plurality of gate lines and a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded gate driving units, the gate lines are electrically connected between corresponding gate driving units and corresponding plurality of sub-pixels, and the gate driving unit comprises: A shift register module, wherein an input end of the shift register module is electrically connected to a frame start line or a first node of the gate driving unit of a previous stage, a control end of the shift register module is electrically connected to a clock line, and the shift register module is used to control the frame start signal transmitted by the frame start line or the signal of the first node of the gate driving unit of the previous stage to act on the second node in response to a first potential of a clock signal transmitted by the clock line; A self-stabilizing module, electrically connected to the shift register module via the second node; a gate output module, electrically connected to the corresponding gate line, connected to the self-stabilizing module through the second node, and used for generating a gate signal transmitted to the corresponding gate line in response to a signal of the second node; Wherein, the shift register module comprises: a first transistor, one of a source and a drain of the first transistor being electrically connected to an input terminal of the shift register module, the other of a source and a drain of the first transistor being electrically connected to a third node, a gate of the first transistor being electrically connected to a control terminal of the shift register module, the first transistor being used to control the frame start signal or the signal of the first node of the gate driving unit of the previous stage to be transmitted to the third node in response to a first potential of the clock signal, the clock signal shifting the frame start signal or the signal of the first node of the gate driving unit of the previous stage through the first transistor to obtain a shift signal; An inverting submodule is electrically connected between the third node and the second node, an input end of the inverting submodule is electrically connected to the voltage line, and the inverting submodule is used to respond to the shift signal of the third node, control the voltage signal transmitted by the voltage line to be transmitted to the second node, so as to obtain an inverted signal with a phase opposite to that of the shift signal.

2. The display device according to claim 1, characterized in that The control end of the inverting submodule is electrically connected to the third node, the first input end of the inverting submodule is electrically connected to the first voltage line, the second input end of the inverting submodule is electrically connected to the second voltage line, and the output end of the inverting submodule is electrically connected to the second node; The inverting submodule is used to respond to the potential of the third node to control the first voltage signal transmitted by the first voltage line or the second voltage signal transmitted by the second voltage line to be transmitted to the second node.

3. The display device according to claim 2, characterized in that: The inverting submodule comprises: a second transistor, wherein one of a source and a drain of the second transistor is electrically connected to the first input terminal of the inverting submodule; a third transistor, wherein one of the source and the drain of the third transistor is electrically connected to the second input terminal of the inverting submodule, and the other of the source and the drain of the second transistor and the other of the source and the drain of the third transistor are both electrically connected to the second node; Wherein, at least the gate of the third transistor is electrically connected to the control end of the inverting submodule, and the amplitude of the second voltage signal is greater than the amplitude of the first voltage signal.

4. The display device according to claim 3, characterized in that: The gate of the second transistor is electrically connected to the control terminal of the inverting submodule or the input terminal of the shift register module.

5. The display device according to any one of claims 1 to 4, characterized in that: The potential of the signal of the second node in the first time period is greater than the potential in the second time period, and the absolute value of the difference between the maximum value and the minimum value of the potential of the signal of the second node in the first time period and the stable value of the potential of the signal of the second node in the first time period are both less than 0.001 volts.

6. The display device according to any one of claims 1 to 4, characterized in that: The potential of the signal of the second node in the first time period is greater than that in the second time period, and the absolute value of the difference between the maximum and minimum potentials of the signal of the second node in the second time period is less than or equal to 3.4V.

7. The display device according to claim 1, characterized in that: The gate driving unit further includes: A gate frequency division module, wherein a control end of the gate frequency division module is electrically connected to the frequency division control line, an input end of the gate frequency division module is electrically connected to the second node, and an output end of the gate frequency division module is electrically connected to the gate output module through a fourth node; The gate frequency division module is used to control the electrical connection between the fourth node and the second node in response to a third potential of the frequency division control signal transmitted by the frequency division control line.

8. The display device according to claim 7, characterized in that: A first control terminal among the control terminals of the gate frequency division module is electrically connected to the frequency division control line, and a second control terminal among the control terminals of the gate frequency division module is electrically connected to the first node; Among them, the gate division module is used to respond to the fourth potential of the signal of the first node to control the division control signal to be transmitted to the fifth node, and is also used to respond to the fifth potential of the signal of the fifth node to control the electrical connection between the fourth node and the second node.

9. The display device according to claim 8, characterized in that: The gate frequency division module comprises: a first gate frequency division submodule, wherein an input end of the first gate frequency division submodule is electrically connected to a first control end of the gate frequency division submodule, an output end of the first gate frequency division submodule is electrically connected to the fifth node, and a control end of the first gate frequency division submodule is electrically connected to the first node; A second gate frequency division submodule, wherein the input end of the second gate frequency division submodule is electrically connected to the second node, the output end of the second gate frequency division submodule is electrically connected to the fourth node, and the control end of the second gate frequency division submodule is electrically connected to the fifth node.

10. The display device according to claim 7, characterized in that: The frequency division control line includes a first frequency division control line and a second frequency division control line, and the fourth node includes a first sub-node and a second sub-node; Wherein, the gate frequency division module comprises: a first gate frequency division module, electrically connected between the second node and the first sub-node, and used to control the electrical connection between the second node and the first sub-node in response to a first sub-potential of a first frequency division control signal transmitted by the first frequency division control line; a second gate frequency division module, electrically connected between the second node and the second sub-node, and used to control the electrical connection between the second node and the second sub-node in response to a second sub-potential of a second frequency division control signal transmitted by the second frequency division control line; The gate output module comprises: A first gate output module, electrically connected between the first sub-node and a first sub-gate line of the corresponding gate lines, for responding to a third sub-potential of the first sub-node to generate a corresponding first gate signal transmitted to the corresponding first sub-gate line; The second gate output module is electrically connected between the second sub-node and the corresponding second sub-gate line of the gate lines, and is used to respond to the fourth sub-potential of the second sub-node to generate a corresponding second gate signal transmitted to the corresponding second sub-gate line.

11. An electronic terminal, characterized in that: include: The display device according to any one of claims 1 to 10; A driving chip, electrically connected to the display device, for generating the frame start signal and the clock signal; A power management chip is electrically connected to the display device and the driving chip, and is used to generate the voltage signal and a power signal transmitted to the driving chip, wherein the power signal is used to generate the frame start signal and the clock signal.

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