Leakage test device, semiconductor wafer, and leakage test method

Abstract

This application discloses a leakage current testing device, a semiconductor wafer, and a leakage current testing method. The leakage current testing device includes a first gallium nitride (GaN) device, which includes a cell region containing multiple cells. Each cell includes a semiconductor stack and source, drain, and field plate electrodes spaced apart on one side of the semiconductor stack. A drain pad is located outside the cell region and electrically connected to the drain of each cell. A source pad is located outside the cell region and electrically connected to the source of each cell. A field plate pad is located outside the cell region and electrically connected to the field plate electrode of each cell. The source pad and the field plate pad are located on the same side of the cell, and the projection of the source pad onto the plane of the field plate pad at least partially coincides with the field plate pad. This configuration solves the problem of the inability to provide timely feedback on device performance and dielectric quality during the manufacturing process of gallium nitride devices, thus saving costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a leakage current testing device, a semiconductor wafer, and a leakage current testing method. Background Technology

[0002] Gallium nitride (GaN) devices possess high breakdown electric field strength, high current density, and high voltage withstand capability. Simultaneously, their wide bandgap and large band gap significantly reduce leakage current issues. Furthermore, due to their large bandgap, they exhibit excellent high-voltage performance, enabling operation at high temperatures, high voltages, and high frequencies, thus improving device efficiency, reducing power consumption, and lowering costs. They also possess high thermal conductivity and excellent heat dissipation properties, allowing for higher integration density and power density compared to conventional components. Therefore, gallium nitride devices are widely used in power electronics.

[0003] The field plate in GaN devices primarily functions to modulate the channel distribution, thereby significantly improving the device's breakdown voltage. It also effectively addresses the limitation imposed by the device's low on-resistance under high speed and high voltage conditions. Furthermore, the introduction of the field plate structure can effectively suppress reliability issues such as current collapse, inverse piezoelectric effect, and stress-related degradation, further improving the power characteristics of GaN devices.

[0004] Currently, in the manufacturing process of GaN devices, the yield of products is unstable due to changes in the manufacturing process and fluctuations in equipment. However, the existing GaN device structure cannot provide timely feedback on the performance of the device and the quality of the dielectric during the manufacturing process, making it impossible to screen out degraded devices in advance, which increases production costs. Summary of the Invention

[0005] This application provides a leakage current testing device, a semiconductor wafer, and a leakage current testing method to solve the problem in the prior art that the device performance and dielectric quality cannot be fed back in a timely manner during the manufacturing process of gallium nitride devices.

[0006] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a leakage current testing device, comprising:

[0007] A first gallium nitride device includes a cell region, wherein a plurality of cells are disposed within the cell region, and each cell includes a semiconductor stack and a source electrode, a drain electrode, and a field plate electrode disposed at intervals on one side of the semiconductor stack.

[0008] Drain pads are disposed outside the cell region and electrically connected to the drain of each cell;

[0009] Source pads are disposed outside the cell region and electrically connected to the source of each cell;

[0010] Field plate pads are disposed outside the cell region and connected to the field plate electrode of each cell;

[0011] The source pad and the field pad are located on the same side of the cell, and the projection of the source pad onto the plane where the field pad is located at least partially coincides with the field pad.

[0012] Wherein, along the direction away from the cell, the source includes a source metal layer, a first metal layer and a second metal layer stacked together, and the drain includes a drain metal layer, the first metal layer and the second metal layer stacked together; the first metal layer and the second metal layer of the source are disconnected from the first metal layer and the second metal layer of the drain.

[0013] The field plate electrode includes a field plate metal layer, the field plate pad includes the field plate metal layer, and the field plate metal layer of the field plate electrode and the field plate metal layer of the field plate pad are connected in communication.

[0014] The source pad includes a second metal layer, the second metal layer of the source is connected to the second metal layer of the source pad, and the second metal layer of the drain is disconnected from the second metal layer of the source pad.

[0015] The drain pad includes the first metal layer, the first metal layer of the drain is connected to the first metal layer of the drain pad, and the first metal layer of the source is disconnected from the first metal layer of the drain pad.

[0016] An insulating dielectric layer is provided between the field plate pad and the source pad.

[0017] The source pad further includes a first metal layer, and the drain pad further includes a second metal layer and the field plate metal layer.

[0018] The leakage current testing device further includes:

[0019] A gate electrode is disposed between the source electrode and the field plate electrode, and the field plate electrode is disposed between the gate electrode and the drain electrode.

[0020] A gate pad is disposed outside the cell region and electrically connected to the gate of each cell;

[0021] Both the gate and the gate pad include the field plate metal layer. The field plate metal layers of the gate and the gate pad are connected in communication. The field plate metal layers of the gate and the gate pad are disconnected from the field plate electrode and the field plate metal layer of the field plate pad.

[0022] The drain pad is connected to the drains in each cell of the cell region.

[0023] The gate pad is connected to the gate in each cell of the cell region.

[0024] The source pads are connected to the source electrodes in each cell of the cell region.

[0025] The field plate pads are connected to the field plate electrodes in each cell.

[0026] The field plate electrode is connected to the field plate pad through a first wire formed by the field plate metal layer;

[0027] The source electrode is connected to the source electrode pad via a second wire formed by the second metal layer;

[0028] The drain electrode is connected to the drain electrode pad via a third conductor formed from the first metal layer;

[0029] The projections of the first conductor and the second conductor on the plane where the pads of the field plate are located are spaced apart.

[0030] Each of the cells further includes a passivation layer disposed on the semiconductor stack, the passivation layer being used to insulate the source, the gate, the field plate electrode and the drain in the cell region.

[0031] The semiconductor stack includes a substrate, a buffer layer disposed on the substrate, a first semiconductor layer disposed on the buffer layer, and a second semiconductor layer disposed on the first semiconductor layer, wherein a heterojunction structure is formed between the first semiconductor layer and the second semiconductor layer.

[0032] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a semiconductor wafer, comprising:

[0033] Multiple device regions, each device region having a second gallium nitride device;

[0034] Multiple test areas are provided, each test area is equipped with at least one leakage current testing device, the leakage current testing device being any of the leakage current testing devices described above, the leakage current testing device being used to test whether the second gallium nitride device leaks current and to determine the source of leakage current.

[0035] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a leakage current testing method, including:

[0036] Obtain a first gallium nitride preform; the first gallium nitride preform includes: a cell region, wherein a plurality of cells are disposed in the cell region, each cell including a semiconductor stack and a source and a drain disposed at intervals on one side of the semiconductor stack; the source includes a source metal layer, and the drain includes a drain metal layer;

[0037] A field plate electrode and a field plate pad are fabricated on one side of the first gallium nitride preform where the source metal layer and the drain metal layer are provided, and the field plate electrode and the field plate pad are connected in communication.

[0038] On the side of the first gallium nitride preform where the source metal layer and the drain metal layer are provided, the source, the drain and the drain pad are further fabricated, and the drain and the drain pad are connected in communication.

[0039] A voltage is applied to the drain pad and the field pad to perform a leakage current test.

[0040] The leakage current testing method further includes:

[0041] After the field plate pads are fabricated, before fabricating the drain electrode and the drain pad that are connected, an insulating dielectric layer is fabricated on the surface of the field plate pads.

[0042] The leakage current testing method further includes:

[0043] After performing the leakage current test, the source pad is fabricated and the source and drain are fabricated, with the source and the source pad connected in a manner.

[0044] The source pad and the field pad are located on the same side of the cell, and the projection of the source pad onto the plane where the field pad is located at least partially coincides with the field pad.

[0045] The step of fabricating a field plate electrode and a field plate pad on the side of the first gallium nitride preform where the source metal layer and the drain metal layer are disposed, wherein the field plate electrode and the field plate pad are connected in communication, includes:

[0046] A field plate metal layer is fabricated on one side of the first gallium nitride preform where the source metal layer and the drain metal layer are provided, forming the field plate electrode and the field plate pad. The field plate electrode and the field plate pad are connected through a first wire formed by the field plate metal layer.

[0047] The step of continuing to fabricate the source, the drain, and the drain pad on one side of the first gallium nitride preform where the source metal layer and the drain metal layer are provided, wherein the drain and the drain pad are connected in communication, includes:

[0048] A first metal layer is formed on the surface of the first gallium nitride preform where a field plate electrode is provided, forming the source, the drain and the drain pad, and the drain and the drain pad are connected through a third wire formed by the first metal layer;

[0049] After performing a leakage current test, the steps of fabricating the source pad and then fabricating the source and drain, wherein the source and the source pad are connected in a manner including:

[0050] A second metal layer is formed on the surface of the first gallium nitride preform where a first metal layer is provided, forming the source, the drain, and the source pad. The source and the source pad are connected through a second wire formed by the second metal layer.

[0051] The beneficial effects of this application are as follows: Unlike existing technologies, this application discloses a leakage current testing device, a semiconductor wafer, and a leakage current testing method. The leakage current testing device includes a first gallium nitride (GaN) device, comprising a cell region containing multiple cells. Each cell includes a semiconductor stack and source, drain, and field plate electrodes spaced apart on one side of the semiconductor stack. A drain pad is located outside the cell region and electrically connected to the drain of each cell. A source pad is located outside the cell region and electrically connected to the source of each cell. A field plate pad is located outside the cell region and electrically connected to the field plate electrode of each cell. The source pad and the field plate pad are located on the same side of the cell, and the projection of the source pad onto the plane of the field plate pad at least partially coincides with the field plate pad. This configuration solves the problem of timely feedback on device performance and dielectric quality during the manufacturing process of gallium nitride devices, thus saving costs. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0053] Figure 1 This is a schematic diagram of an embodiment of the leakage current testing device provided in this application;

[0054] Figure 2 yes Figure 1 A schematic cross-sectional view of the first gallium nitride device in the provided leakage current testing device;

[0055] Figure 3 This is a flowchart illustrating the first embodiment of the leakage current testing method provided in this application;

[0056] Figure 4 This is a flowchart illustrating the second embodiment of the leakage current testing method provided in this application;

[0057] Figure 5 This is a schematic diagram of the structure of an embodiment of the semiconductor wafer provided in this application. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0059] The terms "first," "second," and "third" used in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0060] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0061] See Figures 1 to 2 , Figure 1 This is a schematic diagram of an embodiment of the leakage current testing device provided in this application. Figure 2 yes Figure 1 A cross-sectional schematic diagram of the first gallium nitride device in the provided leakage current testing device.

[0062] See Figure 1 and Figure 2This application provides a leakage current testing device 100, which includes a first gallium nitride device 1, a drain pad 2, a source pad 3, and a field plate pad 4. The first gallium nitride device 1 includes a cell region A, within which multiple cells are disposed. Each cell includes a semiconductor stack 5 and a source electrode 6, a drain electrode 7, and a field plate electrode 8 spaced apart on one side of the semiconductor stack 5. The drain pad 2, source pad 3, and field plate pad 4 are all located outside the cell region A. The drain pad 2 is electrically connected to the drain electrode 7 of each cell, the source pad 3 is electrically connected to the source electrode 6 of each cell, and the field plate pad 4 is electrically connected to the field plate electrode 8 of each cell.

[0063] In this embodiment, the source pad 3 and the field pad 4 are located on the same side of the cell, and the projection of the source pad 3 onto the plane where the field pad 4 is located at least partially coincides with the field pad 4. By setting the projection of the source pad 3 onto the plane of the field plate pad 4 to at least partially coincide with the field plate pad 4, and electrically connecting the source pad 3 to the source 6 of each cell, the field plate pad 4 to the field plate electrode 8 of each cell, and the drain pad 2 to the drain 7 of each cell, a voltage is applied to the field plate pad 4 and the drain pad 2. A leakage current test can be performed using a testing instrument to measure the BV electrical curve (breakdown curve). Based on the leakage current data obtained from the test, the quality of the field plate electrode 8 and the leakage current path can be monitored, allowing for a more accurate determination of the main leakage current source of the first gallium nitride device 1, confirmation of failure points, and accurate feedback on the electrical performance of the device structure, device reliability, dielectric defects, and defects between dielectric contact surfaces. Degraded devices can be screened out in advance, thereby reducing costs without affecting the use of the first gallium nitride device 1. This effectively solves the problem in the prior art that the performance of the device and the quality of the dielectric cannot be fed back in a timely manner during the manufacturing process of gallium nitride devices.

[0064] In some embodiments, the first gallium nitride device 1 is an E-HEMT (Enhancement-Mode High Electron Mobility Transistor) device. The E-HEMT device is structurally identical to a normal gallium nitride device. Using an E-HEMT device instead of a real gallium nitride device avoids potential damage issues that might occur when directly testing a real gallium nitride device. Furthermore, the presence of several pads in the leakage current testing device 100 can effectively improve the breakdown voltage of the E-HEMT device. In other embodiments, the E-HEMT device is composed of several gallium nitride devices, also known as cells. The number of cells is determined according to the actual situation and is not limited here.

[0065] like Figure 1 and Figure 2As shown, in some embodiments, cell region A has a first side and a second side, the direction from the first side to the second side is the extension direction of the cell, the drain pad 2 is disposed on the first side of the cell, the source pad 3 and the field pad 4 are both disposed on the second side of the cell, and the projection of the source pad 3 onto the plane where the field pad 4 is located completely coincides with the field pad 4.

[0066] In other embodiments, the source pad 3 and the field pad 4 may be simultaneously disposed on the first side of the cell, and the drain pad 2 may be disposed on the second side of the cell. Alternatively, the source pad 3 and the field pad 4 may be disposed at any other location, and the projection of the source pad 3 onto the plane where the field pad 4 is located may only partially overlap with the field pad 4.

[0067] Specifically, such as Figure 2 As shown, the semiconductor stack 5 includes a substrate 51, a buffer layer 52 disposed on the substrate 51, a first semiconductor layer 53 disposed on the buffer layer 52, and a second semiconductor layer 54 disposed on the first semiconductor layer 53, which are stacked sequentially. The first semiconductor layer 53 and the second semiconductor layer 54 have a heterojunction structure, and the heterojunction between the first semiconductor layer 53 and the second semiconductor layer 54 can form a two-dimensional electron gas (2DEG) with high mobility, high density, and high conductivity. When a voltage is applied to the drain 7 and the source 6, the two-dimensional electron gas can effectively conduct electrons, enabling the first gallium nitride device 1 to have superior performance.

[0068] In one specific embodiment, the substrate 51 is made of materials including, but not limited to, Si, SiC, etc. The first semiconductor layer 53 is made of GaN, and the second semiconductor layer 54 is made of AlGaN. An AlGaN / GaN heterojunction structure is formed between the first semiconductor layer 53 and the second semiconductor layer 54.

[0069] like Figure 2 As shown, in some embodiments, along the direction away from the cell, the source 6 includes a source metal layer 61, a first metal layer M1, and a second metal layer M2 stacked together, and the drain 7 includes a drain metal layer 71, a first metal layer M1, and a second metal layer M2 stacked together. The first metal layer M1 of the source 6 is disconnected from the first metal layer M1 of the drain 7, and the second metal layer M2 of the source 6 is disconnected from the second metal layer M2 of the drain 7. That is, the first metal layer M1 of the source 6 and the first metal layer M1 of the drain 7 are the same metal layer, but are spaced apart from each other, and the second metal layer M2 of the source 6 and the second metal layer M2 of the drain 7 are the same metal layer, but are spaced apart from each other.

[0070] The field electrode 8 includes a field metal layer M3, and the field pad 4 includes a field metal layer M3. The field metal layer M3 of the field electrode 8 and the field metal layer M3 of the field pad 4 are connected and disposed in communication. That is, the field metal layer M3 of the field electrode 8 and the field metal layer M3 of the field pad 4 are the same metal layer. However, the field metal layer M3 of the field electrode 8 is located in cell region A, and the field metal layer M3 of the field pad 4 is located outside cell region A. The field electrode 8 and the field metal layer M3 of the field pad 4 are connected and disposed in communication with each other.

[0071] In this embodiment, the field plate pad 4 includes only the field plate metal layer M3 and does not include the first metal layer M1 or the second metal layer M2. The field plate electrode 8 includes only the field plate metal layer M3 and does not include the first metal layer M1 or the second metal layer M2. The field plate metal layer M3 of the field plate pad 4 is connected to the field plate metal layer M3 of the field plate electrode 8 to realize the electrical connection between the field plate pad 4 and the field plate electrode 8.

[0072] In one specific embodiment, the field plate electrode 8 is connected to the field plate pad 4 via a first conductor L1 formed by the field plate metal layer M3. That is, the field plate electrode 8, the first conductor L1, and the field plate pad 4 are formed by the same field plate metal layer M3. In other embodiments, the field plate metal layer M3 of the field plate electrode 8 may also be electrically connected to the field plate metal layer M3 of the field plate pad 4 in other ways.

[0073] In some embodiments, the source pad 3 includes a second metal layer M2. The second metal layer M2 of the source 6 is connected to the second metal layer M2 of the source pad 3. The second metal layer M2 of the drain 7 is disconnected from the second metal layer M2 of the source pad 3. That is, the second metal layer M2 of the source pad 3, the second metal layer M2 of the source 6, and the second metal layer M2 of the drain 7 are all the same metal layer. However, the second metal layer M2 of the source pad 3 is connected to the second metal layer M2 of the source 6, while the second metal layer M2 of the drain 7 is disconnected from the second metal layer M2 of the source pad 3 and the second metal layer M2 of the source 6.

[0074] In one specific embodiment, the source electrode 6 is connected to the source electrode pad 3 via a second conductor L2 formed by the second metal layer M2. That is, the second metal layer M2 of the source electrode 6, the second conductor L2, and the second metal layer M2 of the source electrode pad 3 are formed from the same metal layer. Figure 1 As shown, the first conductor L1 and the second conductor L2 are both located on the same side of cell region A, and the projections of the first conductor L1 and the second conductor L2 on the plane where the field plate pad 4 is located are spaced apart. In other embodiments, the source electrode 6 can also be electrically connected to the source pad 3 through other metal layers, conductors, or other means.

[0075] In some embodiments, the drain pad 2 includes a first metal layer M1. The first metal layer M1 of the drain 7 is connected to the first metal layer M1 of the drain pad 2, and the first metal layer M1 of the source 6 is disconnected from the first metal layer M1 of the drain pad 2. That is, the first metal layer M1 of the drain pad 2, the first metal layer M1 of the drain 7, and the first metal layer M1 of the source 6 are the same metal layer, except that the first metal layer M1 of the drain pad 2 is located outside the cell region A, while the first metal layer M1 of the drain 7 and the first metal layer M1 of the source 6 are located inside the cell region A and are separated from each other. The first metal layer M1 of the drain 7 and the first metal layer M1 of the drain pad 2 are connected to each other.

[0076] In one specific embodiment, the drain 7 is connected to the drain pad 2 via a third conductor L3 formed by the first metal layer M1; that is, the first metal layer M1 of the drain 7, the third conductor L3, and the first metal layer M1 of the drain pad 2 are all formed by the same metal layer. Figure 1 As shown, the third conductor L3 is located on the first side of cell region A, and the first conductor L1 and the second conductor L2 are both located on the second side of cell region A. In other embodiments, the first metal layer M1 of the drain electrode 7 can also be electrically connected to the first metal layer M1 of the drain pad 2 via other conductors or methods.

[0077] Specifically, the source metal layer 61 has a 5-ohm contact with the semiconductor stack, and the drain metal layer 71 has a 5-ohm contact with the semiconductor stack. In some embodiments, the source metal layer 61 can be any element, alloy, or compound of Ti, Al, Ni, Au, and Ta, and the drain metal layer 71 can be any element, alloy, or compound of Ti, Al, Ni, Au, and Ta. The field plate metal layer M3 can be any element, alloy, or compound of Ti, Al, Ni, Au, and Ta, and the first metal layer M1 and the second metal layer M2 can also be any element, alloy, or compound of Ti, Al, Ni, Au, and Ta.

[0078] Since the source pad 3 and the field pad 4 are located on the same side of the cell, and the projection of the source pad 3 onto the plane containing the field pad 4 at least partially coincides with the field pad 4, therefore, as Figure 2 As shown, an insulating dielectric layer 9 is provided between the field pad 4 and the source pad 3 to ensure that the source pad 3 and the field pad 4 are mutually insulated, thereby preventing the source pad 3 and the field pad 4 from interfering with each other during testing.

[0079] In some implementations, such as Figure 2As shown, the source pad 3 further includes a first metal layer M1, and the drain pad 2 further includes a second metal layer M2 and a field plate metal layer M3. That is, the source pad 3 includes a first metal layer M1 and a second metal layer M2 stacked sequentially, and the second metal layer M2 of the source pad 3 is connected to the second metal layer M2 of the source 6. The drain pad 2 includes a field plate metal layer M3, a first metal layer M1, and a field plate metal layer M3 stacked sequentially, and the first metal layer M1 of the drain pad 2 is connected to the first metal layer M1 of the drain 7.

[0080] In other embodiments, the source pad 3 may include only the second metal layer M2 without the first metal layer M1, and the drain pad 2 may include only the first metal layer M1, or it may include both the first metal layer M1 and the field metal layer M3 without the second metal layer M2. Alternatively, the drain pad 2 may include both the first metal layer M1 and the second metal layer M2 without the field metal layer M3. The design can be customized as needed, as long as the second metal layer M2 of the source pad 3 is interconnected with the second metal layer M2 of the source 6 to achieve electrical connection between the source pad 3 and the source 6, and the first metal layer M1 of the drain pad 2 is interconnected with the first metal layer M1 of the drain 7 to achieve electrical connection between the drain pad 2 and the drain 7.

[0081] See Figure 1 and Figure 2 The leakage current testing device 100 also includes a gate 10 and a gate pad 11. The gate 10 is located in the cell region A and is disposed between the source electrode 6 and the field plate electrode 8. The field plate electrode 8 is disposed between the gate 10 and the drain electrode 7. The gate pad 11 is disposed outside the cell region A and is electrically connected to the gate 10 of each cell.

[0082] like Figure 2 As shown, in some embodiments, the gate pad 11 is located on the second side of cell region A, that is, the gate pad 11, the source pad 3, and the field pad 4 are located on the same side of cell region A, and the gate pad 11, the source pad 3, and the field pad 4 are all spaced apart. In other embodiments, the gate pad 11 may also be located at any position outside cell region A.

[0083] like Figure 2 As shown, in some embodiments, both the gate 10 and the gate pad 11 include a field metal layer M3. The field metal layer M3 of the gate 10 is connected to the field metal layer M3 of the gate pad 11. The field metal layer M3 of the gate 10 is disconnected from the field metal layer M3 of the field electrode 8. The field metal layer M3 of the gate pad 11 is disconnected from the field metal layer M3 of the field pad 4 and the field metal layer M3 of the field electrode 8. That is, the field metal layer M3 of the gate 10, the field metal layer M3 of the gate pad 11, the field metal layer M3 of the field electrode 8, and the field metal layer M3 of the field pad 4 are all the same metal layer.

[0084] In one embodiment, the gate 10 can be connected to the gate pad 11 via another conductor formed by the field metal layer M3. In other embodiments, the gate 10 can also be electrically connected to the field metal layer M3 of the gate pad 11 in other ways.

[0085] In other embodiments, the gate pad 11 may further include a first metal layer M1 and / or a second metal layer M2. That is, the gate pad 11 may include a field plate metal layer M3, a first metal layer M1 and a second metal layer M2 stacked sequentially, or it may only include a field plate metal layer M3 and a first metal layer M1 stacked, or it may only include a field plate metal layer M3 and a second metal layer M2 stacked, or it may only include a field plate metal layer M3. It can be designed as needed, as long as the field plate metal layer M3 of the gate pad 11 and the field plate metal layer M3 of the gate 10 are interconnected to achieve electrical connection between the gate 10 and the gate pad 11.

[0086] In some embodiments, a capping layer (not shown) may be provided on the side of the field plate metal layer M3 of the gate 10 near the semiconductor stack 5. The capping layer may be a P-GaN layer, which can improve the energy band at the AlGaN / GaN heterojunction interface.

[0087] In some implementations, such as Figure 1 As shown, drain pad 2 is connected to the drains 7 in each cell of cell region A, gate pad 11 is connected to the gates 10 in each cell of cell region A, and field plate pad 4 is connected to the field plate electrodes 8 in each cell. By converging the drains 7, gates 10, and field plate electrodes 8 from multiple cells and connecting them to the corresponding pads, the structure can be simplified and the cost reduced.

[0088] See Figure 2 In some embodiments, each cell also includes a passivation layer 12 disposed on the semiconductor stack 5. The passivation layer 12 is used to insulate the source 6, gate 10, field plate electrode 8 and drain 7 in the cell region A to avoid mutual interference.

[0089] In some implementations, such as Figure 2As shown, the passivation layer 12 includes a first passivation layer 121, a second passivation layer 122, and a third passivation layer 123. The first passivation layer 121 is disposed on the surface of the semiconductor stack 5 near the gate 10 and located between the field electrode 8 and the drain metal layer 71, and the first passivation layer 121 is in direct contact with the AlGaN surface. The second passivation layer 122 is disposed on the side of the gate 10 away from the semiconductor stack 5 and covers the gate 10, the field electrode 8, the first passivation layer 121, and the semiconductor stack 5, and the second passivation layer 122 is located between the source 6 and the drain 7. The third passivation layer 123 covers the side of the second passivation layer 122 away from the semiconductor stack 5 and is located between the source 6 and the drain 7. The main constituent elements of the first passivation layer 121, and / or the second passivation layer 122, and / or the third passivation layer 123 include any one or more of Si, O, Al, and N.

[0090] In one specific implementation, such as Figure 2 As shown, the field plate electrode 8 includes a body portion 81 and an overlapping portion 82 that are connected to each other. The body portion 81 is disposed on the surface of the semiconductor stack 5 near the gate 10 and the side of the body portion 81 is in contact with the side of the first passivation layer 121. The overlapping portion 82 partially covers the surface of the first passivation layer 121 away from the semiconductor stack 5.

[0091] In the embodiments of this application, the leakage current testing device 100 provided in this application is used to perform BV electrical curve (breakdown curve) testing on the first gallium nitride device 1 during the manufacturing process of the first gallium nitride device 1 by applying voltage to the field plate pad 4 and the drain pad 2 and using a testing instrument, such as a B1500 tester. Based on the test results or leakage current data, such as the magnitude of the leakage current, the quality of the field plate electrode 8 and the leakage current channel can be monitored, and the main leakage source of the first gallium nitride device 1 can be more accurately determined. The quality and defects of the first passivation layer 121 and the contact surface between the first passivation layer 121 and AlGaN can be monitored to confirm the failure point. For example, when performing BV electrical curve testing on the first gallium nitride device 1 using a B1500 tester, the voltage is limited to within 200V during the test, and the normal current during the test is in the nA level. If the leakage current is large, the current value will reach the mA level or even directly cause breakdown.

[0092] The above-described configuration allows for accurate feedback on the electrical performance of the device structure, device reliability, dielectric defects, and defects between dielectric contact surfaces. Furthermore, the design of the field plate electrode 8 can be integrated into the E-HEMT device without affecting the use of the first gallium nitride device 1. Utilizing the field plate electrode 8 design, process deficiencies can be detected early, allowing for the early screening of degraded devices, thereby reducing costs and effectively solving the problem of timely feedback on device performance and dielectric quality in the existing gallium nitride device manufacturing process. In this embodiment, since the E-HEMT device and the normal gallium nitride device are structurally identical, leakage current data can be obtained from the test pattern monitoring, allowing for more accurate identification of the main leakage sources and cost savings.

[0093] See Figures 3 to 4 , Figure 3 This is a flowchart illustrating the first embodiment of the leakage current testing method provided in this application. Figure 4 This is a flowchart illustrating the second embodiment of the leakage current testing method provided in this application.

[0094] See Figure 3 This application also provides a leakage current testing method, which can be used to detect the leakage current of a first gallium nitride device 1. Specifically, the leakage current testing method includes:

[0095] S1A: Obtain the first gallium nitride preform.

[0096] Specifically, a first gallium nitride preform is obtained, which includes a cell region A, in which multiple cells are disposed. Each cell includes a semiconductor stack 5 and a source electrode 6 and a drain electrode 7 disposed at intervals on one side of the semiconductor stack 5. The source electrode 6 includes a source metal layer 61, and the drain electrode 7 includes a drain metal layer 71.

[0097] Specifically, the semiconductor stack 5 includes a substrate 51, a buffer layer 52 disposed on the substrate 51, a first semiconductor layer 53 disposed on the buffer layer 52, and a second semiconductor layer 54 disposed on the first semiconductor layer 53, which are stacked sequentially. The first semiconductor layer 53 and the second semiconductor layer 54 have a heterojunction structure, and the heterojunction between the first semiconductor layer 53 and the second semiconductor layer 54 can form a two-dimensional electron gas (2DEG) with high mobility, high density, and high conductivity. When a voltage is applied to the drain 7 and the source 6, the two-dimensional electron gas can effectively conduct electrons, enabling the first gallium nitride device 1 to have superior performance.

[0098] In one specific embodiment, the substrate 51 is made of materials including, but not limited to, Si, SiC, etc. The first semiconductor layer 53 is made of GaN, and the second semiconductor layer 54 is made of AlGaN. An AlGaN / GaN heterojunction structure is formed between the first semiconductor layer 53 and the second semiconductor layer 54.

[0099] The source metal layer 61 is in 5-ohm contact with the semiconductor stack, and the drain metal layer 71 is in 5-ohm contact with the semiconductor stack. In some embodiments, the source metal layer 61 can be any element, alloy or compound of Ti, Al, Ni, Au and Ta, and the drain metal layer 71 can be any element, alloy or compound of Ti, Al, Ni, Au and Ta.

[0100] S2A: A field plate electrode 8 and a field plate pad 4 are fabricated on one side of the first gallium nitride preform where a source metal layer 61 and a drain metal layer 71 are provided. The field plate electrode 8 and the field plate pad 4 are connected.

[0101] Specifically, a field plate electrode 8 and a field plate pad 4 are fabricated on one side of the first gallium nitride preform where the source metal layer 61 and the drain metal layer 71 are provided, wherein the field plate electrode 8 and the field plate pad 4 are interconnected.

[0102] Specifically, in some embodiments, step S2, which involves fabricating a field electrode 8 and a field pad 4 on one side of the first gallium nitride preform where the source metal layer 61 and the drain metal layer 71 are disposed, and the field electrode 8 and the field pad 4 are connected, includes:

[0103] A field plate metal layer M3 is fabricated on one side of the first gallium nitride preform where the source metal layer 61 and the drain metal layer 71 are provided, forming a field plate electrode 8 and a field plate pad 4. The field plate electrode 8 and the field plate pad 4 are connected through a first wire L1 formed by the field plate metal layer M3.

[0104] Specifically, a field plate metal layer M3 can be deposited on one side of the first gallium nitride preform where the source metal layer 61 and drain metal layer 71 are formed, using processes such as evaporation or sputtering. The field plate metal layer M3 is then patterned to form a field plate electrode 8 between the source metal layer 61 and drain metal layer 71 within the cell region A. The field plate electrode 8 is in direct contact with the second semiconductor layer 54 of the semiconductor stack 5. A field plate pad 4 is formed outside the cell region A, and a first conductive line L1 connecting the field plate pad 4 and the field plate electrode 8 is formed, allowing the field plate electrode 8 and the field plate pad 4 to be connected through the first conductive line L1 formed by the field plate metal layer M3. The material of the field plate metal layer M3 can be any element, alloy, or compound of Ti, Al, Ni, Au, and Ta.

[0105] In some embodiments, each cell of the first gallium nitride preform further includes a passivation layer 12, and the leakage current testing method further includes, prior to the fabrication of the field electrode 8 and the field pad 4 described in step S2A:

[0106] A first passivation layer 121 is formed on one side of the first gallium nitride preform where the source metal layer 61 and the drain metal layer 71 are disposed. The first passivation layer 121 is located between the source metal layer 61 and the drain metal layer 71.

[0107] Specifically, the first passivation layer 121 can be deposited using any one of atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), and ion-enhanced chemical vapor deposition (PECVD), such that the first passivation layer 121 is located between the source metal layer 61 and the drain metal layer 71 and is in contact with the surface of the second semiconductor layer 54, i.e., the AlGaN layer, of the semiconductor stack 5, with the first passivation layer 121 and the source metal layer 61 spaced apart.

[0108] In some embodiments, the field plate electrode 8 formed by the field plate metal layer M3 includes a body portion 81 and an overlap portion 82 connected to each other. The body portion 81 is disposed on the surface of the semiconductor stack 5 near the source metal layer 61 and the side of the body portion 81 is in contact with the side of the first passivation layer 121. The overlap portion 82 partially covers the surface of the first passivation layer 121 away from the semiconductor stack 5.

[0109] S3A: On the side where the first gallium nitride preform has a source metal layer 61 and a drain metal layer 71, the source 6, drain 7 and drain pad 2 are fabricated, and the drain 7 and drain pad 2 are connected.

[0110] Specifically, after the field plate electrode 8 and field plate pad 4 are fabricated in step S2A, the source electrode 6, drain electrode 7 and drain pad 2 are fabricated on the side of the first gallium nitride preform where the source metal layer 61 and drain metal layer 71 are provided, and the drain electrode 7 and drain pad 2 are connected.

[0111] Specifically, in some embodiments, step S3A, which involves further fabricating the source 6, drain 7, and drain pad 2 on the side of the first gallium nitride preform where the source metal layer 61 and drain metal layer 71 are provided, and the drain 7 is connected to the drain pad 2, includes:

[0112] A first metal layer M1 is formed on the surface of the first gallium nitride preform where the field plate electrode 8 is located, forming a source electrode 6, a drain electrode 7, and a drain pad 2. The drain electrode 7 and the drain pad 2 are connected through a third conductor L3 formed by the first metal layer M1.

[0113] Specifically, a first metal layer M1 can be deposited on the surface of the first gallium nitride preform where the field electrode 8 is located using processes such as vapor deposition or sputtering. The first metal layer M1 is then patterned so that the first metal layer M1 is formed on the source metal layer 61 and drain metal layer 71 within the cell region A, as well as outside the cell region A. The first metal layer M1 outside the cell region A forms the drain pad 2. The first metal layer M1 on the source metal layer 61 and the first metal layer M1 on the drain metal layer 71 are spaced apart and disconnected. The first metal layer M1 outside the cell region A, i.e., the drain pad 2, is disconnected from the first metal layer M1 on the source metal layer 61. A third conductor L3 is formed between the first metal layer M1 outside the cell region A, i.e., the drain pad 2, and the first metal layer M1 on the drain metal layer 71. The third conductor L3 is also formed by the first metal layer M1.

[0114] A source metal layer 61 and a first metal layer M1 formed on the source metal layer 61 are stacked together to form a source electrode 6, that is, the source electrode 6 includes the stacked source metal layer 61 and the first metal layer M1; a drain metal layer 71 and a first metal layer M1 formed on the drain metal layer 71 are stacked together to form a drain electrode 7, the drain electrode 7 includes the stacked drain metal layer 71 and the first metal layer M1, and the drain pad 2 includes the first metal layer M1. The material of the first metal layer M1 can be any element, alloy, or compound of Ti, Al, Ni, Au, or Ta.

[0115] In other embodiments, the first metal layer M1 of the drain 7, the first metal layer M1 of the source 6, and the first metal layer M1 of the drain pad 2 may not be formed using the same metal layer. The drain pad 2 and the drain 7 may not be connected by the third conductor L3 formed using the first metal layer M1. They can be connected by other conductors or methods, as long as the source 6 and the drain 7 are spaced apart and the drain 7 and the drain pad 2 can be electrically connected.

[0116] S4A: Apply voltage to drain pad 2 and field pad 4 to perform leakage current test.

[0117] Specifically, voltage is applied to the drain pad 2 and the field plate pad 4, and a testing instrument, such as a B1500 tester, is used to perform BV electrical curve analysis on the first gallium nitride preform. Based on the test results or leakage current data, such as the magnitude of the leakage current, the quality of the field plate electrode 8 and the leakage path can be monitored, allowing for a more accurate identification of the main leakage source of the first gallium nitride device 1. The quality and defects of the first passivation layer 121 and the contact surface between the first passivation layer 121 and AlGaN can also be monitored to confirm the failure point. For example, when using a B1500 tester to perform BV electrical curve analysis on the first gallium nitride preform, the voltage is limited to within 200V, and the normal current during testing is in the nA range. If the leakage current is large, the current value will reach the mA level or even lead to direct breakdown.

[0118] The above method can accurately reflect the electrical performance of the device structure, the reliability of the device, dielectric defects, and defects between dielectric contact surfaces. Utilizing the design of the field plate electrode 8, after fabricating the field plate electrode 8, drain 7, field plate pad 4, and drain pad 2, the field plate pad 4 is connected to the field plate electrode 8, and the drain pad 2 is connected to the drain 7. By applying a voltage between the field plate electrode 8 and the drain 7, defects in the first passivation layer 121 and defects at the contact surface between the first passivation layer 121 and AlGaN can be monitored in advance. This allows for early detection of process deficiencies and early screening of aging devices. It can effectively solve the problem of the inability to timely reflect the performance of the device and the quality of the dielectric in the existing gallium nitride device manufacturing process, thereby reducing costs.

[0119] See Figure 4 This application also provides another leakage current testing method, which can be used to detect the leakage current of the first gallium nitride device 1 and to fabricate a device as shown in the figure. Figure 1 The leakage current testing device 100 is shown. Specifically, the leakage current testing method includes:

[0120] S1B: Acquire the first gallium nitride preform.

[0121] Specifically, the steps S1A are the same as those in the first embodiment of the leakage current testing method and can achieve the same or similar technical effects, so they will not be described again.

[0122] S2B: A field plate electrode 8 and a field plate pad 4 are fabricated on one side of the first gallium nitride preform where the source metal layer 61 and the drain metal layer 71 are provided. The field plate electrode 8 and the field plate pad 4 are connected.

[0123] Specifically, the steps S2A are the same as those in the first embodiment of the leakage current testing method and can achieve the same or similar technical effects, so they will not be described again.

[0124] S3B: After the field board pad 4 is fabricated, before fabricating the drain 7 and drain pad 2 that are connected, an insulating dielectric layer 9 is fabricated on the surface of the field board pad 4.

[0125] Specifically, an insulating dielectric layer 9 is deposited on one side of the field pad 4 using any one of the following methods: atomic layer deposition, low-pressure chemical vapor deposition, physical vapor deposition, and ion-enhanced chemical vapor deposition. This insulating dielectric layer 9 covers the surface of the field metal layer M3 outside the field pad 4, i.e., the cell region A. By preparing the insulating dielectric layer 9 on the surface of the field pad 4, the problem of contact between the source pad 3 and the field pad 4 during subsequent fabrication processes, which could affect test results, can be avoided.

[0126] S4B: On the side where the first gallium nitride preform has a source metal layer 61 and a drain metal layer 71, the source 6, drain 7 and drain pad 2 are fabricated, and the drain 7 and drain pad 2 are connected.

[0127] Specifically, the steps S3A of the leakage current testing method are the same as those in the first embodiment and can achieve the same or similar technical effects, so they will not be described again.

[0128] S5B: Apply voltage to drain pad 2 and field pad 4 to perform leakage current test.

[0129] Specifically, the steps S4A of the first embodiment of the leakage current testing method are the same and can achieve the same or similar technical effects, and will not be described again.

[0130] S6B: After performing the leakage test, fabricate source pad 3 and continue to fabricate source 6 and drain 7. Source 6 is connected to source pad 3.

[0131] Specifically, after performing a leakage current test, a source pad 3 is fabricated outside cell region A, and a source electrode 6 and a drain electrode 7 are fabricated inside cell region A, so that the source electrode 6 and the source pad 3 are connected. The source pad 3 and the field pad 4 are located on the same side of the cell, and the projection of the source pad 3 onto the plane of the field pad 4 at least partially coincides with the field pad 4. An insulating dielectric layer 9 is located between the field pad 4 and the source pad 3 to insulate them. In some embodiments, the projection of the source pad 3 onto the plane of the field pad 4 may completely coincide with the field pad 4, or it may only partially coincide.

[0132] Specifically, in one embodiment, step S6B, after performing the leakage current test, involves fabricating the source pad 3 and continuing to fabricate the source 6 and drain 7, with the source 6 connected to the source pad 3. This step includes:

[0133] A second metal layer M2 is formed on the surface of the first gallium nitride preform where a first metal layer M1 is provided, forming a source electrode 6, a drain electrode 7, and a source electrode pad 3. The source electrode 6 and the source electrode pad 3 are connected through a second conductor L2 formed by the first metal layer M1.

[0134] Specifically, a second metal layer M2 can be deposited on the surface of the first gallium nitride preform where the first metal layer M1 is located using processes such as evaporation or sputtering. The second metal layer M2 is then patterned so that the second metal layer M2 is formed on the first metal layer M1 of the source electrode 6 and the first metal layer M1 of the drain electrode 7 within cell region A, as well as on the insulating dielectric layer 9 outside cell region A. Simultaneously, a second conductive line L2 is formed connecting the first metal layer M1 of the source electrode 6 and the second metal layer M2 on the insulating dielectric layer 9. The second metal layer M2 on the first metal layer M1 of the source electrode 6 and the second metal layer M2 on the first metal layer M1 of the drain electrode 7 within cell region A are spaced apart. The source metal layer 61 and the first metal layer M1 and the second metal layer M2 disposed thereon together form the source electrode 6, and the drain metal layer 71 and the first metal layer M1 and the second metal layer M2 disposed thereon together form the drain electrode 7. The second metal layer M2 on the insulating dielectric layer 9 forms the source pad 3, and the source pad 3 is connected to the second metal layer M2 of the source 6 through the second conductor L2.

[0135] In some embodiments, the source pad 3 may also include a first metal layer M1. When the source 6, drain 7, and drain pad 2 are further fabricated on the side of the first gallium nitride preform where the source metal layer 61 and drain metal layer 71 are located, as described in step S4B, the first metal layer M1 may also be deposited simultaneously on the surface of the insulating dielectric layer 9 outside the cell region A. This ensures that the first metal layer M1 on the insulating dielectric layer 9 is disconnected from the first metal layer M1 of the source 6, the first metal layer M1 of the drain 7, and the first metal layer M1 of the drain pad 2, thus avoiding… In step S6B, when the first metal layer M1 on the insulating dielectric layer 9 is used as part of the source electrode 6, and the second metal layer M2 is fabricated on the surface of the first gallium nitride preform where the first metal layer M1 is located, the second metal layer M2 is formed on the first metal layer M1 on the insulating dielectric layer 9 outside the cell region A. The first metal layer M1 and the second metal layer M2 stacked on the insulating dielectric layer 9 together form the source electrode pad 3. The second metal layer M2 of the source electrode pad 3 is connected to the second metal layer M2 of the source electrode 6 through the second wire L2.

[0136] In some embodiments, the drain pad 2 may also include a field metal layer M3 and a second metal layer M2. When fabricating the field electrode 8 and the field pad 4 on the side of the first gallium nitride preform where the source metal layer 61 and drain metal layer 71 are located in step S2B, a field metal layer M3 spaced apart from the field pad 4 can be fabricated outside cell region A simultaneously to serve as part of the drain pad 2. In step S4B, the first metal layer M1 of the drain pad 2 is prepared to cover the surface of the field metal layer M3 of the drain pad 2. The field plate metal layer M3 is spaced apart from the field plate electrode 8 and the field plate pad. In step S6B, when the second metal layer M2 is fabricated on the surface of the first gallium nitride preform where the first metal layer M1 is provided, the second metal layer M2 can be formed simultaneously on the first metal layer M1 of the drain pad 2 outside the cell region A. The drain pad 2 is formed by the stacked field plate metal layer M3, the first metal layer M1 and the second metal layer M2. The first metal layer M1 of the drain pad 2 is connected to the first metal layer M1 of the drain 7 through the third wire L3.

[0137] In other embodiments, the source pad 3 may not include the first metal layer M1, but only the second metal layer M2, and the drain pad 2 may not include the field metal layer M3 and / or the second metal layer M2. For example, the drain pad 2 may include the field metal layer M3 and the first metal layer M1, or the drain pad 2 may include the first metal layer M1 and the second metal layer M2, or the drain pad 2 may only include the first metal layer M1. It can be designed as needed, as long as the second metal layer M2 of the source pad 3 is interconnected with the second metal layer M2 of the source 6 to achieve the electrical connection between the source pad 3 and the source 6, and the first metal layer M1 of the drain pad 2 is interconnected with the first metal layer M1 of the drain 7 to achieve the electrical connection between the drain pad 2 and the drain 7.

[0138] In this embodiment, while fabricating the field plate electrode 8 and field plate pad 4 on the side of the first gallium nitride preform where the source metal layer 61 and drain metal layer 71 are provided, as described in step S2B, the gate 10 and gate pad 11 can also be fabricated. Specifically, when fabricating the field plate metal layer M3 on the side of the first gallium nitride preform where the source metal layer 61 and drain metal layer 71 are provided, the field plate electrode 8 and gate 10 can be formed between the source metal layer 61 and drain metal layer 71, and the gate pad 11 and field plate pad 4 can be formed outside the cell region A. That is, the field plate electrode 8, gate 10, gate pad 11, and field plate pad 4 all include the field plate metal layer M3, but the field plate metal layer M3 of the gate 10 and the gate pad 11 are connected, and the field plate metal layer M3 of the gate 10 and the gate pad 11 are disconnected from the field plate metal layer M3 of the field plate electrode 8 and the field plate pad 4.

[0139] In some embodiments, before fabricating the gate 10 and gate pad 11, a P-type nitride layer (not shown), such as a P-GaN layer, may be deposited on the surface of the semiconductor stack 5. The P-type nitride is then etched using dry or wet etching techniques to form a capping layer, determining the location of the gate 10 in the fabricated E-HEMT device. An ion implantation process is then used to determine the active region of the E-HEMT device. After fabricating the gate 10, a field plate metal layer M3 covers the surface of the capping layer away from the semiconductor stack 5.

[0140] In this embodiment, before fabricating the first metal layer M1 in step S5B, a second passivation layer 122 needs to be deposited, such that the second passivation layer 122 is located on the side of the gate 10 away from the semiconductor stack 5 and covers the gate 10, the field electrode 8, the first passivation layer 121, and the semiconductor stack 5. The second passivation layer 122 is located between the source 6 and the drain 7. Before fabricating the second metal layer M2 in step S6B, a third passivation layer 123 needs to be deposited, such that the third passivation layer 123 covers the side of the second passivation layer 122 away from the semiconductor stack 5 and is located between the source 6 and the drain 7. Specifically, the first passivation layer 121 or the second passivation layer 122 can be deposited using any one of atomic layer deposition, low-pressure chemical vapor deposition, physical vapor deposition, and ion-enhanced chemical vapor deposition. The main constituent elements of the first passivation layer 121, and / or the second passivation layer 122, and / or the third passivation layer 123 include any one or more of Si, O, Al, and N.

[0141] In this embodiment, the BV electrical curve of the first gallium nitride preform can be obtained using the above method. Based on the test results or leakage data, such as the magnitude of the leakage current, the quality of the field plate electrode 8 and the leakage channel can be monitored, and the main leakage source of the first gallium nitride device 1 can be more accurately determined. The quality and defects of the first passivation layer 121 and the contact surface between the first passivation layer 121 and AlGaN can be monitored to identify the failure point. At the same time, it is possible to fabricate a structure such as... Figure 1 The leakage current testing device 100 shown is shown.

[0142] See Figure 5 , Figure 5 This is a schematic diagram of the structure of an embodiment of the semiconductor wafer provided in this application.

[0143] See Figure 5This application also provides a semiconductor wafer 300, which includes multiple device regions 301 and multiple test regions 302. The device regions 301 have a second gallium nitride device 200, which has the same or similar structure to the first gallium nitride device 1 in the above embodiments, and will not be described again here. The test regions 302 can be used for process and fabrication monitoring. The test regions 302 are provided with at least one leakage current testing device 100, which can be used to test whether the second gallium nitride device 200 leaks current and determine the source of leakage. The leakage current testing device 100 can be any of the leakage current testing devices described in the above embodiments.

[0144] The semiconductor wafer 300 provided in this application can not only be used to test whether the first gallium nitride device 1 leaks current and the corresponding leakage condition using the leakage current testing device 100, but also to characterize whether the second gallium nitride device 200 placed within the semiconductor wafer 300 leaks current and the corresponding leakage condition using the leakage current testing device 100. In other words, if the first gallium nitride device 1 does not leak current, it indicates that the second gallium nitride device 200 does not leak current and can be sold; if the first gallium nitride device 1 leaks current, the leakage location / structure can be identified in a timely manner, so as to subsequently improve the leakage current of the second gallium nitride device 200 placed within the semiconductor wafer 300 (process improvement, etc.).

[0145] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A leakage current testing device, characterized in that, include: A first gallium nitride device includes a cell region, wherein a plurality of cells are disposed within the cell region, and each cell includes a semiconductor stack and a source electrode, a drain electrode, and a field plate electrode disposed at intervals on one side of the semiconductor stack. Drain pads are disposed outside the cell region and electrically connected to the drain of each cell; Source pads are disposed outside the cell region and electrically connected to the source of each cell; Field plate pads are disposed outside the cell region and electrically connected to the field plate electrode of each cell; Wherein, the source pad and the field pad are disposed on the same side of the cell; The projection of the source pad onto the plane of the field plate pad partially coincides with the field plate pad; the field plate electrode is connected to the field plate pad via a first conductor; the field plate pad and the first conductor are formed from the same field plate metal layer; or, the projection of the source pad onto the plane of the field plate pad completely coincides with the field plate pad. An insulating dielectric layer is provided between the field plate pad and the source pad, and the source pad is located above the field plate pad.

2. The leakage current testing device according to claim 1, characterized in that, Along a direction away from the cell, the source includes a source metal layer, a first metal layer, and a second metal layer stacked together, and the drain includes a drain metal layer, the first metal layer, and the second metal layer stacked together; the first metal layer and the second metal layer of the source are disconnected from the first metal layer and the second metal layer of the drain. The field plate electrode includes the field plate metal layer, the field plate pad includes the field plate metal layer, and the field plate metal layer of the field plate electrode and the field plate metal layer of the field plate pad are connected in communication. The source pad includes a second metal layer, the second metal layer of the source is connected to the second metal layer of the source pad, and the second metal layer of the drain is disconnected from the second metal layer of the source pad. The drain pad includes the first metal layer, the first metal layer of the drain is connected to the first metal layer of the drain pad, and the first metal layer of the source is disconnected from the first metal layer of the drain pad.

3. The leakage current testing device according to claim 2, characterized in that, The source pad further includes a first metal layer, and the drain pad further includes a second metal layer and the field plate metal layer.

4. The leakage current testing device according to any one of claims 2-3, characterized in that, The leakage current testing device also includes: A gate electrode is disposed between the source electrode and the field plate electrode, and the field plate electrode is disposed between the gate electrode and the drain electrode. A gate pad is disposed outside the cell region and electrically connected to the gate of each cell; Both the gate and the gate pad include the field plate metal layer. The field plate metal layers of the gate and the gate pad are connected in communication. The field plate metal layers of the gate and the gate pad are disconnected from the field plate electrode and the field plate metal layer of the field plate pad.

5. The leakage current testing device according to claim 4, characterized in that, The drain pad is connected to the drain in each cell of the cell region. The gate pad is connected to the gate in each cell of the cell region. The source pads are connected to the source electrodes in each cell of the cell region. The field plate pads are connected to the field plate electrodes in each cell.

6. The leakage current testing device according to claim 5, characterized in that, The field plate electrode is connected to the field plate pad through a first wire formed by the field plate metal layer; The source electrode is connected to the source electrode pad via a second wire formed by the second metal layer; The drain electrode is connected to the drain electrode pad via a third conductor formed from the first metal layer; The projections of the first conductor and the second conductor on the plane where the pads of the field plate are located are spaced apart.

7. The leakage current testing device according to claim 4, characterized in that, Each of the cells further includes: A passivation layer disposed on the semiconductor stack is used to insulate the source, the gate, the field plate electrode and the drain in the cell region.

8. The leakage current testing device according to claim 1, characterized in that, The semiconductor stack includes a substrate, a buffer layer disposed on the substrate, a first semiconductor layer disposed on the buffer layer, and a second semiconductor layer disposed on the first semiconductor layer, wherein a heterojunction structure is formed between the first semiconductor layer and the second semiconductor layer.

9. A semiconductor wafer, characterized in that, include: Multiple device regions, each device region having a second gallium nitride device; Multiple test areas are provided, each test area is equipped with at least one leakage current testing device, the leakage current testing device being the leakage current testing device as described in any one of claims 1-8, the leakage current testing device being used to test whether the second gallium nitride device leaks current and to determine the source of leakage current.

10. A leakage current testing method, characterized in that, include: Obtain the first gallium nitride preform; The first gallium nitride preform includes: a cell region, wherein a plurality of cells are disposed in the cell region, and each cell includes a semiconductor stack and a source and a drain disposed at intervals on one side of the semiconductor stack; the source includes a source metal layer and the drain includes a drain metal layer; A field plate electrode and a field plate pad are fabricated on one side of the first gallium nitride preform where the source metal layer and the drain metal layer are provided, and the field plate electrode and the field plate pad are connected in communication. On the side of the first gallium nitride preform where the source metal layer and the drain metal layer are provided, the source, the drain and the drain pad are further fabricated, and the drain and the drain pad are connected in communication. A voltage is applied to the drain pad and the field plate pad to perform a leakage current test; The leakage current testing method further includes: After the field plate pads are fabricated, and before the drain electrode and the drain pads are fabricated, an insulating dielectric layer is fabricated on the surface of the field plate pads. After performing the leakage current test, the source pad is fabricated and the source and drain are fabricated, with the source and the source pad connected in a manner. The source pad and the field pad are located on the same side of the cell, and the projection of the source pad onto the plane where the field pad is located at least partially coincides with the field pad.

11. The leakage current testing method according to claim 10, characterized in that, The step of fabricating a field plate electrode and a field plate pad on one side of the first gallium nitride preform where the source metal layer and the drain metal layer are disposed, wherein the field plate electrode and the field plate pad are connected in communication, includes: A field plate metal layer is fabricated on one side of the first gallium nitride preform where the source metal layer and the drain metal layer are provided, forming the field plate electrode and the field plate pad. The field plate electrode and the field plate pad are connected through a first wire formed by the field plate metal layer. The step of continuing to fabricate the source, the drain, and the drain pad on one side of the first gallium nitride preform where the source metal layer and the drain metal layer are provided, wherein the drain and the drain pad are connected in communication, includes: A first metal layer is formed on the surface of the first gallium nitride preform where a field plate electrode is provided, forming the source, the drain and the drain pad, and the drain and the drain pad are connected through a third wire formed by the first metal layer; After performing a leakage current test, the steps of fabricating the source pad and then fabricating the source and drain, wherein the source and the source pad are connected in a manner including: A second metal layer is formed on the surface of the first gallium nitride preform where a first metal layer is provided, forming the source, the drain, and the source pad. The source and the source pad are connected through a second wire formed by the second metal layer.

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