Data storage device, data storage system and data collating method used

Abstract

The application discloses a data storage device, a data storage system and a data arrangement method used by the data storage device. The data storage device comprises a memory controller. The memory controller is connected with a host system in communication. The memory controller is used for: acquiring parameter information of target data according to a first instruction generated by the host system, wherein the parameter information comprises an original logical address of the target data, a target logical address and a data size; acquiring the target data according to the original logical address and storing the target data into a target physical address corresponding to the target logical address; and generating and sending a second instruction to the host system to indicate that the first instruction is executed. In this way, the I / O times of the data storage system in executing the data arrangement operation are reduced, the data arrangement operation is completed by the memory controller, and the efficiency of the data arrangement is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a data management technology, in particular to a data storage device configured with a non-volatile memory, a data storage system and a data arrangement method used thereby. BACKGROUND

[0002] Non-volatile memory refers to computer storage whose stored data will not disappear when the current is cut off, and has the advantages of data non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] At present, when performing file system management (such as data arrangement operation) on a storage device, data reading, data writing back, LBA (Logic Block Address) modification and other operations need to be realized through a host system, which will occupy a lot of I / O time, so that the host system cannot interact with the device during this period.

[0004] Therefore, there is an urgent need for a data storage system, a memory controller and a data arrangement method used thereby to solve the above problems. SUMMARY

[0005] The purpose of the present application is to solve the above problems by reducing the I / O times of the data storage system when performing data arrangement operation, and by the memory controller to complete the data arrangement operation, thereby improving the efficiency of data arrangement.

[0006] One or more embodiments of the present application provide a data storage device, which is communicatively connected to a host system. The data storage device comprises: a rewritable non-volatile memory module comprising a plurality of memory dies, wherein each of the memory dies has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, and the plurality of physical pages correspond to a plurality of physical addresses, respectively; and a memory controller electrically connected to the rewritable non-volatile memory module, wherein the memory controller receives a first instruction from the host system to obtain parameter information of target data, wherein the first instruction is generated by the host system, and the parameter information comprises original logical address, target logical address and data size of the target data; the memory controller acquires the target data according to the original logical address and stores the target data into a target physical address corresponding to the target logical address; and the memory controller generates a second instruction and sends the second instruction to the host system, wherein the second instruction is used to indicate that the data storage device has completed the first instruction.

[0007] In one or more embodiments of the present application, the memory controller obtains a target physical address corresponding to the target logical address via a logical-to-physical address table according to the target logical address; and reads the target data from the target physical address of the rewritable non-volatile memory module.

[0008] In one or more embodiments of the present application, the target read instruction and the target write instruction are wrapped into a general flash memory instruction to generate the first instruction.

[0009] In one or more embodiments of the present application, the first instruction further comprises a logical address replacement flag, the logical replacement flag is used to indicate whether to perform an address replacement operation, the address replacement operation is used to represent replacing the original logical address in the logical-to-physical address table with the target logical address, wherein before performing the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, the memory controller determines whether to perform the address replacement operation according to the logical address replacement flag.

[0010] In one or more embodiments of the present application, the logical address replacement flag comprises a first value and a second value, and the determining whether to perform the address replacement operation according to the logical address replacement flag comprises: if the logical address replacement flag is the first value, the memory controller does not perform the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, and performs the address replacement operation; and if the logical address replacement flag is the second value, the memory controller performs the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, and does not perform the address replacement operation.

[0011] In one or more embodiments of the present application, the operation of replacing the original logical address in the logical-to-physical address table with the target logical address comprises: the memory controller obtains the target physical address corresponding to the target logical address via the logical-to-physical address table according to the target logical address; and the memory controller modifies the logical-to-physical address table to replace the original logical address mapped by the target physical address with the target logical address.

[0012] In one or more embodiments of the present application, wherein the storage device further comprises a buffer memory, and wherein the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address comprises: the memory controller obtaining the original physical address corresponding to the original logical address via the logical-to-physical address table according to the original logical address; the memory controller reading the target data from the original physical address into the buffer memory; the memory controller writing the target data in the buffer memory into the target physical address of the rewritable non-volatile memory module; and the memory controller updating the logical-to-physical address table according to the target logical address and the target physical address.

[0013] In one or more embodiments of the present application, wherein the first instruction further comprises a group tag, and wherein the memory controller determines that the target data belongs to one of a plurality of data of a target data group, a total number of the plurality of data, and a target order of the target data in the target data group according to the group tag; the memory controller allocates a plurality of continuous physical addresses corresponding to the plurality of data for storing the plurality of data according to the target data group and the total number of the plurality of data, wherein a total number of the plurality of physical addresses is equal to the total number of the plurality of data, and the plurality of data of the target data group can be read from the plurality of physical addresses via a sequential read operation; and the memory controller selects the target physical address from the plurality of physical addresses for storing the target data according to the target order.

[0014] In one or more embodiments of the present application, wherein the first instruction further comprises a verification key corresponding to the target data, and wherein the memory controller determines whether the first instruction is legal according to the verification key before performing the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, wherein if the first instruction is determined to be legal, the memory controller performs the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address; and if the first instruction is determined to be illegal, the memory controller does not perform the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, and sends an error message corresponding to the first instruction to the host system.

[0015] One or more embodiments of the present application provide a data storage system, comprising: a data storage device configured with a rewritable non-volatile memory module including a plurality of memory dies, wherein each of the memory dies has a plurality of physical blocks, and each of the physical blocks has a plurality of physical pages corresponding to a plurality of physical addresses, respectively; and a host system communicatively connected to the data storage device. The data storage device receives a first instruction from the host system to obtain parameter information of target data, wherein the first instruction is generated by the host system, and the parameter information includes an original logical address, a target logical address and a data size of the target data. The data storage device obtains the target data according to the original logical address and stores the target data into a target physical address corresponding to the target logical address. The data storage device generates a second instruction and sends the second instruction to the host system, wherein the second instruction is used to indicate the data storage device to complete the first instruction.

[0016] One or more embodiments of the present application provide a data arrangement method, comprising: receiving a first instruction from a host system to obtain parameter information of target data, wherein the first instruction is generated by the host system, and the parameter information includes an original logical address, a target logical address and a data size of the target data; obtaining the target data according to the original logical address and storing the target data into a target physical address corresponding to the target logical address; and generating a second instruction and sending the second instruction to the host system, wherein the second instruction is used to indicate a data storage device to complete the first instruction.

[0017] Based on the above, the data storage device, the data storage system and the data arrangement method provided by the embodiments of the present application can process the data address arrangement operation of the target data corresponding to the first instruction at the storage device end according to the first instruction after receiving the first instruction issued by the host system, and respond to the host system that the first instruction has been completed after completing the data address arrangement operation, so as to reduce the problem of too high I / O times of the target data accessed between the host system and the storage device caused by the data arrangement operation in the prior art, and also greatly avoid the busy state of I / O occupied caused by the host system needing to access / process the address migration of the target data, thereby effectively improving the data arrangement efficiency and work efficiency of the data storage system and the memory controller. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1Block diagram of a data storage system according to an embodiment of the present invention;

[0020] Figure 2 Flowchart of a data organization method according to an embodiment of the present invention;

[0021] Figure 3 Operation diagram of a data storage system according to an embodiment of the present invention;

[0022] Figure 4 Diagram of organization target data of a data storage system according to an embodiment of the present invention;

[0023] Figure 5 Diagram of organization target data of a data storage system according to another embodiment of the present invention;

[0024] Figure 6 Diagram of generating a first instruction according to an embodiment of the present invention;

[0025] Figure 7 Diagram of replacing a logical address of target data by a logical-to-physical address table according to an embodiment of the present invention;

[0026] Figure 8 Diagram of replacing a logical address of target data by a physical-to-logical address table according to an embodiment of the present invention.

[0027] BRIEF DESCRIPTION OF DRAWINGS

[0028] 10: host system

[0029] 20: storage device

[0030] 211: first processor

[0031] 110: second processor

[0032] 120: host memory

[0033] 130: data transfer interface circuitry

[0034] 210: memory controller

[0035] 212: data management circuitry

[0036] 213: memory interface control circuitry

[0037] 214: buffer memory

[0038] 220: re-writable non-volatile memory module

[0039] 230: connection interface circuitry

[0040] S210, S220, S230, S240, S250: flow steps of the data arrangement method

[0041] A41-A46, A51, A61-A63, A71, A72, A81: arrow

[0042] DCI, DCI1, DCI2, DCI3: first instruction

[0043] TB71, TB72: logical to physical address table

[0044] TB81, TB82: physical to logical address table DETAILED DESCRIPTION

[0045] Reference will now be made in detail to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0046] Figure 1 A block diagram of a data storage system according to an embodiment of the present application is shown. Referring to Figure 1 , the data storage system includes a host system 10 and a storage device 20. The host system 10 is, for example, a personal computer, a notebook computer, a server. The host system 10 includes a processor 110 (also referred to as a second processor) and a host memory 120, a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 are coupled to each other by a system bus. In this embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 can be disposed on a host board of the host system 10.

[0047] The storage device 20 (also referred to as a data storage device) includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0048] In this embodiment, the host system 10 is coupled to the storage device 20 via the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0049] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Via the data transmission interface circuit 130, the host board can be coupled to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. In addition, the host board can also be coupled to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. via a system bus.

[0050] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the peripheral component interconnect express (PCI Express) standard. Furthermore, the data transmission interface circuit 130 and the connection interface circuit 230 utilize the non-volatile memory express (NVMe) communication protocol to transmit data.

[0051] In another embodiment, the connection interface circuit 230 can be packaged in a chip with the memory controller 210, or the connection interface circuit 230 can be disposed outside a chip including the memory controller 210.

[0052] In the embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the embodiment, the host memory 120 can be a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like. However, it must be understood that the present application is not limited thereto, and the host memory 120 can also be other suitable memories.

[0053] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type, and perform data writing, reading, erasing, and the like in the rewritable non-volatile memory module 220 according to instructions of the host system 10.

[0054] In more detail, the processor 211 in the memory controller 210 is a hardware with computing capability, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the memory device 20 operates, the control instructions / program codes are executed to perform data writing, reading, erasing, and the like. In addition, in the embodiment, the control instructions / program codes can also be executed to perform data reading operations to implement the data reading method provided by the present application. The control instructions / program codes corresponding to the data reading method can also be implemented as circuit units in a hardware form to implement the data reading method provided by the present application.

[0055] It is worth mentioning that, in the embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a micro-processor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar circuit components, and the present application is not limited thereto.

[0056] In this embodiment, as mentioned above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the components of the memory controller 210 can also be considered as operations performed by the memory controller 210.

[0057] The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is configured to accept instructions from the processor 211 for transferring data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 and the read data is written into the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 (the data can be read from one or more memory cells of the one or more physical units) via the memory interface control circuit 213 and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0058] The memory interface control circuit 213 is configured to accept instructions from the processor 211 for performing write (also referred to as programming), read or erase operations on the rewritable non-volatile memory module 220 in cooperation with the data management circuit 212.

[0059] In addition, data to be written into the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 sends corresponding instruction sequences to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform corresponding operations. For example, the instruction sequences can include write instruction sequences for instructing writing of data, read instruction sequences for instructing reading of data, erase instruction sequences for instructing erasing of data, and corresponding instruction sequences for instructing various memory operations. The instruction sequences can include one or more signals or data on a bus. The signals or data can include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, a physical address, etc. is included.

[0060] In addition, the memory controller 210 establishes a logical to physical address table and a physical to logical address table to record the address mapping relationship between the logical units (e.g., logical blocks, logical pages, or logical columns) and the physical units (e.g., physical erase units / physical blocks, physical pages, physical columns) configured to the rewritable non-volatile memory module 220. In other words, the memory controller 210 can look up the physical unit mapped by a logical unit (e.g., look up the physical page mapped by a logical page; look up the physical address mapped by a logical address) through the logical to physical address table (also referred to as a mapping table), and the memory controller 210 can look up the logical unit mapped by a physical unit (e.g., look up the logical page mapped by a physical page; look up the logical address mapped by a physical address) through the physical to logical address table. However, the technical concept regarding the mapping between the logical address and the physical address described above is a common technical means for those skilled in the art and is not the technical solution to be described by the present application, and will not be described here.

[0061] In an embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is coupled to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216.

[0062] The rewritable non-volatile memory module 220 is coupled to the memory controller 210 (memory interface control circuit 213) and is used to store the data written by the host system 10.

[0063] In the present embodiment, the rewritable non-volatile memory module 220 has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of storage units, also referred to as columns (also referred to as physical columns). The plurality of columns on the same word line forms a physical program unit (also referred to as a physical page). Each physical page corresponds to a physical address to record the location of the data stored in the physical page. In addition, a plurality of physical pages can form a physical block (also referred to as a physical erase unit). Each of the plurality of memory dies of the rewritable non-volatile memory module 220 has a plurality of physical blocks. It should be noted that the present application is not limited to the size of each physical page and logical page.

[0064] Figure 2 Flowchart of the data arrangement method shown according to the embodiment of the present application. Figure 3An operational schematic diagram of a data storage system according to an embodiment of the present application.

[0065] In particular, referring to Figure 2 and Figure 3 , the data arrangement method according to the present application comprises the following steps:

[0066] S210, the memory controller 210 receives a first instruction from the host system 10 to obtain parameter information of target data.

[0067] The first instruction is generated by the host system 10, and the parameter information includes the original logical address, target logical address and data size of the target data.

[0068] For example, as Figure 1 indicated above, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations.

[0069] Specifically, after the host system 10 obtains the target data, the original logical address, target logical address and data size corresponding to the target data, a first instruction corresponding to the target data is generated to instruct the memory controller 210 to complete the data arrangement operation. Further, the first instruction is sent to the memory controller 210.

[0070] In an embodiment, the data arrangement operation is, for example, a disk arrangement operation or a file archive arrangement operation performed by the operating system (OS) of the host system 10. The disk arrangement operation is used to change the data that should be sequentially stored from a fragmented storage state to a sequentially stored state. The file archive arrangement operation is used to copy or move multiple pieces of data belonging to the same directory or file archive to other locations on the disk.

[0071] That is, the disk arrangement operation or the file archive arrangement operation changes multiple pieces of data with read-write correlation stored in multiple non-sequential logical units to multiple sequential logical units.

[0072] S220, the memory controller 210 obtains the target data according to the original logical address and stores the target data in a target physical address corresponding to the target logical address.

[0073] For example, the memory controller 210 completes the data arrangement operation according to the received first instruction.

[0074] S230, the memory controller 210 generates a second instruction and sends the second instruction to the host system 10.

[0075] The second instruction is used to indicate the data storage device 20 to execute the first instruction.

[0076] Thus, by the storage device 20 proposed in the embodiments of the present application, the memory controller 210 performs the data arrangement operation according to the received first instruction, and sends the second instruction to the host system 10 to indicate that the current data arrangement operation is executed after the memory controller 210 executes the first instruction. Thus, the number of I / Os of the data storage system in executing the data arrangement operation can be reduced, and the data arrangement efficiency is improved. It should be noted that in an embodiment, the memory controller 210 can give the corresponding response information to the status query instruction from the host system 10 to indicate that the storage device 20 executes the first instruction.

[0077] Figure 6 The schematic diagram for generating the first instruction according to the embodiments of the present application is shown.

[0078] For example, please refer to Figure 6 In this example, the host system 10 (e.g., the second processor 110) identifies three target data TD1, TD2, TD3 to be arranged due to the execution of the data arrangement operation, which are respectively stored in the logical addresses "LBA101", "LBA103", "LBA107" (also referred to as original logical addresses). In addition, it is assumed that the host system 10 also determines that the three target data TD1-TD3 should be stored in the sequential other three logical addresses "LBA201", "LBA202", "LBA203" (also referred to as target logical addresses) according to the data arrangement operation. In addition, the host system 10 also identifies the data size of each of the three target data TD1-TD3 (for the convenience of description, it is assumed that the data size of each of the three target data TD1-TD3 is one program unit).

[0079] In an embodiment, the host system 10 further sets that the three target data TD1-TD3 belong to the same target data group DG1.

[0080] In the example of Figure 6 In the example of FIG. 6A, the host system 10 generates the target read instruction according to the original logical address "LBA101" and the data size of the target data TD1, generates the target write instruction according to the target logical address "LBA201" and the data size of the target data TD1, and generates the first instruction DCI1 according to the target read instruction and the target write instruction, as shown by the arrow A61.

[0081] In an embodiment, the host system 10 packages the target read instruction and the target write instruction into a Universal Flash Storage (UFS) instruction to generate a first instruction.

[0082] By analogy, as shown by arrow A62, the host system 10 generates a first instruction DCI2 according to the original logical address "LBA 103", the target logical address "LBA 202" and the data size of the target data TD2; as shown by arrow A63, the host system 10 generates a first instruction DCI3 according to the original logical address "LBA 107", the target logical address "LBA 203" and the data size of the target data TD3.

[0083] After the first instructions DCI1-DCI3 are generated, the host system 10 sends (issues) the first instructions DCI1-DCI3 to the storage device 20, so that the storage device 20 performs corresponding arrangement on the stored target data according to the first instructions DCI1-DCI3.

[0084] In this way, by the method of the embodiment, the target read instruction and the target write instruction are packaged into a UFS instruction to generate a first instruction, and then the memory controller 210 can be directly instructed by the first instruction to read data and modify the logical address by itself, so as to finally save I / O resources and improve the efficiency of system file arrangement.

[0085] It is worth mentioning that, in an embodiment, the generated first instruction can further include a grouping mark. The grouping mark is used to record which target data group the corresponding target data belongs to, and is also used to record the order (also referred to as a target order) of the corresponding target data in the target data group.

[0086] That is, after receiving the first instruction containing the grouping mark, the memory controller 210 can determine, according to the grouping mark, that the target data belongs to a target data group and the target order of the target data in the target data group. In addition, the memory controller 210 further specifies a target physical address according to the target data group and the target order, so that multiple target data of the same target data group can be stored in sequential multiple physical addresses, thereby facilitating subsequent sequential reading of the data.

[0087] In this way, by the method proposed in the embodiment, the multiple target physical addresses used to store the multiple target data belonging to the target data group are continuous, so that the multiple target data of the target data group can be continuously read from the multiple target physical addresses through a sequential reading operation.

[0088] Upon receiving the first command, the memory controller 210 parses the received first command to obtain the original logical address, the target logical address and the data size corresponding to the target data. Then, the memory controller 210 moves the target data stored in the rewritable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address. Finally, after the target data is stored to the target physical address, the memory controller 210 generates a second command to respond that the host system 10 has completed the first command.

[0089] By the method proposed in this embodiment, the memory controller 210 obtains the parameter information required by the data consolidation operation based on the received first command, and further completes the first command based on the parameter information, and finally generates a second command to respond that the current data consolidation operation of the host system 10 is completed. In this way, the I / O resources can be saved, the transmission time of the target data from the memory controller 210 to the host system 10 can be saved, and the efficiency of the system file consolidation can be improved.

[0090] Step S220 can be implemented in various ways, and the following is an example.

[0091] In an embodiment, the memory controller 210 uses the buffer memory 214 to temporarily store the target data read from the original physical address, and then writes the target data to the target physical address and updates to the target logical address.

[0092] Figure 4 A schematic diagram of consolidating target data of a data storage system according to an embodiment of the present application. Please refer to Figure 4 In this embodiment, the host system 10 transmits a first command DCI to the storage device 20, as shown by arrow A41. Then, the storage device 20 (e.g., the memory controller 210) parses the received first command DCI to obtain the original logical address, the target logical address and the data size corresponding to the target data.

[0093] Then, the memory controller 210 obtains the original physical address corresponding to the target data by querying the logical-to-physical address table according to the original logical address, as shown by arrow A42. Then, the memory controller 210 reads the target data from the original physical address to the buffer memory 214, as shown by arrow A43. Then, the memory controller 210 writes the target data in the buffer memory 214 to the target physical address, as shown by arrow A44. The memory controller 210 can determine the specific value of the target physical address by itself.

[0094] After the target data is written to the target physical address, the memory controller 210 updates the logical-to-physical address table to map the target logical address corresponding to the target data to the target physical address, as indicated by arrow A45. In one embodiment, the memory controller 210 also updates the physical-to-logical address table accordingly.

[0095] Finally, after the logical-to-physical address table is updated, the memory controller 210 responds to the host system 10 (e.g., sends a corresponding response signal (second command)) that the first command DCI has been executed, as indicated by arrow A46.

[0096] In another embodiment, the memory controller 210 modifies the logical-to-physical address table or the physical-to-logical address table directly to achieve the relocation of the data at the logical address (from the original logical address to the target logical address).

[0097] Figure 5 A flowchart illustrating the relocation of target data according to another embodiment of the present application. Please refer to FIG. 4. Figure 5 In this embodiment, the host system 10 transmits a first command DCI to the storage device 20, as indicated by arrow A41. Then, the storage device 20 (e.g., the memory controller 210) parses the received first command DCI to obtain the original logical address, the target logical address and the data size corresponding to the target data. Then, the memory controller 210 obtains the original physical address corresponding to the target data by querying the logical-to-physical address table according to the original logical address, as indicated by arrow A42.

[0098] Then, the memory controller 210 directly modifies the logical-to-physical address table to write the value of the original physical address to the physical address field mapped by the target logical address so as to map the target logical address to the original physical address, as indicated by arrow A51. In addition, the memory controller 210 deletes the value of the original physical address in the physical address field mapped by the original logical address.

[0099] Finally, after the logical-to-physical address table is updated, the memory controller 210 responds to the host system 10 (e.g., sends a corresponding response signal (second command)) that the first command DCI has been executed, as indicated by arrow A46.

[0100] It is worth mentioning that by the above-mentioned manner, the logical address of the target data can be quickly modified from the original logical address to the target logical address without substantially relocating the target data, thereby avoiding the I / O occupation problem caused by the data relocation operation. In addition, since the modified logical address is based on the first command, the efficiency of the operating system of the host system 10 in accessing the corresponding data will certainly be increased.

[0101] In one embodiment, the memory controller 210 can determine whether to directly update the logical-to-physical address table or the physical-to-logical address table (without moving the physical address where the target data is located) by a specific flag. This specific flag can also be referred to as a logical address replacement flag.

[0102] In one embodiment, the host system 10 can set the logical address replacement flag during the generation of the first instruction to determine which way to use to implement the first instruction.

[0103] In more detail, if the logical address replacement flag is a first value (e.g., 1), the memory controller does not perform the operation of moving the target data stored in the rewritable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address; and

[0104] The memory controller 210 directly replaces the original logical address mapped by the original physical address corresponding to the target data in the logical-to-physical address table with the target logical address, and responds to the host system 10 that the first instruction has been completed.

[0105] Figure 7 A diagram showing the replacement of the logical address of the target data by the logical-to-physical address table according to an embodiment of the present application is shown. Please refer to Figure 7 For example, the first instruction DCI1 is assumed to be parsed by the memory controller 210 and to identify the original logical address "LBA101" and the target logical address "LBA201". In addition, it is further assumed that the first instruction DCI1 has the logical address replacement flag with the first value. Upon determining the logical address replacement flag, the memory controller 210 updates the logical-to-physical address table TB71 to the logical-to-physical address table TB72, as shown by arrow A71, in which the value "PBA123" of the original physical address corresponding to the original logical address "LBA101" is directly moved to the field of the physical address mapped by the target logical address "LBA201" (as shown by arrow A72). It should be noted that in this embodiment, the target data itself is not moved.

[0106] In one embodiment, the memory controller 210 further correspondingly modifies the physical-to-logical address table.

[0107] Figure 8 A diagram showing the replacement of the logical address of the target data by the physical-to-logical address table according to an embodiment of the present application is shown. Please refer to Figure 8 For example, the first instruction DCI1 is assumed to be parsed by the memory controller 210 and to identify the original logical address "LBA101" and the target logical address "LBA201". In addition, it is further assumed that the first instruction DCI1 has the logical address replacement flag with the first value. Upon determining the logical address replacement flag, the memory controller 210 updates the logical-to-physical address table TB71 to the logical-to-physical address table TB72, as shown by arrow A71, in which the value "PBA123" of the original physical address corresponding to the original logical address "LBA101" is directly moved to the field of the physical address mapped by the target logical address "LBA201" (as shown by arrow A72). It should be noted that in this embodiment, the target data itself is not moved. Figure 7For example, the first instruction DCI1, assume that the memory controller 210 parses the first instruction DCI1 and identifies the original logical address "LBA101" and the target logical address "LBA201". Furthermore, assume that the first instruction DCI1 has the first value of the logical address replacement flag. Upon determining the logical address replacement flag, the memory controller 210 updates the physical-to-logical address table TB81 to the physical-to-logical address table TB82 as shown by the arrow A71, where the value "LBA101" corresponding to the original physical address "PBA123" is directly modified to the value "LBA201" of the target logical address, so that the original physical address of the target data is mapped to the target logical address. Note that in this embodiment, the target data itself is not moved.

[0108] On the other hand, if the logical address replacement flag is not the first value (e.g., the second value), the memory controller 210 does not implement the first instruction in the manner described above. Figure 7 、 Figure 8

[0109] In more detail, in one embodiment, if the logical address replacement flag is the second value (e.g., 0), in the operation of moving the target data stored in the rewritable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address, the memory controller 210 obtains the original physical address corresponding to the original logical address of the target data according to the logical-to-physical address table; the memory controller 210 reads the target data from the original physical address to the buffer memory 214; the memory controller 210 writes the target data in the buffer memory 214 to the target physical address of the rewritable non-volatile memory module 220; and the memory controller 210 updates the logical-to-physical address table according to the target logical address and the target physical address (i.e., sets the physical address mapped by the target logical address in the logical-to-physical address table to the target physical address).

[0110] That is, if the logical address replacement flag is the second value, the memory controller 210 implements the first instruction in the manner described above. Figure 4

[0111] ​​Thus, by the grouping marking and the logical address replacement marking of the second value proposed by the embodiments of the present application, the memory controller 210 can set the target physical addresses of the plurality of target data belonging to the same target data group to be in a continuous relationship, so as to substantially enable the plurality of target data belonging to the same target data group to be read by a sequential read operation after being moved to the continuous physical addresses, and to accelerate the read efficiency of the plurality of target data belonging to the same target data group.

[0112] In an embodiment, the host system 10 and the storage device 20 can further perform an authentication procedure to filter out illegal first instructions, so as to ensure the security of data storage.

[0113] In more detail, the produced first instruction further comprises a verification key corresponding to the target data, wherein before performing the operation of moving the target data stored in the rewritable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address, the memory controller 210 determines whether the first instruction is legal according to the verification key.

[0114] If the first instruction is determined to be legal, the memory controller 210 performs the operation of moving the target data stored in the rewritable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address; and if the first instruction is determined to be illegal, the memory controller 210 does not perform the operation of moving the target data stored in the rewritable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address, and sends an error notification corresponding to the first instruction to the host system 10.

[0115] In other words, according to the legal verification key agreed between the legal host system 10 and the storage device 20, the storage device 20 can effectively determine whether the currently received first instruction is from the legal host system 10. For example, if the verification key in the first instruction is not the legal verification key, the storage device 20 can determine that the currently received first instruction is illegal, so as to avoid the logical address or / and the physical address of the target data from being changed due to the illegal first instruction.

[0116] Based on the above, the data storage device, the data storage system and the data arrangement method provided by the embodiments of the present application can, after receiving the first instruction issued by the host system, process the data address arrangement operation of the target data corresponding to the first instruction at the storage device end according to the first instruction, and respond to the host system that the first instruction has been completed after completing the data address arrangement operation, so as to reduce the problem of too high I / O frequency of the target data between the host system and the storage device caused by the data arrangement operation in the prior art, and greatly avoid the busy state of I / O occupation caused by the host system needing to access / process the address migration of the target data, thereby effectively improving the data arrangement efficiency and working efficiency of the data storage system and the memory controller.

[0117] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data storage device, communicatively connected to a host system, characterized in that, include: A rewritable non-volatile memory module includes multiple memory dies, wherein each memory die has multiple physical blocks, each physical block has multiple physical pages, and the multiple physical pages are respectively associated with multiple physical addresses; as well as The memory controller is electrically connected to the rewritable non-volatile memory module, wherein... The memory controller receives a first instruction from the host system to obtain parameter information of the target data, wherein the first instruction is generated by the host system, the first instruction includes a grouping tag, and the parameter information includes the original logical address, the target logical address, and the data size of the target data. The memory controller obtains the target data according to the original logical address and stores the target data into the target entity address corresponding to the target logical address, including: determining that the target data belongs to a target data group according to the grouping mark, allocating multiple consecutive entity addresses to the target data group to store multiple data in the target data group, and storing the target data into the target entity address among the multiple entity addresses, so that the multiple data in the target data group can be read in subsequent sequential read operations; as well as The memory controller generates a second instruction and sends the second instruction to the host system, wherein the second instruction is used to instruct the data storage device to complete the execution of the first instruction.

2. The data storage device according to claim 1, characterized in that, in, The memory controller, based on the original logical address, obtains the original physical address corresponding to the original logical address via a logic-to-physical address table; and The target data is read from the original physical address of the rewritable non-volatile memory module.

3. The data storage device according to claim 1, characterized in that, The target read instruction and the target write instruction are packaged into a general flash memory storage instruction to generate the first instruction.

4. The data storage device according to claim 1, characterized in that, The first instruction further includes a logical address replacement flag, which indicates whether to perform an address replacement operation. The address replacement operation represents replacing the original logical address in the logical-to-entity address table with the target logical address. Before performing the operation of obtaining the target data based on the original logical address and storing the target data into the target entity address corresponding to the target logical address, the memory controller determines whether to perform the address replacement operation based on the logical address replacement flag.

5. The data storage device according to claim 4, characterized in that, The logical address replacement flag includes a first value and a second value. Determining whether to perform the address replacement operation based on the logical address replacement flag includes: If the logical address replacement flag is the first value, the memory controller does not perform the operation of obtaining the target data according to the original logical address and storing the target data into the target entity address corresponding to the target logical address, but instead performs the address replacement operation; and If the logical address replacement flag is the second value, the memory controller performs the operation of obtaining the target data according to the original logical address and storing the target data into the target entity address corresponding to the target logical address, and does not perform the address replacement operation.

6. The data storage device according to claim 4, characterized in that, The operation of replacing the original logical address in the logical-to-entity address table with the target logical address includes: The memory controller obtains the original physical address corresponding to the original logical address through the logic-to-physical address table based on the original logical address; and The memory controller modifies the logic-to-entity address table to replace the original logical address mapped by the original entity address with the target logical address.

7. The data storage device according to claim 4, characterized in that, The storage device further includes a buffer memory, wherein the operation of obtaining the target data according to the original logical address and storing the target data into the target entity address corresponding to the target logical address includes: The memory controller obtains the original physical address corresponding to the original logical address through the logic-to-physical address table based on the original logical address. The memory controller reads the target data from the original entity address into the buffer memory; The memory controller writes the target data in the buffer memory to the target entity address of the rewritable non-volatile memory module; and The memory controller updates the logical-to-physical address table based on the target logical address and the target physical address.

8. The data storage device according to claim 1, characterized in that, The process involves determining that the target data belongs to a target data group based on the grouping marker, allocating consecutive entity addresses to the target data group to store the multiple data items within the target data group, and storing the target data in the target entity addresses, including: The memory controller determines, based on the grouping tag, that the target data belongs to one of the plurality of data in the target data group, the total number of the plurality of data, and the target order of the target data in the target data group; The memory controller allocates consecutive physical addresses corresponding to the target data group and the total number of the multiple data items to store the multiple data items, wherein the total number of the multiple physical addresses is equal to the total number of the multiple data items; and The memory controller selects the target entity address from the plurality of entity addresses to store the target data according to the target order.

9. The data storage device according to claim 1, characterized in that, The first instruction further includes a verification key corresponding to the target data, wherein before performing the operation of obtaining the target data based on the original logical address and storing the target data into the target entity address corresponding to the target logical address, The memory controller determines whether the first instruction is valid based on the verification key, wherein If the first instruction is determined to be valid, the memory controller performs the operation of obtaining the target data according to the original logical address and storing the target data into the target entity address corresponding to the target logical address; as well as If the first instruction is determined to be invalid, the memory controller will not perform the operation of obtaining the target data according to the original logical address and storing the target data into the target entity address corresponding to the target logical address, and will send an error notification corresponding to the first instruction to the host system.

10. A data storage system, characterized in that, include: A data storage device is configured with a rewritable non-volatile memory module, including multiple memory chips, wherein each memory chip has multiple physical blocks, each physical block has multiple physical pages, and the multiple physical pages are respectively associated with multiple physical addresses; as well as The host system is communicatively connected to the data storage device, wherein The data storage device receives a first instruction from the host system to obtain parameter information of the target data, wherein the first instruction is generated by the host system, the first instruction includes a grouping tag, and the parameter information includes the original logical address, the target logical address, and the data size of the target data. The data storage device obtains the target data according to the original logical address and stores the target data into the target entity address corresponding to the target logical address, including: determining that the target data belongs to a target data group according to the grouping mark, allocating multiple consecutive entity addresses to the target data group to store multiple data in the target data group, and storing the target data into the target entity address among the multiple entity addresses, so that the multiple data in the target data group can be read in subsequent sequential read operations; as well as The data storage device generates a second instruction and sends the second instruction to the host system, wherein the second instruction is used to instruct the data storage device to complete the execution of the first instruction.

11. A data processing method, characterized in that, include: The host system receives a first instruction to obtain parameter information of the target data, wherein the first instruction is generated by the host system and the first instruction further includes a grouping tag, and the parameter information includes the original logical address, the target logical address, and the data size of the target data; Obtaining the target data according to the original logical address and storing the target data into the target entity address corresponding to the target logical address includes: determining that the target data belongs to a target data group according to the grouping tag, allocating multiple consecutive entity addresses to the target data group to store multiple data within the target data group, and storing the target data into the target entity address among the multiple entity addresses, so that the multiple data within the target data group can be read subsequently via a sequential read operation; and A second instruction is generated and sent to the host system, wherein the second instruction is used to instruct the data storage device to complete the execution of the first instruction.

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