Screenless testing method and related products of LCD timing control board

Abstract

The present application relates to a screenless testing method for a timing control board of a liquid crystal display screen and related products, the method comprising: a host computer transmits a test file to an image signal generator and an FPGA respectively, the test file carrying multiple groups of original RGB data corresponding to multiple image screens and a display frame rate of the image screen; the FPGA processes the original RGB data carried in the test file to obtain multiple groups of first RGB data with the same data structure as the second RGB data and corresponding to the multiple groups of original RGB data; the image signal generator generates a first image signal corresponding to a target image screen, and periodically sends the first image signal to the timing control board according to the display frame rate; the timing control board outputs a second image signal based on each time the first image signal is received; each time the FPGA receives the second image signal, it parses the second image signal to obtain second RGB data, and compares whether the second RGB data is the same as the first RGB data corresponding to the target image screen.

Description

Technical Field

[0001] The present application relates to a screenless testing method for a timing control board of a liquid crystal display and related products. Background Art

[0002] LCD manufacturers usually entrust third-party circuit board manufacturers to produce the timing controller (TCON) board of the LCD. In order to ensure the yield of the final LCD product, the third-party circuit board manufacturer is often required to perform a series of strict tests on the TCON circuit board before leaving the factory.

[0003] The traditional test method of TCON board requires the actual mounting of LCD screen by test fixture and manual testing, which leads to low test efficiency. In addition, the traditional method requires the use of jumper wires to connect TCON board and LCD screen to realize screen dot. However, the speed of the latest COF communication protocol is mostly above 3Gbps. It is easy to cause over-detection and false detection by jumper wires to realize screen dot, which affects economic benefits. Summary of the invention

[0004] In view of this, the present application proposes a screenless testing method for a timing control board of a liquid crystal display and related products.

[0005] In the first aspect, a screenless test method for a timing control board of a liquid crystal display is proposed, which is applied to a screenless test system including a host computer, an image signal generator and an FPGA. The method includes:

[0006] The host computer transmits a test file to the image signal generator and the FPGA respectively, wherein the test file carries multiple groups of original RGB data corresponding to multiple image screens and the display frame rate of the image screens;

[0007] The FPGA processes the original RGB data carried in the test file to obtain a plurality of groups of first RGB data having the same data structure as the second RGB data described below and corresponding to the plurality of groups of original RGB data respectively;

[0008] The image signal generator generates a first image signal corresponding to a target image screen based on the test file, and periodically sends the first image signal to the timing control board according to the display frame rate, wherein the target image screen is any one of the multiple image screens, and the first image signal carries original RGB data corresponding to the target image screen; wherein the timing control board outputs a second image signal based on each receipt of the first image signal, thereby successively outputting multiple second image signals, and the second image signal carries second RGB data;

[0009] The FPGA successively receives the multiple second image signals output by the timing control board, and each time the second image signal is received, parses the second image signal to obtain the second RGB data, and compares whether the second RGB data is the same as the first RGB data corresponding to the target image screen.

[0010] In some possible implementations, the method further includes:

[0011] Among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for more than a set ratio, the FPGA sends a first feedback signal to the host computer, wherein the target RGB data is a group of the first RGB data corresponding to the target image screen;

[0012] In response to receiving the first feedback signal, the host computer sends a first image cutting instruction to the image signal generator;

[0013] The image signal generator responds to the first image cutting instruction and returns to execute the step of "generating a first image signal corresponding to the target image screen based on the test file, and periodically sending the first image signal to the timing control board according to the display frame rate", and the target image screen corresponding to each time the image signal generator executes this step is different from the target image screen corresponding to the previous execution of this step.

[0014] In some possible implementations, the method further includes:

[0015] Among all the second RGB data corresponding to the target image screen, if the proportion of the second RGB data identical to the target RGB data is not greater than the set proportion, the FPGA sends a third feedback signal to the host computer;

[0016] In response to receiving the third feedback signal, the host computer sends a second indication signal, where the second indication signal is used to indicate that the quality of the timing control board is abnormal.

[0017] In some possible implementations, the method further includes:

[0018] Among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for no more than the set ratio, the FPGA determines whether the second feedback signal is stored in the external storage medium, and if not, sends the second feedback signal to the host computer, and caches the second feedback signal in the external storage medium;

[0019] In response to receiving the second feedback signal, the host computer sends a second image cutting instruction to the image signal generator;

[0020] The image signal generator responds to the second image cutting instruction and returns to execute the step of "generating a first image signal corresponding to the target image screen based on the test file, and periodically sending the first image signal to the timing control board according to the display frame rate", and the target image screen corresponding to the current execution of this step by the image signal generator is the same as the target image screen corresponding to the previous execution of this step.

[0021] In some possible implementations, among all the second RGB data corresponding to the target image screen, if the proportion of the second RGB data that is the same as the target RGB data is greater than a set proportion, the FPGA sends a first feedback signal to the host computer, specifically including:

[0022] Among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for more than a set ratio, the FPGA sends a first feedback signal to the host computer, and determines whether the second feedback signal is stored in the external storage medium, and if so, deletes the second feedback signal from the external storage medium;

[0023] Among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for no more than the set ratio, the FPGA sends a third feedback signal to the host computer, specifically including:

[0024] Among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for no more than the set ratio, the FPGA determines whether the second feedback signal is stored in the external storage medium, and if so, sends a third feedback signal to the host computer.

[0025] In some possible implementations, in response to receiving the first feedback signal, the host computer sends a first image cutting instruction to the image signal generator, specifically including:

[0026] In response to receiving the first feedback signal, the host computer determines the total number of the first feedback signals received by the host computer so far, and sends a first image cutting instruction to the image signal generator if the total number does not reach a set number.

[0027] The method further comprises:

[0028] If the total quantity reaches the set quantity, a first indication signal is issued, and the first indication signal is used to indicate that the quality of the timing control board is normal.

[0029] In the second aspect, a screenless testing system for a timing control board of a liquid crystal display is proposed, comprising a host computer, an image signal generator, an FPGA and a test fixture, and the screenless testing system is configured to execute the method described in the first aspect, wherein the test fixture is used to carry the timing control board.

[0030] In the third aspect, a screenless test system for a timing control board of a liquid crystal display is proposed, comprising:

[0031] Memory,

[0032] processor,

[0033] program instructions stored in the memory and executable by the processor;

[0034] When the processor executes the program instructions, the method according to the first aspect is implemented.

[0035] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed on a computer, the computer is caused to execute the method described in the first aspect.

[0036] In a fifth aspect, a computer program product is proposed, wherein the computer program product comprises computer instructions, and when the computer instructions are executed by a computer, the computer is caused to execute the method as described in the first aspect.

[0037] According to the screenless testing method of the LCD display timing control board proposed in this application, there is no need to connect and light up the display screen, thereby avoiding over-detection and false detection that may be caused by traditional jumper solutions. This method can easily and accurately test the quality of the timing control board. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application, rather than limiting the present application.

[0039] Figure 1 It is a structural schematic diagram of a screenless testing system provided in one embodiment of the present application.

[0040] Figure 2 It is a flowchart of a screenless testing method provided in one embodiment of the present application.

[0041] Figure 3It is a flowchart of a screenless testing method provided in one embodiment of the present application.

[0042] Figure 4 It is a flowchart of a screenless testing method provided in one embodiment of the present application.

[0043] Figure 5 It is a flowchart of a screenless testing method provided in one embodiment of the present application.

[0044] Figure 6 It is a flowchart of a screenless testing method provided in one embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the embodiment of the present application will be clearly and completely described below in conjunction with the drawings of the embodiment of the present application. Obviously, the described embodiment is a part of the embodiment of the present application, rather than all the embodiments. Based on the described embodiment of the present application, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of this application. It can be understood that, in the absence of conflict, some technical means of the various embodiments described herein can be replaced or combined with each other.

[0046] In the description of this application, if there are terms such as "first", "second", etc., they are only used to distinguish the objects described and do not have any order or technical meaning. Therefore, an object defined as "first", "second", etc. may explicitly or implicitly include one or more of the objects, and, for example, the term "first element" itself does not mean the existence of the "second element", and the term "second element" itself does not mean the existence of the "first element". In addition, "one" or "a" and similar words do not indicate a quantity limitation, but rather indicate the existence of at least one, and "multiple" means not less than two.

[0047] The present application embodiment provides a non-screen test method for a timing control board of a liquid crystal display screen. The method can be performed by Figure 1 The screenless test system shown is performed. Figure 1 In the present invention, the screenless test system mainly includes a host computer, an FPGA (field programmable gate array) and a pattern generator (PG). In addition, it also includes an external storage medium connected to the FPGA, that is, a storage medium plugged into the FPGA. The external storage medium can be, for example, a DDR3 memory, and the host computer can be, for example, a PC (Personal Computer). In addition, in order to facilitate the understanding of this technology, Figure 1The timing control board under test is also shown in the figure. When executing the method, the timing control board is carried by the test fixture to be positioned. In some implementations, the test fixture can be a fixture structure with multiple electrical contacts. The screenless test system and the corresponding screenless test method can be used to test the screenless display without a display screen. Figure 1 Perform quality inspection on the timing control board.

[0048] Next, combine Figure 1 and Figure 2 , introduces the screenless testing method of this embodiment, the method comprising:

[0049] S201, the host computer sends a test file to the image signal generator and the FPGA respectively, wherein the test file carries multiple groups of original RGB data corresponding to multiple image screens and the display frame rate of the image screens.

[0050] In some embodiments, before step S201, the newly produced timing control board is placed in a test fixture, and the host computer controls the channel switching module (not shown) of the FPGA through the network port to switch the ICT test points and the open-short circuit test points to perform ICT testing and open-short circuit testing respectively. After the ICT test and the open-short circuit test are passed, the FLASH burning module (not shown) is controlled to burn the FLASH on the timing control board, so that the timing control board (to be more specific, the TCON IC in the timing control board) has software functions.

[0051] The host computer sends the test file to both the image signal generator and the FPGA, so that the image signal generator and the FPGA can obtain multiple groups of original RGB data carried in the test file, each group of original RGB data corresponds to an image screen. In some embodiments, the image screens are different from each other, so the groups of original RGB data are different from each other.

[0052] For example, in the first embodiment, there are 10 groups of original RGB data carried in the test file, which correspond to 10 different image screens, wherein the 10 image screens are image screen f1, image screen f2...image screen f10, and the 10 groups of original RGB data are original RGB data d1, original RGB data d2...original RGB data d10, and original RGB data d1 corresponds to image screen f1, original RGB data d2 corresponds to image screen f2... And the display frame rate of each image screen carried in the test file is 60HZ, that is, the host computer intends to display each image screen on the LCD screen at a frame rate of 60HZ.

[0053] S202, the FPGA processes the original RGB data carried in the test file to obtain multiple groups of first RGB data having the same data structure as the second RGB data described below and corresponding to the multiple groups of original RGB data respectively.

[0054] In some embodiments, the tested timing control board has ACC (Accurate Color Capture) debugging and ODC (Over Driver Controlling) debugging functions. Therefore, in the step S204 described later, the second RGB data parsed out has a data structure difference from the original RGB data. If the second RGB data is further subjected to inverse ACC and inverse ODC processing in the step S204 described later to obtain RGB data with the same structure as the original RGB data, the data processing load of the FPGA will become very large and may cause data errors. Therefore, the FPGA can perform similar operations as the tested timing control board on the original RGB data directly obtained from the host computer, such as ACC processing and / or ODC processing, so as to obtain multiple groups of first RGB data with the same data structure as the second RGB data described later and corresponding to multiple groups of original RGB data. Compared with the inverse ACC processing and inverse ODC processing, the data processing amount of the ACC processing and ODC processing is smaller, and the possibility of data distortion is small. Among them, the ACC debugging is to make different grayscales have the same color expression and make the color more uniform. The ODC debugging is to reduce the response time and reduce the liquid crystal afterimage.

[0055] For example, in the aforementioned first embodiment, the FPGA performs relevant processing on the original RGB data carried in the test file, thereby obtaining 10 groups of first RGB data having the same data structure as the second RGB data described below and corresponding to the 10 groups of original RGB data, respectively. The 10 groups of first RGB data are first RGB data d11, first RGB data d12, first RGB data d13…first RGB data d20, and the first RGB data d11 corresponds to the original RGB data d1, the first RGB data d12 corresponds to the original RGB data d2…

[0056] S203, the image signal generator generates a first image signal corresponding to the target image screen based on the test file, and periodically sends the first image signal to the timing control board according to the aforementioned display frame rate, wherein the target image screen is any one of the aforementioned multiple image screens, and the first image signal carries the original RGB data corresponding to the target image screen; and the timing control board outputs a second image signal based on each reception of the first image signal, thereby successively outputting multiple second image signals, and the second image signal carries the second RGB data.

[0057] For example, in the aforementioned first embodiment, the image signal generator generates a first image signal s11 corresponding to one of the 10 image frames, for example, the image frame f1 (target image frame), based on the test file obtained from the host computer, and periodically sends the first image signal s11 to the timing control board at a frame rate of 60 Hz, and the first image signal s11 carries the original RGB data d1 corresponding to the image frame f1. Moreover, the timing control board will output a second image signal s21 correspondingly each time it receives the first image signal s1, thereby successively outputting 120 second image signals s21 (for example, the image signal generator sends the first image signal s11 to the timing control board at a frame rate of 60 Hz within a duration of 2 seconds), and each second image signal S21 carries a set of second RGB data d21, so the 120 second image signals s21 successively output correspond to 120 sets of second RGB data d21. It can be understood that, under normal circumstances, these 120 sets of second RGB data d21 are the same and correspond to the original RGB data d1 in terms of content.

[0058] S204, the FPGA successively receives a plurality of second image signals output by the timing control board, and analyzes the second image signal to obtain second RGB data each time the second image signal is received, and compares whether the second RGB data is the same as the first RGB data corresponding to the target image screen.

[0059] For example, in the aforementioned first embodiment, the FPGA successively receives 120 second image signals s21 output by the timing control board, and each time the second image signal s21 is received, the FPGA analyzes the second image signal s21 to obtain second RGB data d21, and compares the second RGB data d21 with the first RGB data d11 corresponding to the image screen f1 to see if they are the same. According to the above discussion, a total of 120 sets of second RGB data d21 will be obtained for the image screen f1, and the FPGA will successively compare the 120 sets of second RGB data d21 with the first RGB data d11 to see if they are the same.

[0060] S205: The screenless testing system determines the quality of the timing control board based on the comparison result between the second RGB data and the first RGB data.

[0061] It can be understood that the closer the second RGB data is to the first RGB data, the better the quality of the timing control board is, and the original RGB data is not likely to be distorted in data content after being processed by the timing control board.

[0062] See also Figure 3 In some embodiments, the method further comprises:

[0063] S301, among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for more than a set ratio, the FPGA sends a first feedback signal to the host computer, wherein the target RGB data is a group of first RGB data corresponding to the target image screen;

[0064] S302, in response to receiving the first feedback signal, the host computer sends a first image cutting instruction to the image signal generator;

[0065] S303, the image signal generator responds to the first image cutting instruction and returns to execute step S203, and the corresponding target image screen each time the image signal generator executes step S203 is different from the target image screen corresponding to the previous execution of step S203 (that is, the two are two different image screens among the aforementioned multiple image screens).

[0066] For example, in the aforementioned first embodiment, the set ratio is configured to be 90%, and the result of FPGA comparing 120 groups of second RGB data d21 with the first RGB data d11 is: 115 groups of second RGB data d21 are the same as the first group of first RGB data d11, and the other 5 groups of second RGB data d21 are different from the first group of first RGB data d11. 115 / 120>90%, so FPGA sends a first feedback signal to the host computer, and then the host computer sends a first image cutting instruction to the image signal generator in response to the first feedback signal. In addition, the image signal generator returns to execute step S203 in response to the first image cutting instruction sent by the host computer, that is, the image signal generator returns to step S203 and performs the following operations:

[0067] The image signal generator generates a first image signal s12 (different from the aforementioned first image signal s11) corresponding to the image screen f2 (the target image screen corresponding to the current step S203, which is different from the image screen f1) based on the test file obtained from the host computer, and periodically sends the first image signal s12 to the timing control board at a frame rate of 60HZ. The first image signal s12 carries the original RGB data d2 corresponding to the image screen f2. In addition, the timing control board will output a second image signal s22 correspondingly each time it receives the first image signal s12, thereby successively outputting another 120 second image signals s22, and these 120 second image signals s22 correspond to another 120 sets of second RGB data d22. Under normal circumstances, the 120 sets of second RGB data d22 are identical to each other and correspond to the original RGB data d2 in terms of content.

[0068] It is understandable that when the image signal generator returns to execute step S203, the FPGA will also execute step S204 again based on the newly executed step S203, that is:

[0069] The FPGA will successively receive another set of second image signals output by the timing control board, and each time each of the second image signals is received, it will parse the second image signal to obtain another second RGB data, and compare the second RGB data with the set of first RGB data corresponding to the current target image screen to see if they are the same.

[0070] In this way, the screenless test system first compares the multiple second RGB data corresponding to one of the image screens with the corresponding set of first RGB data. When the relevant conditions are met, the multiple second RGB data corresponding to another image screen are compared with the corresponding another set of first RGB data. When the relevant conditions are met, the multiple second RGB data corresponding to yet another image screen are compared with the corresponding yet another set of first RGB data, and so on, until it is confirmed that the comparison results of the second RGB data corresponding to a sufficient number of image screens (for example, all image screens) and the corresponding first RGB data meet the set requirements, then it can be considered that the quality of the tested timing driver board is normal.

[0071] Based on the above description, in some embodiments, the method includes:

[0072] S401, in response to receiving a first feedback signal, the host computer determines a total number of first feedback signals received by the host computer up to the present;

[0073] S402, if the total number does not reach the set number, sending a first image cutting instruction to the image signal generator;

[0074] S403: If the total number reaches the aforementioned set number, a first indication signal is issued, and the first indication signal is used to indicate that the quality of the timing control board is normal.

[0075] For example, in the aforementioned first embodiment, the number is set to 5. When the host computer receives the first feedback signal from the image signal generator for the fourth time, the first indication signal will not be issued, and the first image cutting instruction will continue to be sent to the image signal generator, so that the image signal generator generates the first image signal s15 corresponding to the fifth image screen f5 based on the first image cutting instruction, and periodically sends the first image signal s15 corresponding to the image screen f5 to the timing control board according to the display frame rate. When the host computer receives the first feedback signal from the image signal generator for the fifth time, the first indication signal is issued to inform the operator that the timing control board currently under test is a qualified product. The first indication signal can be, for example, the first prompt sound issued from the host computer. In addition, when the host computer receives the first feedback signal from the image signal generator for the fifth time, the host computer can continue to send the first image cutting instruction to the image signal generator, or stop sending the first image cutting instruction to the image signal generator, and the embodiment of the present application does not limit this.

[0076] In other embodiments, the aforementioned set number may be the total number of image frames corresponding to the test file, that is, until it is confirmed that the difference between the second RGB data corresponding to all image frames and the corresponding first RGB data meets the set requirements, the quality of the tested timing driver board is considered normal.

[0077] It can be understood that the combination of the aforementioned steps S401 and S402 can be regarded as a specific implementation of the aforementioned step S302, and step S403 can be regarded as a further optimization of the method under the specific implementation. In this way, when the system confirms that the difference between the second RGB data corresponding to a sufficient number of different image screens and the corresponding first RGB data meets the set requirements, it is determined that the quality of the tested timing driver board is normal, the test accuracy is high and the operability is strong.

[0078] See also Figure 5 ,exist Figure 3 In the illustrated embodiment, the method may further include:

[0079] S501, among all the second RGB data corresponding to the target image, if the proportion of the second RGB data identical to the target RGB data is not greater than a set proportion, the FPGA sends a third feedback signal to the upper computer;

[0080] S502, in response to receiving the third feedback signal, the host computer sends a second indication signal, where the second indication signal is used to indicate that the quality of the timing control board is abnormal.

[0081] For example, in the aforementioned first embodiment, the comparison result of FPGA on 120 sets of second RGB data d23 and first RGB data d13 is: 100 sets of second RGB data d23 are the same as the first RGB data d13, and 20 sets of second RGB data d23 are different from the first set of first RGB data d13. 100 / 120<90%, so FPGA sends a third feedback signal to the host computer. In addition, the host computer sends a second indication signal in response to receiving the third feedback signal to inform the operator that the timing control board currently under test has quality abnormalities. The second indication signal can be, for example, a second prompt sound sent from the host computer that is different from the aforementioned first prompt sound.

[0082] See also Figure 6 ,exist Figure 3 In the illustrated embodiment, the method may further include:

[0083] S601, among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for no more than a set ratio, the FPGA determines whether a second feedback signal is stored in the external storage medium;

[0084] S602, if not, sending a second feedback signal to the upper computer, and caching the second feedback signal in an external storage medium;

[0085] S603, if yes, send the third feedback signal to the upper computer;

[0086] S604, in response to receiving the second feedback signal, the host computer sends a second image cutting instruction to the image signal generator;

[0087] S605, the image signal generator returns to execute step S203 in response to the second image cutting instruction, and the target image screen corresponding to the current execution of this step by the image signal generator is the same as the target image screen corresponding to the previous execution of this step;

[0088] S606, among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for more than a set ratio, the FPGA sends the first feedback signal to the host computer and determines whether the second feedback signal exists in the external storage medium; if so, the second feedback signal is deleted from the external storage medium.

[0089] It can be understood that the combination of steps S601 and S603 can be regarded as a specific implementation of the aforementioned step S304, step S602 can be regarded as a further optimization of the method under this specific implementation, and step S606 can be regarded as a specific implementation of the aforementioned step S301. It can be known that the second image cutting instruction and the first image cutting instruction are different instructions, wherein the first image cutting instruction is used to control the image signal generator to switch to process the next image screen, and the second image cutting instruction is used to make the image signal generator process the previous image screen again, so the second image cutting instruction can also be called an overload instruction. In this way, when it is preliminarily determined that the second RGB data does not meet the relevant requirements, the FPGA will not immediately send the third feedback signal to the host computer to make the host computer send the second indication signal indicating that the quality of the timing control board is abnormal, but first determine whether the second feedback signal is stored in the external storage medium. If not, the image signal generator is made to reprocess the previous image screen, thereby reducing the possibility of misjudgment. If yes, it means that step S203 for the current image screen has been executed twice in succession and the proportion of the number of second RGB data with the same target RGB data in each time is not greater than the set proportion. The possibility of the timing control board itself being abnormal is very high, so the host computer sends the second indication signal indicating that the quality of the timing control board is abnormal. In addition, when the proportion of the number of second RGB data with the same target RGB data is greater than the set proportion, the second indication signal previously cached in the external storage medium will be deleted (if any), thereby providing the next image screen with an opportunity to perform step S203 twice.

[0090] An embodiment of the present application also proposes a screenless testing system for a timing control board of a liquid crystal display screen, the system comprising a memory, a processor, and program instructions stored in the memory and executable by the processor, and the processor implements the above method when executing the program instructions.

[0091] The embodiment of the present application further proposes a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program. When the computer program is executed on a computer, the computer executes the above method.

[0092] The embodiment of the present application also proposes a computer program product, which includes computer instructions. When the computer instructions are executed by a computer, the computer executes the above method.

Claims

1. A screenless testing method for a timing control board of a liquid crystal display, characterized in that: Applied to a screenless test system including a host computer, an image signal generator and an FPGA, the method includes: The host computer transmits a test file to the image signal generator and the FPGA respectively, wherein the test file carries a plurality of groups of original RGB data corresponding to a plurality of image screens and a display frame rate of the image screens; The FPGA processes the original RGB data carried in the test file to obtain a plurality of groups of first RGB data having the same data structure as the second RGB data described below and corresponding to the plurality of groups of original RGB data respectively; The image signal generator generates a first image signal corresponding to a target image screen based on the test file, and periodically sends the first image signal to the timing control board according to the display frame rate, wherein the target image screen is any one of the multiple image screens, and the first image signal carries original RGB data corresponding to the target image screen; wherein the timing control board outputs a second image signal based on each receipt of the first image signal, thereby successively outputting multiple second image signals, and the second image signal carries second RGB data; The FPGA successively receives the plurality of second image signals output by the timing control board, and analyzes the second image signal to obtain the second RGB data each time the second image signal is received, and compares the second RGB data with the first RGB data corresponding to the target image screen to see whether they are the same; Also includes: Among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for more than a set ratio, the FPGA sends a first feedback signal to the host computer, wherein the target RGB data is a group of the first RGB data corresponding to the target image screen; In response to receiving the first feedback signal, the host computer sends a first image cutting instruction to the image signal generator; The image signal generator responds to the first image cutting instruction and returns to execute the step of "generating a first image signal corresponding to the target image screen based on the test file, and periodically sending the first image signal to the timing control board according to the display frame rate", and the target image screen corresponding to each execution of the step by the image signal generator is different from the target image screen corresponding to the previous execution of the step.

2. The method according to claim 1, characterized in that Also includes: Among all the second RGB data corresponding to the target image screen, if the proportion of the second RGB data identical to the target RGB data is not greater than the set proportion, the FPGA sends a third feedback signal to the host computer; In response to receiving the third feedback signal, the host computer sends a second indication signal, where the second indication signal is used to indicate that the quality of the timing control board is abnormal.

3. The method according to claim 2, characterized in that Also includes: Among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for no more than the set ratio, the FPGA determines whether a second feedback signal is stored in the external storage medium, and if not, sends the second feedback signal to the host computer, and caches the second feedback signal in the external storage medium; In response to receiving the second feedback signal, the host computer sends a second image cutting instruction to the image signal generator; The image signal generator responds to the second image cutting instruction and returns to execute the step of "generating a first image signal corresponding to the target image screen based on the test file, and periodically sending the first image signal to the timing control board according to the display frame rate", and the target image screen corresponding to the current execution of the step by the image signal generator is the same as the target image screen corresponding to the previous execution of the step.

4. The method according to claim 3, characterized in that: Among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for more than a set ratio, the FPGA sends a first feedback signal to the host computer, specifically including: Among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for more than a set ratio, the FPGA sends a first feedback signal to the host computer, and determines whether the second feedback signal is stored in the external storage medium, and if so, deletes the second feedback signal from the external storage medium; Among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for no more than the set ratio, the FPGA sends a third feedback signal to the host computer, specifically including: Among all the second RGB data corresponding to the target image screen, if the number of second RGB data identical to the target RGB data accounts for no more than the set ratio, the FPGA determines whether the second feedback signal is stored in the external storage medium, and if so, sends a third feedback signal to the host computer.

5. The method according to any one of claims 1 to 4, characterized in that In response to receiving the first feedback signal, the host computer sends a first image cutting instruction to the image signal generator, specifically including: In response to receiving the first feedback signal, the host computer determines the total number of the first feedback signals received by the host computer up to the present, and if the total number does not reach a set number, sends a first image cutting instruction to the image signal generator; The method further comprises: If the total quantity reaches the set quantity, a first indication signal is issued, and the first indication signal is used to indicate that the quality of the timing control board is normal.

6. A screenless test system for a timing control board of a liquid crystal display, characterized in that: The screenless test system comprises a host computer, an image signal generator, a FPGA and a test fixture, and the screenless test system is configured to execute the method as described in any one of claims 1 to 5, wherein the test fixture is used to carry the timing control board.

7. A screenless test system for a timing control board of a liquid crystal display, characterized in that: include: Memory, processor, program instructions stored in the memory and executable by the processor; When the processor executes the program instructions, the method according to any one of claims 1 to 5 is implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 5.

9. A computer program product, characterized in that The computer program product comprises computer instructions, which, when executed by a computer, cause the computer to perform the method according to any one of claims 1 to 5.

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