Pixel driving architecture and display device

Abstract

The application discloses a pixel driving architecture and a display device. In the pixel driving architecture, a long-hand pixel unit and a short-hand pixel unit are connected with a same data line, a first gate line and a first source line in a first thin film transistor overlap to form a first parasitic capacitor, a second gate line and a second source line in a second thin film transistor overlap to form a second parasitic capacitor, a first compensation line is connected with the first source line and overlaps with a first scan line to form a first compensation capacitor, a second compensation line is connected with the second source line and overlaps with a second scan line to form a second compensation capacitor, and a sum of the first parasitic capacitor and the first compensation capacitor is equal to a sum of the second parasitic capacitor and the second compensation capacitor. The technical scheme can effectively balance the parasitic capacitors of the long-hand pixel and the short-hand pixel, reduce the non-uniformity of the display panel brightness, and ensure that the display panel can normally display.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, in particular to a pixel driving architecture and a display device. BACKGROUND

[0002] Long-hand pixels and short-hand pixels are usually arranged in a display panel, the long-hand pixels and the short-hand pixels are connected to the same data line, so that the number of data lines can be reduced, and the number of chips can also be reduced. However, parasitic capacitance is generated between the source line and the corresponding gate line, and if the parasitic capacitance generated in the long-hand pixels and the short-hand pixels is different, the display panel will have uneven brightness distribution, which will affect the normal display of the display panel. SUMMARY

[0003] The purpose of the present application is to provide a pixel driving architecture which can effectively balance the parasitic capacitance of long-hand pixels and short-hand pixels, reduce the uneven brightness of the display panel, and ensure that the display panel can display normally.

[0004] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0005] According to one aspect of the embodiments of the present application, the present application provides a pixel driving architecture, which comprises a data line, a long-hand pixel unit and a short-hand pixel unit, the long-hand pixel unit and the short-hand pixel unit are connected to the same data line, and the long-hand pixel unit is located on the side of the short-hand pixel unit away from the data line;

[0006] The pixel driving architecture further comprises a first thin film transistor and a second thin film transistor, the first thin film transistor comprises a first gate line, a first source line and a first drain line, the first drain line is connected to the data line, the first source line is connected to the long-hand pixel unit, and the first gate line and the first source line overlap to form a first parasitic capacitance;

[0007] The second thin film transistor comprises a second gate line, a second source line and a second drain line, the second drain line is connected to the data line, the second source line is connected to the short-hand pixel unit, the second gate line and the second source line overlap to form a second parasitic capacitance, and the pixel driving architecture further comprises:

[0008] A first scan line, the first scan line is arranged in the same layer as the first gate line, and the first scan line is connected to the first gate line;

[0009] A second scan line, the second scan line is arranged in the same layer as the second gate line, and the second scan line is connected to the second gate line;

[0010] a first compensation line connected to the first source line and overlapping the first scan line to form a first compensation capacitor;

[0011] a second compensation line connected to the second source line and overlapping the second scan line to form a second compensation capacitor, and a sum of the first parasitic capacitor and the first compensation capacitor is equal to a sum of the second parasitic capacitor and the second compensation capacitor.

[0012] In one aspect, the first scan line includes a first horizontal segment and a first vertical segment, the first horizontal segment is connected to the first gate line at one end and connected to the first vertical segment at the other end;

[0013] the first compensation line includes a first horizontal compensation segment and a first vertical compensation segment, the first horizontal compensation segment is connected to the first source line, the first horizontal compensation segment overlaps the first vertical segment, and the first vertical compensation segment is connected to the first horizontal compensation segment and overlaps the first horizontal segment;

[0014] the second scan line includes a second horizontal segment and a second vertical segment, the second horizontal segment is connected to the second gate line at one end and connected to the second vertical segment at the other end;

[0015] the second compensation line includes a second horizontal compensation segment and a second vertical compensation segment, the second horizontal compensation segment is connected to the second source line, the second horizontal compensation segment overlaps the second vertical segment, and the second vertical compensation segment is connected to the second horizontal compensation segment and overlaps the second horizontal segment.

[0016] In one aspect, an overlapping area of the first source line and the first gate line is a1, an overlapping area of the first horizontal segment and the first vertical compensation segment is a2, and an overlapping area of the first vertical segment and the first horizontal compensation segment is a3;

[0017] an overlapping area of the second source line and the second gate line is b1, an overlapping area of the second horizontal segment and the second vertical compensation segment is b2, and an overlapping area of the second vertical segment and the second horizontal compensation segment is b3, and a1+a2+a3=b1+b2+b3 is satisfied.

[0018] In one aspect, the first scan line further includes a third horizontal segment, the first gate line, the first horizontal segment, the first vertical segment, and the third horizontal segment are sequentially connected end to end, and the first vertical compensation segment is overlapped at one end with the first horizontal segment and overlapped at the other end with the third horizontal segment.

[0019] The second scan line further comprises a fourth horizontal segment, the second gate line, the second horizontal segment, the second vertical segment and the fourth horizontal segment are sequentially connected end to end, one end of the second vertical compensation segment overlaps the second horizontal segment, and the other end overlaps the fourth horizontal segment.

[0020] In one aspect, the first gate line, the first horizontal segment, the first vertical segment and the third horizontal segment form a first quadrangle, and a connection point of the first horizontal compensation segment and the first vertical compensation segment coincides with a center of the first quadrangle.

[0021] The first gate line, the second gate line, the second horizontal segment, the second vertical segment and the fourth horizontal segment form a second quadrangle, and a connection point of the second horizontal compensation segment and the second vertical compensation segment coincides with a center of the second quadrangle.

[0022] In one aspect, a width of the first horizontal segment is G, and an overlapping length of the first vertical compensation segment and the first horizontal segment is g.

[0023] A width of the first vertical segment is H, and an overlapping length of the first horizontal compensation segment and the first vertical segment is h.

[0024] Then, g / G≥1 / 2 and h / H≥1 / 2 are satisfied.

[0025] In one aspect, a line width of the first source line is equal to line widths of the first horizontal compensation segment and the first vertical compensation segment.

[0026] A line width of the second source line is equal to line widths of the second horizontal compensation segment and the second vertical compensation segment, and the first source line width is equal to the second source line width.

[0027] In one aspect, the long-hand pixel unit comprises a first pixel electrode and a first connection electrode, the first connection electrode is arranged in the same layer as the first pixel electrode, one end of the first connection electrode is connected to the first pixel electrode, and the other end of the first connection electrode is connected to the first compensation line.

[0028] The first thin film transistor further comprises a first semiconductor layer, and the first semiconductor layer is arranged between the first source line and the first gate line.

[0029] The pixel driving architecture further comprises a first compensation semiconductor layer, the first compensation semiconductor layer is arranged in the same layer as the first semiconductor layer, the first compensation semiconductor layer is arranged between the first connection electrode and the first scan line, and the first compensation semiconductor layer overlaps the first connection electrode and the first scan line, respectively.

[0030] In one aspect, the first compensation semiconductor layer overlaps the first scan line with a width of d, and the first connection electrode overlaps the first compensation semiconductor layer with a width of D, and d / D≥1 / 3 is satisfied.

[0031] In addition, in order to solve the above problems, the application also provides a display device, which comprises a display panel and a pixel driving architecture as described above, the display panel comprises a display area and a non-display area surrounding the display area, and the pixel driving architecture is arranged in the display area.

[0032] In the application, a first compensation line is arranged at the position of the long-hand pixel unit, and a second compensation line is arranged at the position of the short-hand pixel unit. The first compensation capacitance generated by the first compensation line and the first scan line and the second compensation capacitance generated by the second compensation line and the second scan line compensate for the parasitic capacitance. The sum of the first parasitic capacitance and the first compensation capacitance is equal to the sum of the second parasitic capacitance and the second compensation capacitance, so that the parasitic capacitance of the long-hand pixel and the short-hand pixel can be effectively balanced, the situation of uneven brightness of the display panel is reduced, and the normal display of the display panel is ensured.

[0033] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the application. BRIEF DESCRIPTION OF DRAWINGS

[0034] The drawings incorporated into the specification and forming a part thereof illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0035] Figure 1 The structural layout schematic diagram of one embodiment of the pixel driving architecture of the application is schematically shown.

[0036] Figure 2 The structural layout schematic diagram of one embodiment of the pixel driving architecture of the application is schematically shown. Figure 1 The structural layout schematic diagram of one embodiment of the pixel driving architecture of the application is schematically shown.

[0037] Figure 3 The structural layout schematic diagram of one embodiment of the pixel driving architecture of the application is schematically shown. Figure 2 The structural layout schematic diagram of one embodiment of the pixel driving architecture of the application is schematically shown.

[0038] Figure 4 The structural layout schematic diagram of one embodiment of the pixel driving architecture of the application is schematically shown. Figure 3 The structural layout schematic diagram of one embodiment of the pixel driving architecture of the application is schematically shown.

[0039] Figure 5 A schematic diagram illustrating a structure layout of another embodiment of the pixel driving architecture of the present application is shown. Figure 2 A schematic diagram illustrating a structure of a semiconductor layer in a first thin film transistor and a second thin film transistor in the pixel driving architecture.

[0040] Figure 6 A schematic diagram illustrating a structure layout of another embodiment of the pixel driving architecture of the present application is shown.

[0041] Figure 7 A schematic diagram illustrating a structure layout of another embodiment of the pixel driving architecture of the present application is shown. Figure 6 A schematic diagram illustrating a structure of a long-hand pixel unit and a short-hand pixel unit in the pixel driving architecture.

[0042] Figure 8 A schematic diagram illustrating a structure layout of another embodiment of the pixel driving architecture of the present application is shown. Figure 7 A schematic diagram illustrating a structure of a semiconductor layer in a first thin film transistor and a second thin film transistor in the pixel driving architecture.

[0043] Figure 9 A schematic diagram illustrating a structure layout of another embodiment of the pixel driving architecture of the present application is shown. Figure 8 A schematic diagram illustrating a structure of a semiconductor layer in a first thin film transistor in the pixel driving architecture.

[0044] Figure 10 A schematic diagram illustrating a structure of a display panel in the display device of the present application is shown.

[0045] The following labels are used in the drawings:

[0046] 100, data line; 200, long-hand pixel unit; 300, short-hand pixel unit; 400, first thin film transistor; 500, second thin film transistor; 610, first scan line; 620, second scan line; 710, first compensation line; 720, second compensation line; 810, first compensation semiconductor layer; 820, second compensation semiconductor layer; 900, display panel; 910, display area; 920, non-display area;

[0047] 210, first pixel electrode; 220, first connection electrode; 310, second pixel electrode; 320, second connection electrode; 410, first gate line; 420, first source line; 430, first drain line; 440, first semiconductor layer; 510, second gate line; 520, second source line; 530, second drain line; 540, second semiconductor layer; 611, first horizontal segment; 612, first vertical segment; 613, third horizontal segment; 621, second horizontal segment; 622, second vertical segment; 623, fourth horizontal segment; 711, first horizontal compensation segment; 712, first vertical compensation segment; 721, second horizontal compensation segment; 722, second vertical compensation segment. DETAILED DESCRIPTION

[0048] Example implementations are now described with reference to the drawings. Example implementations can, however, be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the inventive aspects to those skilled in the art.

[0049] Embodiment one

[0050] Referring to Figures 1 to 3 As shown in the drawings, the present application provides a pixel driving architecture, the pixel driving architecture comprises a data line 100, a long-hand pixel unit 200 and a short-hand pixel unit 300, the long-hand pixel unit 200 and the short-hand pixel unit 300 are connected to the same data line 100, the long-hand pixel unit 200 is located on the side of the short-hand pixel unit 300 away from the data line 100; by connecting the long-hand pixel unit 200 and the short-hand pixel unit 300 to the same data line 100, the number of data lines 100 is reduced, thereby reducing the chip providing data signals.

[0051] The pixel driving architecture further comprises a first thin film transistor 400 and a second thin film transistor 500, the first thin film transistor 400 comprises a first gate line 410, a first source line 420 and a first drain line 430, the first drain line 430 is connected to the data line 100, the first source line 420 is connected to the long-hand pixel unit 200, the data signal on the data line 100 is transmitted to the first source line 420 through the first drain line 430, and then loaded on the long-hand pixel unit 200. The first gate line 410 and the first source line 420 overlap to form a first parasitic capacitance.

[0052] The second thin film transistor 500 comprises a second gate line 510, a second source line 520 and a second drain line 530, the second drain line 530 is connected to the data line 100, the second source line 520 is connected to the short-hand pixel unit 300, the second gate line 510 and the second source line 520 overlap to form a second parasitic capacitance, the data signal on the data line 100 is transmitted to the second source line 520 through the second drain line 530, and then loaded on the short-hand pixel unit 300. The pixel driving architecture further comprises a first scan line 610, a second scan line 620, a first compensation line 710 and a second compensation line 720.

[0053] The first scan line 610 is provided in the same layer as the first gate line 410, and the first scan line 610 is connected to the first gate line 410; the first scan line 610 provides a first scan signal, the first scan signal acts on the first gate line 410, so that the first source line 420 and the first drain line 430 are turned on, and the data signal can be smoothly loaded on the long-hand pixel unit 200.

[0054] The second scan line 620 is arranged in the same layer as the second gate line 510, and the second scan line 620 is connected to the second gate line 510; the second scan line 620 provides a second scan signal, and the second scan signal acts on the second gate line 510, so that the second source line 520 and the second drain line 530 are turned on, and the data signal can be smoothly loaded to the short-hand pixel unit 300.

[0055] The first compensation line 710 is connected to the first source line 420, and overlaps with the first scan line 610 to form a first compensation capacitor; the second compensation line 720 is connected to the second source line 520, and overlaps with the second scan line 620 to form a second compensation capacitor, and the sum of the first parasitic capacitor and the first compensation capacitor is equal to the sum of the second parasitic capacitor and the second compensation capacitor. It can be understood that the first compensation line 710 is arranged in the same layer as the first source line 420, and it can also be understood that the first compensation line 710 is an extension line of the first source line 420. Similarly, the second compensation line 720 is arranged in the same layer as the second source line 520, and it can also be understood that the second compensation line 720 is an extension line of the second source line 520.

[0056] In the embodiment, the first compensation line 710 is arranged at the position of the long-hand pixel unit 200, and the second compensation line 720 is arranged at the position of the short-hand pixel unit 300, and the first compensation capacitor generated by the first compensation line 710 and the first scan line 610 and the second compensation capacitor generated by the second compensation line 720 and the second scan line 620 compensate the parasitic capacitor. The sum of the first parasitic capacitor and the first compensation capacitor is equal to the sum of the second parasitic capacitor and the second compensation capacitor, so that the parasitic capacitor of the long-hand pixel and the short-hand pixel can be effectively balanced, the uneven brightness of the display panel 900 is reduced, and the normal display of the display panel 900 is ensured.

[0057] Further, by arranging the first compensation line 710 and the second compensation line 720, when the gate layer and the source layer move relatively, the first compensation capacitor and the second compensation capacitor can be effectively formed, and the difference in capacitance caused by the relative movement is reduced.

[0058] For example, the source layer moves right relative to the gate layer, so that the first compensation capacitor decreases, but the first parasitic capacitor increases, and similarly, the second compensation capacitor increases, but the second parasitic capacitor decreases. Therefore, the sum of the first parasitic capacitor and the first compensation capacitor is still equal to the sum of the second parasitic capacitor and the second compensation capacitor. The difference in parasitic capacitor in the long-hand pixel unit 200 and the short-hand pixel unit 300 is reduced, and uneven distribution of light and shade is avoided.

[0059] In an embodiment of the present application, the relative movement between the gate layer and the source layer can be inclined, that is, horizontally offset and vertically offset. To this end, the first scan line 610 includes a first horizontal segment 611 and a first vertical segment 612, one end of the first horizontal segment 611 is connected to the first gate line 410, and the other end is connected to the first vertical segment 612; the first vertical segment 612 is located at the end of the first horizontal segment 611 away from the first gate line 410. The first horizontal segment 611 can be arranged in parallel with the first source line 420, and the first vertical segment 612 is arranged perpendicularly to the first source line 420.

[0060] The first compensation line 710 includes a first horizontal compensation segment 711 and a first vertical compensation segment 712, the first horizontal compensation segment 711 is connected to the first source line 420, and the first horizontal compensation segment 711 is arranged in the same direction as the first source line 420. The first horizontal compensation segment 711 and the first vertical segment 612 overlap, the first vertical compensation segment 712 is connected to the first horizontal compensation segment 711 and overlaps the first horizontal segment 611; thus, the first compensation capacitor is composed of two parts, one part is the capacitor formed by the overlapping of the first horizontal compensation segment 711 and the first vertical segment 612, and the other part is the capacitor formed by the overlapping of the first vertical compensation segment 712 and the first horizontal segment 611.

[0061] The second scan line 620 includes a second horizontal segment 621 and a second vertical segment 622, one end of the second horizontal segment 621 is connected to the second gate line 510, and the other end is connected to the second vertical segment 622; the second vertical segment 622 is located at the end of the second horizontal segment 621 away from the second gate line 510. The second horizontal segment 621 can be arranged in parallel with the second source line 520, and the second vertical segment 622 is arranged perpendicularly to the second source line 520.

[0062] The second compensation line 720 includes a second horizontal compensation segment 721 and a second vertical compensation segment 722, the second horizontal compensation segment 721 is connected to the second source line 520, the second horizontal compensation segment 721 and the second vertical segment 622 overlap, and the second vertical compensation segment 722 is connected to the second horizontal compensation segment 721 and overlaps the second horizontal segment 621. Thus, the second compensation capacitor is also composed of two parts, one part is the capacitor formed by the overlapping of the second horizontal compensation segment 721 and the second vertical segment 622, and the other part is the capacitor formed by the overlapping of the second vertical compensation segment 722 and the second horizontal segment 621.

[0063] The horizontal direction offset can be compensated by the overlapping of the first horizontal compensation segment 711 and the first vertical segment 612, and the overlapping of the second horizontal compensation segment 721 and the second vertical segment 622. The vertical direction offset can be compensated by the overlapping of the first vertical compensation segment 712 and the first horizontal segment 611, and the overlapping of the second vertical compensation segment 722 and the second horizontal segment 621. Therefore, in the embodiment, the capacitance of the long-hand pixel unit 200 is compensated by the first horizontal compensation segment 711 and the first vertical compensation segment 712, and the capacitance of the short-hand pixel unit 300 is compensated by the second horizontal compensation segment 721 and the second vertical compensation segment 722. The adaptability of the relative movement direction of the gate layer and the source layer is improved, and any offset direction in the same plane can be compensated.

[0064] In an embodiment of the present application, the overlapping area of the first source line 420 and the first gate line 410 is a1, the overlapping area of the first horizontal segment 611 and the first vertical compensation segment 712 is a2, and the overlapping area of the first vertical segment 612 and the first horizontal compensation segment 711 is a3.

[0065] The overlapping area of the second source line 520 and the second gate line 510 is b1, the overlapping area of the second horizontal segment 621 and the second vertical compensation segment 722 is b2, and the overlapping area of the second vertical segment 622 and the second horizontal compensation segment 721 is b3, which satisfies a1+a2+a3=b1+b2+b3. Therefore, the total overlapping area of the long-hand pixel unit 200 is equal to the total overlapping area of the short-hand pixel unit 300, and the parasitic capacitance generated in the long-hand pixel unit 200 and the short-hand pixel unit 300 can be equal by keeping the two overlapping areas equal.

[0066] In an embodiment of the present application, the first scan line 610 further includes a third horizontal segment 613, the first gate line 410, the first horizontal segment 611, the first vertical segment 612, and the third horizontal segment 613 are sequentially and circularly connected, one end of the first vertical compensation segment 712 overlaps the first horizontal segment 611, and the other end overlaps the third horizontal segment 613. The first gate line 410, the first horizontal segment 611, the first vertical segment 612, and the third horizontal segment 613 are sequentially and circularly connected to form a meandering structure. And one end of the first vertical compensation segment 712 overlaps the first horizontal segment 611, and the other end overlaps the third horizontal segment 613, which means that the first vertical compensation segment 712 can overlap the first scan line 610 at both ends, further improving the size of the first compensation capacitance, which is equivalent to increasing the proportion of the first compensation capacitance in the parasitic capacitance on one side of the long-hand pixel unit 200, and reducing the impact of brightness instability caused by the change of the first parasitic capacitance.

[0067] The second scan line 620 further comprises a fourth horizontal segment 623, the second gate line 510, the second horizontal segment 621, the second vertical segment 622 and the fourth horizontal segment 623 are sequentially connected end to end, and the second vertical compensation segment 722 is overlapped at one end with the second horizontal segment 621 and at the other end with the fourth horizontal segment 623. A meandering structure can also be formed by sequentially connecting end to end the second gate line 510, the second horizontal segment 621, the second vertical segment 622 and the fourth horizontal segment 623. And the second vertical compensation segment 722 can be overlapped at both ends with the second scan line 620, further improving the size of the second compensation capacitor, improving the proportion of the second compensation capacitor in the parasitic capacitance on the short side of the pixel unit 300, and reducing the impact of brightness instability caused by changes in the second parasitic capacitance.

[0068] In an embodiment of the present application, the first gate line 410, the first horizontal segment 611, the first vertical segment 612 and the third horizontal segment 613 form a first quadrilateral, and the connection point of the first horizontal compensation segment 711 and the first vertical compensation segment 712 coincides with the center of the first quadrilateral. The extension directions of the first horizontal compensation segment 711 and the first vertical compensation segment 712 are orthogonal, and the two form a cross structure, and the intersection point is the connection point. By making the connection point of the first horizontal compensation segment 711 and the first vertical compensation segment 712 coincide with the center of the first quadrilateral, the distance between the two sides of the first horizontal compensation segment 711 and the first scan line 610 can be made as equal as possible, and the distance between the two sides of the first vertical compensation segment 712 and the first scan line 610 can also be made as equal as possible, reducing the generation of lateral parasitic capacitance.

[0069] The first gate line 410, the second gate line 510, the second horizontal segment 621, the second vertical segment 622 and the fourth horizontal segment 623 form a second quadrilateral, and the connection point of the second horizontal compensation segment 721 and the second vertical compensation segment 722 coincides with the center of the second quadrilateral. The extension directions of the second horizontal compensation segment 721 and the second vertical compensation segment 722 are orthogonal, and the two form a cross structure, and the intersection point is the connection point. Similarly, by making the distance between the two sides of the second horizontal compensation segment 721 and the first scan line 610 as equal as possible, and the distance between the two sides of the first vertical compensation segment 712 and the first scan line 610 as equal as possible, the generation of lateral parasitic capacitance can also be reduced.

[0070] Referring to Figure 4As shown, in an embodiment of the present application, the width of the first horizontal segment 611 is G, and the length of the overlap between the first vertical compensation segment 712 and the first horizontal segment 611 is g; the width of the first vertical segment 612 is H, and the length of the overlap between the first horizontal compensation segment 711 and the first vertical segment 612 is h; then g / G≥1 / 2 and h / H≥1 / 2 are satisfied. It can be known from this that the area of the overlap between the first vertical compensation segment 712 and the first horizontal segment 611 occupies a large enough area of the first horizontal segment 611, reducing the case that the first vertical compensation segment 712 is separated from the first horizontal segment 611 when the gate layer moves relative to the source layer. The area of the overlap between the first horizontal compensation segment 711 and the first vertical segment 612 is also large, and the case that the first horizontal compensation segment 711 is separated from the first vertical segment 612 can also be reduced. The specific proportion can be 1 / 2, 2 / 3 or 3 / 5, etc.

[0071] In an embodiment of the present application, the line width of the first source line 420 is equal to the line width of the first horizontal compensation segment 711 and the line width of the first vertical compensation segment 712; and the line width of the second source line 520 is equal to the line width of the second horizontal compensation segment 721 and the line width of the second vertical compensation segment 722. Further, the line width of the first source line 420 can also be equal to the line width of the second source line 520. By equalizing the line widths, the area of the overlap between the long-hand pixel unit position and the short-hand pixel unit position is equalized, so as to ensure that the parasitic capacitances generated in the long-hand pixel unit and the short-hand pixel unit are also equal.

[0072] In an embodiment of the present application, the long-hand pixel unit 200 includes the first pixel electrode 210 and the first connection electrode 220, the first connection electrode 220 is disposed in the same layer as the first pixel electrode 210, one end of the first connection electrode 220 is connected to the first pixel electrode 210, and the other end of the first connection electrode 220 is connected to the first compensation line 710; for example, the pixel driving architecture in the present application is applied in a liquid crystal panel (Liquid Crystal Display, LCD), the first pixel electrode 210 faces a liquid crystal layer, the first connection electrode 220 extends to above the first compensation line 710, and is connected to the first compensation line 710 in a way of opening a hole.

[0073] Reference is made to Figure 5As shown, the first thin film transistor 400 further comprises a first semiconductor layer 440, which is arranged between the first source line 420 and the first gate line 410; the pixel driving architecture further comprises a first compensation semiconductor layer 810, which is arranged in the same layer as the first semiconductor layer 440, the first compensation semiconductor layer 810 is arranged between the first connecting electrode 220 and the first scan line 610, and the first compensation semiconductor layer 810 overlaps the first connecting electrode 220 and the first scan line 610 respectively. Therefore, by arranging the first compensation semiconductor layer 810, the first connecting electrode 220 and the first scan line 610 can be isolated, and the capacitance between the first connecting electrode 220 and the first scan line 610 can be reduced.

[0074] Similarly, for the second thin film transistor 500, the second thin film transistor 500 further comprises a second semiconductor layer 540, which is arranged between the second source line 520 and the second gate line 510; the pixel driving architecture further comprises a second compensation semiconductor layer 820, which is arranged in the same layer as the second semiconductor layer 540, the second compensation semiconductor layer 820 is arranged between the second connecting electrode 320 and the second scan line 620, and the second compensation semiconductor layer 820 overlaps the second connecting electrode 320 and the second scan line 620 respectively. By arranging the second compensation semiconductor layer 820, the capacitance between the first connecting electrode 220 and the first scan line 610 can be reduced.

[0075] In addition, the first semiconductor layer 440 also extends between the first drain line 430 and the first gate line 410, and the second semiconductor layer 540 also extends between the second drain line 530 and the second gate line 510. The first semiconductor layer 440 and the second semiconductor layer 540 are also arranged in the same layer. Moreover, by arranging the first compensation semiconductor layer 810, the arrangement environment between the first compensation line 710 and the first scan line 610 can be the same as the arrangement environment between the first source line 420 and the first gate line 410, and the compensation of the first parasitic capacitance can be better completed. Similarly, by arranging the second compensation semiconductor layer 820, the arrangement environment between the second compensation line 720 and the second scan line 620 can be the same as the arrangement environment between the second source line 520 and the second gate line 510, and the compensation of the second parasitic capacitance can be better completed.

[0076] Referring to Figures 6 to 9 As shown, in an embodiment of the present application, the overlapping width of the first compensation semiconductor layer 810 and the first scan line 610 is d, which is equal, the overlapping width of the first connecting electrode 220 and the first compensation semiconductor layer 810 is D, and d / D≥1 / 3 is satisfied. The specific ratio can be 1 / 3, 1 / 2, 2 / 3 or 3 / 5, etc.

[0077] For the short-hand pixel unit 300, the ratio of the overlap width of the second compensation semiconductor layer 820 and the second scan line 620 to the overlap width of the second connecting electrode 320 and the second compensation semiconductor layer 820 can refer to the setting in the long-hand pixel unit 200, or it can be greater than or equal to 1 / 3 of the width.

[0078] The first connecting electrode 220 can be connected to the first source line 420 in one of the following ways: the first connecting electrode 220 can be connected to the first compensation line 710. For example, the first connecting electrode 220 can be connected to the intersection of the first horizontal compensation segment 711 and the first vertical compensation segment 712. When the first connecting electrode 220 is close to the intersection, it can be parallel to the first horizontal compensation segment 711 or parallel to the first vertical compensation segment 712.

[0079] Furthermore, the first compensation semiconductor layer 810 can be uniformly overlapped on opposite sides of the square region, that is, overlapped on both sides of the first connecting electrode, corresponding to the position of the first scan line. Similarly, the second compensation semiconductor layer can also be overlapped on both sides of the second connecting electrode, corresponding to the position of the second scan line.

[0080] Example 2

[0081] See Figure 10 As shown, this application also provides a display device, which includes a display panel 900 and a pixel driving architecture as described above. The display panel 900 includes a display area 910 and a non-display area 920 surrounding the display area 910, and the pixel driving architecture is disposed in the display area 910.

[0082] The specific implementation methods and beneficial effects of the display device are described in the section on pixel driving architecture above, and will not be repeated here.

[0083] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0084] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A pixel-driven architecture, characterized in that, The pixel driving architecture includes a data line, a long-hand pixel unit, and a short-hand pixel unit. The long-hand pixel unit and the short-hand pixel unit are connected to the same data line, and the long-hand pixel unit is located on the side of the short-hand pixel unit away from the data line. The pixel driving architecture further includes a first thin-film transistor and a second thin-film transistor. The first thin-film transistor includes a first gate line, a first source line and a first drain line. The first drain line is connected to the data line, and the first source line is connected to the long-handed pixel unit. The first gate line and the first source line overlap to form a first parasitic capacitance. The second thin-film transistor includes a second gate line, a second source line, and a second drain line. The second drain line is connected to the data line, and the second source line is connected to the short-handed pixel unit. The second gate line and the second source line overlap to form a second parasitic capacitance. The pixel driving architecture further includes: A first scan line is disposed on the same layer as the first gate line and is connected to the first gate line. The second scan line is disposed on the same layer as the second gate line and is connected to the second gate line. A first compensation line is connected to the first source line and overlaps with the first scan line to form a first compensation capacitor. The second compensation line is connected to the second source line and overlaps with the second scan line to form a second compensation capacitor. The sum of the first parasitic capacitance and the first compensation capacitor is equal to the sum of the second parasitic capacitance and the second compensation capacitor. The first scan line includes a first horizontal segment and a first vertical segment, one end of the first horizontal segment is connected to the first gate line, and the other end is connected to the first vertical segment; The first compensation line includes a first horizontal compensation segment and a first vertical compensation segment. The first horizontal compensation segment is connected to the first source line. The first horizontal compensation segment and the first vertical segment overlap. The first vertical compensation segment is connected to the first horizontal compensation segment and overlaps with the first horizontal segment. The second scan line includes a second horizontal segment and a second vertical segment, one end of the second horizontal segment is connected to the second gate line, and the other end is connected to the second vertical segment; The second compensation line includes a second horizontal compensation segment and a second vertical compensation segment. The second horizontal compensation segment is connected to the second source line. The second horizontal compensation segment and the second vertical segment overlap. The second vertical compensation segment is connected to the second horizontal compensation segment and overlaps with the second horizontal segment.

2. The pixel driving architecture according to claim 1, characterized in that, The overlap area of ​​the first source line and the first gate line is a1, the overlap area of ​​the first horizontal segment and the first vertical compensation segment is a2, and the overlap area of ​​the first vertical segment and the first horizontal compensation segment is a3. The overlap area between the second source line and the second gate line is b1, the overlap area between the second horizontal segment and the second vertical compensation segment is b2, and the overlap area between the second vertical segment and the second horizontal compensation segment is b3. Then, the following condition is satisfied: a1+a2+a3=b1+b2+b3.

3. The pixel driving architecture according to claim 1, characterized in that, The first scan line further includes a third horizontal segment. The first gate line, the first horizontal segment, the first vertical segment, and the third horizontal segment are connected end to end in sequence. One end of the first vertical compensation segment overlaps with the first horizontal segment, and the other end overlaps with the third horizontal segment. The second scan line also includes a fourth horizontal segment. The second gate line, the second horizontal segment, the second vertical segment, and the fourth horizontal segment are connected end to end in sequence. One end of the second vertical compensation segment overlaps with the second horizontal segment, and the other end overlaps with the fourth horizontal segment.

4. The pixel driving architecture according to claim 3, characterized in that, The first gate line, the first horizontal segment, the first vertical segment, and the third horizontal segment are arranged to form a first square, and the connection point of the first horizontal compensation segment and the first vertical compensation segment coincides with the center of the first square; The first gate line, the second gate line, the second horizontal segment, the second vertical segment, and the fourth horizontal segment are arranged to form a second square, and the connection point of the second horizontal compensation segment and the second vertical compensation segment coincides with the center of the second square.

5. The pixel driving architecture according to claim 1, characterized in that, The width of the first horizontal segment is G, and the overlap length between the first vertical compensation segment and the first horizontal segment is g. The width of the first vertical segment is H, and the overlap length between the first horizontal compensation segment and the first vertical segment is h. Then the following conditions must be met: g / G≥1 / 2, h / H≥1 / 2.

6. The pixel driving architecture according to claim 1, characterized in that, The linewidth of the first source line is equal to the linewidth of both the first horizontal compensation segment and the first vertical compensation segment; The linewidth of the second source line is equal to the linewidth of the second horizontal compensation segment and the second vertical compensation segment, and the linewidth of the first source line is equal to the linewidth of the second source line.

7. The pixel driving architecture according to any one of claims 1 to 6, characterized in that, The long-hand pixel unit includes a first pixel electrode and a first connecting electrode. The first connecting electrode is disposed on the same layer as the first pixel electrode. One end of the first connecting electrode is connected to the first pixel electrode, and the other end of the first connecting electrode is connected to the first compensation line. The first thin-film transistor further includes a first semiconductor layer disposed between the first source line and the first gate line; The pixel driving architecture further includes a first compensation semiconductor layer, which is disposed on the same layer as the first semiconductor layer. The first compensation semiconductor layer is disposed between the first connecting electrode and the first scan line, and overlaps with the first connecting electrode and the first scan line respectively.

8. The pixel driving architecture according to claim 7, characterized in that, If the overlap width between the first compensation semiconductor layer and the first scan line is d, and the overlap width between the first connecting electrode and the first compensation semiconductor layer is D, then d / D ≥ 1 / 3 is satisfied.

9. A display device, characterized in that, The display device includes a display panel and a pixel driving architecture as described in any one of claims 1 to 8, the display panel including a display area and a non-display area surrounding the display area, and the pixel driving architecture disposed in the display area.

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