A digital transmitter

Abstract

This disclosure provides a digital transmitter, relating to the field of transmitter technology. It includes: a baseband data generation unit for multi-phase output of baseband data; and a basic unit including an I-channel mixer and a Q-channel mixer. The I-channel mixer performs mixing processing on the multi-phase outputs of the positive-phase I-channel baseband data and the negative-phase I-channel baseband data, while the Q-channel mixer performs mixing processing on the multi-phase outputs of the positive-phase Q-channel baseband data and the negative-phase Q-channel baseband data. The positive-phase outputs of the I-channel and Q-channel mixers are respectively connected to the positive-phase RF input of the digital transmitter, and the negative-phase outputs of the I-channel and Q-channel mixers are respectively connected to the negative-phase RF input of the digital transmitter. This disclosure simplifies the circuit structure of traditional digital transmitters and enables effective bandwidth expansion. Furthermore, by introducing multi-tap filtering for the baseband data, better spectrum shaping can be achieved.

Description

Technical Field

[0001] This disclosure relates to the field of transmitter technology, and more particularly to a digital transmitter. Background Technology

[0002] With the rapid development of millimeter wave technology, the millimeter wave band has been widely used in communication and radar systems due to its abundant spectrum resources.

[0003] In related technologies, digital transmitters used for millimeter-wave transmission require complex and high-speed digital-to-analog converters (DACs), mixers, and power amplifiers (PAs). Among these, high-speed DACs are difficult to design and consume a lot of power, while the implementation of power amplifiers is limited by manufacturing processes, making it difficult to achieve high power output. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this disclosure provides a digital transmitter.

[0005] According to a first aspect of the present disclosure, a digital transmitter is provided, comprising:

[0006] At least one baseband data generation unit is used to output baseband data in multiple phases; the baseband data includes I-channel baseband data and Q-channel baseband data, the I-channel baseband data includes positive-phase I-channel baseband data and anti-phase I-channel baseband data, and the Q-channel baseband data includes positive-phase Q-channel baseband data and anti-phase Q-channel baseband data.

[0007] At least one basic unit, each basic unit including an I-channel mixer and a Q-channel mixer, wherein the I-channel mixer is used to perform mixing processing on the multiphase output of the positive-phase I-channel baseband data and the multiphase output of the negative-phase I-channel baseband data, and the Q-channel mixer is used to perform mixing processing on the multiphase output of the positive-phase Q-channel baseband data and the multiphase output of the negative-phase Q-channel baseband data; the positive-phase output terminals of the I-channel mixer and the Q-channel mixer are respectively connected to the positive-phase RF input terminal of the digital transmitter, and the negative-phase output terminals of the I-channel mixer and the Q-channel mixer are respectively connected to the negative-phase RF input terminal of the digital transmitter, so as to transmit RF signals externally.

[0008] In some embodiments, the positive phase I-path baseband data, the negative phase I-path baseband data, the positive phase Q-path baseband data, and the negative phase Q-path baseband data are all baseband data transmitted in parallel with multiple bits.

[0009] The number of the at least one baseband data generation unit is the same as the number of bits transmitted in parallel, and each baseband data generation unit in the at least one baseband data generation unit is used to process different bits of baseband data transmitted in parallel.

[0010] The number of the at least one basic unit is the same as the number of bits transmitted in parallel, and each basic unit in the at least one basic unit is used to process the multiphase baseband data output by different baseband data generation units.

[0011] In some embodiments, each baseband data generation unit in the at least one baseband data generation unit includes four multiphase data generators, the four multiphase data generators being respectively corresponding to the positive phase I-path baseband data, the anti-phase I-path baseband data, the positive phase Q-path baseband data, and the anti-phase Q-path baseband data;

[0012] Each of the four multiphase data generators is used to output the baseband data corresponding to that multiphase data in a multiphase manner.

[0013] In some embodiments, each of the four multiphase data generators includes:

[0014] Multiple first-stage D flip-flops are provided, with the clock input of each first-stage D flip-flop being used to connect to baseband clock signals of different phases; the D input of each first-stage D flip-flop is used to receive specified baseband data corresponding to the multiphase data generator; each first-stage D flip-flop can sample the specified baseband data according to the input baseband clock signal and output the sampled specified baseband data through the Q output of the first-stage D flip-flop.

[0015] In some embodiments, the plurality of first-level D flip-flops are arranged sequentially according to the phase of their respective baseband clock signals;

[0016] For the plurality of first-level D flip-flops arranged in sequence, the phase difference of the baseband clock signals corresponding to any two adjacent first-level D flip-flops is the same, and the Q output of the Nth first-level D flip-flop is connected to the D input of the (N+1)th first-level D flip-flop, where N is a positive integer.

[0017] In some embodiments, the plurality of first-level D flip-flops are arranged sequentially according to the phase of their respective baseband clock signals;

[0018] For the plurality of first-level D flip-flops arranged in sequence, the phase difference of the baseband clock signals corresponding to every two adjacent first-level D flip-flops is the same, and the Q output terminal of the Nth first-level D flip-flop is connected to the D input terminal of the (N+2)th first-level D flip-flop, where N is a positive integer.

[0019] A retiming D flip-flop is provided before the first and second stage D flip-flops. The retiming D flip-flop is used to delay the specified baseband data by the phase difference of the clock signal between the first and second stage D flip-flops. The D input terminals of the first and second stage D flip-flops are respectively connected to the Q output terminal of the retiming D flip-flop.

[0020] In some embodiments, each of the four multiphase data generators further includes:

[0021] Multiple two-stage D flip-flops, each with its clock input terminal connected to a baseband clock signal of a different phase;

[0022] For a first-stage D flip-flop and a second-stage D flip-flop connected to the same baseband clock signal, the Q output of the first-stage D flip-flop is connected to the D input of the second-stage D flip-flop, and the Q output of the second-stage D flip-flop is used to output the baseband data after secondary sampling.

[0023] In some embodiments, each of the inverting input terminals of the I-channel mixer, the non-inverting input terminal of the I-channel mixer, the inverting input terminal of the Q-channel mixer, and the Q-channel mixer has multiple transistors. The multiple transistors at each mixer input terminal correspond one-to-one with the multiphase outputs of the multiphase data generator corresponding to that mixer input terminal. The multiphase outputs of the multiphase data generator corresponding to that mixer input terminal are respectively connected to the gates of their corresponding transistors. The sources of the multiple transistors are grounded, and the drains of the multiple transistors are respectively connected to their respective mixer input terminals.

[0024] In some embodiments, when there are multiple basic units, the drain current of transistors at the same position in the multiple basic units is in a binary relationship when they are turned on.

[0025] In some embodiments, when the digital transmitter is used to transmit radar signals, the gates of multiple transistors at each mixer input are all set to a high level.

[0026] The technical solutions provided in this disclosure may have the following beneficial effects:

[0027] The digital transmitter provided in this disclosure includes at least one baseband data generation unit and at least one basic unit. The at least one baseband data generation unit is used to output baseband data in multiple phases; the baseband data includes I-channel baseband data and Q-channel baseband data, the I-channel baseband data includes positive-phase I-channel baseband data and anti-phase I-channel baseband data, and the Q-channel baseband data includes positive-phase Q-channel baseband data and anti-phase Q-channel baseband data. Each of the at least one basic unit includes an I-channel mixer and a Q-channel mixer. The I-channel mixer is used to mix the multiphase outputs of the positive-phase I-channel baseband data and the multiphase outputs of the negative-phase I-channel baseband data. The Q-channel mixer is used to mix the multiphase outputs of the positive-phase Q-channel baseband data and the multiphase outputs of the negative-phase Q-channel baseband data. The positive-phase outputs of the I-channel mixer and the Q-channel mixer are respectively connected to the positive-phase RF input of the digital transmitter, and the negative-phase outputs of the I-channel mixer and the Q-channel mixer are respectively connected to the negative-phase RF input of the digital transmitter for transmitting RF signals. The digital transmitter provided in this disclosure reduces the need for separate design of DAC, mixer circuit, and PA in conventional digital transmitters, simplifies the circuit structure of conventional digital transmitters, and enables effective bandwidth expansion. Furthermore, by introducing multi-tap filtering for the baseband data, better spectrum shaping can be achieved. Attached Figure Description

[0028] Figure 1 A schematic diagram of the structure of a digital transmitter according to an embodiment of the present disclosure is shown.

[0029] Figure 2 A schematic diagram of the structure of a multiphase data generator according to an embodiment of this disclosure is shown.

[0030] Figure 3 A schematic diagram of another multiphase data generator in an embodiment of this disclosure is shown.

[0031] Figure 4 This diagram illustrates a timing diagram of baseband data in an embodiment of the present disclosure.

[0032] Figure 5 A schematic diagram of the structure of a basic unit in an embodiment of this disclosure is shown.

[0033] Figure 6 This diagram illustrates the process of converting a digital signal into a current signal in an embodiment of the present disclosure.

[0034] Figure 7 A schematic diagram of an impedance matching network according to an embodiment of this disclosure is shown. Detailed Implementation

[0035] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0036] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0037] Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0038] Figure 1 This diagram illustrates the structure of a digital transmitter according to an embodiment of the present disclosure, as shown below. Figure 1 As shown, the digital transmitter includes at least one baseband data generation unit and at least one basic unit.

[0039] The baseband data generation unit can be used to output baseband data in multiple phases. The baseband data can include I-channel and Q-channel baseband data, which are generated by processing the original baseband signal into a baseband digital processing circuit. For example, both the I-channel and Q-channel baseband data are differential signals. That is, the I-channel baseband data includes both positive-phase and negative-phase I-channel baseband data, and the Q-channel baseband data includes both positive-phase and negative-phase Q-channel baseband data.

[0040] Each of the at least one basic unit includes an I-channel mixer and a Q-channel mixer. The I-channel mixer performs mixing processing on the multiphase outputs of the positive-phase I-channel baseband data and the multiphase outputs of the negative-phase I-channel baseband data. The Q-channel mixer performs mixing processing on the multiphase outputs of the positive-phase Q-channel baseband data and the multiphase outputs of the negative-phase Q-channel baseband data. The positive-phase outputs of the I-channel mixer and the Q-channel mixer are respectively connected to the positive-phase RF inputs of the digital transmitter, and the negative-phase outputs of the I-channel mixer and the Q-channel mixer are respectively connected to the negative-phase RF inputs of the digital transmitter.

[0041] In other words, the analog signals output from the I-channel mixer and the Q-channel mixer do not require a power amplifier and can be connected to the RF input of the impedance matching network of the digital transmitter in order to transmit RF signals.

[0042] In some embodiments, the baseband data is multi-bit parallel transmission data. That is, the aforementioned positive-phase I-channel baseband data, negative-phase I-channel baseband data, positive-phase Q-channel baseband data, and negative-phase Q-channel baseband data are all multi-bit parallel transmission baseband data. In this case, the number of baseband data generation units can be the same as the number of bits transmitted in parallel, and the number of basic units can also be the same as the number of bits transmitted in parallel, thereby enabling the digital transmitter provided in this disclosure to process multi-bit parallel data. Each baseband data generation unit is used to process different bits of baseband data transmitted in parallel, and each basic unit is used to process the multiphase baseband data output by different baseband data generation units.

[0043] In some embodiments, each baseband data generation unit in the digital transmitter includes four polyphase data generators. The four polyphase data generators correspond to the aforementioned positive-phase I-channel baseband data, negative-phase I-channel baseband data, positive-phase Q-channel baseband data, and negative-phase Q-channel baseband data, respectively. Each of the four polyphase data generators is used to output the baseband data corresponding to that generator in multiple phases.

[0044] The digital transmitter provided in this disclosure reduces the need for separate design of DAC, mixer circuit, and PA in traditional digital transmitters, simplifies the circuit structure of traditional digital transmitters, and enables effective bandwidth expansion.

[0045] To facilitate understanding, the following will combine... Figure 2 The structure of the multiphase data generator is explained.

[0046] Figure 2 This diagram illustrates the structure of a multiphase data generator according to an embodiment of the present disclosure, as shown below. Figure 2 As shown, a multiphase data generator may include multiple first-stage D flip-flops. The clock input of each first-stage D flip-flop is used to connect to baseband clock signals of different phases. The D input of each first-stage D flip-flop is used to receive specified baseband data corresponding to that multiphase data generator. Each first-stage D flip-flop can sample the specified baseband data according to the input baseband clock signal and output the sampled specified baseband data through the Q output of the first-stage D flip-flop. For example, Figure 2 There are four single-stage D flip-flops and four baseband clock signals with different phases (CLK_IP, CLK_QP, CLK_IN, CLK_QN), which enables... Figure 2The multiphase data generator shown can realize four-phase output of positive / inverted I-channel baseband data or four-phase output of positive / inverted Q-channel baseband data based on four baseband clock signals with different phases.

[0047] Please continue to refer to Figure 2 In a multiphase data generator, multiple first-stage D flip-flops can be arranged sequentially according to the phase of their respective baseband clock signals. For these sequentially arranged first-stage D flip-flops, the phase difference between the baseband clock signals corresponding to any two adjacent first-stage D flip-flops is the same, and the Q output of the Nth first-stage D flip-flop is connected to the D input of the (N+1)th first-stage D flip-flop, where N is a positive integer. For example, Figure 2 The four first-stage D flip-flops can be arranged sequentially according to the phase order CLK_IP, CLK_QP, CLK_IN, and CLK_QN. The phases of these four baseband clock signals are 0°, 90°, 180°, and 360°, respectively, meaning that the baseband clock signals corresponding to any two adjacent first-stage D flip-flops differ by 90°. The D input of the first first-stage D flip-flop is directly connected to the input of either the positive / inverted I-channel or the positive / inverted Q-channel baseband data. The Q output, while completing data sampling, is connected to the D input of the second first-stage D flip-flop. The Q output of the second first-stage D flip-flop, while completing data sampling, is connected to the D input of the third first-stage D flip-flop, and so on. This embodiment will not be elaborated further in this manner.

[0048] Please refer to this again. Figure 2 The multiphase data generator may also include multiple second-stage D flip-flops. The clock input of each second-stage D flip-flop is used to connect to baseband clock signals of different phases. For first-stage and second-stage D flip-flops connected to the same baseband clock signal, the Q output of the first-stage D flip-flop is connected to the D input of the second-stage D flip-flop, and the Q output of the second-stage D flip-flop is used to output the baseband data after double sampling.

[0049] By sampling the data output from each first-stage D flip-flop twice, errors caused by transmission loss during the initial sampling to data output can be eliminated, thus ensuring that the phase difference between the data outputs of any two adjacent D flip-flops is the same. In other words, the transmission line length from the Q output of each second-stage D flip-flop to the corresponding output port in the multiphase data generator can be made the same, ensuring that the resynchronized signal after the second sampling maintains consistent line loss during output.

[0050] It is understood that the terms "first-level" and "second-level" in this disclosure are used only to distinguish the location and connection relationship of the D flip-flops, and are not used to limit the model or function of the D flip-flops.

[0051] Please refer to the following. Figure 3 , Figure 3 A schematic diagram of another multiphase data generator is shown. Figure 3 The multiphase data generator shown still includes multiple first-stage D flip-flops, which are arranged sequentially according to the phase of their respective baseband clock signals, and the phase difference of the baseband clock signals corresponding to any two adjacent first-stage D flip-flops is the same.

[0052] and Figure 2 The difference is that, in Figure 3 In the illustrated multiphase data generator, the Q output of the Nth stage D flip-flop is connected to the D input of the (N+2)th stage D flip-flop, where N is a positive integer. Furthermore, a retiming D flip-flop is positioned before the first and second stage D flip-flops. The retiming D flip-flop delays the specified baseband data by the phase difference of the clock signal between the first and second stage D flip-flops. The D inputs of the first and second stage D flip-flops are respectively connected to the Q output of the retiming D flip-flop. The specified baseband data corresponds to the baseband data generated by this multiphase data generator and can be one of the following: positive I-channel baseband data, negative I-channel baseband data, positive Q-channel baseband data, or negative Q-channel baseband data.

[0053] Because the propagation delay of each first-stage D flip-flop must be less than the phase difference between the clock inputs of two interconnected D flip-flops, and at the same time, it must meet the sampling and holding time requirements of the next first-stage D flip-flop connected to its Q output. Figure 3 The polyphase data generator shown can reduce the timing requirements of sampling by connecting two D flip-flops that are separated by one D flip-flop, thereby making the polyphase data generator suitable for processing high-frequency baseband data.

[0054] It is worth noting that, due to Figure 3 The second stage D flip-flop is no longer connected to the Q output of the first stage D flip-flop. Therefore, by setting a retiming D flip-flop before the first and second stage D flip-flops, the original input baseband data is passed through the retiming D flip-flop and then input to the first and second stage D flip-flops respectively. This ensures the correct timing of the output data and avoids the baseband data that was missed by the first stage D flip-flop due to transmission delay being directly sampled by the second stage D flip-flop.

[0055] The retiming D flip-flop is used to delay specified baseband data by the phase difference of the clock signal between the first-stage D flip-flop and the second-stage D flip-flop. Figure 3In this case, since the clock signal CLK_IP of the first stage D flip-flop is 0° and the clock signal CLK_QP of the second stage D flip-flop is 90°, and the two are 90° apart, CLK_QP can be directly connected to the clock input of the retiming D flip-flop.

[0056] about Figure 3 The description of a two-stage D flip-flop can be found above. Figure 2 The description of the two-stage D flip-flop is not repeated in this embodiment.

[0057] exist Figure 3 On this basis, Figure 4 It shows Figure 3 The data time sequence of each node marked in the middle, where t clk2q This is the propagation delay for a first-level D flip-flop.

[0058] The above combination Figures 2 to 4 The structure of the baseband data generation unit has been described in detail. Below, we will combine... Figures 5 to 6 The structure of the basic unit is explained in detail.

[0059] like Figure 5 As shown, each basic unit can include an I-channel mixer and a Q-channel mixer. The I-channel and Q-channel mixers can be double-balanced mixers, enabling the digital transmitter to achieve better local oscillator leakage suppression. The structure of a double-balanced mixer is shown below. Figure 5 As shown, since double-balanced mixers are commonly used by those skilled in the art, for the sake of brevity, the specific structure of double-balanced mixers will not be described in detail in the embodiments of this disclosure.

[0060] Please continue to refer to Figure 5 In the inverting input (IN) of the I-channel mixer, the non-inverting input (IP) of the I-channel mixer, the inverting input (IN) of the Q-channel mixer, and the inverting input (QN) of the Q-channel mixer, each mixer input has multiple transistors (in... Figure 5 In this system, each mixer input terminal has four transistors (TAP0 to TAP3). The multiple transistors at each mixer input terminal correspond one-to-one with the multiphase outputs of the multiphase data generator corresponding to that mixer input terminal. The multiphase outputs of the multiphase data generator corresponding to that mixer input terminal are respectively connected to the gates of their corresponding transistors. The sources of the multiple transistors are grounded, and the drains of the multiple transistors are respectively connected to the corresponding mixer input terminals.

[0061] For example, please combine Figure 2 and Figure 3 The multiphase data generator shown is in Figure 2 and Figure 3In the illustrated multiphase data generator, the Q output of each second D flip-flop is also connected to a level shifter. The level shifter is used to convert the level of the baseband data after secondary sampling into a level that can drive the multiple transistors to turn on or off.

[0062] Specifically, in Figure 2 and Figure 3 In the process, the four-phase data (TAP0_DATA, TAP1_DATA, TAP2_DATA, TAP3_DATA) output by the multiphase data generator are compared with... Figure 5 The transistors shown correspond one-to-one (TAP0, TAP1, TAP2, TAP3). That is, TAP0_DATA can be connected to the gate of TAP0, TAP1_DATA can be connected to the gate of TAP1, and so on. This embodiment of the present disclosure will not elaborate further. In other words, for the four baseband data channels—positive I-channel baseband data, negative I-channel baseband data, positive Q-channel baseband data, and negative Q-channel baseband data—there is a multiphase data generator that converts them into four-phase outputs. These four-phase outputs are respectively connected to the gates of four transistors at the input terminals of the mixer (corresponding to the baseband data type).

[0063] Please refer to Figure 6 Based on the above implementation, the multiphase baseband data output by the multiphase data generator can be used to control the conduction or cutoff of the transistors at the input of each mixer, thereby converting the baseband data composed of 0 and 1 into a current signal that approximates a triangular wave.

[0064] Please continue to refer to Figure 5 These current signals, after being mixed by the mixer, can output analog signals at radio frequency at various output terminals of the mixer. Specifically, the non-inverting output terminals of the I-channel mixer and the Q-channel mixer are connected to the non-inverting radio frequency input terminal (RF_P) of the digital transmitter, and the inverting output terminals of the I-channel mixer and the Q-channel mixer are connected to the inverting radio frequency input terminal (RF_N) of the digital transmitter.

[0065] In some embodiments, for multiple transistors connected to the same mixer input, the drain current when the transistor is turned on can be adjusted by changing the channel width of each transistor. This allows the current signal resulting from the superposition of the outputs of the individual transistors to better match the shape of a triangular wave, thus achieving a better mixing effect.

[0066] For example, each multiphase data generator is used to output four-phase data, and each mixer input has four transistors. When the four transistors are turned on, the ratio of the drain current output is 1:4:2:1 (i.e., corresponding to...). Figure 5 The transistors are labeled ×1, ×4, ×2, and ×1.

[0067] Thus, the embodiments of this disclosure can utilize a set of transistors at each mixer input to achieve arrayed multi-phase input, thereby realizing equivalent digital domain windowed filtering, enabling the digital transmitter to obtain better out-of-band filtering capabilities and better spectral characteristics. By increasing the number of transistors in each set, a smoother filtering effect can also be obtained, thereby giving the digital transmitter better performance. At the same time, by introducing multi-tap (multi-transistor) filtering to the baseband data, better spectral shaping can be achieved.

[0068] In some embodiments, when there are multiple basic units, the drain current outputs of transistors at the same location in the multiple basic units, when turned on, exhibit a binary relationship. For example, when the baseband data is transmitted in three bits in parallel, there are three baseband data generation units and three basic units. The three baseband data generation units have identical structures and are used to receive different bits of baseband data input in parallel. However, the drain current outputs of the transistors in the three basic units differ when turned on. Continuing the previous example, suppose the four transistors used to receive the first bit of four-phase baseband data have drain currents of 1A, 4A, 2A, and 1A respectively when turned on (these current values ​​are for illustrative purposes only and do not represent actual current values). Then, the four transistors used to receive the second bit of four-phase baseband data have drain currents of 2A, 8A, 4A, and 2A respectively when turned on. And the four transistors used to receive the third bit of four-phase baseband data have drain currents of 4A, 16A, 8A, and 4A respectively when turned on.

[0069] In other words, in the three basic units corresponding to three bits of baseband data, the ratio of the drain current output of the transistors at the same location when they are turned on is 1:2:4, i.e., 2 0 :2 1 :2 2 .

[0070] This concludes the detailed explanation of the structure and implementation principle of the basic unit.

[0071] Next, please refer to Figure 7 , Figure 7 A schematic diagram of an impedance matching network according to an embodiment of this disclosure is shown. Figure 7 As shown, after receiving the analog signal output from the basic unit, the non-inverting RF input (RF_P) and inverting RF input (RF_N) of the digital transmitter can... Figure 7 The impedance matching network shown achieves impedance matching with the antenna, thereby enabling the antenna to output radio frequency signals.

[0072] It is worth noting that the digital transmitter provided in this embodiment can also be used for transmitting radar signals. When the digital transmitter is used to transmit radar signals, the gates of multiple transistors at the input of each mixer in the basic unit can be set to a high level, thereby maximizing the output power of the radar signal.

[0073] For example, it can be Figure 2 and Figure 3 A continuous high-level signal is input to the input terminal of each level converter, thereby setting the gate of each transistor to a high level.

[0074] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0075] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A digital transmitter, characterized in that, include: At least one baseband data generation unit is provided for multi-phase output of baseband data. Each baseband data generation unit includes four multi-phase data generators, which correspond to positive-phase I-channel baseband data, negative-phase I-channel baseband data, positive-phase Q-channel baseband data, and negative-phase Q-channel baseband data, respectively. Each multi-phase data generator includes multiple first-stage D flip-flops, the clock input of each first-stage D flip-flop being used to connect to baseband clock signals of different phases. The D input of each first-stage D flip-flop is used to receive the specified baseband data corresponding to that multi-phase data generator. Each first-stage D flip-flop samples the specified baseband data according to the input baseband clock signal and outputs the sampled specified baseband data through the Q output of the first-stage D flip-flop. At least one basic unit, each basic unit including an I-channel mixer and a Q-channel mixer, wherein the I-channel mixer is used to perform mixing processing on the multiphase output of the positive-phase I-channel baseband data and the multiphase output of the negative-phase I-channel baseband data, and the Q-channel mixer is used to perform mixing processing on the multiphase output of the positive-phase Q-channel baseband data and the multiphase output of the negative-phase Q-channel baseband data; the positive-phase output terminals of the I-channel mixer and the Q-channel mixer are respectively connected to the positive-phase RF input terminal of the digital transmitter, and the negative-phase output terminals of the I-channel mixer and the Q-channel mixer are respectively connected to the negative-phase RF input terminal of the digital transmitter, so as to transmit RF signals externally.

2. The digital transmitter according to claim 1, characterized in that, The positive phase I-path baseband data, the negative phase I-path baseband data, the positive phase Q-path baseband data, and the negative phase Q-path baseband data are all baseband data transmitted in parallel with multiple bits. The number of the at least one baseband data generation unit is the same as the number of bits transmitted in parallel, and each baseband data generation unit in the at least one baseband data generation unit is used to process different bits of baseband data transmitted in parallel. The number of the at least one basic unit is the same as the number of bits transmitted in parallel, and each basic unit in the at least one basic unit is used to process the multiphase baseband data output by different baseband data generation units.

3. The digital transmitter according to claim 1, characterized in that, The plurality of first-level D flip-flops are arranged sequentially according to the phase of their respective baseband clock signals; For the plurality of first-level D flip-flops arranged in sequence, the phase difference of the baseband clock signals corresponding to any two adjacent first-level D flip-flops is the same, and the Q output of the Nth first-level D flip-flop is connected to the D input of the (N+1)th first-level D flip-flop, where N is a positive integer.

4. The digital transmitter according to claim 1, characterized in that, The plurality of first-level D flip-flops are arranged sequentially according to the phase of their respective baseband clock signals; For the plurality of first-level D flip-flops arranged in sequence, the phase difference of the baseband clock signals corresponding to every two adjacent first-level D flip-flops is the same, and the Q output terminal of the Nth first-level D flip-flop is connected to the D input terminal of the (N+2)th first-level D flip-flop, where N is a positive integer. A retiming D flip-flop is provided before the first and second stage D flip-flops. The retiming D flip-flop is used to delay the specified baseband data by the phase difference of the clock signal between the first and second stage D flip-flops. The D input terminals of the first and second stage D flip-flops are respectively connected to the Q output terminal of the retiming D flip-flop.

5. The digital transmitter according to claim 3 or 4, characterized in that, Each of the four multiphase data generators further includes: Multiple two-stage D flip-flops, each with its clock input terminal connected to a baseband clock signal of a different phase; For a first-stage D flip-flop and a second-stage D flip-flop connected to the same baseband clock signal, the Q output of the first-stage D flip-flop is connected to the D input of the second-stage D flip-flop, and the Q output of the second-stage D flip-flop is used to output the baseband data after secondary sampling.

6. The digital transmitter according to claim 1, characterized in that, In the non-inverting input terminal of the I-channel mixer, the inverting input terminal of the I-channel mixer, the non-inverting input terminal of the Q-channel mixer, and the inverting input terminal of the Q-channel mixer, each mixer input terminal is provided with multiple transistors. The multiple transistors of each mixer input terminal correspond one-to-one with the multiphase outputs of the multiphase data generator corresponding to that mixer input terminal. The multiphase outputs of the multiphase data generator corresponding to that mixer input terminal are respectively connected to the gates of their corresponding transistors. The sources of the multiple transistors are grounded, and the drains of the multiple transistors are respectively connected to the corresponding mixer input terminals.

7. The digital transmitter according to claim 6, characterized in that, When there are multiple basic units, the magnitude ratio of the drain current output by transistors at the same position in the multiple basic units when they are turned on is binary.

8. The digital transmitter according to claim 6, characterized in that, When the digital transmitter is used to transmit radar signals, the gates of multiple transistors at the input of each mixer are all set to a high level.

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