Pixel driving device and display panel

Abstract

Embodiments of the present application provide a pixel driving device and a display panel, wherein the pixel driving device comprises: a first driving circuit comprising a first pull-up module, a first output module, a first pull-down module and a first reset module formed by a plurality of first transistors, the first driving circuit having a first pull-up node and a first pull-down node; and a second driving circuit comprising a second pull-up module, a second output module and a second reset module formed by a plurality of second transistors, the number of the second transistors being less than the number of the first transistors; wherein the second driving circuit has a second pull-down node coupled to the first pull-down node, or the second driving circuit has a second pull-up node coupled to the first pull-up node. According to the technology of the present application, the number of transistors of the pixel driving circuit can be reduced, thereby reducing the occupation of the pixel driving circuit in the horizontal space, and further meeting the display requirement of narrow frame.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display devices, and in particular to a pixel driving device and a display panel. BACKGROUND

[0002] For the field of liquid crystal displays (LCD), major manufacturers are pursuing high refresh rate and low power consumption of display screens, and the requirements for the frame specifications of display screens are becoming higher and higher. In order to meet the requirement of high refresh rate, a scheme of double-side simultaneous driving by GOA (Gate On Array) is proposed in the related technology, that is, the GOA unit is used to control the gate output of each row of display pixels to ensure the charging rate of the pixels. Compared with the single-side GOA driving mode, the longitudinal space of each GOA in the scheme becomes one pixel size from two pixel sizes, the longitudinal space becomes smaller and the transverse space becomes larger, thereby increasing the frame size of the display screen. In terms of low power consumption, the GOA signal line width is increased, the resistance and load of the line are reduced, but the increase of the line width increases the wiring space of the GOA cascade relationship line, which also increases the frame size of the display screen. In summary, the display screen in the related technology is difficult to meet the requirement of narrow frame design while meeting the requirements of high refresh rate and low power consumption. SUMMARY

[0003] Embodiments of the present application provide a pixel driving device and a display panel to solve or alleviate one or more technical problems in the prior art.

[0004] In a first aspect, embodiments of the present application provide a pixel driving device, comprising: a first driving circuit comprising a first pull-up module, a first output module, a first pull-down module and a first reset module formed by a plurality of first transistors coupled, the first driving circuit having a first pull-up node and a first pull-down node; and a second driving circuit comprising a second pull-up module, a second output module and a second reset module formed by a plurality of second transistors coupled, the number of the second transistors being less than the number of the first transistors; wherein the second driving circuit has a second pull-down node coupled to the first pull-down node, or the second driving circuit has a second pull-up node coupled to the first pull-up node.

[0005] In an embodiment, the first pull-up module is coupled with the first input signal terminal and the first pull-up node respectively, and is configured to provide the first input signal to the first pull-up node in response to the control of the first input signal terminal; the first output module is coupled with the first clock signal terminal, the first pull-up node and the first output signal terminal respectively, and is configured to provide the signal of the first clock signal terminal to the first output signal terminal under the control of the first pull-up node; the first pull-down module is coupled with the first pull-up node, the first pull-down node and the first low-level signal terminal respectively, and is configured to provide the signal of the second low-level signal terminal to the first pull-down node and the first control node under the control of the first pull-up node; and the first reset module is coupled with the first reset signal terminal, the first pull-up node and the first low-level signal terminal respectively, and is configured to provide the signal of the first low-level signal terminal to the first pull-up node under the control of the first reset signal terminal.

[0006] In an embodiment, the first driving circuit further comprises a first reset control module, the first reset control module is coupled with the first start signal terminal, the first low-level signal terminal and the first pull-up node respectively, and is configured to provide the signal of the first low-level terminal to the first pull-up node in response to the control of the first start signal terminal.

[0007] In an embodiment, the first driving circuit further comprises a first noise reduction module, the first noise reduction module is coupled with the first high-level signal terminal, the first pull-down node and the first control node respectively, and is configured to provide the signal of the first high-level signal terminal to the first control node in response to the control of the first high-level signal terminal, and provide the signal of the first high-level signal terminal to the first pull-down node under the control of the first control node.

[0008] In an embodiment, the second pull-up module is coupled with the second input signal terminal and the second pull-up node respectively, and is configured to provide the second input signal to the second pull-up node in response to the control of the second input signal terminal; the second output module is coupled with the second clock signal terminal, the second pull-up node and the second output signal terminal respectively, and is configured to provide the signal of the second clock signal terminal to the second output signal terminal under the control of the second pull-up node; and the second reset module is coupled with the second reset signal terminal, the second pull-up node and the second low-level signal terminal respectively, and is configured to provide the signal of the second low-level signal terminal to the second pull-up node under the control of the second reset signal terminal.

[0009] In an embodiment, the pixel driving apparatus comprises at least one column of driving circuits located at least one side of the display area, each column of driving circuits comprises a plurality of second driving circuits and a plurality of first driving circuits arranged in a column, and the second driving circuits and the first driving circuits are arranged alternately; adjacent second driving circuits and first driving circuits are used to drive adjacent two rows of pixel units respectively; wherein the second driving circuit has a second pull-down node, and the second pull-down node of the second driving circuit is coupled with a first pull-down node of the first driving circuit adjacent in the column direction.

[0010] In an embodiment, the at least one column of driving circuits comprises two columns of driving circuits respectively located at opposite sides of the display area; wherein the second driving circuit in any column of driving circuits is arranged correspondingly in the row direction with the first driving circuit in the other column of driving circuits, and is used to drive the same row of pixel units correspondingly.

[0011] In an embodiment, the second driving circuit further has a second pull-up node, and the second driving circuit further comprises a second pull-down module and a second reset control module; the second pull-down module is coupled with the second pull-up node, the second pull-down node and the second low-level signal terminal respectively, and is configured to provide the signal of the second low-level signal terminal to the second pull-down node and the second control node under the control of the second pull-up node; the second reset control module is coupled with the second start signal terminal, the second low-level signal terminal and the second pull-up node respectively, and is configured to provide the signal of the second low-level terminal to the second pull-up node in response to the control of the second start signal terminal.

[0012] In an embodiment, the pixel driving apparatus comprises two columns of driving circuits respectively located at opposite sides of the display area, each column of driving circuits comprises a plurality of second driving circuits and a plurality of first driving circuits arranged in a column, and the second driving circuits and the first driving circuits are arranged alternately; wherein the second driving circuit in any column of driving circuits is arranged correspondingly in the row direction with the first driving circuit in the other column of driving circuits; the second driving circuit has a second pull-down node, and the second pull-down node of the second driving circuit is coupled with a first pull-down node of the first driving circuit arranged correspondingly in the row direction.

[0013] In a second aspect, the embodiments of the present application provide a display panel comprising the pixel driving apparatus of any of the above embodiments.

[0014] According to the pixel driving device provided in the embodiment of the present application, by arranging the first driving circuit and the second driving circuit, and the number of the first transistors of the first driving circuit is greater than the number of the second transistors of the second driving circuit, and the first pull-up node of the first driving circuit is coupled with the second pull-up node of the second driving circuit or the first pull-down node of the first driving circuit is coupled with the second pull-down node of the second driving circuit, the first driving circuit and the second driving circuit can be applied to the GOA double-side simultaneous driving, and compared with the two same 11T1C driving circuits in the prior art, the number of transistors is significantly reduced, thereby facilitating the reduction of the horizontal space of the driving device, and further facilitating the reduction of the frame size of the display product.

[0015] The above summary is intended to illustrate, but not limit, the present application in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features will be readily apparent to those skilled in the art from the drawings and detailed description of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0016] In the drawings, like reference numerals refer to same or similar functionalities throughout the several views. The drawings are not necessarily to scale. It is to be understood that the drawings only depict several embodiments of the present application and are not to be considered as limiting the scope of the present application.

[0017] Figure 1 A schematic diagram of a pixel driving circuit in the prior art is shown;

[0018] Figure 2 A driving circuit schematic diagram of a pixel driving device according to an embodiment of the present application is shown;

[0019] Figure 3 A schematic diagram of the cascade relationship between the first driving circuit and the second driving circuit of a pixel driving device according to an embodiment of the present application is shown;

[0020] Figure 4 A timing diagram of a pixel driving device according to an embodiment of the present application is shown;

[0021] Figure 5 A driving circuit schematic diagram of another pixel driving device according to an embodiment of the present application is shown;

[0022] Figure 6 A schematic diagram of the cascade relationship between the first driving circuit and the second driving circuit of another pixel driving device according to an embodiment of the present application is shown;

[0023] Figure 7 A timing diagram of another pixel driving device according to an embodiment of the present application is shown;

[0024] Figure 8 A reduced bezel effect diagram of a pixel driving device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] In the following, only certain exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and the description are considered to be exemplary in nature rather than limiting.

[0026] In the description of this specification, it is understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0027] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0028] Figure 1 A schematic diagram of a pixel driving circuit in the related art is shown. As Figure 1 shown, a pixel driving circuit is proposed in the related art, which can be applied to a GOA double-side simultaneous driving scheme. The pixel driving circuit can be arranged in two columns and in the bezel area on the opposite sides of the display area, and the two ends of each row of pixel units in the display area are provided with the pixel driving circuit for driving. Each pixel driving circuit can adopt the 11T1C architecture in the diagram. It should be noted that the double-side GOA simultaneous driving scheme of the pixel driving circuit with the 11T1C architecture in the related art cannot meet the narrow bezel display requirement due to the large space occupied by the pixel driving circuit in the lateral direction because of the large number of transistors included in the pixel driving circuit.

[0029] In view of the above-mentioned defects in the related technologies, this application provides a pixel driving device 1, which can reduce the number of transistors in the pixel driving circuit, thereby reducing the occupancy of the pixel driving circuit in the horizontal space, and thus meeting the display requirements of narrow bezels.

[0030] Figure 2 This diagram illustrates a driving circuit diagram of a pixel driving device 1 according to an embodiment of this application. Figure 2 As shown, the pixel driving device 1 in this embodiment may include a first driving circuit 10 and a second driving circuit 20. Specifically, the first driving circuit 10 includes a first pull-up module 11, a first output module 12, a first pull-down module 13, and a first reset module 14, all formed by coupling a plurality of first transistors. The first driving circuit 10 has a first pull-up node and a first pull-down node. The second driving circuit 20 includes a second pull-up module 21, a second output module 22, and a second reset module 23, all formed by coupling a plurality of second transistors. The number of second transistors is less than the number of first transistors. The second driving circuit 20 may have a second pull-down node coupled to the first pull-down node; or, the second driving circuit 20 may have a second pull-up node coupled to the first pull-up node.

[0031] In the embodiments of this application, one of the first driving circuit 10 and the second driving circuit 20 can be a stable output unit, and the other can be a compensation output unit. For example, the first driving circuit 10 can be a stable output unit, used to output a stable gate driving signal to the pixel unit of the corresponding row; the second driving circuit 20 can be a compensation output unit, used to compensate for the voltage drift of the pixel unit of the corresponding row caused by time, temperature changes or other factors, thereby improving display stability.

[0032] In the description of this application, coupling may include: direct physical contact between the two ends or indirect connection between the two ends (such as connection between the two ends via a signal line). This disclosure does not limit the coupling method between the two ends.

[0033] In some specific examples, the first driving circuit 10 can specifically adopt a 10T1C circuit, and the second driving circuit 20 can specifically adopt a 7T1C circuit. It can be understood that the first driving circuit 10 can include 10 first transistors and one capacitor, and the second driving circuit 20 can include 7 second transistors and one capacitor. The first driving circuit 10 can have a first pull-up node and a first pull-down node, and the second driving circuit 20 can have a second pull-up node and a second pull-down node. The first pull-down node of the first driving circuit 10 is coupled with the second pull-down node of the second driving circuit 20. It can be understood that the first driving circuit 10 and the second driving circuit 20 can be located on one side of the display area and arranged adjacently in the column direction. The column direction can be understood as the arrangement direction of the pixel units in the display area in the vertical direction. The second driving circuit 20 is configured to drive the Nth row of pixel units, and the first driving circuit 10 is configured to drive the N+1th row of pixel units, where N is an integer greater than or equal to 1. By coupling the second pull-down node of the second driving circuit 20 with the first pull-down node of the first driving circuit 10, the pull-down state of the first pull-down node of the first driving circuit 10 can be synchronized to the second pull-down node of the second driving circuit 20, so as to realize the noise reduction of the second pull-up node.

[0034] In some specific examples, the first driving circuit 10 can specifically adopt a 10T1C circuit, and the second driving circuit 20 can specifically adopt a 7T1C circuit. It can be understood that the first driving circuit 10 can include 10 first transistors and one capacitor, and the second driving circuit 20 can include 7 second transistors and one capacitor. The first driving circuit 10 can have a first pull-up node and a first pull-down node, and the second driving circuit 20 can have a second pull-up node and a second pull-down node. The first pull-down node of the first driving circuit 10 is coupled with the second pull-down node of the second driving circuit 20. It can be understood that the first driving circuit 10 and the second driving circuit 20 can be located on one side of the display area and arranged adjacently in the column direction. The column direction can be understood as the arrangement direction of the pixel units in the display area in the vertical direction. The second driving circuit 20 is configured to drive the Nth row of pixel units, and the first driving circuit 10 is configured to drive the N+1th row of pixel units, where N is an integer greater than or equal to 1. By coupling the second pull-down node of the second driving circuit 20 with the first pull-down node of the first driving circuit 10, the pull-down state of the first pull-down node of the first driving circuit 10 can be synchronized to the second pull-down node of the second driving circuit 20, so as to realize the noise reduction of the second pull-up node.

[0035] In the embodiments of the present application, the first transistors included in the first driving circuit 10 and the second transistors included in the second driving circuit 20 can all adopt NMOS tubes. In the case where all the transistors are NMOS tubes, the effective level signals of the transistors are high level signals.

[0036] According to the pixel driving device 1 provided by the embodiment of the present application, by arranging the first driving circuit 10 and the second driving circuit 20, and arranging the number of the first transistors of the first driving circuit 10 to be greater than the number of the second transistors of the second driving circuit 20, and coupling the first pull-up node of the first driving circuit 10 with the second pull-up node of the second driving circuit 20 or coupling the first pull-down node of the first driving circuit 10 with the second pull-down node of the second driving circuit 20, the first driving circuit 10 and the second driving circuit 20 can be applied to the GOA double-side simultaneous driving, and compared with the two same 11T1C driving circuits in the prior art, the number of transistors is significantly reduced, thereby facilitating the reduction of the horizontal space of the driving device, and further facilitating the reduction of the frame size of the display product.

[0037] In an embodiment, the first pull-up module 11 is coupled with the first input signal end and the first pull-up node respectively, and is configured to provide the first input signal to the first pull-up node in response to the control of the first input signal end; the first output module 12 is coupled with the first clock signal end, the first pull-up node and the first output signal end respectively, and is configured to provide the signal of the first clock signal end to the first output signal end under the control of the first pull-up node; the first pull-down module 13 is coupled with the first pull-up node, the first pull-down node and the first low-level signal end respectively, and is configured to provide the signal of the second low-level signal end to the first pull-down node and the first control node under the control of the first pull-up node; and the first reset module 14 is coupled with the first reset signal end, the first pull-up node and the first low-level signal end respectively, and is configured to provide the signal of the first low-level signal end to the first pull-up node under the control of the first reset signal end.

[0038] Optionally, the second pull-up module 21 is coupled with the second input signal end and the second pull-up node respectively, and is configured to provide the second input signal to the second pull-up node in response to the control of the second input signal end; the second output module 22 is coupled with the second clock signal end, the second pull-up node and the second output signal end respectively, and is configured to provide the signal of the second clock signal end to the second output signal end under the control of the second pull-up node; the second reset module 23 is coupled with the second reset signal end, the second pull-up node and the second low-level signal end respectively, and is configured to provide the signal of the second low-level signal end to the second pull-up node under the control of the second reset signal end.

[0039] It can be understood that in actual use, the types of the transistors are not limited. The transistors can be set to NMOS or PMOS as needed, and the signals of the first input signal terminal INPUT1, the first low-level signal terminal VGL1, the first clock signal terminal CLK1, the first reset signal terminal RST1, the second input signal terminal INPUT2, the second low-level signal terminal VGL2, the second clock signal terminal CLK2, and the second reset signal terminal RST2 are set correspondingly. In the case where the transistors included in the first driving circuit 10 and the second driving circuit 20 are all PMOS, the active level signals of the transistors are low-level signals.

[0040] It should be noted that in the display panel, the first output signal terminal OUTPUT1 of the first driving circuit 10 and the second output signal terminal OUTPUT2 of the second driving circuit 20 can be connected with the gate line to provide a gate driving signal to the gate line. In a frame, the working state of the first driving circuit 10 can include a driving stage and a reset stage. In the driving stage, the first pull-up module 11 provides the signal of the first input signal terminal INPUT1 to the first pull-up node PU1 under the control of the first input signal terminal INPUT1, and at this time, the voltage of the pull-up stage PU1 is the same as the voltage of the first input signal terminal INPUT1; the first output module 12 provides the signal of the first clock signal terminal CLK1 to the first output signal terminal OUTPUT1 under the control of the first pull-up node PU1, to provide a gate signal to the gate line through the first output signal terminal OUTPUT1 to drive the pixel units corresponding to a row to display. In the reset stage, the first reset module 14 inputs the signal of the first low-level signal terminal VGL1 to the first pull-up node PU1 under the control of the first reset signal terminal RST1, and at this time, the voltage of the pull-up stage PU1 is the same as the voltage of the first low-level signal terminal VGL1; the first output module 12 is closed, and the gate line has no gate signal output, and the pixel units corresponding to a row do not display. The signal input by the first input signal terminal INPUT1 is a high-level signal, and the signal input by the first low-level signal terminal VGL1 is a low-level signal.

[0041] In an embodiment, as shown in Figure 2 The first driving circuit 10 further includes a first reset control module 15, which is coupled with the first start signal terminal, the first low-level signal terminal, and the first pull-up node, and is configured to provide the signal of the first low-level terminal to the first pull-up node in response to the control of the first start signal terminal.

[0042] In an embodiment, continuing to refer to Figure 2As shown, the first drive circuit 10 further includes a first noise reduction module 16, which is coupled with the first high-level signal end, the first pull-down node and the first control node, and is configured to provide the signal of the first high-level signal end to the first control node in response to the control of the first high-level signal end, and provide the signal of the first high-level signal end to the first pull-down node under the control of the first control node.

[0043] Figure 3 A schematic diagram of the cascade relationship of the first drive circuit 10 and the second drive circuit 20 of the pixel driving device 1 according to an embodiment of the present application is shown. The following will be described with reference to the schematic diagram. Figure 2 and Figure 3 The pixel driving device 1 according to an embodiment of the present application will be described with a specific example. In the example, the first drive circuit 10 and the second drive circuit 20 can be arranged adjacent in the column direction.

[0044] As shown in FIG. 1, the pixel driving device 1 includes a plurality of pixel units arranged in a matrix, and each pixel unit includes a first drive circuit 10 and a second drive circuit 20 arranged adjacent in the row direction. Figure 2 and Figure 3 As shown, the pixel driving device 1 includes at least one column of drive circuits located at least one side of the display area, each column of drive circuits includes a plurality of second drive circuits 20 and a plurality of first drive circuits 10 arranged in a column, and the second drive circuits 20 and the first drive circuits 10 are arranged alternately. The adjacent second drive circuit 20 and the first drive circuit 10 are used to drive the adjacent two rows of pixel units respectively. The second drive circuit 20 has a second pull-down node, and the second pull-down node of the second drive circuit 20 is coupled with the first pull-down node of the first drive circuit 10 adjacent in the column direction.

[0045] In the embodiment, the at least one column of drive circuits includes two columns of drive circuits located at opposite sides of the display area respectively. The second drive circuit 20 in any column of drive circuits is arranged corresponding to the first drive circuit 10 in the other column of drive circuits in the row direction, and is used to drive the same row of pixel units together.

[0046] Specifically, the first driving circuit 10 can adopt a 10T1C circuit, and specifically can include a first pull-up module 11, a first output module 12, a first pull-down module 13, a first reset module 14, a first reset control module 15, a first noise reduction module 16, a third reset control module 17, and a fourth reset control module 18. The first pull-up module 11 includes a first transistor M1, the source and the gate of the first transistor M1 are coupled with a first input signal end INPUT1 respectively, and the drain is coupled with a first pull-up node PU1. The first output module 12 includes a first transistor M3, the source of the first transistor M3 is coupled with a first clock signal end CLK1, the gate is coupled with the first pull-up node PU1, and the drain is coupled with a first output signal end OUTPUT1. The first pull-down module 13 includes a first transistor M8 and a first transistor M10; the source of the first transistor M8 is coupled with a first control node PD CN, the gate is coupled with the first pull-up node PU1, and the drain is coupled with a first low-level signal end VGL1; the source of the first transistor M10 is coupled with the first pull-up node PU1, the gate is coupled with a first pull-down node PD1, and the drain is coupled with the first low-level signal end VGL1. The first reset module 14 includes a first transistor M2, the source of the first transistor M2 is coupled with the first pull-up node PU1, the gate is coupled with a first reset signal end RST1, and the drain is coupled with the first low-level signal end VGL1. The first reset control module 15 includes a first transistor M7, the source of the first transistor M7 is coupled with the first pull-up node PU1, the gate is coupled with a first start signal end stv01, and the drain is coupled with the first low-level signal end VGL1. The first noise reduction module 16 includes a first transistor M5 and a first transistor M9; the source of the first transistor M5 is coupled with a first high-level signal end VGH1, the gate is coupled with a first control node, and the drain is coupled with the first pull-down node PD1; the source and the gate of the first transistor M9 are coupled with the first high-level signal end VGH1 respectively, and the drain is coupled with the first control node PD CN. The third reset control module 17 includes a first transistor M11, the source of the first transistor M11 is coupled with the first output signal end OUTPUT1, the gate is coupled with the first pull-down node PD1, and the drain is coupled with the first low-level signal end VGL1. The fourth reset control module 18 includes a first transistor M4, the source of the first transistor M4 is coupled with the first signal output end OUTPUT1, the gate is coupled with the first start signal end stv01, and the drain is coupled with the first low-level signal end.

[0047] The second driving circuit 20 can adopt a 7T1C circuit, and can include a second pull-up module 21, a second output module 22, and a second reset module 23. The second pull-up module 21 includes a second transistor M1, a source and a gate of the second transistor M1 are coupled with a second input signal end INPUT2 respectively, and a drain is coupled with a second pull-up node. The second output module 22 includes a second transistor M3, a source of the second transistor M3 is coupled with a second clock signal end CLK2, a gate is coupled with the second pull-up node PU2, and a drain is coupled with a second output signal end OUTPUT2. The second reset module 23 includes a second transistor M2, a source of the second transistor M2 is coupled with the second pull-up node PU2, a gate is coupled with a second reset signal end RST2, and a drain is coupled with a second low-level signal end VGL2.

[0048] Further, the second driving circuit 20 can further include a second pull-down module 24 and a second reset control module. The second pull-down module 24 includes a second transistor M8 and a second transistor M10; a source of the second transistor M8 is coupled with a second pull-down node PD2, a gate is coupled with the second pull-up node PU2, and a drain is coupled with the second low-level signal end VGL2; a source of the second transistor M10 is coupled with the second pull-up node PU2, a gate is coupled with the second pull-down node PD2, and a drain is coupled with the second low-level signal end VGL2. The second reset control module includes a second transistor M7, a source of the second transistor M7 is coupled with the second pull-up node PU2, a gate is coupled with a second start signal end stv02, and a drain is coupled with the second low-level signal end VGL2. The second pull-down module 24 is configured to provide a signal of the second low-level signal end VGL2 to the second pull-down node PD2 and a second control node under control of the second pull-up node PU2.

[0049] In addition, the second driving circuit 20 can further include a sixth reset control module 26. The sixth reset control module 26 can include a second transistor M4, a source of the second transistor M4 is coupled with the second output signal end, a gate is coupled with the second start signal end stv02, and a drain is coupled with the second low-level signal end VGL2.

[0050] It should be noted that if the normal 11T1C circuit is used as the first drive circuit 10 and the 7T1C circuit is used as the second drive circuit 20 to construct the GOA double-side simultaneous drive model, the TFT M6 that controls the discharge of the pull-down node will exist. If the transistor M6 in the compensation output unit 7T1C circuit is removed, when the pull-up node in the 7T1C circuit is raised, the pull-down node is still in the high state (the transistor M10 is turned on to discharge the pull-up node), which causes the pull-up node to fail to continuously rise. When the pull-up node of the first drive circuit 10 is high, the pull-up node of the second drive circuit 20 is raised again. Therefore, the transistor M6 in the traditional 11T1C architecture needs to be removed, and finally the first drive circuit 10 formed by the 10T1C circuit and the second drive circuit 20 formed by the 7T1C circuit in the GOA double-side drive model mentioned in the present solution are formed.

[0051] Figure 4 A timing diagram of a pixel driving device 1 of an embodiment of the present application is shown, and the working principle of the pixel driving device 1 of the above specific example is described below. Figure 4 The pixel driving device 1 of the embodiment of the present application specifically includes the following control processes: Figure 4

[0052] (1) The pull-up stage includes the first pull-up stage and the second pull-up stage. In the first pull-up stage: about the second drive circuit 20, in response to the input of the valid level signal of the second input signal end INPUT2, the second transistor M1 is turned on to provide the signal of the second input signal end INPUT2 to the second pull-up node PU2, and the voltage of the second pull-up node PU2 is pulled up to the first voltage value. About the first drive circuit 10, in response to the input of the valid level signal of the first input signal end INPUT1, the first transistor M1 is turned on to provide the signal of the first input signal end INPUT1 to the first pull-up node PU1, and the voltage of the first pull-up node PU1 is pulled up to the first voltage value.

[0053] In the second pull-up stage: about the second drive circuit 20, in response to the voltage of the first pull-up node PU1 being pulled up to the first voltage value, the second transistor M3 is turned on, the high level signal input from the second clock signal end CLK2 is output to the second pull-up node PU2, and the voltage value of the second pull-up node PU2 is pulled up to the second voltage value again. About the first drive circuit 10, in response to the voltage of the first pull-up node PU1 being pulled up to the first voltage value, the first transistor M3 is turned on, the high level signal input from the first clock signal end CLK1 is output to the first pull-up node PU1, and the voltage value of the first pull-up node PU1 is pulled up to the first voltage value.

[0054] ​Since the second pull-down node PD2 of the second driving circuit 20 is coupled with the first pull-down node PD1 of the first driving circuit 10, the first driving circuit 10 can make the second pull-down node of the second driving circuit 20 also in the pull-down state when the first pull-down node is in the pull-down state, so as to make the second transistor M10 conductive and realize the noise reduction of the second pull-up node.

[0055] (2) Reset stage: as to the second driving circuit 20, the second transistor M2 is conductive in response to the second reset signal of the second reset signal end RST2, and a low level signal input from the second low level signal end is provided to the second pull-up node, so as to reset the second pull-up node to the initial voltage value. As to the first driving circuit 10, the first transistor M1 is conductive in response to the first reset signal of the first reset signal end RST1, and a low level signal input from the first low level signal end is provided to the first pull-up node, so as to reset the first pull-up node to the initial voltage value.

[0056] Figure 5 a driving circuit schematic diagram of another pixel driving device 1 of the embodiment of the present application is shown, Figure 6 a cascade relationship schematic diagram of the first driving circuit 10 and the second driving circuit 20 of a pixel driving device 1 of the embodiment of the present application is shown. The following refers to Figure 5 and Figure 6 A pixel driving device 1 of the embodiment of the present application is described in a specific example. In the example, the first driving circuit 10 and the second driving circuit 20 can be arranged in the row direction and respectively located at opposite sides of the display area.

[0057] As shown in Figure 5 and Figure 6 illustratively, the pixel driving device 1 includes two columns of driving circuits respectively located at opposite sides of the display area, each column of driving circuits includes a plurality of second driving circuits 20 and a plurality of first driving circuits 10 arranged in columns, and the second driving circuits 20 and the first driving circuits 10 are arranged alternately. Among them, the second driving circuit 20 in any column of driving circuits is arranged in correspondence with the first driving circuit 10 in the other column of driving circuits in the row direction; the second driving circuit 20 has a second pull-down node, and the second pull-down node of the second driving circuit 20 is coupled with the first pull-down node of the first driving circuit 10 arranged in correspondence in the row direction.

[0058] Specifically, the first driving circuit 10 can adopt an 11T1C circuit, and specifically can include a first pull-up module 11, a first output module 12, a first pull-down module 13, a first reset module 14, a first reset control module 15, a first noise reduction module 16, a third reset control module 17, a fourth reset control module 18, and a fifth reset control module 19. Among them, the first driving circuit 10 can add the fifth reset control module 19 on the basis of the 10T1C circuit in the foregoing specific example. The fifth reset control module 19 can include a first transistor M6, the source of the first transistor M6 is coupled with the first pull-down node PD1, the gate is coupled with the first pull-up node PU1, and the drain is coupled with the first low voltage signal end VGL1. Except for the fifth reset control module 19, the other functional modules can be set according to the same functional modules in the 10T1C circuit in the foregoing example, which will not be described here.

[0059] The second driving circuit 20 can adopt a 3T1C circuit, and specifically can include a second pull-up module 21, a second output module 22, and a second reset module 23. The second pull-up module 21 can include a second transistor M1, the source and the gate of the second transistor M1 are coupled with the second input signal end respectively, and the drain is coupled with the second pull-up node PU2. The second output module 22 can include a second transistor M3, the source of the second transistor M3 is coupled with the second clock signal end CLK2, the gate is coupled with the second pull-up node PU2, and the drain is coupled with the second output signal end OUTPUT2. The second reset module 23 includes a second transistor M2, the source of the second transistor M2 is coupled with the second pull-up node PU2, the gate is coupled with the second reset signal end RST2, and the drain is coupled with the second low voltage signal end VGL2.

[0060] Figure 7 A timing diagram of a pixel driving device 1 of an embodiment of the present application is shown, and the working principle of the pixel driving device 1 of the above specific example is described below Figure 7 The working principle of the pixel driving device 1 of the above specific example is described. As shown in the figure, Figure 4 The pixel driving device 1 of the embodiment of the present application specifically includes the following control processes:

[0061] (1) The pull-up stage includes a first pull-up stage and a second pull-up stage. In the first pull-up stage: about the second driving circuit 20, in response to the input of the effective level signal of the second input signal end INPUT2, the second transistor M1 is turned on, the signal of the second input signal end INPUT2 is provided to the second pull-up node PU2, and the voltage of the second pull-up node PU2 is pulled up to the first voltage value. About the first driving circuit 10, in response to the input of the effective level signal of the first input signal end INPUT1, the first transistor M1 is turned on, the signal of the first input signal end INPUT1 is provided to the first pull-up node PU1, and the voltage of the first pull-up node PU1 is pulled up to the first voltage value.

[0062] In the second pull-up phase: as for the second drive circuit 20, in response to the voltage of the first pull-up node PU1 being pulled up to the first voltage value, the second transistor M3 is turned on, the high level signal input from the second clock signal end CLK2 is output to the second pull-up node PU2, and the voltage value of the second pull-up node PU2 is pulled up to the second voltage value. As for the first drive circuit 10, in response to the voltage of the first pull-up node PU1 being pulled up to the first voltage value, the first transistor M3 is turned on, the high level signal input from the first clock signal end CLK1 is output to the first pull-up node PU1, and the voltage value of the first pull-up node PU1 is pulled up to the first voltage value.

[0063] Since the second pull-down node PD2 of the second drive circuit 20 is coupled with the first pull-down node PD1 of the first drive circuit 10, the first drive circuit 10 can make the second pull-down node of the second drive circuit 20 also in the pull-down state when the first pull-down node is in the pull-down state, so as to make the second transistor M10 turned on and realize the noise reduction of the second pull-up node.

[0064] (2) Reset phase: as for the second drive circuit 20, in response to the second reset signal of the second reset signal end RST2, the second transistor M2 is turned on, the low level signal input from the second low level signal end is provided to the second pull-up node, so as to reset the second pull-up node to the initial voltage value. As for the first drive circuit 10, in response to the first reset signal of the first reset signal end RST1, the first transistor M1 is turned on, the low level signal input from the first low level signal end is provided to the first pull-up node, so as to reset the first pull-up node to the initial voltage value.

[0065] Figure 8 The reduced frame effect of the pixel driving device 1 of the embodiment of the present application is shown. For example, for a display product with a size of 15.6 inches and a refresh rate of 120 Hz or more, the display product can be prepared based on an α-Si (amorphous silicon) process. As shown in Figure 8 compared with the pixel driving device 1 of the related art which adopts an 11T1C circuit to realize GOA double-side driving, the scheme of adopting a 10T1C circuit as the first drive circuit 10 and a 7T1C circuit as the second drive circuit 20 in the embodiment of the present application can effectively reduce the frame size 156um, and the scheme of adopting an 11T1C circuit as the first drive circuit 10 and a 3T1C circuit as the second drive circuit 20 can effectively reduce the frame size 244um. As can be seen, the driving device of the embodiment of the present application can effectively reduce the frame size in the display product of GOA double-side driving, so as to meet the design requirement of narrow frame.

[0066] The embodiment of the present application further provides a display panel comprising the pixel driving device of any of the above embodiments.

[0067] Other configurations of the display panel of the embodiment of the present application can adopt any scheme known or knowable by those skilled in the art, and the embodiment of the present application does not make specific limitation thereto.

[0068] In the present application, unless specifically defined and limited otherwise, the terms "mount", "connect", "connection", "fix", and like terms should be interpreted broadly, for example, can be fixed connection, can also be detachable connection, or be integrated; can be mechanical connection, can also be electrical connection, or communication; can be direct connection, or indirect connection through intermediate medium; can be internal communication of two elements or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0069] In the present application, unless specifically defined and limited otherwise, the first feature "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "over" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "under", "below" and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0070] The above disclosure provides many different embodiments or examples for implementing the different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of the specific examples are described in the above. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to the same reference numerals and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0071] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any skilled person in the art can easily think of various changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A pixel driving device, characterized by comprising: The application relates to a pixel driving device. The first driving circuit comprises a first pull-up module, a first output module, a first pull-down module and a first reset module formed by coupling a plurality of first transistors, and has a first pull-up node and a first pull-down node. The second driving circuit comprises a second pull-up module, a second output module and a second reset module formed by coupling a plurality of second transistors, and the number of the second transistors is less than that of the first transistors. The second driving circuit has a second pull-down node, and the second pull-down node is coupled with the first pull-down node; or the second driving circuit has a second pull-up node, and the second pull-up node is coupled with the first pull-up node. The pixel driving device comprises at least one column of driving circuits arranged on at least one side of a display area, each column of driving circuits comprises a plurality of second driving circuits and a plurality of first driving circuits arranged in columns, and the second driving circuits and the first driving circuits are alternately arranged; the second driving circuit and the first driving circuit adjacent to each other are used for driving two rows of pixel units adjacent to each other, respectively; the second driving circuit has the second pull-down node, and the second pull-down node of the second driving circuit is coupled with the first pull-down node of the first driving circuit adjacent in the column direction.

2. The pixel driving apparatus according to claim 1, wherein The first pull-up module is coupled with a first input signal end and the first pull-up node, respectively, and is configured to provide a first input signal to the first pull-up node in response to the control of the first input signal end. The first output module is coupled with a first clock signal end, the first pull-up node and a first output signal end, respectively, and is configured to provide a signal of the first clock signal end to the first output signal end under the control of the first pull-up node. The first pull-down module is coupled with the first pull-up node, the first pull-down node and a first low-level signal end, respectively, and is configured to provide a signal of the first low-level signal end to the first pull-down node and a first control node under the control of the first pull-up node. The first reset module is coupled with a first reset signal end, the first pull-up node and the first low-level signal end, respectively, and is configured to provide a signal of the first low-level signal end to the first pull-up node under the control of the first reset signal end.

3. The pixel driving apparatus according to claim 1, wherein The first driving circuit further comprises a first reset control module, the first reset control module is coupled with a first start signal end, a first low-level signal end and a first pull-up node, respectively, and is configured to provide a signal of the first low-level end to the first pull-up node in response to the control of the first start signal end.

4. The pixel driving apparatus according to claim 1, wherein The first driving circuit further comprises a first noise reduction module, the first noise reduction module is coupled with a first high-level signal end, a first pull-down node and a first control node, respectively, and is configured to provide a signal of the first high-level signal end to the first control node in response to the control of the first high-level signal end, and to provide a signal of the first high-level signal end to the first pull-down node under the control of the first control node.

5. The pixel driving apparatus according to claim 1, wherein The second pull-up module is coupled with the second input signal end and the second pull-up node, and is configured to provide the second input signal to the second pull-up node in response to the control of the second input signal end; The second output module is coupled with the second clock signal end, the second pull-up node and the second output signal end, and is configured to provide the signal of the second clock signal end to the second output signal end under the control of the second pull-up node; The second reset module is coupled with the second reset signal end, the second pull-up node and the second low-level signal end, and is configured to provide the signal of the second low-level signal end to the second pull-up node under the control of the second reset signal end.

6. The pixel driving apparatus according to any one of claims 1 to 5, wherein The at least one column drive circuit includes two column drive circuits located at opposite sides of the display area respectively; wherein the second drive circuit in any column drive circuit is arranged in the row direction to correspond to the first drive circuit in the other column drive circuit, for jointly driving the corresponding same row of pixel units.

7. The pixel driving apparatus according to any one of claims 1 to 5, wherein The second drive circuit further has a second pull-up node, and the second drive circuit further includes a second pull-down module and a second reset control module; The second pull-down module is coupled with the second pull-up node, the second pull-down node and the second low-level signal end, and is configured to provide the signal of the second low-level signal end to the second pull-down node and the second control node under the control of the second pull-up node; The second reset control module is coupled with the second start signal end, the second low-level signal end and the second pull-up node, and is configured to provide the signal of the second low-level end to the second pull-up node in response to the control of the second start signal end.

8. A pixel driving device, characterized in that, It comprises: A first drive circuit including a first pull-up module, a first output module, a first pull-down module and a first reset module formed by a plurality of first transistors coupled, the first drive circuit having a first pull-up node and a first pull-down node; A second drive circuit including a second pull-up module, a second output module and a second reset module formed by a plurality of second transistors coupled, the number of second transistors being less than the number of first transistors; Wherein, the second drive circuit has a second pull-down node, and the second pull-down node is coupled with the first pull-down node; or, the second drive circuit has a second pull-up node, and the second pull-up node is coupled with the first pull-up node; Wherein, the pixel drive device includes two column drive circuits located at opposite sides of the display area respectively, each column drive circuit includes a plurality of second drive circuits and a plurality of first drive circuits arranged in columns, and the second drive circuits and the first drive circuits are alternately arranged; wherein the second drive circuit in any column drive circuit is arranged in the row direction to correspond to the first drive circuit in the other column drive circuit; the second drive circuit has a second pull-down node, and the second pull-down node of the second drive circuit is coupled with the first pull-down node of the first drive circuit arranged in the row direction.

9. The pixel driving apparatus according to claim 8, wherein The first pull-up module is coupled with the first input signal end and the first pull-up node respectively, and is configured to provide the first input signal to the first pull-up node in response to the control of the first input signal end. The first output module is coupled with the first clock signal end, the first pull-up node and the first output signal end respectively, and is configured to provide the signal of the first clock signal end to the first output signal end under the control of the first pull-up node. The first pull-down module is coupled with the first pull-up node, the first pull-down node and the first low-level signal end respectively, and is configured to provide the signal of the first low-level signal end to the first pull-down node and the first control node under the control of the first pull-up node. The first reset module is coupled with the first reset signal end, the first pull-up node and the first low-level signal end respectively, and is configured to provide the signal of the first low-level signal end to the first pull-up node under the control of the first reset signal end.

10. The pixel driving apparatus according to claim 8, wherein The first driving circuit further comprises a first reset control module, which is coupled with the first start signal end, the first low-level signal end and the first pull-up node respectively, and is configured to provide the signal of the first low-level end to the first pull-up node in response to the control of the first start signal end.

11. The pixel driving apparatus according to claim 8, wherein The first driving circuit further comprises a first noise reduction module, which is coupled with the first high-level signal end, the first pull-down node and the first control node respectively, and is configured to provide the signal of the first high-level signal end to the first control node in response to the control of the first high-level signal end, and provide the signal of the first high-level signal end to the first pull-down node under the control of the first control node.

12. The pixel driving apparatus according to claim 8, wherein The second pull-up module is coupled with the second input signal end and the second pull-up node respectively, and is configured to provide the second input signal to the second pull-up node in response to the control of the second input signal end. The second output module is coupled with the second clock signal end, the second pull-up node and the second output signal end respectively, and is configured to provide the signal of the second clock signal end to the second output signal end under the control of the second pull-up node. The second reset module is coupled with the second reset signal end, the second pull-up node and the second low-level signal end respectively, and is configured to provide the signal of the second low-level signal end to the second pull-up node under the control of the second reset signal end.

13. A display panel, characterized by The pixel driving device comprises the pixel driving device according to any one of claims 1 to 12.

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