Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present disclosure disclose a semiconductor device and a preparation method thereof. The semiconductor device comprises: a wafer, the wafer comprising a plurality of first dies, a cutting lane located between two adjacent first dies, and a first alignment mark located on the cutting lane; wherein the first die comprises a first contact pad; a second die is arranged in a stacked manner with the first die; wherein the second die comprises a second contact pad; the second contact pad is aligned with the first contact pad through the first alignment mark; a first contact pillar is located between the first contact pad and the second contact pad; wherein the first contact pillar is connected with the first contact pad and the second contact pad, respectively.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to a semiconductor device and a method for fabricating the same. Background Technology

[0002] With the development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher bit density and higher integration, and the demand for bandwidth is increasing. The method of using chip stacking to improve bandwidth is widely used in semiconductor devices.

[0003] Chip stacking uses a bonding process to bond two or more chips together to achieve circuit connectivity. However, misalignment can occur during chip bonding, leading to poor electrical connections or even open circuits between chips, thus affecting the performance of semiconductor devices. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising:

[0005] A wafer, the wafer including a plurality of first dies, a dicing channel between two adjacent first dies and a first alignment mark on the dicing channel; wherein, the first die includes a first contact pad;

[0006] A second die is stacked with the first die; wherein the second die includes a second contact pad; the second contact pad and the first contact pad are aligned by the first alignment mark;

[0007] A first contact post is located between the first contact pad and the second contact pad; wherein the first contact post is connected to both the first contact pad and the second contact pad.

[0008] In some embodiments, the semiconductor device further includes:

[0009] Multiple second grains are stacked with multiple first grains respectively;

[0010] An insulating layer is located between two adjacent second grains;

[0011] The second alignment mark is located in the insulating layer.

[0012] In some embodiments, the semiconductor device further includes:

[0013] A third die is stacked with the second die; wherein the second die is located between the wafer and the third die; the third die includes a third contact pad; the third contact pad is aligned with the second contact pad by a first alignment mark and / or a second alignment mark;

[0014] The second contact post is located between the second contact pad and the third contact pad; wherein the second contact post is connected to both the second contact pad and the third contact pad.

[0015] In some embodiments, the dimensions of the first contact post and the second contact post are less than 5 micrometers along the direction of the stacking of the second grain and the first grain.

[0016] In some embodiments, the first grain further includes a substrate and a first dielectric layer covering the substrate; wherein the first contact pad is located in the first dielectric layer;

[0017] The second die further includes a first semiconductor layer and a second dielectric layer covering the first semiconductor layer; wherein the first semiconductor layer is bonded to the first dielectric layer and is located between the first dielectric layer and the second dielectric layer; the second contact pad is located in the second dielectric layer.

[0018] In some embodiments, the first contact post extends at least through the first semiconductor layer.

[0019] In some embodiments, the size of the first semiconductor layer is less than 2 micrometers along the direction in which the second grain and the first grain are stacked.

[0020] In some embodiments, the material of the first semiconductor layer includes: monocrystalline silicon, polycrystalline silicon, doped monocrystalline silicon, doped polycrystalline silicon, silicon-germanium, or germanium.

[0021] According to a second aspect of the present disclosure, a method for fabricating a semiconductor device is provided, comprising:

[0022] A wafer is provided; wherein the wafer includes a plurality of first dies, a dicing channel located between two adjacent first dies, and a first alignment mark located on the dicing channel; the first die includes a first contact pad;

[0023] A second grain is formed and stacked with the first grain; wherein the second grain includes a second contact pad; the second contact pad is aligned with the first contact pad by the first alignment mark;

[0024] A first contact post is formed between the first contact pad and the second contact pad; wherein the first contact post is connected to the first contact pad and the second contact pad respectively.

[0025] In some embodiments, the semiconductor device includes: a plurality of second dies, respectively stacked with a plurality of first dies; the fabrication method further includes:

[0026] An insulating layer is formed between two adjacent second grains;

[0027] A second alignment mark is formed in the insulating layer.

[0028] In some embodiments, the preparation method further includes:

[0029] A third die is formed and stacked with the second die; wherein the second die is located between the wafer and the third die; the third die includes a third contact pad; the third contact pad is aligned with the second contact pad by a first alignment mark and / or a second alignment mark;

[0030] A second contact post is formed between the second contact pad and the third contact pad; wherein the second contact post is connected to the second contact pad and the third contact pad respectively.

[0031] In some embodiments, providing the wafer includes:

[0032] Provide substrate;

[0033] A first dielectric layer is formed covering the substrate;

[0034] The first contact pad is formed in the first dielectric layer;

[0035] The formation of the second grain stacked with the first grain includes:

[0036] Bonding the first semiconductor layer and the first dielectric layer;

[0037] A second dielectric layer is formed to cover the first semiconductor layer; wherein the first semiconductor layer is located between the first dielectric layer and the second dielectric layer;

[0038] The second contact pad is formed in the second dielectric layer.

[0039] In some embodiments, forming the first contact post between the first contact pad and the second contact pad includes:

[0040] Before forming the second dielectric layer, a contact hole is formed that penetrates at least through the first semiconductor layer; wherein the bottom of the contact hole exposes the first contact pad;

[0041] The first contact post is formed in the contact hole.

[0042] In this embodiment, by setting a first alignment mark on the wafer dicing path, the first contact pad and the second contact pad can be aligned through the first alignment mark, and the second contact pad and the first contact pad are connected by a first contact post. This helps to improve the alignment accuracy between multilayer dies, reduce overlay errors, and thus ensure good circuit connection between upper and lower dies. It can improve the situation where the pitch between adjacent contact pads is large when connected by microbumps, or the alignment deviation between upper and lower contact pads is prone to occur when connected by hybrid bonding. Attached Figure Description

[0043] Figure 1a and Figure 1b This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present disclosure;

[0044] Figure 2 This is a cross-sectional view of another semiconductor device according to an embodiment of the present disclosure;

[0045] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0046] Figures 4a to 4i This is a schematic diagram illustrating the fabrication process of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0047] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0048] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0049] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0050] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0051] Figure 1a and Figure 1b This is a schematic diagram of the structure of a semiconductor device 10 according to an embodiment of the present disclosure; wherein, Figure 1a A cross-sectional view of the semiconductor device 10 is shown. Figure 1b A top view of the semiconductor device 10 is shown. (Refer to...) Figure 1a and Figure 1b As shown, the semiconductor device 10 includes:

[0052] Wafer 100 includes a plurality of first dies 110, a dicing channel 120 located between two adjacent first dies 110, and a first alignment mark 160 located on the dicing channel 120; wherein, the first die 110 includes a first contact pad 111;

[0053] The second die 130 is stacked with the first die 110; wherein the second die 130 includes a second contact pad 131; the second contact pad 131 and the first contact pad 111 are aligned by a first alignment mark 160.

[0054] The first contact post 141 is located between the first contact pad 111 and the second contact pad 131; wherein the first contact post 141 is connected to the first contact pad 111 and the second contact pad 131 respectively.

[0055] In some embodiments, refer to Figure 1a As shown, the first grain 110 further includes a substrate 112 and a first dielectric layer 113 covering the substrate 112; wherein, the first contact pad 111 is located in the first dielectric layer 113;

[0056] The second die 130 further includes a first semiconductor layer 132 and a second dielectric layer 133 covering the first semiconductor layer 132; wherein the first semiconductor layer 132 is bonded to the first dielectric layer 113, and the first semiconductor layer 132 is located between the first dielectric layer 113 and the second dielectric layer 133; the second contact pad 131 is located in the second dielectric layer 133.

[0057] Reference Figure 1a As shown, wafer 100 includes a plurality of first dies 110, and the first dies 110 include: dynamic random access memory (DRAM), NAND flash memory, ferroelectric random access memory (FeRAM) or phase change memory (PCM), etc.

[0058] The first die 110 includes a substrate 112, a first dielectric layer 113, and a first functional circuit, the first functional circuit being located in the first dielectric layer 113. Here, the first functional circuit includes a first memory cell array 114 and / or a first peripheral circuit 115.

[0059] In one specific embodiment, the first functional circuit includes a first storage cell array 114 and a first peripheral circuit 115. The first storage cell array 114 and the first peripheral circuit 115 are coupled together by a metal wiring (not shown in the figure). The first peripheral circuit 115 is used to control the operation of the first storage cell array 114, such as a read operation or a write operation.

[0060] The substrate 112 may be made of elemental semiconductor materials (e.g., silicon, germanium), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In other embodiments, the substrate 112 may also be made of silicon-on-insulator (SiI).

[0061] The material of the first dielectric layer 113 includes silicon oxide, silicon nitride, or silicon nitride. The first dielectric layer 113 can be a single film layer or a composite film layer composed of multiple film layers.

[0062] The dicing channel 120 is located between two adjacent first dies 110, and the wafer 100 can be cut into multiple first dies 110 along the extension direction of the dicing channel 120.

[0063] The first alignment mark 160 is located on the dicing 120 and is used for alignment during the subsequent formation of other grains (e.g., a second or third grain). The material of the first alignment mark includes a conductive material, such as a metal material like tungsten, copper, or aluminum. Here, the first alignment mark 160 can be formed simultaneously with the metal wiring in the first grain 110, or it can be formed separately. It should be noted that in this embodiment of the present disclosure, the number of first alignment marks 160 can be one or more.

[0064] The first contact pad 111 is located in the first dielectric layer 113. The material of the first contact pad 111 includes conductive materials, such as metals such as tungsten, copper or aluminum. The number of first contact pads 111 can be one or more, and this disclosure does not have any special limitations on this.

[0065] The second die 130 and the first die 110 are stacked together in a direction perpendicular to the plane of the substrate 112. The second die 130 includes: Dynamic Random Access Memory (DRAM), NAND flash memory, Ferroelectric RAM (FeRAM), or Phase Change Memory (PCM), etc.

[0066] In one embodiment, the second die 130 and the first die 110 can be the same type of memory, for example, both the second die 130 and the first die 110 are DRAM. In other embodiments, the second die 130 and the first die 110 can be different types of memory.

[0067] The second die 130 includes a first semiconductor layer 132, a second dielectric layer 133, and a second functional circuit, the second functional circuit being located in the second dielectric layer 133. Here, the second functional circuit includes a second memory cell array 134 and / or a second peripheral circuit 135.

[0068] In one specific embodiment, the second functional circuit includes a second storage cell array 134 and a second peripheral circuit 135. The second storage cell array 134 and the second peripheral circuit 135 are coupled together by a metal wiring (not shown in the figure). The second peripheral circuit 135 is used to control the operation of the second storage cell array 134, such as a read operation or a write operation.

[0069] A first semiconductor layer 132 is located on a first die 110. In one example, the first semiconductor layer 132 can be disposed on a first dielectric layer 113 by a bonding process; in another example, the first semiconductor layer 132 can be disposed on a first dielectric layer 113 by a thin film deposition process. The material of the first semiconductor layer 132 includes: single-crystal silicon, polycrystalline silicon, doped single-crystal silicon, doped polycrystalline silicon, silicon-germanium (SiGe), or germanium (Ge), etc. At least a portion of the first semiconductor layer 132 can be used as an active region of the second die 130.

[0070] The material of the second dielectric layer 133 includes silicon oxide, silicon nitride, or silicon nitride. The second dielectric layer 133 can be a single film layer or a composite film layer composed of multiple film layers.

[0071] The second contact pad 131 is located in the second dielectric layer 133. The material of the second contact pad 131 includes conductive materials, such as metals such as tungsten, copper or aluminum. The number of second contact pads 131 can be one or more, and this disclosure does not have any special limitations on this.

[0072] The first contact post 141 is located between the first contact pad 111 and the second contact pad 131, and the first contact post 141 penetrates the first semiconductor layer 132. The first end of the first contact post 141 is connected to the first contact pad 111, and the second end of the first contact post 141 is connected to the second contact pad 131. Here, the material of the first contact post 141 includes conductive materials, such as metals such as tungsten, copper, or aluminum.

[0073] In some embodiments, the overlay error between the second grain 130 and the first grain 110 is less than a preset value. In one specific embodiment, the preset value can be 50 nanometers.

[0074] In this embodiment, by setting a first alignment mark on the wafer dicing path, the first contact pad and the second contact pad can be aligned through the first alignment mark, and the second contact pad and the first contact pad are connected by a first contact post. This helps to improve the alignment accuracy between multilayer dies, reduce overlay errors, and thus ensure good circuit connection between upper and lower dies. It can improve the situation where the pitch between adjacent contact pads is large when connected by microbumps, or the alignment deviation between upper and lower contact pads is prone to occur when connected by hybrid bonding.

[0075] In some embodiments, refer to Figure 1a As shown, the semiconductor device 10 further includes: a plurality of second dies 130, which are stacked with a plurality of first dies 110 respectively; an insulating layer 150 located between two adjacent second dies 130; and a second alignment mark (not shown in the figure) located in the insulating layer 150. Here, the plurality of second dies 130 are respectively arranged in a one-to-one correspondence with the plurality of first dies 110.

[0076] It should be noted that, Figure 1a Only two first granules 110 and two second granules 130 are shown in the present disclosure, but it should be understood that in the embodiments of this disclosure, the number of first granules 110 and second granules 130 is not limited to two, but can also be one, three or more.

[0077] The insulating layer 150 is located between two adjacent second grains 130 and is stacked with the dicing 120. The material of the insulating layer 150 includes silicon oxide, silicon nitride, or silicon nitride.

[0078] The second alignment mark is located in the insulating layer 150 and is used for alignment during the subsequent formation of other grains (e.g., a third grain). The material of the second alignment mark includes conductive materials, such as metallic materials like tungsten, copper, or aluminum. Here, the second alignment mark can be formed simultaneously with the metal wiring in the second grain 130 or formed separately.

[0079] In some embodiments, the second alignment mark and the first alignment mark are substantially aligned. Here, substantially aligned includes: the second alignment mark and the first alignment mark being perfectly aligned; or, there is a deviation between the second alignment mark and the first alignment mark, but the deviation is within an allowable error range.

[0080] In some embodiments, the second alignment mark is the same size as the first alignment mark, and when the second alignment mark and the first alignment mark are fully aligned, their orthogonal projections on a plane parallel to the substrate coincide.

[0081] In other embodiments, the first alignment mark and the second alignment mark are different in size, and when the second alignment mark and the first alignment mark are perfectly aligned, the center of the second alignment mark and the center of the first alignment mark coincide on the projection of their centers onto a plane parallel to the substrate.

[0082] In this embodiment of the present disclosure, by setting an insulating layer between two adjacent second dies and setting a second alignment mark in the insulating layer, other dies subsequently formed on the second dies can be aligned through the second alignment mark, which is beneficial to further improve the alignment accuracy between multilayer dies, reduce overlay error, and thus ensure good circuit connection between upper and lower dies.

[0083] Figure 2 This is a schematic diagram illustrating the structure of another semiconductor device 10 according to an embodiment of this disclosure. (Refer to...) Figure 2 As shown, the semiconductor device 10 further includes: a third die 160, stacked with the second die 130; wherein the second die 130 is located between the wafer 100 and the third die 160; the third die 160 includes a third contact pad 161; the third contact pad 161 and the second contact pad 131 are aligned by a first alignment mark and / or a second alignment mark;

[0084] The second contact post 142 is located between the second contact pad 131 and the third contact pad 161; wherein the second contact post 142 is connected to the second contact pad 131 and the third contact pad 161 respectively.

[0085] Reference Figure 2 As shown, the third die 160 and the second die 130 are stacked along a direction perpendicular to the plane of the substrate 112. The second die 130 is located between the wafer 100 and the third die 160. Here, the third die 160 includes: Dynamic Random Access Memory (DRAM), NAND flash memory, ferroelectric random access memory (FeRAM), or phase change memory (PCM), etc.

[0086] The third die 160 includes a second semiconductor layer 162, a third dielectric layer 163, and a third functional circuit, the third functional circuit being located in the third dielectric layer 163. Here, the third functional circuit includes a third memory cell array 164 and / or a third peripheral circuit 165.

[0087] In one specific embodiment, the third functional circuit includes a third storage cell array 164 and a third peripheral circuit 165. The third storage cell array 164 and the third peripheral circuit 165 are coupled together by a metal wiring (not shown in the figure). The third peripheral circuit 165 is used to control the operation of the third storage cell array 164, such as a read operation or a write operation.

[0088] The second semiconductor layer 162 is located on the second die 130. In one example, the second semiconductor layer 162 can be disposed on the second dielectric layer 133 by a bonding process; in another example, the second semiconductor layer 162 can be disposed on the second dielectric layer 133 by a thin film deposition process. The material of the second semiconductor layer 162 includes: single-crystal silicon, polycrystalline silicon, doped single-crystal silicon, doped polycrystalline silicon, silicon-germanium (SiGe), or germanium (Ge), etc. At least a portion of the second semiconductor layer 162 can be used as the active region of the third die 160.

[0089] The material of the third dielectric layer 163 includes silicon oxide, silicon nitride, or silicon nitride. The third dielectric layer 163 can be a single film layer or a composite film layer composed of multiple film layers.

[0090] The third contact pad 161 is located in the third dielectric layer 163. The material of the third contact pad 161 includes conductive materials, such as metals such as tungsten, copper or aluminum. The number of third contact pads 161 can be one or more, and this disclosure does not have any particular limitation in this regard.

[0091] The second contact post 142 is located between the second contact pad 131 and the third contact pad 161, and penetrates the second semiconductor layer 162. The first end of the second contact post 142 is connected to the second contact pad 131, and the second end of the second contact post 142 is connected to the third contact pad 161. Here, the material of the second contact post 142 includes conductive materials, such as tungsten, copper, or aluminum.

[0092] In some embodiments, the third contact pad 161 and the second contact pad 131 are aligned by a first alignment mark and / or a second alignment mark.

[0093] In one example, a first alignment mark is provided between two adjacent first dies 110, and the third contact pad 161 and the second contact pad 131 are aligned with each other using the first alignment mark. Since the second contact pad 131 is also aligned with the first contact pad 111 using the first alignment mark, the alignment accuracy among the third contact pad 161, the second contact pad 131, and the first contact pad 111 is improved, thereby reducing overlay errors. Furthermore, in this example, since the third contact pad 161, the second contact pad 131, and the first contact pad 111 are all aligned with the first alignment mark, the second alignment mark can be omitted, thereby reducing the manufacturing cost of the semiconductor device.

[0094] In another example, a second alignment mark is provided between two adjacent second dies 130. The third contact pad 161 is aligned with the second contact pad 131 through the second alignment mark. Since the second contact pad 131 is aligned with the first contact pad 111 through the first alignment mark, and the first alignment mark and the second alignment mark are substantially aligned, the alignment accuracy between the third contact pad 161, the second contact pad 131, and the first contact pad 111 is improved, thereby reducing overlay errors. Furthermore, in this example, the third contact pad 161 is aligned with the second contact pad 131 through the second alignment mark. Compared to aligning the third contact pad 161 with the second contact pad 131 through the first alignment mark, the second alignment mark is closer to the third contact pad 161, which is more conducive to the alignment and positioning of the third contact pad 161.

[0095] In another example, there is a first alignment mark between two adjacent first dies 110 and a second alignment mark between two adjacent second dies 130. The first alignment mark and the second alignment mark are substantially aligned. The third contact pad 161 and the second contact pad 131 are aligned through the first alignment mark and the second alignment mark, so that the alignment accuracy between the third contact pad 161, the second contact pad 131 and the first contact pad 111 can be further improved, thereby further reducing the overlay error.

[0096] It should be noted that the semiconductor device 10 includes a first alignment mark located on the dicing channel 120, which enables alignment between multilayer dies. Whether a second alignment mark is provided on the insulating layer between two adjacent second dies 130, or a third alignment mark is provided on the insulating layer between two adjacent third dies 160, can be selected by those skilled in the art according to actual needs, and this disclosure does not impose any restrictions.

[0097] In this embodiment of the present disclosure, the third contact pad is aligned with the second contact pad through the first alignment mark and / or the second alignment mark, and the third contact pad is connected to the second contact pad through the second contact post. This can improve the alignment accuracy between multilayer dies, reduce overlay error, and thus ensure good circuit connection between upper and lower dies.

[0098] It should be emphasized that the terms "first grain," "second grain," and "third grain" are used to distinguish their different positions in the stacking direction, and are not intended to describe a specific order or sequence.

[0099] In some embodiments, refer to Figure 2 As shown, the semiconductor device 10 further includes: a plurality of third dies 160, which are stacked with a plurality of second dies 130 respectively; an insulating layer located between two adjacent third dies 160; and a third alignment mark (not shown in the figure) located in the insulating layer. Here, the plurality of third dies 160 are respectively arranged in a one-to-one correspondence with the plurality of second dies 130.

[0100] It should be noted that, Figure 2 Only two third grains 160 are shown in the illustration, but it should be understood that in the embodiments of this disclosure, the number of third grains 160 is not limited to two, but may be one, three or more.

[0101] In some embodiments, refer to Figure 2 As shown, along the stacking direction of the second grain 130 and the first grain 110, the size of the first contact post 141 and the second contact post 142 is less than 5 micrometers.

[0102] It should be noted that the through-silicon via (TSV) structure in related technologies runs through the entire stacked structure, and its size in the grain stacking direction is typically 30 micrometers or 60 micrometers. The larger the TSV structure, the greater the technological challenges. In the embodiments disclosed in this disclosure, the first contact post and the second contact post only need to penetrate the semiconductor layer and part of the dielectric layer, making the size of the first contact post and the second contact post less than 5 micrometers, which helps to reduce the fabrication difficulty of the first contact post and the second contact post.

[0103] In some embodiments, the first contact post 141 penetrates at least the first semiconductor layer 132.

[0104] In some embodiments, refer to Figure 1a As shown, the first contact post 141 penetrates the first semiconductor layer 132. The first end of the first contact post 141 is connected to the first contact pad 111 located in the first dielectric layer 113, and the second end of the first contact post 141 is connected to the second contact pad 131 located in the second dielectric layer 133. The size of the first contact post 141 is the distance from the first end of the first contact post 141 to the second end of the first contact post 141, and its length is less than 5 micrometers.

[0105] In this embodiment of the disclosure, by setting the dimensions of the first contact post and the second contact post along the direction of the stacking of the second grain and the first grain to be less than 5 micrometers, it is beneficial to reduce the manufacturing difficulty of the first contact post and the second contact post.

[0106] In some embodiments, the size of the first semiconductor layer 132 is less than 2 micrometers along the direction of the stacking of the first and second grains.

[0107] Reference Figure 1a As shown, a first contact post 141 is formed through the first semiconductor layer 132 along the direction of the stacking of the first and second grains. The size of the first contact post 141 is less than 5 micrometers. Setting the size of the first semiconductor layer 132 to be less than 2 micrometers is beneficial to forming the small-sized first contact post 141, thereby reducing the manufacturing difficulty of the first contact post 141.

[0108] In some embodiments, refer to Figure 2 As shown, the semiconductor device 10 also includes a stacked fourth die 170. Here, the fourth die 170 has a similar structure to the second die 130 and the third die 130, and will not be described in detail here.

[0109] It should be noted that the stacked grains in the embodiments of this disclosure are not limited to 4 layers, but can also be 8 layers, 16 layers or more. Those skilled in the art can choose according to actual needs, and this disclosure does not impose any restrictions.

[0110] Based on the above-described semiconductor device, this disclosure also provides a method for fabricating a semiconductor device.

[0111] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. (Refer to...) Figure 3 As shown, the preparation method includes at least the following steps:

[0112] S201: A wafer is provided; wherein the wafer includes a plurality of first dies, a dicing track between two adjacent first dies, and a first alignment mark on the dicing track; the first die includes a first contact.

[0113] S202: Forming a second grain stacked with the first grain; wherein the second grain includes a second contact pad; the second contact pad is aligned with the first contact pad by a first alignment mark;

[0114] S203: A first contact post is formed between the first contact pad and the second contact pad; wherein the first contact post is connected to the first contact pad and the second contact pad respectively.

[0115] It should be noted that, Figure 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be adjusted in order according to actual needs.

[0116] Figures 4a to 4iThis is a schematic diagram illustrating the fabrication process of a semiconductor device according to an embodiment of this disclosure. The following will be combined with... Figure 3 , Figures 4a to 4i The method for fabricating the semiconductor device provided in the embodiments of this disclosure will be described in detail.

[0117] In step S201, a wafer is provided; wherein the wafer includes a plurality of first dies, a dicing track between two adjacent first dies, and a first alignment mark on the dicing track; the first die includes a first contact pad.

[0118] Reference Figure 4a and Figure 4b As shown, a wafer 200 is provided, which includes a plurality of first dies 210, cleavages 220 located between two adjacent first dies 210, and first alignment marks (not shown) located on the cleavages 220. The first dies 210 include: Dynamic Random Access Memory (DRAM), NAND flash memory, ferroelectric random access memory (FeRAM), or phase change memory (PCM), etc.

[0119] In some embodiments, step S201 includes: providing a substrate; forming a first dielectric layer covering the substrate; and forming a first contact pad in the first dielectric layer.

[0120] Reference Figure 4b As shown, a substrate 212 is provided. The material of the substrate 212 includes: elemental semiconductor materials (e.g., silicon, germanium), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In other embodiments, the material of the substrate 212 may also be silicon-on-insulator (SiI), etc.

[0121] Still refer to Figure 4b As shown, a first dielectric layer 213 is formed over the substrate 212; a first contact pad 211 is formed in the first dielectric layer 213. Here, at least one of thin film deposition, photolithography, and etching processes can be used to form the first dielectric layer 213 and the first contact pad 211. Thin film deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or combinations thereof.

[0122] The material of the first dielectric layer 213 includes silicon oxide, silicon nitride, or silicon nitride. The first dielectric layer 113 can be a single film layer or a composite film layer composed of multiple film layers.

[0123] The material of the first contact pad 211 includes conductive materials, such as metals such as tungsten, copper or aluminum. The number of first contact pads 211 can be one or more, and this disclosure does not impose any special restrictions on this.

[0124] In some embodiments, step S201 further includes forming a first functional circuit in the first dielectric layer 213. Here, at least one of thin-film deposition, photolithography, and etching processes can be used to form the first functional circuit. The first functional circuit includes a first memory cell array 214 and / or a first peripheral circuit 215.

[0125] In one specific embodiment, the first functional circuit includes a first storage cell array 214 and a first peripheral circuit 215. The first storage cell array 214 and the first peripheral circuit 215 are coupled together by a metal wiring (not shown in the figure). The first peripheral circuit 215 is used to control the operation of the first storage cell array 214, such as a read operation or a write operation.

[0126] Still refer to Figure 4b As shown, the film layer located between two adjacent first dies 210 can serve as a dicing channel 220 of the wafer, and the wafer 200 can be diced into multiple first dies 210 along the extension direction of the dicing channel 220. Here, a first alignment mark (not shown in the figure) can be formed on the dicing channel 220 by photolithography and etching processes. The first alignment mark is used for alignment when other dies (e.g., a second die or a third die) are subsequently formed. The material of the first alignment mark includes conductive materials, such as metals such as tungsten, copper, or aluminum. Here, the first alignment mark can be formed simultaneously with the metal wiring in the first die 210, or it can be formed separately.

[0127] In step S202, a second grain is formed stacked with the first grain; wherein the second grain includes a second contact pad; the second contact pad is aligned with the first contact pad by a first alignment mark.

[0128] Reference Figure 4iAs shown, a second die 230 is formed on the first die, and the second die 230 is aligned with the first die 210 by a first alignment mark. The second die 230 includes: Dynamic Random Access Memory (DRAM), NAND flash memory, ferroelectric random access memory (FeRAM), phase change memory (PCM), etc.

[0129] In one embodiment, the second die 230 and the first die 210 can be the same type of memory, for example, both the second die 230 and the first die 210 are DRAM. In other embodiments, the second die 230 and the first die 210 can be different types of memory.

[0130] In some embodiments, step S202 includes: bonding a first semiconductor layer and a first dielectric layer; forming a second dielectric layer covering the first semiconductor layer; wherein the first semiconductor layer is located between the first dielectric layer and the second dielectric layer; and forming a second contact pad in the second dielectric layer.

[0131] Reference Figure 4c As shown in Figures 4d and 4d, a first semiconductor layer 232 is formed on the first die 210. In this example, the first semiconductor layer 232 can be formed by a bonding process; in other examples, the first semiconductor layer 232 can be formed by a thin film deposition process. An active region of the second die 230 can be formed by performing a doping process on at least a portion of the first semiconductor layer 232. A gap exists between adjacent first semiconductor layers 232, and this gap is located on the dicing channel 220. The material of the first semiconductor layer 232 includes: single-crystal silicon, polycrystalline silicon, doped single-crystal silicon, doped polycrystalline silicon, silicon-germanium (SiGe), or germanium (Ge), etc.

[0132] Reference Figure 4e As shown, a capping layer 234 is formed covering the first semiconductor layer 232. In the stacking direction, the size of the capping layer 234 is 2 micrometers to 3 micrometers, and it is used to fill the gaps between two adjacent first semiconductor layers 232. The material of the capping layer 234 includes silicon oxide, silicon nitride, or silicon nitride, etc.

[0133] Planarization is performed on the capping layer 234 until the first semiconductor layer 232 is exposed, such as Figure 4fAs shown, the planarization process includes, but is not limited to, chemical mechanical polishing (CMP). A capping layer 234 located between the first semiconductor layers 232 serves as a first sub-insulating layer 250a. After planarization, the oxide on the surface of the first semiconductor layer 232 can be removed by wet etching, which helps ensure good circuit connectivity of the subsequently formed second functional circuit.

[0134] In step S203, a first contact post is formed between the first contact pad and the second contact pad; wherein the first contact post is connected to the first contact pad and the second contact pad respectively.

[0135] Reference Figure 4g As shown, a first insulating layer is formed covering the first semiconductor layer 232. The material of the first insulating layer includes silicon oxide, silicon nitride, or silicon nitride. The first insulating layer can be a single film layer or a composite film layer composed of multiple film layers. In this example, the first insulating layer also covers a first sub-insulating layer 250a, and the first insulating layer covering the first sub-insulating layer 250a serves as a second sub-insulating layer 250b.

[0136] Reference Figure 4h As shown, a first contact post 241 is formed that penetrates the first insulating layer, the first semiconductor layer 232, and a portion of the first dielectric layer 213. The first end of the first contact post 241 is located in the first dielectric layer 213 and connected to the first contact pad 211. The material of the first contact post 241 includes a conductive material, such as a metal material like tungsten, copper, or aluminum. Here, the number of first contact posts 241 can be one or more, which can be selected by those skilled in the art according to specific needs.

[0137] Reference Figure 4i As shown, a second insulating layer is formed on the first insulating layer. The material of the second insulating layer includes silicon oxide, silicon nitride, or silicon nitride. The second insulating layer can be a single film layer or a composite film layer composed of multiple film layers. Here, the second dielectric layer 233 includes the first insulating layer and the second insulating layer. In this example, the second insulating layer also covers the second sub-insulating layer 250b, and the second insulating layer covering the second sub-insulating layer 250b serves as the third sub-insulating layer.

[0138] Still refer to Figure 4i As shown, a second contact pad 231 is formed in the second insulating layer, and the second end of the first contact post 241 is located in the second dielectric layer 233 and connected to the second contact pad 231.

[0139] In some embodiments, the above-described fabrication method further includes forming a second functional circuit in the second dielectric layer 233. Here, at least one of thin-film deposition, photolithography, and etching processes can be used to form the second functional circuit. The second functional circuit includes a second memory cell array 234 and / or a second peripheral circuit 235.

[0140] In one specific embodiment, reference is made to Figure 4g As shown, the second functional circuit includes a second storage cell array 234 and a second peripheral circuit 235. The second storage cell array 234 and the second peripheral circuit 235 are coupled together by a metal wiring (not shown in the figure). The second peripheral circuit 235 is used to control the operation of the second storage cell array 234, such as read operation or write operation.

[0141] In some embodiments, the semiconductor device further includes: a plurality of second dies, each stacked with a plurality of first dies; and the fabrication method further includes: forming an insulating layer between two adjacent second dies; and forming a second alignment mark in the insulating layer. In this example, the insulating layer 250 includes the aforementioned first sub-insulating layer 250a, second sub-insulating layer 250b, and third sub-insulating layer. The material of the insulating layer 250 includes silicon oxide, silicon nitride, or silicon nitride, etc.

[0142] A second alignment mark (not shown) can be formed on the insulating layer 250 using photolithography and etching processes. This second alignment mark is used for alignment during the subsequent formation of other grains (e.g., a third grain). The material of the second alignment mark includes conductive materials, such as metallic materials like tungsten, copper, or aluminum. Here, the second alignment mark can be formed simultaneously with the metal wiring in the second grain 230, or it can be formed separately.

[0143] Reference Figure 4i As shown, a second contact pad 231 is formed in the second dielectric layer 233 by a first alignment mark. The second contact pad 231 is connected to the second end of the first contact post 241 located in the second dielectric layer 233. The first contact post 241 is connected to the first contact pad 211 and the second contact pad 231 respectively.

[0144] The material of the second contact pad 211 includes conductive materials, such as metals such as tungsten, copper or aluminum. The number of second contact pads 211 can be one or more, and this disclosure does not impose any special restrictions on this.

[0145] In some embodiments, step S203 includes: forming a contact hole that penetrates at least through the first semiconductor layer before forming the second dielectric layer; wherein the bottom of the contact hole exposes a first contact pad; and forming a first contact post in the contact hole.

[0146] Reference Figure 4h As shown, after the first insulating layer is formed, a contact hole is formed that penetrates the first insulating layer and the first semiconductor layer 232. The bottom of the contact hole exposes the first contact pad 211. The contact hole is filled with conductive material to form the first contact post 241. The conductive material includes metal materials such as tungsten, copper or aluminum.

[0147] In some embodiments, the above-described preparation method further includes forming a third grain stacked with the second grain; wherein the second grain is located between the wafer and the third grain; the third grain includes a third contact pad; the third contact pad is aligned with the second contact pad by a first alignment mark and / or a second alignment mark;

[0148] A second contact post is formed between the second contact pad and the third contact pad; wherein the second contact post is connected to the second contact pad and the third contact pad respectively.

[0149] Available Figure 4i On this basis, continue to implement similar Figures 4d to 4i The steps shown involve forming a third grain stacked with the second grain and forming a fourth grain stacked with the third grain, as described above. Figure 2 As shown.

[0150] It should be noted that multiple stacked dies can be formed by performing the method provided in the embodiments of this disclosure. Here, the number of dies can be 4, 8 or 16 layers, the number of alignment marks can be one or more, and alignment marks may not be formed on the insulating layer between the topmost dies.

[0151] Based on the aforementioned semiconductor device, this disclosure also provides a memory. In some embodiments, the memory can be obtained by dicing and packaging the semiconductor device described in this disclosure. The memory includes, but is not limited to, high-bandwidth memory.

[0152] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A wafer, the wafer comprising a plurality of first dies, a dicing channel located between two adjacent first dies, and a first alignment mark located on the dicing channel; wherein, the first die comprises a substrate, a first dielectric layer, and a first contact pad, the first contact pad being located in the first dielectric layer and not in contact with the substrate; The second die is stacked with the first die; wherein the second die includes a first semiconductor layer, a second dielectric layer and a second contact pad; the second contact pad is located in the second dielectric layer, does not contact the first semiconductor layer and is aligned with the first contact pad by the first alignment mark; A first contact post is located between the first contact pad and the second contact pad; wherein the first contact post is connected to both the first contact pad and the second contact pad.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: Multiple second grains are stacked with multiple first grains respectively; An insulating layer is located between two adjacent second grains; The second alignment mark is located in the insulating layer.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: A third die is stacked with the second die; wherein the second die is located between the wafer and the third die; the third die includes a third contact pad; the third contact pad is aligned with the second contact pad by a first alignment mark and / or a second alignment mark; The second contact post is located between the second contact pad and the third contact pad; wherein the second contact post is connected to both the second contact pad and the third contact pad.

4. The semiconductor device according to claim 3, characterized in that, Along the direction of the stacking of the second grain and the first grain, the size of the first contact post and the second contact post is less than 5 micrometers.

5. The semiconductor device according to claim 1, characterized in that, The first grain further includes a substrate and a first dielectric layer covering the substrate; wherein the first contact pad is located in the first dielectric layer; The second die further includes a first semiconductor layer and a second dielectric layer covering the first semiconductor layer; wherein the first semiconductor layer is bonded to the first dielectric layer and is located between the first dielectric layer and the second dielectric layer; the second contact pad is located in the second dielectric layer.

6. The semiconductor device according to claim 5, characterized in that, The first contact post penetrates at least through the first semiconductor layer.

7. The semiconductor device according to claim 5, characterized in that, Along the direction of the stacking of the second and first grains, the size of the first semiconductor layer is less than 2 micrometers.

8. The semiconductor device according to claim 5, characterized in that, The material of the first semiconductor layer includes: monocrystalline silicon, polycrystalline silicon, doped monocrystalline silicon, doped polycrystalline silicon, silicon-germanium, or germanium.

9. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A wafer is provided; wherein the wafer includes a plurality of first dies, a dicing channel located between two adjacent first dies, and a first alignment mark located on the dicing channel; the first die includes a substrate, a first dielectric layer, and a first contact pad, the first contact pad being located in the first dielectric layer and not in contact with the substrate; A second grain is formed stacked with the first grain; wherein the second grain includes a first semiconductor layer, a second dielectric layer and a second contact pad; the second contact pad is located in the second dielectric layer, does not contact the first semiconductor layer and is aligned with the first contact pad by the first alignment mark; A first contact post is formed between the first contact pad and the second contact pad; wherein the first contact post is connected to the first contact pad and the second contact pad respectively.

10. The preparation method according to claim 9, characterized in that, The semiconductor device includes: a plurality of second dies, respectively stacked with a plurality of first dies; the fabrication method further includes: An insulating layer is formed between two adjacent second grains; A second alignment mark is formed in the insulating layer.

11. The preparation method according to claim 10, characterized in that, The preparation method further includes: A third die is formed and stacked with the second die; wherein the second die is located between the wafer and the third die; the third die includes a third contact pad; the third contact pad is aligned with the second contact pad by a first alignment mark and / or a second alignment mark; A second contact post is formed between the second contact pad and the third contact pad; wherein the second contact post is connected to the second contact pad and the third contact pad respectively.

12. The preparation method according to claim 9, characterized in that, The provision of the wafer includes: Provide substrate; A first dielectric layer is formed covering the substrate; The first contact pad is formed in the first dielectric layer; The formation of the second grain stacked with the first grain includes: Bonding the first semiconductor layer and the first dielectric layer; A second dielectric layer is formed to cover the first semiconductor layer; wherein the first semiconductor layer is located between the first dielectric layer and the second dielectric layer; The second contact pad is formed in the second dielectric layer.

13. The preparation method according to claim 12, characterized in that, The step of forming the first contact post between the first contact pad and the second contact pad includes: Before forming the second dielectric layer, a contact hole is formed that penetrates at least through the first semiconductor layer; wherein the bottom of the contact hole exposes the first contact pad; The first contact post is formed in the contact hole.

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