Multi-system hibernation method, device and storage medium

Abstract

The embodiment of the present invention discloses a multi-system hibernation method, device and storage medium, the method comprising: a non-root cell receives an SPI interrupt number of a SOC system sent by a root cell; the non-root cell determines whether the SPI interrupt number is a hibernation interrupt number, and when it is a hibernation interrupt number, freezes the user process of the non-root cell; the power management linked list maintained determines the external device, traverses the power management linked list of the system, and sequentially calls the pause function of each device to turn off the clock and power supply of the peripheral device; saves the CPU context of the non-root cell, and saves the general register of the CPU to the stack; writes a hibernation flag at a designated position of the hibernation flag bit in the memory, and sends the hibernation state SPI interrupt number of the SOC system to the root cell; uses the power management interface to realize CPU power-off, and sends a hibernation completion interrupt signal to the root cell. The non-root cell can be enabled to enter deep hibernation, thereby enabling the entire system to achieve the maximum low-power operation.

Description

Technical Field

[0001] The present invention relates to the field of SOC multi-system technology, and in particular to a multi-system hibernation method, device and storage medium. Background Art

[0002] In the embedded field, RTOS (Real Time Operating System) is being used more and more widely. The core of RTOS is real-time task scheduling and inter-task communication. Using RTOS can make more reasonable and efficient use of CPU resources, better event real-time processing mechanism, universal task management framework, simplify application software design, shorten system development time, and better ensure system real-time performance and reliability.

[0003] Jailhouse is a virtualization solution for embedded systems. It is mainly used to run multiple real-time operating systems (RTOS) and Linux kernels on the same hardware platform to provide strong isolation and real-time performance. In multi-core embedded systems, Jailhouse can be used to achieve resource sharing and isolation between multiple real-time operating systems and Linux kernels, so as to make more efficient use of hardware resources. The mixed deployment of RTOS and Linux allows users to take advantage of the perfect ecosystem and complex functions of Linux on the one hand, and give full play to the real-time characteristics of the RTOS system on the other hand. In embedded systems, system hibernation technology is of great significance. Because embedded systems generally have strict requirements on energy consumption, hibernation technology can achieve effective energy conservation and emission reduction, while extending battery life and reducing the requirements of the cooling system. In some specific scenarios, system hibernation can avoid problems such as system resource exhaustion and program errors caused by long-term operation, thereby improving the stability and reliability of the system. However, RTOS systems may not be good at managing certain hardware and functions because the implementation of system hibernation on RTOS systems is not perfect. Deep hibernation cannot be achieved. Summary of the invention

[0004] The embodiments of the present invention provide a multi-system hibernation method, device and storage medium to solve the technical problem of imperfect hibernation in SOC multi-systems due to insufficient hardware management capability of RTOS system in the prior art.

[0005] In a first aspect, an embodiment of the present invention provides a multi-system hibernation method, comprising:

[0006] The non-root cell receives the SPI interrupt number of the SOC system sent by the root cell;

[0007] The non-root cell determines whether the SPI interrupt number is a sleep interrupt number. If it is a sleep interrupt number,

[0008] Freeze user processes for non-root cells;

[0009] Determine the external device according to the maintained power management linked list, traverse the system's power management linked list, and call the pause function of each device in turn to shut down the clock and power supply of the peripheral;

[0010] Save the CPU context of the non-root cell and save the CPU's general registers to the stack;

[0011] Write the sleep flag to the specified location of the sleep flag in the memory, and send the sleep state SPI interrupt number of the SOC system to the root cell;

[0012] The power management interface is used to power down the CPU and send an interrupt signal indicating that the sleep is complete to the root cell.

[0013] In a second aspect, an embodiment of the present invention further provides a multi-system hibernation device, comprising:

[0014] A receiving module is used to use a non-root cell to receive the SPI interrupt number of the SOC system sent by the root cell;

[0015] A freezing module, used to use a non-root cell to determine whether the SPI interrupt number is a dormant interrupt number, and when it is a dormant interrupt number, freeze the user process of the non-root cell;

[0016] The traversal module is used to determine the external device according to the maintained power management linked list, traverse the system's power management linked list, and call the pause function of each device in turn to shut down the clock and power supply of the peripheral device;

[0017] A writing module is used to write a sleep flag into a location specified by the sleep flag in the memory;

[0018] The sending module is used to realize CPU power-off by using the power management interface and send an interrupt signal of sleep completion to the root cell.

[0019] In a third aspect, an embodiment of the present invention further provides a storage medium comprising computer executable instructions, wherein the computer executable instructions, when executed by a computer processor, are used to execute the multi-system hibernation method provided in the above embodiment.

[0020] The multi-system hibernation method, device and storage medium provided by the embodiment of the present invention receive the SPI interrupt number of the SOC system sent by the root cell through the non-root cell; the non-root cell determines whether the SPI interrupt number is a hibernation interrupt number, and when it is a hibernation interrupt number, freezes the user process of the non-root cell; determines the external device according to the maintained power management chain list, traverses the system's power management chain list, and sequentially calls the pause function of each device to turn off the clock and power supply of the peripheral device; saves the CPU context of the non-root cell, and saves the general register of the CPU to the stack; writes the hibernation flag at the designated position of the hibernation flag bit in the memory, and sends the hibernation state SPI interrupt number of the SOC system to the root cell; uses the power management interface to realize CPU power-off, and sends the hibernation completion interrupt signal to the root cell. The non-root cell system itself completes the hibernation function of the hardware of this system. The non-root cell system is responsible for the device driver hibernation and CPU hibernation management of this system, without managing the DDR self-refresh module. The root cell sets the DDR to the self-refresh mode, so that the non-root cell can enter deep hibernation, and then the entire system can achieve the maximum low-power operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0022] Figure 1 This is a schematic diagram of a multi-system sleep and wake-up process provided by an embodiment of the present invention;

[0023] Figure 2 is a flowchart of a multi-system hibernation method provided in Embodiment 1 of the present invention;

[0024] Figure 3 is a flowchart of a multi-system hibernation method provided in Embodiment 2 of the present invention;

[0025] Figure 4 It is a structural diagram of a multi-system hibernation device provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0027] Embodiment 1

[0028] Figure 1 This is a schematic diagram of a multi-system sleep and wake-up process provided by an embodiment of the present invention; Figure 2: is a flowchart of a multi-system sleep method provided in Embodiment 1 of the present invention. This embodiment is applicable to the case where the RTOS in the SOC system is put into deep sleep. The method can be executed by a multi-system sleep device and specifically includes the following steps:

[0029] Step 110: The non-root cell receives the SPI interrupt number of the SOC system sent by the root cell.

[0030] System sleep has different depths. The deeper the sleep, the lower the power consumption, and the corresponding wake-up delay is greater. The shallower the sleep, the higher the power consumption, and the smaller the wake-up delay is.

[0031] According to the sleep state from light to deep, Linux currently supports four sleep modes: freeze, standby, mem and disk.

[0032] freeze (suspend to idle): This method freezes the processes in the system, suspends all devices that need to be suspended, and then switches the CPU to the idle process to put it into the idle state. It does not remove the CPU from the kernel, so once it is awakened, it only needs to exit from the idle state and restore the suspended devices and frozen processes.

[0033] Standby (suspend to standby): In addition to executing all freeze-related processes, this method also removes the secondary CPU from the kernel, and then the primary CPU enters standby sleep mode. Standby mode is a shallow sleep mode that does not power off the CPU, so there is no need to save the CPU context during sleep. Once it is awakened, the CPU can immediately start working and resume system operation in sequence.

[0034] mem (suspend to mem): also known as system suspension or hibernation mode, saves the system state to memory, shuts down most hardware devices to reduce power consumption, but the memory remains active. After the system is suspended, the CPU stops executing instructions, the hardware devices enter a low-power state, but the data in the memory is still maintained, so that the system can be quickly awakened and restored to the state before suspension.

[0035] Disk (suspend to disk or hibernate): This is the deepest type of hibernation mode, also known as cold boot or hibernation mode, which saves the system state to the hard disk or solid-state drive and then shuts down the computer. In hibernation mode, the CPU stops executing instructions, all hardware devices are turned off, and memory data is saved to disk. When the user restarts the computer, the system reads the data saved on the disk and restores to the state before hibernation.

[0036] For RTOS, taking freertos as an example, the main way for the system to sleep is to enter shallow sleep through task suspension, low power mode, etc., which is equivalent to freeze and standby of Linux system. Deep sleep cannot be achieved.

[0037] The multi-system sleep method provided in this embodiment can realize the deep sleep of RTOS. In this embodiment, based on the ARM64 architecture, the jailhouse version is v0.12, and the RTOS system is implemented using the freertos SOC system.

[0038] In a jailhouse, there are two types of cells: root cells and non-root cells. The root cell is the main cell in the jailhouse, and it is the environment where the main operating system and applications in the system run. The root cell is responsible for managing the entire hardware resources and has access to all functions of the system. Usually, the root cell will run a complete operating system, such as Linux or other similar systems, as well as user applications.

[0039] Non-root cells are auxiliary cells in the jailhouse. They run under the management of the root cell and are used to run specific real-time tasks or process specific hardware devices. The number and functions of non-root cells depend on the configuration and requirements of the system. Non-root cells usually focus on real-time tasks or specific hardware control, such as real-time data acquisition, real-time control, or drivers for specific devices. Compared with root cells, the permissions and functions of non-root cells are usually more strictly restricted to ensure the stability and security of the system. This embodiment is explained by taking the example of running the Linux system in the root cell and the FreeRTOS system in the non-root cell.

[0040] Jailhouse allows multiple operating systems to run on the same hardware through hardware isolation. The Linux system and the freertos system occupy different CPUs respectively. In this embodiment, the Linux system serves as the core of multi-system hibernation, especially executing the hibernation process. SPI is an interrupt signal generated by software used in SOC, which is used for communication and synchronization between processor cores in a multi-core system. When hibernation is required, the Linux system sends the SPI interrupt number of the SOC system to the freertos system, and puts the current process into hibernation

[0041] Step 120 , the non-root cell determines whether the SPI interrupt number is a dormant interrupt number, and when it is a dormant interrupt number, freezes the user process of the non-root cell.

[0042] In SOC, each interrupt number has a corresponding event, for example, serial port interrupt uses 34, network port interrupt uses 40, etc. However, some interrupt numbers are not used, that is, they are in idle state and are not occupied by hardware events.

[0043] The sleep process on the Linux system side sends an asynchronous SPI interrupt to the freertos system. After receiving the SPI interrupt, freertos determines whether it is a sleep request based on the interrupt number. For example, 216 is set as the interrupt number for the freertos system to sleep. Then, after receiving the interrupt, freeros determines the interrupt number. Only when the interrupt number is equal to 216, it is determined to be the sleep interrupt number. The freertos CPU triggers the sleep process, first freezing the freertos user process to prevent the user process from using the device.

[0044] Step 130, determine the external device according to the maintained power management linked list, traverse the system power management linked list, and call the pause function of each device in turn to turn off the clock and power supply of the peripheral device.

[0045] In this embodiment, when using jailhouse to allocate freertos hardware resources, the non-root cell freertos registers the devices used by the non-root cell and the corresponding sleep and wake-up functions into the power management list according to the configuration. The power management list contains which devices the freertos system is to manage, such as the serial port, I2C, SPI and other peripheral devices used by the freertos system itself. The drivers of these devices are registered with the freertos system, and thus added to the power management list of the system.

[0046] Correspondingly, when putting the device to sleep, the device interrupt can be turned off through GIC to prevent interference to the CPU during the device sleep period. Then the system power management list is traversed, and the pause function of each device is called in turn to turn off the clock and power supply of the peripherals to put the device to sleep.

[0047] Step 140, save the CPU context of the non-root cell and save the general registers of the CPU to the stack.

[0048] After completing the hibernation of the FreeRTOS system device, the CPU needs to be hibernated. First, turn off the CPU's interrupt response, so that the CPU shields all external interrupts, and then enters the CPU's hibernation process. The most important thing about CPU hibernation is the preservation of the CPU context. Its purpose is to save the CPU's operating status to the memory when the CPU is hibernating, and then restore the operating status from the memory to the CPU when the CPU wakes up. In this way, the system can quickly restore the power supply, clock, chip internal IP and external devices after waking up, so as not to affect the user's experience. Save the CPU's general registers to the stack, including the stack pointer, pc pointer, lr register, and X0-X28, and then save the system registers to the stack.

[0049] Step 150, write a sleep flag to the designated location of the sleep flag in the memory, and send the sleep state SPI interrupt number of the SOC system to the root cell.

[0050] A sleep flag is added to the sleep process of freertos. The sleep flag is actually a software variable. It is essentially a memory variable stored in a specific location in the memory. Because the memory is in self-refresh mode after the system is in sleep mode, the data in the memory will not be lost due to power failure. The memory variable can be used to mark the system sleep, which is different from the system shutdown. Set the sleep flag. And send an SPI interrupt to the CPU of the Linux system to wake up the sleep process of the Linux system. So that the sleep process of the Linux system can continue to perform subsequent sleep operations.

[0051] Step 160: Power off the CPU using the power management interface, and send a sleep completion interrupt signal to the root cell.

[0052] The power management interface uses the psci interface (Power State CoordinationInterface) in the arm SOC to start, shut down, and hot-swap the core. The psci interface is used to shut down freertos.

[0053] When there is a Linux and multiple RTOS systems, the Linux system sends a sleep command to multiple RTOS systems. The RTOS system falls into its own sleep process, which is the same as the method provided above. Then it is necessary to wait until all RTOS systems have completed sleep before sending a sleep completion interrupt to Linux, so that the Linux system can continue the sleep process of the Linux system. Until the Linux system itself is asleep.

[0054] In this embodiment, the non-root cell receives the SPI interrupt number of the SOC system sent by the root cell; the non-root cell determines whether the SPI interrupt number is a dormancy interrupt number, and when it is a dormancy interrupt number, freezes the user process of the non-root cell; determines the external device according to the maintained power management chain list, traverses the system's power management chain list, and sequentially calls the pause function of each device to turn off the clock and power supply of the peripheral device; saves the CPU context of the non-root cell, and saves the general register of the CPU to the stack; writes the dormancy flag at the designated position of the dormancy flag in the memory, and sends the dormancy state SPI interrupt number of the SOC system to the root cell; uses the power management interface to realize CPU power-off, and sends the dormancy completion interrupt signal to the root cell. The non-root cell system itself completes the dormancy function of the hardware of this system. The non-root cell system is responsible for the device driver dormancy and CPU dormancy management of this system, without the need to manage the DDR self-refresh module. The root cell sets the DDR to self-refresh mode, so that the non-root cell can enter deep dormancy, and the entire system can achieve the maximum low-power operation.

[0055] In a preferred implementation of the present embodiment, the method may further add the following steps: after receiving the interrupt signal of sleep completion sent by all non-root cells, the root cell turns off the memory controller, sets the DDR to self-refresh mode, and stops the external clock of DRAM. At the end of the Linux system sleep, the memory controller will be turned off, the DDR will be set to self-refresh mode, and the external clock of DRAM will be stopped, and the self-refresh state will be used to maintain the data in DRAM to save power. Linux implements the hardware management of the entire DDR, which makes freertos not need to complete the self-refresh function of DDR by itself. This is also the reason why a synchronization strategy is needed between the dual systems. If the Linux system enters sleep faster than the freertos system, it will cause the memory to be locked and the freertos system will fail to read and write memory. In the above manner, the above situation can be avoided.

[0056] Embodiment 2

[0057] Figure 3It is a flow chart of the multi-system sleep method provided by the second embodiment of the present invention. This embodiment is optimized based on the above embodiment, and the method can also add the following steps: after the wake-up source triggers the wake-up event, the wake-up process of the root cell is executed to restore the root cell to the state before the sleep; the root cell falls into the jailhouse through the HVC call, and the power management interface is called through the jailhouse to power on the non-root cell CPU; the non-root cell starts execution from the reset address set by the jailhouse, and reads the sleep flag in the position specified by the sleep flag, and determines whether it is a wake-up operation according to the sleep flag; when it is determined to be a wake-up operation, the data in the stack is restored to the corresponding general register, and the CPU context is restored; the power management linked list is traversed, and the clock and power supply of the peripherals are turned on in turn; the user process of the non-root cell is restored, and the sleep flag is cleared.

[0058] See also Figure 3 and Figure 1 , the multi-system hibernation method comprises:

[0059] Step 210, the non-root cell receives the SPI interrupt number of the SOC system sent by the root cell, and the non-root cell determines whether the SPI interrupt number is a sleep interrupt number. If it is a sleep interrupt number, the user process of the non-root cell is frozen.

[0060] Step 220, determine the external device according to the maintained power management linked list, traverse the system power management linked list, and call the pause function of each device in turn to turn off the clock and power supply of the peripheral device.

[0061] Step 230, save the CPU context of the non-root cell, save the general registers of the CPU to the stack, write the sleep flag to the designated location of the sleep flag in the memory, and send the sleep state SPI interrupt number of the SOC system to the root cell.

[0062] Step 240, use the power management interface to power off the CPU, and send a sleep completion interrupt signal to the root cell.

[0063] Step 250: After the wake-up source triggers the wake-up event, the wake-up process of the root cell is executed to restore the root cell to the state before the sleep state.

[0064] The wake-up process of multiple systems corresponds to the sleep process one by one. When the wake-up source triggers a wake-up event, the wake-up process of the Linux system is executed, and finally the Linux system is restored to the state before the sleep state.

[0065] Step 260: The root cell falls into the jailhouse through the HVC call, and the jailhouse calls the power management interface to power on the non-root cell CPU.

[0066] The Linux system falls into the jailhouse through HVC calls, and the jailhouse calls the power management interface to power on the FreeRTOS system CPU. After the CPU is powered on, it starts to execute from the reset address set by the jailhouse. The reset address is set by the jailhouse for the FreeRTOS system and has nothing to do with hibernation. After the FreeRTOS system is started or awakened, it starts to execute from the reset address, that is, the compilation location of the system link.

[0067] Step 270, the non-root cell starts executing from the reset address set by the jailhouse, and reads the sleep flag in the position specified by the sleep flag, and determines whether it is a wake-up operation based on the sleep flag; when it is determined to be a wake-up operation, the data in the stack is restored to the corresponding general register, and the CPU context is restored.

[0068] The system first reads the sleep flag. If it determines that this reset is a wake-up operation, it executes the subsequent wake-up process and clears the sleep flag. Otherwise, it executes the normal power-on initialization program. The wake-up process is the opposite of the sleep process. The contents of the registers during sleep are restored, and the freertosCPU context is read and restored.

[0069] Step 280, traverse the power management linked list, turn on the clock and power supply of the peripherals in turn; restore the user process of the non-root cell, and clear the sleep flag.

[0070] The power supply of the external device is restored through the corresponding device function, and the corresponding clock is turned on. After the device is restored, the user process frozen during sleep is restored, and the sleep flag is cleared from the specified location in the memory.

[0071] This embodiment adds the following steps: after the wake-up source triggers the wake-up event, the root cell wake-up process is executed to restore the root cell to the state before the sleep state; the root cell falls into the jailhouse through the HVC call, and the jailhouse calls the power management interface to power on the non-root cell CPU; the non-root cell starts to execute from the reset address set by the jailhouse, and reads the sleep flag in the position specified by the sleep flag, and determines whether it is a wake-up operation according to the sleep flag; when it is determined to be a wake-up operation, the data in the stack is restored to the corresponding general register, and the CPU context is restored; the power management linked list is traversed, and the clock and power supply of the peripherals are turned on in turn; the user process of the non-root cell is restored, and the sleep flag is cleared. The RTOS and the entire system can enter a deep sleep state, further saving power consumption. At the same time, the wake-up process is accelerated, and there is no need to execute the initialization program of the entire system, but the operating state of the system is directly restored from the memory, so that the system responds to user needs faster. At the same time, it can extend the life of the hardware, reduce the temperature, improve performance and reduce noise.

[0072] Embodiment 3

[0073] Figure 4 is a schematic diagram of the structure of a multi-system sleep device provided by Embodiment 3 of the present invention, see Figure 3 , the multi-system hibernation device comprises:

[0074] The receiving module 310 is used to receive the SPI interrupt number of the SOC system sent by the root cell using the non-root cell;

[0075] A freezing module 320, used to use a non-root cell to determine whether the SPI interrupt number is a dormant interrupt number, and when it is a dormant interrupt number, freeze the user process of the non-root cell;

[0076] The traversal module 330 is used to determine the external device according to the maintained power management linked list, traverse the power management linked list of the system, and call the pause function of each device in turn to shut down the clock and power supply of the peripheral device;

[0077] A saving module 340 is used to save the CPU context of the non-root cell and save the general registers of the CPU into a stack;

[0078] A writing module 350 is used to write a sleep flag into a location specified by the sleep flag in the memory;

[0079] The sending module 360 ​​is used to realize CPU power-off by using the power management interface, and send an interrupt signal of sleep completion to the root cell.

[0080] The multi-system hibernation device provided in this embodiment receives the SPI interrupt number of the SOC system sent by the root cell through the non-root cell; the non-root cell determines whether the SPI interrupt number is a hibernation interrupt number, and when it is a hibernation interrupt number, freezes the user process of the non-root cell; determines the external device according to the maintained power management chain list, traverses the system's power management chain list, and sequentially calls the pause function of each device to turn off the clock and power supply of the peripheral device; saves the CPU context of the non-root cell, and saves the general register of the CPU to the stack; writes the hibernation flag at the designated position of the hibernation flag bit in the memory, and sends the hibernation state SPI interrupt number of the SOC system to the root cell; uses the power management interface to realize CPU power-off, and sends the interrupt signal of hibernation completion to the root cell. The non-root cell system itself completes the hibernation function of the hardware of this system. The non-root cell system is responsible for the device driver hibernation and CPU hibernation management of this system, without the need to manage the DDR self-refresh module. The root cell sets the DDR to the self-refresh mode, so that the non-root cell can enter deep hibernation, and then the entire system can achieve the maximum low-power operation.

[0081] Based on the above embodiments, the device further includes:

[0082] The setting module is used for the root cell to shut down the memory controller, set the DDR to the self-refresh mode, and stop the external clock of the DRAM after receiving the interrupt signal of the sleep completion sent by all non-root cells.

[0083] Based on the above embodiments, the device further includes:

[0084] The device interrupt disabling module is used to disable device interrupts through GIC to prevent interference to the CPU during device sleep.

[0085] Based on the above embodiments, the device further includes:

[0086] A wake-up process execution module is used to execute the wake-up process of the root cell after the wake-up source triggers the wake-up event, so that the root cell is restored to the state before the sleep state;

[0087] The power-on module is used to make the root cell fall into the jailhouse through HVC calls, and to power on the non-root cell CPU by calling the power management interface through the jailhouse;

[0088] A determination module, used to make the non-root cell start execution from the reset address set by the jailhouse, and read the sleep flag in the position specified by the sleep flag bit, and determine whether it is a wake-up operation according to the sleep flag;

[0089] A recovery module, used to restore the data in the stack to the corresponding general register and restore the CPU context when it is determined to be a wake-up operation;

[0090] The opening module is used to traverse the power management list and turn on the clock and power supply of the peripherals in turn;

[0091] The clear module is used to resume the user process of non-root cells and clear the sleep flag.

[0092] Based on the above embodiments, the sending module includes:

[0093] The execution module is used to execute the shutdown function of the CPU by utilizing the psci interface of the SOC.

[0094] Based on the above embodiments, the device further includes:

[0095] The registration module is used to enable the non-root cell to register the device used by the non-root cell and the corresponding sleep and wake-up functions into the power management linked list according to the configuration.

[0096] The multi-system sleep device provided in the embodiment of the present invention can execute the multi-system sleep method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0097] Embodiment 4

[0098] Embodiment 4 of the present invention further provides a storage medium containing computer executable instructions, and when the computer executable instructions are executed by a computer processor, they are used to execute any of the multi-system hibernation methods provided in the above embodiments.

[0099] The computer storage medium of the embodiment of the present invention may adopt any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device.

[0100] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0101] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0102] Computer program code for performing the operation of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or device. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0103] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A multi-system hibernation method, characterized in that: include: The non-root cell receives the SPI interrupt number of the SOC system sent by the root cell; The non-root cell determines whether the SPI interrupt number is a dormant interrupt number, and when it is a dormant interrupt number, freezes the user process of the non-root cell; Determine the external device according to the maintained power management linked list, traverse the system's power management linked list, turn off the device interrupt through GIC to prevent interference to the CPU during device sleep, and call the pause function of each device in turn to turn off the clock and power supply of the peripheral; After finishing the hibernation of the FreeRTOS system device, save the CPU context of the non-root cell and save the general registers of the CPU to the stack; Write the sleep flag to the designated location of the sleep flag in the memory, and send the sleep state SPI interrupt number of the SOC system to the root cell; use the power management interface to power off the CPU, and send a sleep completion interrupt signal to the root cell; After receiving the interrupt signals of sleep completion sent by all non-root cells, the root cell shuts down the memory controller, sets the DDR to the self-refresh mode, and stops the external clock of the DRAM.

2. The method according to claim 1, characterized in that The method further comprises: After the root cell sends the SPI interrupt number of the SOC system, the process goes into sleep mode; After receiving the SPI interrupt number of the SOC system, wake up the sleeping process.

3. The method according to claim 1, characterized in that The method further comprises: After the wake-up source triggers the wake-up event, the wake-up process of the root cell is executed to restore the root cell to the state before sleep; The root cell falls into the jailhouse through HVC calls, and the jailhouse calls the power management interface to power on the non-root cell CPU; The non-root cell starts executing from the reset address set by the jailhouse, and reads the sleep flag in the position specified by the sleep flag bit, and determines whether it is a wake-up operation according to the sleep flag; When it is determined to be a wake-up operation, the data in the stack is restored to the corresponding general registers, and the CPU context is restored; Traverse the power management linked list and turn on the clock and power supply of the peripherals in turn; Resume the user process of the non-root cell and clear the sleep flag.

4. The method according to claim 1, characterized in that: The method of using the power management interface to power off the CPU includes: The CPU shutdown function is executed using the psci interface of the SOC.

5. The method according to claim 1, characterized in that The method further comprises: The non-root cell registers the device used by the non-root cell and the corresponding sleep and wake-up functions into the power management linked list according to the configuration.

6. A multi-system hibernation device, characterized in that: include: A receiving module is used to use a non-root cell to receive the SPI interrupt number of the SOC system sent by the root cell; A freezing module, used to use a non-root cell to determine whether the SPI interrupt number is a dormant interrupt number, and when it is a dormant interrupt number, freeze the user process of the non-root cell; The traversal module is used to determine the external device according to the maintained power management linked list, traverse the system's power management linked list, turn off the device interrupt through GIC to prevent interference to the CPU during device sleep, and call the pause function of each device in turn to turn off the clock and power supply of the peripheral; The saving module is used to save the CPU context of the non-root cell and save the general registers of the CPU to the stack after completing the hibernation of the freertos system device; A writing module is used to write a sleep flag into a location specified by the sleep flag in the memory; The sending module is used to realize CPU power-off by using the power management interface and send an interrupt signal of sleep completion to the root cell; The setting module is used for the root cell to shut down the memory controller, set the DDR to the self-refresh mode, and stop the external clock of the DRAM after receiving the interrupt signal of the sleep completion sent by all non-root cells.

7. A storage medium containing computer executable instructions, characterized in that: When the computer executable instructions are executed by a computer processor, they are used to execute the multi-system hibernation method according to any one of claims 1 to 5.

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