Sub-pixel circuit, display panel and display device

Abstract

An embodiment of the present application may provide a sub-pixel circuit including: a light emitting element configured to receive a high-potential driving voltage at an anode; a driving transistor including a first node, a second node, and a third node; a scan transistor controlled by a first scan signal and transmitting a data voltage through a data line; a storage capacitor; and a control circuit configured to control operations of the driving transistor, the scan transistor, and the storage capacitor and located between a cathode of the light emitting element and a low potential reference voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0118949, filed on September 7, 2023, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] Embodiments of the present application relate to a sub-pixel circuit, a display panel, and a display device capable of stable operation. Background Art

[0004] Representative display devices that display images based on digital data include a liquid crystal display device (LCD) using liquid crystals and an organic light emitting display device using an organic light emitting diode (OLED).

[0005] Among them, the active matrix organic light emitting display device uses an organic light emitting diode that emits light by itself, and has the advantages of fast response speed, high light emitting efficiency, high brightness and wide viewing angle.

[0006] The organic light-emitting display device includes a driving transistor (thin film transistor) to control the driving current flowing through the organic light-emitting diode. It is ideal that the electrical characteristics of the driving transistor (such as threshold voltage and mobility) are designed to be the same in all sub-pixels, but in practice, the electrical characteristics of the driving transistor of each sub-pixel are variable depending on process conditions, driving environment, etc. Therefore, the driving current based on the same data voltage may be different for each sub-pixel, resulting in brightness deviation between sub-pixels.

[0007] To solve this problem, image quality compensation technology can be used to reduce brightness deviation by sensing the electrical characteristics (threshold voltage, mobility) of the driving transistor in each sub-pixel and appropriately compensating the input data according to the sensing results.

[0008] The internal compensation method in the image quality compensation technology controls the driving timing of the sub-pixels to eliminate the change in the electrical characteristics of the driving transistor when the organic light-emitting diode emits light. The internal compensation method can basically use a source follower scheme to increase the gate voltage of the driving transistor, thereby performing a sampling operation that saturates the driving transistor to a certain level.

[0009] During the internal compensation process, the gate node and the source node of the driving transistor become floating states, and the gate-source voltage of the driving transistor may vary due to parasitic capacitance other than the storage capacitor, which may cause defects such as crosstalk. Summary of the invention

[0010] Here, the inventors of the present application have invented a sub-pixel circuit, a display panel, and a display device capable of stably operating a driving transistor during an internal compensation process.

[0011] Embodiments of the present application may provide a sub-pixel circuit, a display panel, and a display device that can stably maintain a source voltage of a driving transistor by connecting an organic light emitting diode to a common anode structure.

[0012] In addition, the embodiments of the present application may provide a low-power sub-pixel circuit, a display panel, and a display device that can reduce power consumption by stably operating a driving transistor.

[0013] According to an embodiment, the present application may provide a sub-pixel circuit, comprising: a light-emitting element configured to receive a high-potential driving voltage at an anode; a driving transistor comprising a first node, a second node, and a third node; a scanning transistor controlled by a first scanning signal and transmitting a data voltage through a data line; a storage capacitor; and a control circuit configured to control the operation of the driving transistor, the scanning transistor, and the storage capacitor and located between the cathode of the light-emitting element and a low-potential reference voltage line.

[0014] According to an embodiment, the present application may provide a display panel, comprising: a light-emitting element configured to receive a high-potential driving voltage at an anode; a driving transistor comprising a first node, a second node, and a third node; a scanning transistor controlled by a first scanning signal and transmitting a data voltage through a data line; a storage capacitor; and a control circuit configured to control the operation of the driving transistor, the scanning transistor, and the storage capacitor and located between the cathode of the light-emitting element and a low-potential reference voltage line.

[0015] According to an embodiment, the present application may provide a display device, comprising: a display panel having a plurality of sub-pixels; a gate driving circuit configured to provide a plurality of gate signals to the display panel through a plurality of gate lines; a data driving circuit configured to provide a plurality of data voltages to the display panel through a plurality of data lines; and a timing controller configured to control the gate driving circuit and the data driving circuit, wherein each of the plurality of sub-pixels comprises: a light-emitting element configured to receive a high-potential driving voltage at an anode; a driving transistor comprising a first node, a second node, and a third node; a scanning transistor controlled by a first scanning signal and transmitting a data voltage through a corresponding data line; a storage capacitor; and a control circuit configured to control the operation of the driving transistor, the scanning transistor, and the storage capacitor and located between the cathode of the light-emitting element and a low-potential reference voltage line.

[0016] According to the embodiments of the present invention, the driving transistor can be stably operated during the internal compensation process.

[0017] According to the embodiments of the present invention, the source voltage of the driving transistor can be stably maintained by connecting the organic light emitting diode to the common anode structure.

[0018] According to the embodiments of the present invention, power consumption can be reduced by stably operating a driving transistor, thereby achieving low-power operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present application will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a view schematically showing a configuration of a display device according to an embodiment of the present application;

[0021] Figure 2 is a schematic diagram showing a system of a display device according to an embodiment of the present application;

[0022] Figure 3 is a schematic diagram showing a sub-pixel circuit of a display device according to an embodiment of the present application;

[0023] Figure 4 is a schematic diagram showing the driving timing of sub-pixels according to an embodiment of the present application;

[0024] Figure 5 is a schematic diagram showing signal waveforms in respective nodes of a driving transistor depending on driving timing of a sub-pixel according to an embodiment of the present application;

[0025] Figure 6 is a schematic diagram showing a sub-pixel circuit of a display device according to another embodiment of the present application;

[0026] Figure 7 is a schematic diagram showing the driving timing of a sub-pixel according to another embodiment of the present application;

[0027] Figure 8 is a schematic diagram showing signal waveforms in respective nodes of a driving transistor depending on driving timing of a sub-pixel according to another embodiment of the present application;

[0028] Fig. 9 A structure considering possible deformation of sub-pixels in a display device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] Hereinafter, some embodiments of the present application will be described in detail with reference to the exemplary drawings. In the following description of the examples or embodiments of the present invention, reference will be made to the drawings, in which specific examples or embodiments that can be implemented are shown, and even when the same or similar parts are shown in different drawings from each other, the same reference numerals and symbols may be used to represent the same or similar parts. In addition, in the following description of the examples or embodiments of the present invention, when it is determined that the description may make the subject matter in some embodiments of the present invention less clear, the detailed description of the well-known functions and components contained in this article will be omitted. Terms such as "including", "having", "containing", "consisting of", "consisting of" and "formed of" used herein generally tend to allow the addition of other components unless these terms are used with "only". The singular form used in this article tends to include the plural form unless the context clearly indicates otherwise.

[0030] Terms such as "first", "second", "A", "B", "(A)" or "(B)" etc. may be used herein to describe elements of the present invention. Each of these terms is not used to define the nature, order, sequence or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0031] When it is mentioned that a first element is “connected or coupled”, “contacting or overlapping” a second element, it should be interpreted that the first element may not only be “directly connected or coupled” or “directly contacting or overlapping” the second element, but also a third element may be “inserted” between the first element and the second element, or the first element and the second element may be “connected or coupled”, “contacting or overlapping” each other via a fourth element. Here, at least one of the two or more elements that are “connected or coupled”, “contacting or overlapping” each other may include the second element.

[0032] When time-related terms such as “after,” “later,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or method of manufacture, these terms may be used to describe non-sequential or non-sequential processes or operations unless used with “directly” or “immediately.”

[0033] In addition, when referring to any dimension, relative size, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if the relevant description is not specifically stated. In addition, "may" fully encompasses all meanings of "can".

[0034] Hereinafter, various embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a view schematically showing a configuration of a display device according to an embodiment of the present application.

[0036] Reference Figure 1 According to an embodiment of the present application, a display device 100 may include a display panel 110, a gate driving circuit 120, a data driving circuit 130, a timing controller 140, and a power management circuit 150. A plurality of gate lines GL and data lines DL are connected to the display panel 110 and a plurality of sub-pixels SP are arranged in a matrix form. The gate driving circuit 120 is used to drive the plurality of gate lines GL, the data driving circuit 130 is used to provide data voltages through the plurality of data lines DL, and the timing controller 140 is used to control the gate driving circuit 120 and the data driving circuit 130.

[0037] The display panel 110 displays an image based on a scan signal transmitted from the gate driving circuit 120 through the plurality of gate lines GL and a data voltage transmitted from the data driving circuit 130 through the plurality of data lines DL.

[0038] In the case of a liquid crystal display, the display panel 110 may include a liquid crystal layer formed between two substrates, and may operate in any known mode, such as a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching (IPS) mode, or a fringe field switching (FFS) mode. In the case of an organic light emitting display, the display panel 110 may be implemented in a top emission scheme, a bottom emission scheme, or a bidirectional emission scheme.

[0039] In the display panel 110, a plurality of pixels may be arranged in a matrix form, and each pixel may include sub-pixels SP having different colors, such as white, red, green, and blue sub-pixels, and each sub-pixel SP may be defined by a plurality of data lines DL and a plurality of gate lines GL.

[0040] One subpixel SP may include, for example, a thin film transistor (TFT) formed at an intersection between one data line DL and one gate line GL, a light emitting element (eg, an organic light emitting diode) charged with a data voltage, and a storage capacitor electrically connected to the light emitting element to maintain a voltage.

[0041] For example, when the display device 100 having a resolution of 2160×3840 includes four sub-pixels SP of white (W), red (R), green (G), and blue (B), 2160 gate lines GL may be connected to the four sub-pixels WRGB, and 3840×4=15360 data lines DL may be provided. Each sub-pixel SP is arranged at the intersection of the corresponding gate line GL and the corresponding data line DL.

[0042] The gate driving circuit 120 may be controlled by the timing controller 140 to sequentially output scan signals to a plurality of gate lines GL disposed in the display panel 110 , thereby controlling driving timings of the plurality of sub-pixels SP.

[0043] Depending on the actual situation, the gate driving circuit 120 may output a scanning signal for controlling the driving timing of the sub-pixel SP and a light emitting signal for controlling the light emitting timing of the sub-pixel SP. In this case, the gate signal output from the gate driving circuit 120 may include a scanning signal and a light emitting signal. The circuit outputting the scanning signal and the circuit outputting the light emitting signal may be implemented as independent circuits or as one circuit.

[0044] In the display device 100 with a resolution of 2160×3840, the scanning signal is sequentially output to 2160 gate lines GL from the first gate line to the 2160th gate line, which is called 2160-phase driving. The scanning signal is sequentially output to each unit composed of four gate lines GL, for example, after the scanning signal is sequentially output to the first gate line to the fourth gate line, the scanning signal is sequentially output to the fifth gate line to the eighth gate line, which is called 4-phase driving. In other words, the scanning signal is sequentially output to every N gate lines GL can be called N-phase driving.

[0045] The gate drive circuit 120 may include one or more gate drive integrated circuits (GDICs). Depending on the driving scheme, the gate drive circuit 120 may be located only on one side of the display panel 110, or on each of two opposite sides of the display panel 110. The gate drive circuit 120 may be implemented in the form of a gate-in-panel (GIP) embedded in the border area of ​​the display panel 110.

[0046] The data driving circuit 130 receives the image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, when the data voltage is output to each data line DL according to the timing of applying the scan signal to the gate line GL, each sub-pixel SP connected to the data line DL displays an image with brightness corresponding to the data voltage.

[0047] Likewise, the data driving circuit 130 may include one or more source driver integrated circuits SDIC, and the source driver integrated circuits SDIC may be connected to bonding pads of the display panel 110 in a tape automated bonding (TAB) form or a chip on glass (COG) form or may be directly disposed on the display panel 110 .

[0048] In some cases, each source driver integrated circuit SDIC may be integrated and disposed on the display panel 110. In addition, each source driver integrated circuit SDIC may be implemented in a chip on film (COF) form, and in this case, each source driver integrated circuit SDIC may be mounted on a circuit film and may be electrically connected to the data line DL of the display panel 110 through the circuit film.

[0049] The timing controller 140 provides various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130. In other words, the timing controller 140 may control the gate driving circuit 120 to output a scan signal according to the timing in each frame, and on the other hand, transmit the image data DATA received from the outside to the data driving circuit 130.

[0050] In this case, the timing controller 140 receives several timing signals including, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK, and the image data DATA from the external host system 200 .

[0051] The host system 200 may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

[0052] Therefore, the timing controller 140 may generate a control signal according to various timing signals received from the host system 200 and transmit the control signal to the gate driving circuit 120 and the data driving circuit 130 .

[0053] For example, the timing controller 140 outputs various gate control signals including, for example, a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE to control the gate drive circuit 120. The gate start pulse GSP controls the timing at which one or more gate drive integrated circuits GDIC constituting the gate drive circuit 120 start operating. The gate clock GCLK is a clock signal commonly input to one or more gate drive integrated circuits GDIC and controls the shift timing of the scan signal. The gate output enable signal GOE indicates timing information of one or more gate drive integrated circuits GDIC.

[0054] The timing controller 140 outputs various data control signals including, for example, a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE to control the data driving circuit 130. The source start pulse SSP controls the timing at which one or more source driver integrated circuits SDIC constituting the data driving circuit 130 start data sampling. The source clock SCLK is a clock signal that controls the timing of sampling data in the source driver integrated circuit SDIC. The source output enable signal SOE controls the output timing of the data driving circuit 130.

[0055] The display device 100 may further include a power management circuit 150 that provides various voltages or currents to, for example, the display panel 110 , the gate driving circuit 120 , and the data driving circuit 130 , or controls the various voltages or currents to be provided.

[0056] The power management circuit 150 regulates a direct current (DC) input voltage Vin provided from the host system 200 to generate power required to drive the display panel 100 , the gate driving circuit 120 , and the data driving circuit 130 .

[0057] The sub-pixel SP is located at the intersection between the gate line GL and the data line DL, and a light emitting element may be provided in each sub-pixel SP. For example, an organic light emitting diode display may include a light emitting element such as an organic light emitting diode in each sub-pixel SP, and may display an image by controlling a current flowing to the light emitting element according to a data voltage.

[0058] The display apparatus 100 may be one of various types of devices, such as a liquid crystal display, an organic light emitting diode display, or a plasma display panel.

[0059] Figure 2 is a schematic diagram showing a system of a display device according to an embodiment of the present application.

[0060] Reference Figure 2 According to an embodiment of the present application, the display device 100 may include a plurality of source driver integrated circuits SDIC and a gate driver circuit 120 in a data driver circuit 130, and the source driver integrated circuit SDIC is implemented by a COF structure among various structures such as TAB, COG and COF, and the gate driver circuit 120 is implemented by a GIP structure among various structures such as TAB, COG, COF and GIP.

[0061] When the gate driving circuit 120 has a GIP structure, a plurality of gate driving integrated circuits GDIC in the gate driving circuit 120 may be directly formed in the frame region of the display panel 110. Here, various signals required to generate a scanning signal, such as a clock, a gate high signal, and a gate low signal, may be provided to the gate driving integrated circuit GDIC through gate driving related signal lines disposed in the frame region.

[0062] Similarly, the source driver integrated circuits SDIC of the data driver circuit 130 may be mounted on the source films SF, respectively. One side of each source film SF may be electrically connected to the display panel 110. In addition, a conductive line for electrically connecting the source driver integrated circuit SDIC to the display panel 110 may be provided on the top of the source film SF.

[0063] The display device 100 may include at least one source printed circuit board SPCB and a control printed circuit board CPCB for connecting a plurality of source driving integrated circuits SDIC to circuits of other devices. Here, control components and various electrical devices may be mounted on the control printed circuit board CPCB.

[0064] Here, the other side of the source film SF on which the source driver integrated circuit SDIC is mounted may be connected to the source printed circuit board SPCB. That is, each source film SF on which the source driver integrated circuit SDIC is mounted may be configured such that one side thereof is electrically connected to the display panel 110 and the other side thereof is electrically connected to the source printed circuit board SPCB.

[0065] The timing controller 140 and the power management circuit 150 may be mounted on the control printed circuit board CPCB. The timing controller 140 may control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may provide a driving voltage or current to the display panel 110, the data driving circuit 130, the gate driving circuit 120, etc., and may control the provided voltage or current.

[0066] The source printed circuit board SPCB and the control printed circuit board CPCB may be circuit-connected to each other through at least one connecting member. The connecting member may be, for example, a flexible flat cable (FFC), a flexible printed circuit (FPC), etc. In addition, the source printed circuit board SPCB and the control printed circuit board CPCB may be integrated into a single printed circuit board (PCB).

[0067] The display device 100 may further include a setting board 170 electrically connected to the control printed circuit board CPCB. Here, the setting board 170 may also be referred to as a power distribution board. The setting board 170 may be provided with a main power management circuit 160 to manage the total power of the display device 100. The main power management circuit 160 may operate in conjunction with the power management circuit 150.

[0068] In the display device 100 having the above configuration, a driving voltage is generated by the setting board 170 and transmitted to the power management circuit 150 in the control printed circuit board CPCB. The power management circuit 150 transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board SPCB through a flexible printed circuit or a flexible flat cable (FFC). The driving voltage transmitted to the source printed circuit board SPCB is provided through the source driver integrated circuit SDIC to make a specific sub-pixel SP in the display panel 110 emit light or sense a specific sub-pixel SP in the display panel 110.

[0069] Here, each sub-pixel SP arranged in the display panel 110 of the display device 100 may include a light emitting element and a circuit element for driving the light emitting element, for example, a driving transistor.

[0070] The type and number of circuit elements provided in each sub-pixel SP may be determined differently depending on the function and design to be provided.

[0071] Figure 3 is a schematic diagram showing a sub-pixel circuit of a display device according to an embodiment of the present application.

[0072] Reference Figure 3 According to an embodiment of the present application, the sub-pixel circuit SPC of the display device 100 may include a light emitting element ED, a plurality of transistors T1 - T7 for driving the light emitting element ED, and a plurality of capacitors Cst, CA.

[0073] Here, as an example, a 7T2C sub-pixel SP composed of 7 transistors T1-T7 and 2 capacitors Cst and CA is shown, but the circuit elements arranged in the sub-pixel SP may be implemented in various ways according to the type of the display device 100. In addition, the case where the transistors T1-T7 provided in the sub-pixel SP are N-type transistors is shown, but in some cases, the sub-pixel SP may also be composed of P-type transistors.

[0074] When the sub-pixel SP is composed of a P-type transistor, the scan signals SCAN1 , SCAN2 , SCAN3 , SCAN4 may have opposite polarities to those when the sub-pixel SP is composed of an N-type transistor.

[0075] When the sub-pixel SP is configured as 7T2C, each sub-pixel SP may include 7 transistors T1 - T7 and 2 capacitors Cst, CA.

[0076] The sub-pixel SP of the present application may be configured such that a high potential driving voltage VDD is commonly supplied to anodes of the light emitting elements ED to stably operate the driving transistor.

[0077] The high potential driving voltage VDD is supplied to the anode of the light emitting element ED, and the cathode of the light emitting element ED is electrically connected to the first transistor T1. For example, the light emitting element ED may be an organic light emitting diode OLED.

[0078] The first transistor T1 may be controlled by the light emitting signal EM and may be electrically connected between the cathode of the light emitting element ED and the second transistor T2. The first transistor T1 may also be referred to as a light emitting transistor.

[0079] The second transistor T2 may have a first node N1, a second node N2, and a third node N3. The first node N1 may be a gate node and may be electrically connected to the fourth transistor T4 and the fifth transistor T5. The second node N2 may be a drain node or a source node and may receive a low potential reference voltage VSS provided by the third transistor T3. The third node N3 may be a source node or a drain node and may be electrically connected to the cathode of the light emitting element ED through the first transistor T1. The second transistor T2 may also be referred to as a driving transistor.

[0080] The third transistor T3 can be controlled by the light emitting signal EM and can be electrically connected between the second node N2 and the low potential reference voltage VSS, for example, between the second node N2 and the line providing the low potential reference voltage VSS. The line providing the low potential reference voltage VSS can be any entity or part providing the voltage VSS. The third transistor T3 can also be referred to as a light emitting transistor. Therefore, here, the first transistor T1 and the third transistor T3 can be equivalent to light emitting transistors.

[0081] The fourth transistor T4 may be controlled by the first scan signal SCAN1 and may be electrically connected between a line for supplying the data voltage VDATA and the first node N1 of the second transistor T2. The fourth transistor T4 may also be referred to as a scan transistor.

[0082] The fifth transistor T5 may be controlled by the third scan signal SCAN3 and may be electrically connected between a node for providing the gate initialization voltage VINIT and the first node N1 of the second transistor T2. The fifth transistor T5 may also be referred to as an initialization transistor.

[0083] The sixth transistor T6 may be controlled by the fourth scan signal SCAN4 and may be electrically connected between a node for providing the set voltage VSET and the third node N3 of the second transistor T2. The sixth transistor T6 may also be referred to as a set transistor.

[0084] The seventh transistor T7 may be controlled by the second scan signal SCAN2 and may be electrically connected between a node for providing a reset voltage VAR and a second node N2 of the second transistor T2. The seventh transistor T7 may also be referred to as a reset transistor.

[0085] However, the second scan signal SCAN2 supplied to the seventh transistor T7 may be the same signal having a different phase from the fourth scan signal SCAN4 supplied to the sixth transistor T6. For example, when the fourth scan signal SCAN4 is supplied to the nth gate line, the second scan signal SCAN2 may use the fourth scan signal SCAN4 supplied to the n-1th gate line. That is, depending on the phase of driving the display panel 110, the second scan signal SCAN2 may use the fourth scan signal SCAN4 at a different gate line GL.

[0086] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the second transistor T2 and may maintain the data voltage VDATA for one frame.

[0087] The auxiliary capacitor CA may be connected between the second node N2 of the second transistor T2 and the low potential reference voltage VSS line and may be used to maintain the voltage supplied to the second node N2. The auxiliary capacitor CA may be connected to the second node N2 and may function as a source follower to improve the efficiency of the voltage supplied to the second node N2 of the second transistor T2.

[0088] The transistors T1 - T7 constituting the sub-pixel SP may be P-type transistors or N-type transistors.

[0089] P-type transistors are more reliable than N-type transistors. In the case of a P-type transistor, the driving transistor T2 can be fixed to the high potential driving voltage VDD during the period when the light emitting element ED emits light, so the current flowing through the light emitting element ED can be stably provided without fluctuation.

[0090] When operating in a saturation period, the P-type transistor can flow a constant current regardless of a change in a threshold voltage, and thus it has higher reliability.

[0091] On the other hand, because the N-type transistor uses electrons rather than holes as carriers, it has faster mobility than the P-type transistor, which can increase the switching speed.

[0092] The N-type transistor may be an oxide transistor formed using an oxide semiconductor, for example, a transistor having a channel formed of an oxide semiconductor such as indium gallium zinc oxide or IGZO. The P-type transistor may be a silicon transistor formed using a silicon semiconductor, for example, a transistor having a polysilicon channel formed using a low temperature process (referred to as LTPS or low temperature polysilicon).

[0093] In the display device 100 of the present application, when the sub-pixel circuit SPC is configured so that the high-potential driving voltage VDD is commonly provided to the anode of the light-emitting element ED, all transistors T1-T7 constituting the sub-pixel SP can be N-type transistors, or at least the second transistor (driving transistor) T2 can be an N-type transistor for stable operation.

[0094] Here, a case is shown where the transistors T1 to T7 constituting the sub-pixel SP are N-type transistors.

[0095] In addition, the terminology of the source node and the drain node of the transistor may change depending on the polarity of the input voltage.

[0096] Figure 4 is a schematic diagram showing the driving timing of sub-pixels according to an embodiment of the present application, Figure 5 is a schematic diagram showing signal waveforms in respective nodes of a driving transistor depending on driving timing of a sub-pixel according to an embodiment of the present application.

[0097] Reference Figure 4 and Figure 5 According to the embodiment of the present application, the sub-pixel can operate in an initialization period Initial, a sampling period Sampling, a programming period Program and a light emitting period Emission.

[0098] The initialization period Initial is a period in which a reset voltage VAR is supplied to the sub-pixel SP to reset the data voltage supplied to the light-emitting element ED. The sampling period Sampling is a period in which the threshold voltage of the driving transistor T2 is stored in the capacitor connected to the driving transistor T2. The programming period Program is a period in which a data voltage VDATA is supplied to the sub-pixel SP to store the data voltage VDATA in the capacitor connected to the driving transistor T2.

[0099] Although the sampling period Sampling is different from the programming period Program, the sampling period Sampling and the programming period Program may be performed sequentially or simultaneously according to the sub-pixel structure. In the sub-pixel structure described in the embodiment of the present application, the case where the sampling period Sampling and the programming period Program are performed sequentially is shown.

[0100] The light emission period Emission is a period in which the light emitting element ED is caused to emit light using the data voltage VDATA stored in the capacitor without supplying the data voltage VDATA through the data line connected to each light emitting element ED.

[0101] During the initialization period Initial, the third scan signal SCAN3 and the second scan signal SCAN2 are provided at a high level, and thus the fifth transistor T5 and the seventh transistor T7 are turned on.

[0102] Therefore, the gate node of the second transistor (driving transistor) T2 may be initialized to the gate initialization voltage VINIT, and the second node N2 of the second transistor T2 may be reset to the reset voltage VAR.

[0103] During the initialization period Initial, the emission signal EM, the first scan signal SCAN1, and the fourth scan signal SCAN4 are provided at a low level, and thus the first transistor T1, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned off.

[0104] Therefore, the gate initialization voltage VINIT and the reset voltage VAR may be supplied to both ends of the storage capacitor Cst, and the reset voltage VAR and the low potential reference voltage VSS may be supplied to both ends of the auxiliary capacitor CA.

[0105] During the sampling period Sampling, the third scan signal SCAN3 is provided at a high level, the second scan signal SCAN2 is provided at a low level, and the fourth scan signal SCAN4 is provided at a high level.

[0106] Therefore, the first node N1 of the second transistor T2 maintains the gate initialization voltage VINIT, and the third node N3 of the second transistor T2 receives the set voltage VSET.

[0107] At this time, because the seventh transistor T7 is turned off, the second node N2 of the second transistor T2 may have a difference voltage (VINIT-Vth) corresponding to the difference between the gate initialization voltage VINIT and the threshold voltage Vth of the second transistor T2. Therefore, the driving current flowing through the light emitting element ED through the second transistor T2 is not affected by the threshold voltage Vth. That is, the compensation of the threshold voltage Vth of the second transistor T2 is completed.

[0108] In other words, during the sampling period Sampling, the sub-pixel increases the voltage of the second node N2 of the second transistor (driving transistor) T2 in a source follower manner to perform a sampling operation to saturate the second transistor T2 to a specific level.

[0109] During the program period Program, the third scan signal SCAN3 , the second scan signal SCAN2 , and the fourth scan signal SCAN4 are provided at a low level, and the first scan signal SCAN1 is provided at a high level.

[0110] Therefore, the data voltage VDATA supplied to the first node N1 of the second transistor T2 is charged in the storage capacitor Cst and the auxiliary capacitor CA.

[0111] In addition, at the second node N2 of the second transistor T2, the difference voltage (VINIT-Vth) between the gate initialization voltage VINIT and the threshold voltage Vth of the second transistor T2 is added to the charging voltage a*(VDATA-VINIT) of the storage capacitor Cst. Here, a=Cst / (Cst+CA).

[0112] During the emission period Emission, the first to fourth scan signals SCAN1 to SCAN4 are maintained at a low level, and the emission signal EM is provided at a high level.

[0113] Therefore, the corresponding sub-pixel SP emits light using the driving current flowing through the light emitting element ED from the high potential driving voltage VDD to the low potential reference voltage VSS.

[0114] At this time, since the low potential reference voltage VSS is provided to the second node N2 of the second transistor (driving transistor) T2 during the emission period Emission, the second transistor T2 can have a stable state. As a result, the gate-source voltage of the second transistor T2 can be prevented from changing due to parasitic capacitance, and image defects such as crosstalk can be reduced.

[0115] At the same time, the sub-pixel circuit of the present application can achieve the same effect by providing the same scan signal to some transistors. In this way, when the same scan signal is provided to some transistors, the number of gate lines can be reduced, and the structure of the gate drive circuit can be minimized, which has the effect of reducing the border area.

[0116] Figure 6 is a schematic diagram showing a sub-pixel circuit of a display device according to another embodiment of the present application.

[0117] Reference Figure 6 According to an embodiment of the present application, the sub-pixel circuit SPC of the display device 100 may include a light emitting element ED, a plurality of transistors T1 - T7 for driving the light emitting element ED, and a plurality of capacitors Cst, CA.

[0118] Figure 6 The sub-pixel and Figure 3 The difference between the sub-pixels is that the fifth transistor T5 for providing the gate initialization voltage VINIT to the first node N1 of the second transistor (driving transistor) T2 and the sixth transistor T6 for providing the set voltage VSET to the third node N3 of the second transistor T2 are controlled by the same third scan signal SCAN3.

[0119] The sub-pixel SP of the present application may be configured to stably operate the driving transistor so that the high potential driving voltage VDD is commonly provided to the anodes of the light emitting elements ED.

[0120] The high potential driving voltage VDD is supplied to the anode of the light emitting element ED, and the cathode of the light emitting element ED is electrically connected to the first transistor T1.

[0121] The first transistor T1 may be controlled by the light emitting signal EM, and may be electrically connected between a cathode of the light emitting element ED and the second transistor T2.

[0122] The second transistor T2 may have a first node N1, a second node N2, and a third node N3. The first node N1 may be a gate node and may be electrically connected to the fourth transistor T4 and the fifth transistor T5. The second node N2 may be a drain node or a source node and may receive a low potential reference voltage VSS provided by the third transistor T3. The third node N3 may be a source node or a drain node and may be electrically connected to the cathode of the light emitting element ED through the first transistor T1. The second transistor T2 may also be referred to as a driving transistor.

[0123] The third transistor T3 may be controlled by the light emitting signal EM, and may be electrically connected between the second node N2 and the low potential reference voltage VSS line.

[0124] The fourth transistor T4 may be controlled by the first scan signal SCAN1 and may be electrically connected between a line for supplying the data voltage VDATA and the first node N1 of the second transistor T2 .

[0125] The fifth transistor T5 may be controlled by the third scan signal SCAN3 and may be electrically connected between a node for providing the gate initialization voltage VINIT and the first node N1 of the second transistor T2 .

[0126] The sixth transistor T6 may be controlled by the third scan signal SCAN3 and may be electrically connected between a node for supplying the set voltage VSET and the third node N3 of the second transistor T2 .

[0127] The seventh transistor T7 may be controlled by the second scan signal SCAN2 and may be electrically connected between a node for supplying the reset voltage VAR and the second node N2 of the second transistor T2.

[0128] However, the second scan signal SCAN2 supplied to the seventh transistor T7 may be the same signal having a different phase from the third scan signal SCAN3 supplied to the sixth transistor T6. For example, when the third scan signal SCAN3 is supplied to the nth gate line, the second scan signal SCAN2 may use the third scan signal SCAN3 supplied to the n-1th gate line. That is, depending on the phase of driving the display panel 110, the second scan signal SCAN2 may use the third scan signal SCAN3 at different gate lines GL.

[0129] Therefore, the sub-pixel SP of the present application may be controlled by the first to third scan signals SCAN1 to SCAN3 .

[0130] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the second transistor T2 and may maintain the data voltage VDATA for one frame.

[0131] The auxiliary capacitor CA may be connected between the second node N2 of the second transistor T2 and the low potential reference voltage VSS line and may be used to maintain the voltage supplied to the second node N2. The auxiliary capacitor CA may be connected to the second node N2 and may function as a source follower to improve the efficiency of the voltage supplied to the second node N2 of the second transistor T2.

[0132] Here, as an example, a case where the transistors T1 to T7 constituting the sub-pixel are N-type transistors is shown.

[0133] Figure 7 is a schematic diagram showing the driving timing of sub-pixels according to another embodiment of the present application, Figure 8 is a schematic diagram showing signal waveforms in respective nodes of a driving transistor depending on driving timing of a sub-pixel according to another embodiment of the present application.

[0134] Reference Figure 7 and Figure 8 According to the embodiment of the present application, the sub-pixel can operate in an initialization period Initial, a sampling period Sampling, a programming period Program and a light emitting period Emission.

[0135] The initialization period Initial is a period in which a reset voltage VAR is supplied to the sub-pixel SP to reset the data voltage supplied to the light emitting element ED. The sampling period Sampling is a period in which the threshold voltage of the driving transistor T2 is stored in the capacitor connected to the driving transistor T2. The programming period Program is a period in which a data voltage VDATA is supplied to the sub-pixel SP to store the data voltage VDATA in the capacitor connected to the driving transistor T2.

[0136] The light emission period Emission is a period in which the light emitting element ED is caused to emit light using the data voltage VDATA stored in the capacitor without supplying the data voltage VDATA through the data line connected to each light emitting element ED.

[0137] During the initialization period Initial, the second scan signal SCAN2 is provided at a high level, and thus the seventh transistor T7 is turned on.

[0138] Therefore, the second node N2 of the second transistor (driving transistor) T2 may be reset to the reset voltage VAR.

[0139] During the initialization period Initial, the emission signal EM, the first scan signal SCAN1, and the third scan signal SCAN3 are provided at a low level, and thus the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0140] Therefore, the reset voltage VAR and the low potential reference voltage VSS can be supplied to both ends of the auxiliary capacitor CA.

[0141] During the sampling period Sampling, the third scan signal SCAN3 is provided at a high level, and the second scan signal SCAN2 and the first scan signal SCAN1 are provided at a low level.

[0142] Therefore, the first node N1 of the second transistor T2 maintains the gate initialization voltage VINIT, and the third node N3 of the second transistor T2 receives the set voltage VSET.

[0143] At this time, because the seventh transistor T7 is turned off, the second node N2 of the second transistor T2 may have a difference voltage (VINIT-Vth) corresponding to the difference between the gate initialization voltage VINIT and the threshold voltage Vth of the second transistor T2. Therefore, the driving current flowing through the light emitting element ED through the second transistor T2 is not affected by the threshold voltage Vth. That is, the compensation of the threshold voltage Vth of the second transistor T2 is completed.

[0144] In other words, during the sampling period Sampling, the sub-pixel increases the voltage of the second node N2 of the second transistor (driving transistor) T2 in a source follower manner to perform a sampling operation to saturate the second transistor T2 to a specific level.

[0145] During the program period Program, the third scan signal SCAN3 and the second scan signal SCAN2 are provided at a low level, and the first scan signal SCAN1 is provided at a high level.

[0146] Therefore, the data voltage VDATA supplied to the first node N1 of the second transistor T2 is charged in the storage capacitor Cst and the auxiliary capacitor CA.

[0147] In addition, at the second node N2 of the second transistor T2, the difference voltage (VINIT-Vth) between the gate initialization voltage VINIT and the threshold voltage Vth of the second transistor T2 is added to the charge voltage a*(VDATA-VINIT) at the storage capacitor Cst. Here, a=Cst / (Cst+CA).

[0148] During the emission period Emission, the first to third scan signals SCAN1 to SCAN3 are maintained at a low level, and the emission signal EM is provided at a high level.

[0149] Therefore, the corresponding sub-pixel SP emits light using the driving current flowing through the light emitting element ED from the high potential driving voltage VDD to the low potential reference voltage VSS.

[0150] At this time, since the low potential reference voltage VSS is provided to the second node N2 of the second transistor (driving transistor) T2 during the emission period Emission, the second transistor T2 can have a stable state. As a result, the gate-source voltage of the second transistor T2 can be prevented from changing due to parasitic capacitance, and image defects such as crosstalk can be reduced.

[0151] The sub-pixel SP shown here is merely an example, and the sub-pixel SP may be modified in various ways by including or removing one or more transistors and including or removing one or more capacitors.

[0152] Fig. 9 FIG. 1 shows a structure in which a sub-pixel may be deformed in a display device according to an embodiment of the present application. Figure 3 or Figure 6 The same structure or components as those in the sub-pixel SP are described herein.

[0153] Reference Fig. 9 Each of the plurality of sub-pixel circuits SPC provided on the display panel 110 of the display device 100 according to the embodiment of the present application may include a light emitting element ED and a plurality of circuit elements for driving the light emitting element ED.

[0154] Here, the light emitting element ED may be one of an organic light emitting diode (OLED), an inorganic light emitting diode (LED), and a quantum dot light emitting element.

[0155] Circuit elements constituting the sub-pixel circuit SPC may basically include a driving transistor DRT, a scanning transistor SCT, and a storage capacitor CST, and may further include a control circuit CC including one or more transistors and / or one or more capacitors.

[0156] The sub-pixel circuit SPC may be connected to a data line DL providing a data voltage VDATA and a scan signal line SCL providing a scan signal SC.

[0157] The sub-pixel circuit SPC may receive a high potential driving voltage VDD through a driving voltage line DVL, and receive a low potential reference voltage VSS lower than the high potential driving voltage VDD.

[0158] The sub-pixel circuit SPC may also receive one or more other voltages depending on the circuit configuration of the control circuit CC.

[0159] The sub-pixel circuit SPC may also receive one or more other gate signals according to the circuit configuration of the control circuit CC. For example, the other gate signals may include a scan signal and / or a light emitting signal.

[0160] The driving transistor DRT is a transistor for driving the light emitting element ED, and may include a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT may be a gate node of the driving transistor DRT. The second node N2 of the driving transistor DRT may be a source node or a drain node of the driving transistor DRT. The third node N3 of the driving transistor DRT may be a drain node or a source node of the driving transistor DRT, and may be applied with a high potential driving voltage VDD.

[0161] The scan transistor SCT may be connected between the data line DL and the control circuit CC. A gate node of the scan transistor SCT may be electrically connected to a scan line SCL for providing a scan signal SC, and a drain node or a source node of the scan transistor SCT may be electrically connected to the data line DL.

[0162] The source node or the drain node of the scanning transistor SCT may be electrically connected to the fourth node N4 of the control circuit CC. For example, the fourth node N4 of the control circuit CC may be electrically connected to one of the first node N1, the second node N2, and the third node N3 of the driving transistor DRT, or may be electrically connected to one of the two ends of the storage capacitor Cst.

[0163] Both ends of the storage capacitor Cst may be connected to a fifth node N5 and a sixth node N6 of the control circuit CC, respectively. One of the fifth node N5 and the sixth node N6 of the control circuit CC may be electrically connected to the first node N1 of the driving transistor DRT.

[0164] The driving voltage line DVL may be electrically connected to the light emitting element ED.

[0165] The light emitting element ED may be electrically connected to the seventh node N7 of the control circuit CC. The light emitting element ED may include an anode AND, a light emitting layer EL, and a cathode CAT. For example, the anode AND may receive a high potential driving voltage VDD. The cathode CAT may be electrically connected to the seventh node N7 of the control circuit CC.

[0166] The driving transistor DRT and the scanning transistor SCT may be N-type transistors or P-type transistors. One or more transistors included in the control circuit CC may also be N-type transistors or P-type transistors.

[0167] Meanwhile, the sub-pixel circuit SPC may include or not include the control circuit CC. Although the sub-pixel circuit SPC includes the control circuit CC, the control circuit CC may also have various circuit configurations. Here, the various circuit configurations may include the number and connection structure of transistors and the number and connection structure of capacitors.

[0168] For example, the presence or absence of the control circuit CC or the circuit configuration may vary depending on the size of the display device 100 (e.g., large, medium, small), the type of the display device 100 (e.g., TV, monitor, smartphone, tablet), the driving scheme or the functions provided, etc.

[0169] When the sub-pixel circuit SPC does not include the control circuit CC, the sub-pixel circuit SPC may have a most basic circuit configuration including a light emitting element ED, two transistors DRT, SCT and a capacitor CST. In this case, the seventh node N7 and the third node N3 may be electrically connected, the fourth node N4, the fifth node N5 and the first node N1 may be electrically connected, and the sixth node N6, the eighth node N8 and the second node N2 may be electrically connected.

[0170] The above-mentioned embodiments of the present application will be briefly reviewed as follows.

[0171] The sub-pixel circuit of the present application may include: a light-emitting element configured to receive a high-potential driving voltage at an anode; a driving transistor including a first node, a second node, and a third node; a scanning transistor controlled by a first scanning signal and transmitting a data voltage through a data line; a storage capacitor; and a control circuit configured to control the operation of the driving transistor, the scanning transistor, and the storage capacitor and located between the cathode of the light-emitting element and a low-potential reference voltage.

[0172] The cathode of the light emitting element is electrically connected to the third node of the driving transistor through the control circuit.

[0173] The driving transistor has a first node as a gate node and a second node receiving a low potential reference voltage through a control circuit.

[0174] The driving transistor is made of an N-type oxide semiconductor.

[0175] The control circuit may include: a first light-emitting transistor controlled by a light-emitting signal and electrically connected between a cathode of a light-emitting element and a driving transistor; a second light-emitting transistor controlled by a light-emitting signal and electrically connected to a second node and a node providing a low-potential reference voltage; a reset transistor controlled by a second scan signal and electrically connected between a node providing a reset voltage and the second node; an initialization transistor controlled by a third scan signal and electrically connected between a node providing a gate initialization voltage and the first node; a setting transistor controlled by a fourth scan signal and electrically connected between a node providing a setting voltage and a third node; and an auxiliary capacitor connected between the second node and a node providing a low-potential reference voltage.

[0176] The second scanning signal is the same signal with a different phase from the fourth scanning signal.

[0177] The sub-pixel circuit is operable in an initialization period for resetting the light-emitting element by a reset voltage, a sampling period for storing a threshold voltage of the driving transistor in a storage capacitor and an auxiliary capacitor, a programming period for storing a data voltage in the storage capacitor and the auxiliary capacitor, and a light-emitting period for causing the light-emitting element to emit light by the data voltage stored in the storage capacitor and the auxiliary capacitor.

[0178] The control circuit may include a first light-emitting transistor controlled by a light-emitting signal and electrically connected between a cathode of the light-emitting element and a driving transistor; a second light-emitting transistor controlled by a light-emitting signal and electrically connected to a second node and a node providing a low-potential reference voltage; a reset transistor controlled by a second scan signal and electrically connected between a node providing a reset voltage and the second node; an initialization transistor controlled by a third scan signal and electrically connected between a node providing a gate initialization voltage and the first node; a setting transistor controlled by a third scan signal and electrically connected between a node providing a setting voltage and a third node; and an auxiliary capacitor connected between the second node and a node providing a low-potential reference voltage.

[0179] The second scanning signal is the same signal with a different phase from the third scanning signal.

[0180] The sub-pixel circuit is operable in an initialization period for resetting the light-emitting element by a reset voltage, a sampling period for storing a threshold voltage of the driving transistor in a storage capacitor and an auxiliary capacitor, a programming period for storing a data voltage in the storage capacitor and the auxiliary capacitor, and a light-emitting period for causing the light-emitting element to emit light by the data voltage stored in the storage capacitor and the auxiliary capacitor.

[0181] The display panel of the present application may include a sub-pixel circuit, which includes: a light-emitting element configured to receive a high-potential driving voltage at an anode; a driving transistor including a first node, a second node and a third node; a scanning transistor controlled by a first scanning signal and transmitting a data voltage through a data line; a storage capacitor; and a control circuit configured to control the operation of the driving transistor, the scanning transistor and the storage capacitor and located between the cathode of the light-emitting element and a low-potential reference voltage line.

[0182] The display device of the present application may include: a display panel having a plurality of sub-pixels; a gate driving circuit configured to provide a plurality of gate signals to the display panel through a plurality of gate lines; a data driving circuit configured to provide a plurality of data voltages to the display panel through a plurality of data lines; and a timing controller configured to control the gate driving circuit and the data driving circuit, wherein each of the plurality of sub-pixels includes: a light-emitting element configured to receive a high-potential driving voltage at an anode; a driving transistor including a first node, a second node, and a third node; a scanning transistor controlled by a first scanning signal and transmitting a data voltage through a data line; a storage capacitor; and a control circuit configured to control the operation of the driving transistor, the scanning transistor, and the storage capacitor and located between the cathode of the light-emitting element and a low-potential reference voltage line.

[0183] The above description has been presented to enable those skilled in the art to make and use the technical concept of the present invention, and the above description has been provided in the context of a specific application and its requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. The above description and accompanying drawings provide examples of the technical concept of the present invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present invention.

Claims

1. A sub-pixel circuit, comprising: a light emitting element configured to receive a high potential driving voltage at an anode; a driving transistor including a first node, a second node and a third node; a scan transistor controlled by a first scan signal and configured to transmit a data voltage through the data line; Storage capacitors; as well as A control circuit is configured to control operations of the driving transistor, the scanning transistor, and the storage capacitor, and is located between a cathode of the light emitting element and a low potential reference voltage line for providing a low potential reference voltage.

2. The sub-pixel circuit according to claim 1, wherein: The cathode of the light emitting element is electrically connected to the third node of the driving transistor through the control circuit.

3. The sub-pixel circuit according to claim 1, wherein: The driving transistor has the first node as a gate node and the second node receiving the low potential reference voltage through the control circuit.

4. The sub-pixel circuit according to claim 1, wherein: The driving transistor includes an N-type oxide semiconductor.

5. The sub-pixel circuit according to claim 1, wherein: The control circuit comprises: a first light emitting transistor, controlled by a light emitting signal and electrically connected between a cathode of the light emitting element and the driving transistor; a second light emitting transistor controlled by the light emitting signal and electrically connected to the second node and a node providing the low potential reference voltage; a reset transistor controlled by a second scanning signal and electrically connected between a node providing a reset voltage and the second node; an initialization transistor, controlled by a third scanning signal and electrically connected between a node providing a gate initialization voltage and the first node; a setting transistor controlled by a fourth scanning signal and electrically connected between a node providing a setting voltage and the third node; and The auxiliary capacitor is connected between the second node and a node providing the low potential reference voltage.

6. The sub-pixel circuit according to claim 5, wherein: The second scanning signal is the same signal having a different phase from the fourth scanning signal.

7. The sub-pixel circuit according to claim 5, wherein: The sub-pixel circuit operates: An initialization period, used to reset the light emitting element by using the reset voltage; a sampling period for storing a threshold voltage of the driving transistor in the storage capacitor and the auxiliary capacitor; a programming period for storing the data voltage in the storage capacitor and the auxiliary capacitor; as well as A light emitting period is used to make the light emitting element emit light by the data voltage stored in the storage capacitor and the auxiliary capacitor.

8. The sub-pixel circuit according to claim 1, wherein: The control circuit comprises: a first light emitting transistor, controlled by a light emitting signal and electrically connected between a cathode of the light emitting element and the driving transistor; a second light emitting transistor controlled by the light emitting signal and electrically connected to the second node and a node providing the low potential reference voltage; a reset transistor controlled by a second scanning signal and electrically connected between a node providing a reset voltage and the second node; an initialization transistor, controlled by a third scanning signal and electrically connected between a node providing a gate initialization voltage and the first node; a setting transistor controlled by the third scanning signal and electrically connected between a node providing a setting voltage and the third node; and The auxiliary capacitor is connected between the second node and a node providing the low potential reference voltage.

9. The sub-pixel circuit according to claim 8, wherein: The second scanning signal is the same signal having a different phase from the third scanning signal.

10. The sub-pixel circuit according to claim 8, wherein: The sub-pixel circuit operates: An initialization period, used to reset the light emitting element by using the reset voltage; a sampling period for storing a threshold voltage of the driving transistor in the storage capacitor and the auxiliary capacitor; a programming period for storing the data voltage in the storage capacitor and the auxiliary capacitor; as well as A light emitting period is used to make the light emitting element emit light by the data voltage stored in the storage capacitor and the auxiliary capacitor.

11. A display panel comprising a sub-pixel circuit, the sub-pixel circuit comprising: a light emitting element configured to receive a high potential driving voltage at an anode; a driving transistor including a first node, a second node and a third node; a scan transistor controlled by a first scan signal and configured to transmit a data voltage through the data line; Storage capacitors; as well as A control circuit is configured to control operations of the driving transistor, the scanning transistor, and the storage capacitor, and is located between a cathode of the light emitting element and a low potential reference voltage line for providing a low potential reference voltage.

12. A display device, comprising: A display panel including a plurality of sub-pixels; a gate driving circuit configured to provide a plurality of gate signals to the display panel through a plurality of gate lines; a data driving circuit configured to provide a plurality of data voltages to the display panel through a plurality of data lines; as well as a timing controller configured to control the gate driving circuit and the data driving circuit, Wherein, each of the plurality of sub-pixels comprises: a light emitting element configured to receive a high potential driving voltage at an anode; a driving transistor including a first node, a second node and a third node; a scan transistor controlled by a first scan signal and configured to transmit a data voltage through a corresponding data line of the plurality of data lines; a storage capacitor; and The control circuit is configured to control the operations of the driving transistor, the scanning transistor and the storage capacitor and is located between the cathode of the light emitting element and a low potential reference voltage line.

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