A method and apparatus for real-time processing of multi-parameter sensor data

Abstract

This invention relates to the field of distributed fiber optic sensing technology, and provides a method and apparatus for real-time processing of multi-parameter sensing data. The invention converts multiple sensing signals into corresponding digital signals; transmits these digital signals to appropriate processing modules according to their parameter types; the processing modules process the received digital signals and then send write requests to a bus control arbitration module; the bus control arbitration module uses the host number carried in the received write request to establish communication between the processing modules and a data cache control module; the data cache control module converts the received write request into a processing command and sends it to the data cache storage. Executing the processing command enables communication between multiple processing modules and the data cache storage, thus meeting the requirements for integrated real-time processing of multiple parameter data.

Description

Technical Field

[0001] This invention relates to the field of distributed optical fiber sensing technology, and in particular to a method and apparatus for real-time processing of multi-parameter sensing data. Background Technology

[0002] Fiber optic sensing technology utilizes the sensitivity of the amplitude, phase, polarization state, and wavelength of the optical signal transmitted through optical fibers to external physical quantities. Through a series of demodulation techniques, the optical signal is demodulated to obtain external information, including parameters such as vibration, attenuation, temperature, and strain. Mature fiber optic sensing technology has already found applications in various industries.

[0003] Currently, commercially available fiber optic sensing devices detect relatively limited external physical quantities, failing to monitor fiber vibration, attenuation, temperature, and strain in real time, and lacking multi-parameter, wide-area real-time sensing capabilities. Existing Field-Programmable Gate Array (FPGA) algorithms can only process a single type of signal at a time, unable to meet the demands for integrated real-time processing of multiple parameters. Furthermore, they often rely on on-chip Random Access Memory (RAM) within the FPGA for storage; however, the limited storage resources within the FPGA cannot meet the real-time monitoring requirements of long-distance fiber optic sensing systems.

[0004] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method and apparatus for real-time processing of multi-parameter sensor data. Its purpose is to complete real-time communication between multiple algorithm processing modules and the data cache storage through an external data cache storage and its data cache control module, thereby realizing large-capacity segmented storage and real-time processing of multi-parameter data, and solving the problem that the prior art does not support integrated real-time processing of multi-parameter sensor data.

[0006] The present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a real-time processing method for multi-parameter sensor data, comprising:

[0008] Multiple sensor signals are converted into corresponding digital signals; according to the parameter type of the converted digital signals, the converted digital signals are transmitted to the corresponding processing modules.

[0009] The processing module processes the received digital signal and, after processing, sends a write request to the bus control arbitration module. The write request carries the host number of the processing module.

[0010] The bus control arbitration module enables communication between the processing module and the data cache control module based on the host number carried in the received write request.

[0011] The data cache control module converts the received write request into a processing command and sends the processing command to the data cache storage. The data cache storage executes the processing command to realize communication between multiple processing modules and the data cache storage.

[0012] Furthermore, the real-time processing method for the multi-parameter sensing data also includes:

[0013] The stored data required by the corresponding processing module is determined according to the parameter type; before the processing module receives the corresponding digital signal, a read address request is sent to the bus control arbitration module; wherein, the read address request includes the address of the stored data in the data cache storage, and the read address request carries the host number of the processing module;

[0014] The bus control arbitration module transmits the received read address request to the data cache control module according to the host number; the data cache control module converts the read address request into a first access command and transmits the first access command to the data cache storage; the data cache storage prepares the stored data according to the received first access command in response to the first access command.

[0015] After confirming that the data cache storage has completed its response to the first access command, the processing module retrieves the stored data from the read storage.

[0016] Further, after the processing module confirms that the data cache storage has completed its response to the first access command, retrieving the stored data from the read memory includes:

[0017] After confirming that the data cache storage has completed its response to the first access command, the processing module sends a read data request corresponding to the read address request to the bus control arbitration module; wherein the read data request carries the host number;

[0018] The bus control arbitration module transmits the received read data request to the data cache control module according to the host number; the data cache control module converts the read data request into a second access command and transmits the second access command to the data cache storage; the data cache storage responds to the received second access command and returns the stored data to the data cache control module.

[0019] The data cache control module returns the stored data to the read memory corresponding to the processing module through the bus control arbitration module according to the host number carried in the read data request, so that the processing module can retrieve the stored data from the read memory.

[0020] Furthermore, the write request includes a write address request;

[0021] The processing module processes the received digital signal, and after processing, sends a write request to the bus control arbitration module. The write request carries the host number of the processing module, including:

[0022] Based on the data stored in the read memory, the received digital signal is processed in real time according to its own configured algorithm to generate data to be transmitted.

[0023] The data to be transmitted is transferred to the write memory corresponding to the processing module so that the data to be transmitted can be temporarily stored in the write memory when the data to be transmitted is not transferred to the bus control arbitration module.

[0024] Send a write address request corresponding to the data to be transmitted to the bus control arbitration module; wherein the write address request carries the host number.

[0025] Furthermore, the processing command includes a first processing command;

[0026] The data cache control module converts the received write request into a processing command and sends the processing command to the data cache storage; the data cache storage executes the processing command including:

[0027] The data cache control module receives a write address request from the bus control arbitration module and converts the received write address request into a first processing command.

[0028] The data cache storage responds to the received first processing command and prepares the memory location for writing the data to be transmitted, so that the data to be transmitted can be written to the data cache storage according to the memory location.

[0029] Furthermore, the write request also includes a write data request;

[0030] The bus control arbitration module, based on the host number carried in the received write request, enables communication between the processing module and the data cache control module, including:

[0031] The bus control arbitration module determines the current write request that should be responded to immediately from the received write data requests according to a preset scheduling mechanism; wherein, the write data request is sent to the bus control arbitration module by the processing module after confirming that the data cache storage has responded to the first processing command, and the write data request carries the host number and the data to be transmitted;

[0032] In response to the current write request, the current write request is transmitted to the data cache control module according to the host number carried in the current write request, so that the data cache control module can convert the current write request into a second processing command and write the data to be transmitted into the data cache storage based on the second processing command.

[0033] Furthermore, the processing module includes a first algorithm module, a second algorithm module, and a third algorithm module;

[0034] The step of transmitting the converted digital signals to the corresponding processing modules according to the parameter type of the converted digital signals includes:

[0035] When the parameter type is attenuation sensing data, the digital signal is sent to the first algorithm module;

[0036] When the parameter type is temperature sensing data and / or strain sensing data, the digital signal is sent to the second algorithm module;

[0037] When the parameter type is vibration parameter sensing data, the digital signal is sent to the third algorithm module.

[0038] Secondly, the present invention also provides a real-time processing device for multi-parameter sensor data, used to implement the real-time processing method for multi-parameter sensor data described in the first aspect. The real-time processing device for multi-parameter sensor data includes an analog-to-digital conversion module, a processing module, a bus control arbitration module, a data cache control module, and a data cache storage unit, wherein:

[0039] The analog-to-digital converter module is used to convert multiple sensing signals into corresponding digital signals respectively; it is also used to transmit the converted digital signals to the corresponding processing modules according to the parameter type of the converted digital signals.

[0040] The processing module is used to process the received digital signal and send a write request to the bus control arbitration module after processing.

[0041] The bus control arbitration module is used to enable communication between the processing module and the data cache control module based on the host number carried in the received write request.

[0042] The data cache control module is used to convert the received write request into a processing command and send the processing command to the data cache storage.

[0043] The data cache storage is used to execute the processing commands to enable communication between multiple processing modules and the data cache storage.

[0044] Further, the processing module includes a first algorithm module, a second algorithm module, and a third algorithm module; the write memory corresponding to the first algorithm module is a first write memory, the write memory corresponding to the second algorithm module is a second write memory, and the write memory corresponding to the third algorithm module is a third write memory; the read memory corresponding to the first algorithm module is a first read memory, the read memory corresponding to the second algorithm module is a second read memory, and the read memory corresponding to the third algorithm module is a third read memory, wherein:

[0045] The analog-to-digital conversion module is connected to the first algorithm module; the analog-to-digital conversion module is connected to the second algorithm module; the analog-to-digital conversion module is connected to the third algorithm module.

[0046] The write side of the first algorithm module is connected to the first write memory, and the read side of the first algorithm module is connected to the first read memory; the write side of the second algorithm module is connected to the second write memory, and the read side of the second algorithm module is connected to the second read memory; the write side of the third algorithm module is connected to the third write memory, and the read side of the third algorithm module is connected to the third read memory.

[0047] The first algorithm module, the second algorithm module, and the third algorithm module are respectively connected to the bus control arbitration module via an AXI bus;

[0048] The bus control arbitration module is connected to the data cache control module via an AXI bus;

[0049] The data cache storage is connected to the data cache control module.

[0050] Furthermore, among which:

[0051] The first write memory is used to convert the bit width of the data to be processed generated by the first algorithm module from a first bit width range to a second bit width range; the first read memory is used to convert the bit width of the stored data required by the first algorithm module from a second bit width range to a first bit width range; wherein, the first bit width range is smaller than the second bit width range;

[0052] The second write memory is used to convert the bit width of the data to be processed generated by the second algorithm module from a third bit width range to a fourth bit width range; the second read memory is used to convert the bit width of the stored data required by the second algorithm module from a fourth bit width range to a third bit width range; wherein the third bit width range is smaller than the fourth bit width range;

[0053] The third write memory is used to convert the bit width of the data to be processed generated by the third algorithm module from the fifth bit width range to the sixth bit width range; the third read memory is used to convert the bit width of the stored data required by the third algorithm module from the sixth bit width range to the fifth bit width range; wherein the fifth bit width range is smaller than the sixth bit width range.

[0054] The real-time processing device for the multi-parameter sensor data also includes:

[0055] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor for performing the real-time processing method for multi-parameter sensing data as described in the first aspect.

[0056] Thirdly, the present invention also provides a non-volatile computer storage medium storing computer-executable instructions, which are executed by one or more processors to perform the real-time processing method for multi-parameter sensing data described in the first aspect.

[0057] Fourthly, a chip is provided, comprising: a processor and an interface for calling and running a computer program stored in a memory, and executing a real-time processing method for multi-parameter sensing data as described in the first aspect.

[0058] Fifthly, a computer program product containing instructions is provided, which, when executed on a computer or processor, causes the computer or processor to perform a real-time processing method for multi-parameter sensing data as described in the first to fourth aspects and any one thereof.

[0059] In a sixth aspect, a real-time processing method system for multi-parameter sensor data is provided, including a real-time processing device for multi-parameter sensor data as described in the second aspect, and using the real-time processing method for multi-parameter sensor data as described in the first aspect to complete the interaction with the real-time processing device for multi-parameter sensor data in the second aspect.

[0060] Unlike existing technologies, the present invention has at least the following beneficial effects:

[0061] This invention utilizes an external data cache storage unit as the storage unit for system data. Simultaneously, through the interconnection of the bus control arbitration module and the data cache control module, multiple processing modules can access a single data cache control module at the same time, completing real-time communication between multiple processing modules and the data cache storage unit. By realizing large-capacity segmented storage and real-time processing of multi-parameter data, it breaks through the bottleneck of existing technologies that can only sense a single external physical quantity, and meets the requirements for integrated real-time processing of multiple parameter data. Attached Figure Description

[0062] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0063] Figure 1 This is a flowchart illustrating a real-time processing method for multi-parameter sensor data provided in an embodiment of the present invention.

[0064] Figure 2 This is a schematic diagram of the system structure of a real-time processing device for multi-parameter sensor data provided in an embodiment of the present invention;

[0065] Figure 3 This is a flowchart illustrating another real-time processing method for multi-parameter sensor data provided in an embodiment of the present invention.

[0066] Figure 4 This is a flowchart illustrating step 10 provided in an embodiment of the present invention;

[0067] Figure 5 This is a schematic diagram of the system structure of a real-time processing device for multi-parameter sensor data provided in an embodiment of the present invention;

[0068] Figure 6 This is a flowchart illustrating step 20 provided in an embodiment of the present invention;

[0069] Figure 7 This is a flowchart illustrating step 30 provided in an embodiment of the present invention;

[0070] Figure 8 This is a schematic diagram illustrating how multiple hosts can access a single slave device via an AXI bus through a bus control arbitration module, as provided in an embodiment of the present invention.

[0071] Figure 9 This is a schematic diagram of an embodiment of the present invention that enables multiple processing modules to access a data cache control module via an AXI bus through a bus control arbitration module;

[0072] Figure 10 This is a flowchart illustrating step 40 provided in an embodiment of the present invention;

[0073] Figure 11 This is a schematic diagram of the system structure of a specific example of a real-time processing device for multi-parameter sensor data provided in an embodiment of the present invention;

[0074] Figure 12 This is a detailed schematic diagram of the system structure of a specific example of a real-time processing device for multi-parameter sensor data provided in an embodiment of the present invention;

[0075] Figure 13 This is a schematic diagram provided by an embodiment of the present invention, showing how the OTDR algorithm module, BOTDR algorithm module, and Φ-OTDR algorithm module access a MIG (IP core) via an AXI bus through a bus control arbitration module;

[0076] Figure 14 This is a schematic diagram of the architecture of a real-time processing device for multi-parameter sensor data provided in an embodiment of the present invention. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0078] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0079] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0080] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0081] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0082] In describing some embodiments, the terms "coupled," "coupled," and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "connected" or "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other, such as "optical coupling," "wireless connection," etc. The embodiments disclosed herein are not necessarily limited to the scope of this invention.

[0083] In the description of this invention, the expression “A and / or B” (where A and B are used to formally represent specific features) will be used. The corresponding expression includes the following three combinations: only A, only B, and a combination of A and B.

[0084] As used in this invention, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from a particular value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0085] In this application, the words "for example" or "as" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "for example" or "as" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of the words "for example" or "as" is intended to present the relevant concepts in a specific manner.

[0086] It should be noted that the terms "at...time" or "when...time" in the embodiments of this application can refer to the instant at which a certain situation occurs, or to a period of time after the occurrence of a certain situation. The embodiments of this application do not specifically limit this. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0087] Example 1:

[0088] Existing fiber optic sensing devices can only sense a limited range of external physical quantities, making it impossible to monitor multiple parameters such as fiber vibration, attenuation, temperature, and strain in real time. Taking ultra-high-voltage (UHV) power grids as an example, a single transmission line can stretch for thousands of kilometers. Long-distance transmission lines are inevitably affected by various natural factors; some extreme factors can significantly impact transmission line safety, such as lightning strikes, icing, wind deflection, and flashover. Therefore, corresponding monitoring methods are needed to perceive the transmission line status in real time and promptly issue warnings or report hazardous events. This objectively requires fiber optic sensing devices to possess multi-functional sensing capabilities, comprehensively sensing status parameters along the fiber optic line, such as temperature, stress, galloping, vibration, and line faults.

[0089] In existing technologies, fiber optic sensing devices primarily rely on FPGA algorithms to sense external physical quantities. FPGA is a further development based on Programming Array Logic (PAL), Generic Array Logic (GAL), and Complex Programmable Logic Device (CPLD). It allows users to design circuits using hardware description languages ​​(Verilog, etc.), and generate configuration files through corresponding synthesis tools. Once the FPGA loads the configuration file, it can implement the required logic functions.

[0090] Fiber optic sensing devices utilize the optical fiber itself as the sensing medium to monitor external physical quantities such as vibration, attenuation, temperature, and strain, achieving long-distance, real-time, and comprehensive condition monitoring. As mentioned earlier, to achieve integrated real-time detection of parameters such as vibration, attenuation, temperature, and strain, it is necessary to simultaneously acquire and store the Brillouin and Rayleigh signals contained in the scattered light from the monitored optical fiber, and then process the various signal data in real time according to corresponding algorithms.

[0091] However, traditional FPGA algorithm processing solutions have poor practicality. Specifically, they cannot simultaneously acquire and store Brillouin and Rayleigh signals corresponding to optical fibers, nor can they process various signal data in real time according to the corresponding algorithms. On the one hand, when sensing external physical quantities, traditional FPGA algorithm processing solutions can only process a single type of signal at a time, failing to simultaneously acquire and store Brillouin and Rayleigh signals from optical fibers. Consequently, they cannot support real-time processing of various signal data according to the corresponding algorithms, meaning they cannot meet the integrated real-time processing of multiple parameter data. On the other hand, in traditional FPGA algorithm processing solutions, after acquiring various signal data, they mostly use the FPGA's on-chip RAM for storage. Since the storage resources on the FPGA are limited, and in long-distance real-time omnidirectional status monitoring scenarios, the amount of data acquired from the optical fibers is large, using only the FPGA's on-chip storage resources cannot meet the data storage requirements of long-distance optical fiber sensing systems.

[0092] To solve the above problems, such as Figure 1 As shown, this embodiment of the invention provides a real-time processing method for multi-parameter sensor data, including:

[0093] Step 10: Convert the multiple sensor signals into corresponding digital signals; according to the parameter type of the converted digital signals, transmit the converted digital signals to the corresponding processing modules.

[0094] Based on existing technologies, this invention provides a real-time processing method for multi-parameter sensor data implemented in an FPGA. By implementing a large-capacity segmented storage function in the FPGA, and simultaneously enabling multiple processing modules to access the data cache storage, real-time processing of multi-parameter sensor data is achieved.

[0095] To facilitate the description of the data flow in the FPGA of this embodiment of the invention, the system modules of this embodiment of the invention are described below:

[0096] like Figure 2 As shown, the FPGA design of this embodiment of the invention mainly includes an analog-to-digital conversion module, a processing module, a bus control arbitration module, a data cache control module, and a data cache storage.

[0097] The analog-to-digital conversion module is used to digitize the acquired sensor signals to obtain corresponding digital signals, and transmits the obtained digital signals to different processing modules according to the parameter types of the corresponding signals (such as fiber vibration, attenuation, temperature and strain).

[0098] The FPGA in this embodiment of the invention has multiple different processing modules; in an optional embodiment, the multiple different processing modules together constitute an FPGA algorithm module; different processing modules are used to process signal data of different parameter types, and each processing module uses its preset algorithm to process the signal data of the corresponding parameter type in real time; the preset algorithm in the processing module is selected by those skilled in the art according to the specific application scenario.

[0099] This invention employs a bus control arbitration module based on the Advanced eXtensible Interface (AXI) protocol to transmit data processed by multiple processing modules via the AXI bus, facilitating the reading and writing of the corresponding data. In an optional embodiment, the bus control arbitration module may be based on the AXI4 protocol, and the AXI bus may be an AXI4 bus.

[0100] Due to the limited on-chip storage resources of FPGAs, this embodiment of the invention uses an external data buffer storage unit as the storage unit to meet the data storage requirements of long-distance fiber optic sensing systems. The data buffer storage unit can be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR) chip; in an optional embodiment, the DDR chip can be a DDR3 chip. However, in order to achieve real-time processing of various external physical quantities collected by multiple processing modules, real-time read and write operations to the data buffer storage unit are required. But when multiple ports (i.e., ports of multiple processing modules) attempt to read and write to the same DDR chip simultaneously, conflicts are highly likely to occur, leading to data errors or performance degradation.

[0101] Therefore, in this embodiment of the invention, each processing module performs real-time read and write operations on different regions of the DDR chip. The bus control arbitration module realizes data transmission between multiple processing modules and a data cache control module through the AXI bus, and the data cache control module completes the read and write of corresponding data in the data cache storage it controls through the AXI bus. In turn, through the external data cache storage, a large-capacity segmented storage function is realized. Specific details are described in detail below.

[0102] Step 20: The processing module processes the received digital signal, and after processing, sends a write request to the bus control arbitration module. The write request carries the host number of the processing module.

[0103] The host number is a unique identifier for the processing module during data transmission. In an optional embodiment, the host number can be an ID.

[0104] In the FPGA design of this invention embodiment, in order to adapt to the needs of different interfaces or modules, improve system performance and reliability, and reduce hardware costs, the processing module also needs to perform bit width conversion on the results of algorithm processing. That is, the processing of digital signals by each processing module includes processing with corresponding algorithms and bit width conversion.

[0105] Step 30: The bus control arbitration module enables communication between the processing module and the data cache control module based on the host number carried in the received write request.

[0106] In this embodiment of the invention, each processing module initiates a write request to the bus control arbitration module to write the data output by the processing module into the data cache storage. Through the host number, the bus control arbitration module ensures that the requests and data transmitted from multiple processing modules are not confused, and that each processing module can receive the data it requested.

[0107] Step 40: The data cache control module converts the received write request into a processing command and sends the processing command to the data cache storage; the data cache storage executes the processing command to realize communication between multiple processing modules and the data cache storage.

[0108] This invention converts multiple sensor signals into corresponding digital signals. Based on the parameter type of the converted digital signals, they are transmitted to the corresponding processing modules. Each processing module processes the received digital signals and, upon completion, sends a write request to the bus control arbitration module. The bus control arbitration module, based on the host number carried in the received write request, enables communication between the processing modules and the data cache control module. The data cache control module converts the received write request into a processing command and sends it to the data cache storage. The data cache storage executes the processing command, thus enabling communication between multiple processing modules and the data cache storage. Specifically, an external data cache storage is used as the system data storage. Simultaneously, the interconnection between the bus control arbitration module and the data cache control module allows multiple processing modules to simultaneously access a single data cache control module, achieving real-time communication between multiple processing modules and the data cache storage. This realizes large-capacity segmented storage and real-time processing of multi-parameter data, meeting the requirements for integrated real-time processing of various parameters.

[0109] Since each processing module often needs to use the already processed data when processing the received digital signals, and the already processed data is stored in the data cache storage, it is necessary to read it from the data cache storage to the corresponding processing module.

[0110] To illustrate the process of reading processed data into the corresponding processing module, such as... Figure 3 As shown, the real-time processing method for multi-parameter sensor data further includes:

[0111] In step 501, the stored data required by the corresponding processing module is determined according to the parameter type; before the processing module receives the corresponding digital signal, a read address request is sent to the bus control arbitration module; wherein, the read address request includes the address of the stored data in the data cache storage, and the read address request carries the host number of the processing module.

[0112] The stored data refers to the data that has already been processed and is required by the processing module.

[0113] The processing module needs to process the received digital signal in real time. If the required stored data is requested after the digital signal has been received, the data caching control module may delay its response, causing data interruption and affecting system performance.

[0114] To address this issue, each processing module pre-reads stored data by sending a request. When a processing module needs to read data from the data cache control module, it first sends a read address request, which includes the target address, host number, and other control information.

[0115] In step 502, the bus control arbitration module transmits the received read address request to the data cache control module according to the host number; the data cache control module converts the read address request into a first access command and transmits the first access command to the data cache storage; the data cache storage prepares the stored data according to the received first access command in response to the first access command.

[0116] The bus control arbitration module transmits the read address request based on the host number. The data cache control module converts the read address request into a first access command that the data cache storage can directly execute. The data cache storage confirms the corresponding stored data based on the address information in the read address request.

[0117] After confirming that the data cache storage has completed its response to the first access command, the processing module retrieves the stored data from the read memory. The specific process is as follows:

[0118] In step 503, after the processing module confirms that the data cache storage has completed its response to the first access command, it sends a read data request corresponding to the read address request to the bus control arbitration module; wherein the read data request carries the host number.

[0119] After the read address request is confirmed and ready, the processing module for the corresponding host number will receive the returned signal and can then send a read data request. Similarly, the read data request also includes the host number to ensure that the stored data obtained from the data cache storage can be correctly transmitted back to the processing module that sent the read data request.

[0120] In step 504, the bus control arbitration module transmits the received read data request to the data cache control module according to the host number; the data cache control module converts the read data request into a second access command and transmits the second access command to the data cache storage; the data cache storage responds to the received second access command and returns the stored data to the data cache control module.

[0121] In step 505, the data cache control module returns the stored data to the read memory corresponding to the processing module through the bus control arbitration module according to the host number carried in the read data request, so that the processing module can retrieve the stored data from the read memory.

[0122] Each processing module has a corresponding read memory, which will be described below. When a processing module receives the required stored data, it temporarily stores it in its own read memory and waits for the processing module to receive the corresponding digital signal before performing calculations on both.

[0123] To explain in detail the process of transmitting digital signals based on different parameter types, such as Figure 4 As shown, the processing module includes a first algorithm module, a second algorithm module, and a third algorithm module;

[0124] In step 10, transmitting the converted digital signals to the corresponding processing modules according to the parameter type of the converted digital signals includes:

[0125] Step 101: When the parameter type is attenuation sensing data, the digital signal is sent to the first algorithm module.

[0126] The first algorithm module can be the optical time domain reflectometer (OTDR) algorithm module;

[0127] This invention utilizes backscattered Rayleigh light technology based on the OTDR algorithm to determine the loss along the optical fiber and to monitor the location of optical fiber faults and breaks; for example, it can be applied to perimeter security and long-distance power transmission line fault alarms.

[0128] like Figure 5As shown, the analog-to-digital conversion module transmits digital signals to the first algorithm module, the second algorithm module, and the third algorithm module according to different parameter types.

[0129] Step 102: When the parameter type is temperature sensing data and / or strain sensing data, the digital signal is sent to the second algorithm module.

[0130] The second algorithm module can be the Brillouin Optical Time Domain Reflectometry (BOTDR) algorithm module.

[0131] This invention applies Brillouin optical time-domain reflectometry based on the BOTDR algorithm to monitor the temperature and stress of optical fibers; for example, it can be applied to temperature / stress monitoring of submarine pipelines, temperature monitoring of train carriages, and icing monitoring of power transmission lines.

[0132] Step 103: When the parameter type is vibration parameter sensing data, the digital signal is sent to the third algorithm module.

[0133] The first algorithm module can be a phase-sensitive optical time domain reflectometry (φ-OTDR) algorithm module.

[0134] This invention applies coherent Rayleigh scattering light technology based on the φ-OTDR algorithm to fiber optic disturbance location monitoring; for example, it can be applied to perimeter intrusion and vibration monitoring alarms for deeply buried underground pipelines and cables.

[0135] To provide a detailed explanation of how each processing module processes and transmits digital signals, such as... Figure 6 As shown, the write request includes a write address request;

[0136] Step 20 includes:

[0137] Step 201: Based on the data stored in the read memory, process the received digital signal in real time according to the algorithm configured by itself to generate data to be transmitted.

[0138] The algorithms configured for each processing module are selected by those skilled in the art based on the specific application scenario; the first algorithm module can be configured based on the OTDR algorithm; the second algorithm module can be configured based on the BOTDR algorithm; and the third algorithm module can be configured based on the φ-OTDR algorithm.

[0139] Step 202: Transfer the data to be transmitted to the write memory corresponding to the processing module so that the data to be transmitted can be temporarily stored in the write memory when the data to be transmitted is not transferred to the bus control arbitration module.

[0140] like Figure 5 As shown, each processing module includes corresponding read memory and write memory; both read memory and write memory can be First-In-First-Out (FIFO) data buffers. The read memory of each processing module temporarily stores already stored data, while the write memory temporarily stores data to be transmitted. Simultaneously, data bit width conversion is performed through the read and write memories. Since the AXI bus bandwidth fully meets the bandwidth requirements for simultaneous access to DDR read and write requests from multiple ports, data is only temporarily stored in the read and write memories and will not overflow over time.

[0141] Step 203: Send a write address request corresponding to the data to be transmitted to the bus control arbitration module; wherein the write address request carries the host number.

[0142] The processing module performs relevant algorithmic calculations on the digital signal and the read-back stored data, such as bitwise accumulation or bitwise multiplication. After completion, it inputs the data into the write memory and sends a write address request. Specifically, to write the data to be transmitted into the data buffer memory, similar to the process of retrieving stored data, the processing module first initiates a write address request to the bus control arbitration module. After receiving a return signal confirming that the write address request has been acknowledged and is ready, the processing module sends a write data request, the specific process of which is the same as the process of sending the write address request, and will not be described in detail here.

[0143] The process of the bus control arbitration module transmitting a write address request is similar to the process of retrieving stored data, and will not be described in detail here. To provide a more detailed explanation of the process of the bus control arbitration module transmitting a write data request, as follows... Figure 7 As shown, the write request also includes a write data request;

[0144] Step 30 includes:

[0145] Step 301: The bus control arbitration module determines the current write request that will respond immediately from the received write data requests according to a preset scheduling mechanism; wherein, the write data request is sent to the bus control arbitration module by the processing module after confirming that the data cache storage has responded to the first processing command, and the write data request carries the host number and the data to be transmitted.

[0146] The preset scheduling mechanism is selected by those skilled in the art based on the specific use case; in optional embodiments, the preset scheduling mechanism can be an RR (Round-Robin) polling scheduling mechanism or a fixed priority scheduling mechanism.

[0147] like Figure 8 and Figure 9 As shown, the data cache control module acts as a slave based on the AXI4 protocol, and each processing module acts as a master based on the AXI4 protocol. According to the needs, each module sends a write data request to the bus control arbitration module based on the AXI4 protocol. The bus control arbitration module arbitrates and schedules the received write data requests based on a preset scheduling mechanism, and responds to the write data request of only one master at a time.

[0148] Step 302: In response to the current write request, the current write request is transmitted to the data cache control module according to the host number carried in the current write request, so that the data cache control module can convert the current write request into a second processing command and write the data to be transmitted into the data cache storage based on the second processing command.

[0149] It should be noted that in this embodiment of the invention, there may be multiple hosts making simultaneous requests at the same time. Since only one host's write data request can be responded to at a time, the data to be transmitted by the corresponding host will be temporarily held in its write memory for the unresponsive write data request.

[0150] To provide a detailed explanation of the processes by which the data cache control module and the data cache storage respond to each processing module, such as... Figure 10 As shown, the processing command includes a first processing command;

[0151] Step 40 includes:

[0152] Step 401: The data cache control module receives a write address request from the bus control arbitration module and converts the received write address request into a first processing command.

[0153] Step 402: The data cache storage responds to the received first processing command and prepares the write memory location for the data to be transmitted, so that the data to be transmitted can be written to the data cache storage according to the write memory location.

[0154] The process of the data cache control module and the data cache storage responding to write data requests is the same as the process of responding to write address requests, and will not be described in detail here.

[0155] This invention uses an external data cache storage unit to store system data. At the same time, through the interconnection of the bus control arbitration module and the data cache control module, multiple processing modules can access a single data cache control module simultaneously. This solves the conflict problem of multiple ports reading and writing to the same DDR chip and realizes real-time communication between multiple processing modules and the data cache storage unit. Thus, it realizes the functions of large-capacity segmented storage and real-time processing of multi-parameter data, and supports the integrated real-time processing of multi-parameter sensor data.

[0156] Example 2:

[0157] Based on Embodiment 1, this embodiment of the invention also provides a real-time processing device for multi-parameter sensor data, used to implement the real-time processing method for multi-parameter sensor data described in Embodiment 1, such as... Figure 5 As shown, the real-time processing device for multi-parameter sensor data includes an analog-to-digital conversion module, a processing module, a bus control arbitration module, a data cache control module, and a data cache storage unit, wherein:

[0158] The analog-to-digital conversion module is used to convert multiple sensor signals into corresponding digital signals respectively; it is also used to transmit the converted digital signals to the corresponding processing modules according to the parameter type of the converted digital signals.

[0159] like Figure 11 As shown, the analog-to-digital conversion module can be an ADC module, which is used to digitize the sensing signal of the distributed optical fiber sensing after photoelectric conversion, amplification and filtering, and then convert it into a digital signal for transmission.

[0160] The processing module is used to process the received digital signal and send a write request to the bus control arbitration module after processing.

[0161] The analog-to-digital conversion module is connected to multiple processing modules; such as... Figure 5 and Figure 11 As shown, in an optional embodiment, multiple processing modules and their read and write memories constitute an FPGA algorithm module, and the analog-to-digital conversion module is connected to the FPGA algorithm module.

[0162] The bus control arbitration module is used to enable communication between the processing module and the data cache control module based on the host number carried in the received write request.

[0163] The bus control arbitration module, based on a preset scheduling mechanism, arbitrates and schedules the received write data requests internally, sending the data to be transmitted from each responding host to the data cache control module; and responds to only one host's write data request at a time.

[0164] like Figure 11As shown, the bus control arbitration module uses the Interconnect (Intellectual Property Core, abbreviated as IP core) based on the AXI4 protocol. The AXI4 interconnect IP core manages the AXI4 bus, supporting multiple hosts accessing a single slave device via the AXI4 bus. Each host is assigned a different host number, and multiple hosts reading from or writing to a single slave device are achieved through these different host numbers. Internally, during the read / write process, the corresponding host number is added to the address to represent the accessing host, and the returned data is sent back to the corresponding host based on the corresponding host number. The bus control arbitration module performs transaction arbitration, thereby enabling real-time access to DDR read / write requests from multiple ports.

[0165] The data cache control module is used to convert the received write request into a processing command and send the processing command to the data cache storage.

[0166] The data cache control module can be a DDR control module. The DDR control module is implemented using a Memory Interface Generator (MIG) IP core, which serves as the access interface for the DDR chip. This IP core supports the AXI4 bus interface and is a slave device. When the host sends the corresponding read / write address request and the corresponding read / write data request, this IP core is responsible for converting the corresponding request into commands that the DDR chip can directly process.

[0167] The data cache storage is used to execute the processing commands to enable communication between multiple processing modules and the data cache storage.

[0168] like Figure 11 As shown, the data cache storage can be a DDR3 chip, which is the actual data cache storage. This invention uses the AXI4 protocol to control access to the DDR3 chip. The theoretical total bandwidth of the DDR3 chip is determined by the clock frequency and the read / write data bit width, which is the AXI4 bus bandwidth. In this embodiment of the invention, the AXI4 bus bandwidth must meet the bandwidth requirements of read / write requests from multiple ports accessing the DDR3 chip simultaneously.

[0169] The processing module includes a first algorithm module, a second algorithm module, and a third algorithm module; wherein, as shown in the figure... Figure 12 As shown, attenuation parameter sensing data (digital signals corresponding to attenuation parameters) are processed by the OTDR algorithm module, temperature and / or strain parameter sensing data (digital signals corresponding to temperature and / or strain parameters) are processed by the BOTDR algorithm module, and vibration parameter sensing data (digital signals corresponding to vibration parameters) are processed by the Φ-OTDR algorithm module.

[0170] The write memory corresponding to the first algorithm module is the first write memory, the write memory corresponding to the second algorithm module is the second write memory, and the write memory corresponding to the third algorithm module is the third write memory; the read memory corresponding to the first algorithm module is the first read memory, the read memory corresponding to the second algorithm module is the second read memory, and the read memory corresponding to the third algorithm module is the third read memory, wherein:

[0171] The analog-to-digital conversion module is connected to the first algorithm module; the analog-to-digital conversion module is connected to the second algorithm module; the analog-to-digital conversion module is connected to the third algorithm module.

[0172] like Figure 12 As shown, the write memory is W-FIFO and the read memory is R-FIFO.

[0173] The write side of the first algorithm module is connected to the first write memory, and the read side of the first algorithm module is connected to the first read memory; the write side of the second algorithm module is connected to the second write memory, and the read side of the second algorithm module is connected to the second read memory; the write side of the third algorithm module is connected to the third write memory, and the read side of the third algorithm module is connected to the third read memory.

[0174] For example, the write side of the OTDR algorithm module is connected to the corresponding W-FIFO, the read side of the OTDR algorithm module is connected to the corresponding R-FIFO, the write side of the BOTDR algorithm module is connected to the corresponding W-FIFO, the read side of the BOTDR algorithm module is connected to the corresponding R-FIFO, the write side of the Φ-OTDR algorithm module is connected to the corresponding W-FIFO, and the read side of the Φ-OTDR algorithm module is connected to the corresponding R-FIFO.

[0175] like Figure 13 As shown, the arbitrator in the bus control arbitration module responds to only one host's write data request at a time according to the preset scheduling mechanism. For write data requests that are not responded to, the corresponding data to be transmitted is temporarily stored in the W-FIFO on the write side. Similarly, the acquired stored data is temporarily stored in the R-FIFO on the read side.

[0176] Wherein: the first write memory is used to convert the bit width of the data to be processed generated by the first algorithm module from the first bit width range to the second bit width range; the first read memory is used to convert the bit width of the stored data required by the first algorithm module from the second bit width range to the first bit width range; wherein, the first bit width range is smaller than the second bit width range.

[0177] The specific sizes of the first and second width ranges are to be selected by those skilled in the art based on the actual usage scenario, and are not limited here.

[0178] The second write memory is used to convert the bit width of the data to be processed generated by the second algorithm module from the third bit width range to the fourth bit width range; the second read memory is used to convert the bit width of the stored data required by the second algorithm module from the fourth bit width range to the third bit width range; wherein the third bit width range is smaller than the fourth bit width range.

[0179] The specific sizes of the third and fourth bit width ranges are to be selected by those skilled in the art based on the actual usage scenario, and are not limited here.

[0180] The third write memory is used to convert the bit width of the data to be processed generated by the third algorithm module from the fifth bit width range to the sixth bit width range; the third read memory is used to convert the bit width of the stored data required by the third algorithm module from the sixth bit width range to the fifth bit width range; wherein the fifth bit width range is smaller than the sixth bit width range.

[0181] The specific sizes of the fifth and sixth bit width ranges are to be selected by those skilled in the art based on the actual usage scenario, and are not limited here.

[0182] Each write memory converts the small-width data to be transmitted to a large-width data, and each read memory converts the large-width stored data to a small-width data. The original data bit width of each processing module is much smaller than the data bit width of the AXI bus, and there is a multiple relationship between the two. With the bandwidth requirements of each processing module remaining unchanged, the data bit width conversion through the read memory and write memory can reduce the frequency of each processing module sending read and write requests to the data cache memory. This enables the function of real-time access to the DDR chip read and write requests from multiple ports.

[0183] The first algorithm module is connected, and the second and third algorithm modules are respectively connected to the bus control arbitration module via the AXI bus.

[0184] The bus control arbitration module is connected to the data cache control module via the AXI bus.

[0185] The data cache storage is connected to the data cache control module.

[0186] The real-time processing device for multi-parameter sensing data in this invention is a highly integrated fiber optic sensing device. It utilizes the optical fiber itself as the sensing medium and, through multi-sensor fusion technology, integrates vibration, attenuation, temperature, and strain monitoring to achieve long-distance, real-time, all-around condition monitoring. It simultaneously collects and stores Brillouin and Rayleigh signals contained in the scattered light from the sensing fiber, and then processes various data in real time according to corresponding algorithms, achieving integrated real-time detection of parameters such as vibration, attenuation, temperature, and strain.

[0187] The data storage, acquisition, and algorithm processing of the real-time processing device for multi-parameter sensor data in this embodiment of the invention are implemented in an FPGA. By implementing large-capacity segmented storage in the FPGA, and simultaneously enabling multiple processing modules to access the data cache storage, real-time processing of multi-parameter sensor data is supported. Furthermore, because it supports the use of IP cores based on the AXI4 protocol, it offers enhanced portability while ensuring the reliability of the solution, which is of great significance for the widespread application of the design method.

[0188] Example 3:

[0189] In one alternative embodiment, such as Figure 14 The diagram shown is an architectural schematic of a real-time processing device for multi-parameter sensor data according to an embodiment of the present invention. This embodiment of the real-time processing device for multi-parameter sensor data further includes one or more processors 21 and a memory 22. Figure 14 Take a processor 21 as an example.

[0190] Processor 21 and memory 22 can be connected via a bus or other means. Figure 14 Taking the example of a connection between China and Israel via a bus.

[0191] The memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs and non-volatile computer-executable programs, such as the real-time processing method for multi-parameter sensor data in this embodiment. The processor 21 executes the real-time processing method for multi-parameter sensor data by running the non-volatile software programs and instructions stored in the memory 22.

[0192] Memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 22 may optionally include memory remotely located relative to processor 21, which can be connected to processor 21 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0193] The program instructions / modules are stored in the memory 22. When executed by one or more processors 21, they perform the real-time processing method for multi-parameter sensor data described in the above embodiments, for example, the method described above. Figure 1 , Figures 3-4 , Figures 6-7 and Figure 10 The steps shown.

[0194] This invention also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors, for example... Figure 14 A processor 21 enables one or more of the processors to execute the real-time processing method for multi-parameter sensing data according to a specific embodiment of the present invention, for example, to execute the method described above. Figure 1 , Figures 3-4 , Figures 6-7 and Figure 10 The steps shown can also be implemented. Figure 14 The various modules and units described above; or the real-time processing method for multi-parameter sensing data implemented in the specific embodiments of the present invention, for example, the method described above. Figure 1 , Figures 3-4 , Figures 6-7 and Figure 10 The steps shown can also be implemented. Figure 14 The various modules and units mentioned above.

[0195] It is worth noting that the information interaction and execution process between the modules and units in the above-mentioned device and system are based on the same concept as the processing method embodiment of the present invention. For details, please refer to the description in the method embodiment of the present invention, and will not be repeated here.

[0196] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0197] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for real-time processing of multi-parameter sensor data, characterized in that, The method comprises the following steps: Converting a plurality of sensing signals into corresponding digital signals respectively; the plurality of sensing signals comprise sensing signals of vibration, attenuation, temperature and strain parameters of an optical fiber; transmitting the converted digital signals to corresponding processing modules according to the parameter types of the converted digital signals; the processing modules comprise a first algorithm module, a second algorithm module and a third algorithm module; when the parameter type is attenuation sensing data, the digital signal is sent to the first algorithm module; when the parameter type is temperature sensing data and / or strain sensing data, the digital signal is sent to the second algorithm module; when the parameter type is vibration parameter sensing data, the digital signal is sent to the third algorithm module; The processing modules process the received digital signals, and send a write request to a bus control arbitration module after the processing is completed; the write request carries a host number of the processing module; the write request also comprises a write data request; the bus control arbitration module determines a current write request that needs to be responded immediately from the received write data request according to a preset scheduling mechanism; the write data request is sent by a data cache storage body of the processing module in response to a first processing command, and carries the host number and to-be-transmitted data; in response to the current write request, the current write request is transmitted to a data cache control module according to the host number carried by the current write request, so that the data cache control module converts the current write request into a second processing command, and writes the to-be-transmitted data into the data cache storage body based on the second processing command; The data cache control module receives a write address request from the bus control arbitration module, and converts the received write address request into a first processing command; The data cache storage body responds to the received first processing command, and prepares a write-in memory position of the to-be-transmitted data, so as to subsequently write the to-be-transmitted data into the data cache storage body according to the write-in memory position, thereby realizing communication between a plurality of processing modules and the data cache storage body.

2. The method of real-time processing of multi-parameter sensing data according to claim 1, wherein, The real-time processing method of the multi-parameter sensing data further comprises: Determining stored data required by a corresponding processing module according to a parameter type; sending a read address request to the bus control arbitration module before the processing module receives corresponding digital signals; the read address request comprises an address of the stored data in the data cache storage body, and carries a host number of the processing module; The bus control arbitration module transmits the received read address request to the data cache control module according to the host number; the data cache control module converts the read address request into a first access command, and transmits the first access command to the data cache storage body; the data cache storage body prepares the stored data according to the received first access command, so as to respond to the first access command. The processing module acquires the stored data from the read memory after the data cache memory bank completes responding to the first access command.

3. The method of real-time processing of multi-parameter sensing data according to claim 2, wherein, The processing module acquires the stored data from the read memory after the data cache memory bank completes responding to the first access command. The processing module sends a read data request corresponding to the read address request to the bus control arbitration module after the data cache memory bank completes responding to the first access command; the read data request carries the host number; The bus control arbitration module transmits the received read data request to the data cache control module according to the host number; the data cache control module converts the read data request into a second access command and transmits the second access command to the data cache memory bank; the data cache memory bank returns the stored data to the data cache control module in response to the received second access command; The data cache control module returns the stored data to the read memory corresponding to the processing module through the bus control arbitration module according to the host number carried by the read data request, so that the processing module acquires the stored data from the read memory.

4. The method of real-time processing of multi-parameter sensing data according to claim 3, wherein, The write request includes a write address request; The processing module processes the received digital signal, and sends a write request to the bus control arbitration module after processing is completed; the write request carries the host number of the processing module, including: Based on the stored data in the read memory, the received digital signal is processed in real time according to an algorithm configured by itself to generate to-be-transmitted data; The to-be-transmitted data is transmitted to the write memory corresponding to the processing module, so that the to-be-transmitted data is temporarily stored in the write memory when the to-be-transmitted data is not transmitted to the bus control arbitration module; The bus control arbitration module is sent a write address request corresponding to the to-be-transmitted data; the write address request carries the host number.

5. A real-time processing apparatus for multi-parameter sensor data, characterized by The system comprises an analog-to-digital conversion module, a processing module, a bus control arbitration module, a data cache control module, and a data cache memory bank, wherein: The analog-to-digital conversion module is configured to convert a plurality of sensing signals into corresponding digital signals; the plurality of sensing signals include sensing signals of vibration, attenuation, temperature, and strain parameters of an optical fiber; and the analog-to-digital conversion module is further configured to transmit the converted digital signals to corresponding processing modules according to the types of the parameters of the converted digital signals; the processing modules include a first algorithm module, a second algorithm module, and a third algorithm module; when the type of the parameter is attenuation sensing data, the digital signal is sent to the first algorithm module; when the type of the parameter is temperature sensing data and / or strain sensing data, the digital signal is sent to the second algorithm module; and when the type of the parameter is vibration parameter sensing data, the digital signal is sent to the third algorithm module. The processing module is used for processing the received digital signal and sending a write request to the bus control arbitration module after processing; the processing module is also used for sending a write data request to the bus control arbitration module after the data cache memory bank responds to the first processing command, and the write data request carries a host number and to-be-transmitted data; The bus control arbitration module is used for realizing communication between the processing module and the data cache control module according to the host number carried by the received write request; the write request also includes a write data request; the bus control arbitration module is also used for determining the current write request that is to be responded immediately from the received write data request according to a preset scheduling mechanism; The data cache control module is used for converting the received write request into a processing command and sending the processing command to the data cache memory bank; the data cache control module is also used for responding to the current write request, transmitting the current write request to the data cache control module according to the host number carried by the current write request, so that the data cache control module converts the current write request into a second processing command and writes the to-be-transmitted data into the data cache memory bank based on the second processing command; the data cache control module is also used for receiving a write address request from the bus control arbitration module and converting the received write address request into a first processing command; the data cache memory bank responds to the received first processing command, prepares a write-in memory position of the to-be-transmitted data, so as to subsequently write the to-be-transmitted data into the data cache memory bank according to the write-in memory position; The data cache memory bank is used for executing the processing command to realize communication between a plurality of processing modules and the data cache memory bank.

6. The apparatus for real-time processing of multi-parameter sensing data according to claim 5, wherein, The processing module includes a first algorithm module, a second algorithm module and a third algorithm module; the first algorithm module corresponds to a first write memory, the second algorithm module corresponds to a second write memory, and the third algorithm module corresponds to a third write memory; The first algorithm module corresponds to a first read memory, the second algorithm module corresponds to a second read memory, and the third algorithm module corresponds to a third read memory, wherein: The analog-digital conversion module is connected with the first algorithm module, the second algorithm module and the third algorithm module; The write side of the first algorithm module is connected with the first write memory, and the read side of the first algorithm module is connected with the first read memory; the write side of the second algorithm module is connected with the second write memory, and the read side of the second algorithm module is connected with the second read memory; the write side of the third algorithm module is connected with the third write memory, and the read side of the third algorithm module is connected with the third read memory; The first algorithm module, the second algorithm module and the third algorithm module are connected with the bus control arbitration module through AXI buses respectively. The bus control arbitration module is connected with the data cache control module through an AXI bus. The data cache memory is connected with the data cache control module.

7. The apparatus for real-time processing of multi-parameter sensor data of claim 6, wherein, Wherein: The first write memory is configured to convert the bit width of the to-be-processed data generated by the first algorithm module from a first bit width range to a second bit width range; the first read memory is configured to convert the bit width of the stored data required by the first algorithm module from the second bit width range to the first bit width range; wherein the first bit width range is smaller than the second bit width range; The second write memory is configured to convert the bit width of the to-be-processed data generated by the second algorithm module from a third bit width range to a fourth bit width range; the second read memory is configured to convert the bit width of the stored data required by the second algorithm module from the fourth bit width range to the third bit width range; wherein the third bit width range is smaller than the fourth bit width range; The third write memory is configured to convert the bit width of the to-be-processed data generated by the third algorithm module from a fifth bit width range to a sixth bit width range; the third read memory is configured to convert the bit width of the stored data required by the third algorithm module from the sixth bit width range to the fifth bit width range; wherein the fifth bit width range is smaller than the sixth bit width range.

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