BMC and BIOS communication method and device

Abstract

The application provides a BMC and BIOS communication method and device, wherein the method comprises the following steps: a baseboard management controller (BMC) sends a request message to a basic input / output system (BIOS) based on a target data channel, so that the BIOS performs corresponding response based on the request message after receiving the request message; the construction process of the target data channel comprises the following steps: the BMC splits a PCIe 5.0 bus channel constructed between the BMC and the BIOS based on a distributed virtual channel technology, obtains a plurality of parallel virtual communication channels, and constructs the target data channel based on the plurality of parallel virtual communication channels. The BMC and BIOS communication method and device provided by the application can realize multiple advantages such as high-speed data transmission, low-delay communication, stable reliability and hardware standardization compatibility, and improve the communication efficiency between the BMC and the BIOS.

Description

Technical Field

[0001] This invention relates to the field of server technology, and in particular to a communication method and apparatus between a BMC and a BIOS. Background Technology

[0002] As AI server systems develop and become more complex, communication between the BMC and BIOS within the server becomes increasingly important. Currently, the BMC and BIOS in servers communicate via the I2C bus. The BMC, acting as the master, controls the I2C bus, while the BIOS, acting as the slave, responds to the BMC's requests. The master sends a start signal to activate the bus and specifies the slave address and transmission direction with one byte of data; the slave responds with an acknowledge signal. Subsequently, the transmitter sends one byte of data, and the receiver acknowledges receipt with an acknowledge signal, thus achieving system communication interaction.

[0003] The existing method of communication between the BMC and BIOS in servers via the I2C bus may be insufficient for applications that transmit large amounts of data or have high speed requirements due to the relatively low I2C communication rate (typically in the range of hundreds of kHz). Summary of the Invention

[0004] This invention provides a communication method and apparatus between a BMC and a BIOS to improve the communication efficiency between the BMC and the BIOS.

[0005] This invention provides a communication method between a BMC and a BIOS, comprising:

[0006] The Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on the target data channel, so that the BIOS, upon receiving the request message, executes the corresponding response based on the request message.

[0007] The construction process of the target data channel includes:

[0008] The BMC uses distributed virtual channel technology to divide the PCIe 5.0 bus channel between the BMC and the BIOS into multiple parallel virtual communication channels, and constructs the target data channel based on these multiple parallel virtual communication channels.

[0009] According to a communication method between a BMC and a BIOS provided by the present invention, before the Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on a target data channel, the method further includes:

[0010] The BMC initializes the PCIe 5.0 bus channel between the BMC and the BIOS;

[0011] The initialization includes:

[0012] The BMC identifies the device where the BIOS is located based on the PCIe 5.0 bus channel between the BMC and the BIOS;

[0013] The BMC is based on a multi-channel communication protocol and configures the multiple parallel virtual communication channels. The multi-channel communication protocol is used to manage the multiple parallel virtual communication channels, define the data packet format in the multiple parallel virtual communication channels, define the error handling mechanism of the multiple parallel virtual communication channels, and determine the adaptation of the multiple parallel virtual communication channels to the underlying protocol.

[0014] The BMC performs link state training on the PCIe 5.0 bus channel between the BMC and the BIOS based on the link training state machine, so as to manage the state of the PCIe 5.0 bus channel between the BMC and the BIOS.

[0015] The communication method between BMC and BIOS provided by the present invention further includes:

[0016] The BMC determines the historical communication load of each virtual communication channel based on historical communication data from multiple virtual communication channels.

[0017] Based on the historical communication load, the resource scheduling of multiple virtual communication channels in the target data channel is adjusted in real time.

[0018] According to a communication method between a BMC and a BIOS provided by the present invention, the step of sending a request message to the Basic Input / Output BIOS system further includes:

[0019] When the request message consists of multiple messages, the BMC sends the multiple messages to the BIOS system in parallel based on multiple parallel virtual communication channels in the target data channel.

[0020] The communication method between BMC and BIOS provided by the present invention further includes:

[0021] Based on the characteristics of data transmission in the multiple parallel virtual communication channels and the priority of each virtual communication channel, the BMC divides the bandwidth of the PCIe 5.0 bus channel between the BMC and the BIOS to allocate bandwidth to each virtual communication channel.

[0022] The communication method between BMC and BIOS provided by the present invention further includes:

[0023] The BMC is based on a software-defined networking (SDN) controller, which adjusts the QoS policy of each virtual channel and adjusts the bandwidth allocation and priority of each virtual channel according to real-time network status and application requirements.

[0024] The communication method between BMC and BIOS provided by the present invention further includes:

[0025] Error data during transmission of the target data channel is obtained based on BMC;

[0026] The error data is categorized based on its error type, and the priority of processing the error data is determined based on the category of the error data.

[0027] The present invention also provides a communication device between a BMC and a BIOS, comprising:

[0028] The data transmission module is used for the Baseboard Management Controller (BMC) to send a request message to the Basic Input / Output BIOS system based on the target data channel, so that the BIOS can execute a corresponding response based on the request message after receiving it.

[0029] The construction process of the target data channel includes:

[0030] The BMC uses distributed virtual channel technology to divide the PCIe 5.0 bus channel between the BMC and the BIOS into multiple parallel virtual communication channels, and constructs the target data channel based on these multiple parallel virtual communication channels.

[0031] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement any of the above-described BMC-BIOS communication methods.

[0032] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the above-described BMC-BIOS communication methods.

[0033] The communication method and apparatus between the BMC and BIOS provided by this invention divides the PCIe 5.0 bus channel constructed between the BMC and the BIOS into multiple parallel virtual communication channels, thereby realizing the construction of a data transmission channel between the BMC and the BIOS. The multiple parallel virtual communication channels constructed based on the PCIe 5.0 bus channel division have higher bandwidth, lower latency, and stronger signal integrity, enabling high-speed data transmission, low-latency communication, stable reliability, and hardware standardization compatibility, thus improving the communication efficiency between the BMC and the BIOS. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly described below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart illustrating the communication method between the BMC and BIOS provided by the present invention;

[0036] Figure 2 This is a schematic diagram of the data transmission process provided by the present invention;

[0037] Figure 3 This is a schematic diagram of the communication device between BMC and BIOS provided by the present invention;

[0038] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0040] This invention proposes a communication method between the BMC and the BIOS. Figure 1 This is a flowchart illustrating the communication method between the BMC and BIOS provided by the present invention. (Refer to...) Figure 1 The communication method between the BMC and BIOS provided by this invention may include:

[0041] Step 110: The Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on the target data channel, so that the BIOS receives the request message and executes the corresponding response based on the request message.

[0042] The construction process of the target data channel includes:

[0043] The BMC uses distributed virtual channel technology to divide the PCIe 5.0 bus channel between the BMC and the BIOS into multiple parallel virtual communication channels, and constructs the target data channel based on these multiple parallel virtual communication channels.

[0044] The following example, using the BMC executing the communication method between the BMC and BIOS provided by this invention, illustrates the technical solution of this invention in detail.

[0045] Specifically, in step 110, the Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on the target data channel, so that the BIOS receives the request message and executes the corresponding response based on the request message.

[0046] Communication between the BMC and BIOS plays a crucial role in the operation of a computer system. Specifically, the BIOS can send control commands to the BMC to adjust the settings and behavior of hardware devices; conversely, the BMC can send monitoring information to the BIOS to assist in system management and fault diagnosis.

[0047] Before data transfer can occur between the BMC and BIOS, a target data channel for data transfer between the BMC and BIOS needs to be established.

[0048] Specifically, the construction process can be as follows:

[0049] Build the target data channel hardware configuration: Ensure that the server hardware supports the PCIe 5.0 interface and that both the BMC and BIOS modules can communicate with the PCIe 5.0 interface.

[0050] PCIe 5.0 refers to the fifth generation PCI Express (Peripheral Component Interconnect Express) interface, a high-speed, low-latency computer bus standard. PCIe 5.0 boasts a maximum transfer rate of 32GT / s, double that of PCIe 4.0's 16GT / s. This improvement is achieved through enhanced signal coding, increased channel bandwidth, and optimized hardware design. PCIe 5.0 offers significant improvements over PCIe 4.0 in terms of transfer rate, bandwidth, latency, power efficiency, and error detection and correction capabilities, resulting in substantial enhancements to the overall performance and efficiency of servers.

[0051] Unlike other methods, the BMC employs Distributed Virtual Channel (DVC) technology to establish a communication link with the BIOS. By dividing the PCIe 5.0 bus channel into multiple virtual channels, the BMC can establish multiple parallel communication channels with the BIOS, thereby enabling parallel data transmission and improving communication efficiency.

[0052] Develop the BMC: Develop software drivers for the communication protocol and data transmission between the BMC and BIOS. Internally, these drivers are responsible for data encoding and decoding, data transmission via the PCIe 5.0 interface, and clock synchronization within the BMC.

[0053] Testing and Verification: Perform BMC integration testing to ensure stable and reliable communication and data transmission between the BMC and BIOS. This includes testing the correctness of the communication protocol, the accuracy of data transmission, and the stability of clock synchronization.

[0054] Deployment and Maintenance: Deploy the tested BMC version to a live server environment and perform regular BMC version maintenance and updates. This includes monitoring the BMC system's operational status, handling anomalies, and regularly updating drivers and firmware within the BMC.

[0055] Specifically, the communication process between the BMC and BIOS is as follows:

[0056] When the system starts up, the BMC initializes via the PCIe Gen5 bus;

[0057] Establish a communication link between the BMC and the BIOS;

[0058] The interaction between responses and replies involves the BMC sending request messages to the BIOS based on a pre-built target data channel. Upon receiving the data from the BMC, the BIOS processes it accordingly and generates response or reply data. Through distributed virtual channel technology, the BIOS can process multiple data streams in parallel and simultaneously send multiple response or reply data to the BMC, improving communication efficiency.

[0059] Error handling and retries: During communication, if a data transmission error or loss occurs, the BMC will perform error detection and handling according to the PCIe 5.0 protocol specification.

[0060] After the BMC and BIOS establish the target data channel, they can transmit data based on the target data channel. A schematic diagram of the specific data transmission process can be seen as follows: Figure 2 The data transmission process provided by this invention is illustrated in the diagram.

[0061] BMC sends data to BIOS receiving process:

[0062] Data Encoding: The BMC first encodes the data to be sent, represented as (S_{encoded} = f(S_{original})), where (S_{original}) is the original data and (f()) is the encoding function. The encoded data (S_{encoded}) is then prepared to be sent to the BIOS.

[0063] Differential signal transmission: The encoded data is transmitted to the BIOS via the PCIe 5 interface in the form of differential signals. During transmission, the voltage difference of the differential signals represents the logical state of the data, i.e., (V_{diff}=V_{P}-V_{N}), where (V_{diff}) is the differential signal, and (V_{P}) and (V_{N}) are the voltage values ​​on the positive and negative signal lines, respectively.

[0064] Clock synchronization: To ensure synchronous data transmission, the clock signals (t_{BMC}) and (t_{BIOS}) between the BMC and the BIOS need to be synchronized, i.e., (t_{BMC} = t_{BIOS}).

[0065] BIOS data reception and return process:

[0066] Data Decoding: After receiving data through PCIe 5.0, the BIOS first decodes the data, which is represented as (S_{decoded}=g(S_{received})), where (S_{received}) is the received data, (S_{decoded}) is the decoded data, and (g()) is the decoding function.

[0067] Data processing and return: The BIOS processes the decoded data, which may include updating the system status, responding to commands from the BMC, etc. After processing the data, the BIOS can send the data back to the BMC through the same process, realizing bidirectional communication between the BMC and the BIOS.

[0068] Optionally, the specific communication process based on the target data channel can be as follows:

[0069] The BMC and BIOS negotiate and establish the necessary virtual channels during system startup, allocate resources for each channel, and record relevant parameters. For example, the BMC has negotiated and established two virtual channels with the BIOS: one for emergency alarms and the other for firmware updates, with the emergency alarm channel having higher priority.

[0070] When the BMC detects that the CPU temperature exceeds a preset threshold, it generates an emergency alarm message and encapsulates it into a protocol data packet with an emergency alarm channel identifier.

[0071] The BMC sends data packets to the BIOS via the emergency alarm channel. Because this channel has high priority, it will immediately interrupt and prioritize alarm information transmission, even if a firmware update is in progress. Upon receiving the data packet with the emergency alarm channel identifier, the BIOS immediately unpacks it and identifies it as a CPU temperature alarm. It then quickly adjusts the system state, such as by reducing the clock speed and lowering the temperature. The BIOS sends a confirmation response back to the BMC, indicating that the alarm has been properly handled. After ensuring the alarm information has been successfully sent, the BMC begins sending new firmware data packets via the firmware update channel.

[0072] The BMC and BIOS employ a data block checksum and confirmation mechanism to ensure the integrity of firmware data during transmission.

[0073] If packet loss or errors are detected during firmware transmission, BMC will retransmit the lost portion according to the error retransmission policy in the protocol.

[0074] The BMC needs to send temperature sensor data to the BIOS: After completing its internal data collection, the BMC encapsulates the data into a protocol packet with a "sensor data channel" ID. The BMC then sends this packet to the BIOS through the established "sensor data channel." Upon receiving the data packet, the BIOS parses the data based on the channel ID and updates its internal system state.

[0075] Exception handling:

[0076] If errors occur during transmission, such as lost or corrupted data packets, appropriate handling can be performed according to the retransmission policy configured for the channel. Please refer to the adaptive error handling policy above.

[0077] Channel maintenance and shutdown: When a function no longer needs communication, the resources of that virtual channel can be released. For example, after the system is running stably, some temporarily used diagnostic channels can be shut down. Throughout the process, the BMC and BIOS exchange system status and progress information in real time through another lower-priority channel (such as the system status channel).

[0078] Communication between the BIOS and BMC is typically based on specific embedded management interfaces, such as IPMI (Intelligent Platform Management Interface) and other proprietary low-level communication protocols, rather than directly using the native PCIe protocols. Therefore, by appropriately encapsulating and mapping DVC technology, and further abstracting and encapsulating DVC technology, a sub-protocol (BMC-DVC) suitable for communication between the BMC and BIOS can be created.

[0079] The BMC-DVC multi-channel communication protocol allows each channel to correspond to a specific function or data type, such as a system event channel, firmware update channel, sensor data channel, etc.

[0080] Each virtual channel has its own identifier (ID) and priority, allowing the BMC and BIOS to manage channel allocation and data transfer at their respective software levels.

[0081] This protocol explicitly describes how to divide and manage virtual channels, defining packet formats, error handling mechanisms, and flow control rules to adapt to the characteristics of IPMI or other underlying protocols. In this way, the DVC mechanism originally on the PCIe bus can be mapped to the communication link between the BIOS and BMC, enabling efficient transmission of different types of data through independent virtual channels.

[0082] The communication stack between the BMC and BIOS should include a BMC-DVC management layer for creating, deleting, activating, and deactivating virtual channels.

[0083] When creating a channel, specify its attributes, such as maximum transfer rate, buffer size, and error retransmission policy.

[0084] Before transmission, data is encapsulated in protocol packets with channel identifiers, allowing the sender and receiver to distinguish between different types of communication content.

[0085] Information with high real-time requirements (such as system alarms) can be transmitted quickly through the high-priority channel; non-urgent information is transmitted through the ordinary-priority channel.

[0086] Communication between the BMC and BIOS often involves sensitive system management and configuration information, requiring additional security measures such as encrypted transmission and access control mechanisms. These are not provided by default in the DVC standard. Adding encryption and authentication mechanisms ensures that all data transmitted through the virtual channel is protected. Data transmission on each channel can be encrypted using a specific key, accompanied by a Message Authentication Code (MAC) or digital signature to ensure data confidentiality and integrity. Only authenticated entities are allowed to access specific virtual channels.

[0087] Communication between the BIOS and BMC can occur during various states, including system startup, hibernation, and wake-up. This necessitates that the DVC (Dynamic Control Center) be designed with energy efficiency and fast response in mind, especially ensuring effective operation under low power conditions. Virtual channels can be dynamically enabled or disabled based on actual needs to save power. For example, during system hibernation, only essential alarm and wake-up channels can be kept active, while the rest can be disabled.

[0088] Optimize the scheduling algorithm to ensure that high-priority management information and critical commands are transmitted first under limited hardware resources, thereby guaranteeing the system's rapid response.

[0089] Understandably, leveraging the high-speed transmission characteristics of the PCIe 5.0 standard enables multiple advantages, including high-speed data transmission, low-latency communication, stable reliability, and hardware standardization compatibility. First, PCIe 5.0 provides a high-speed transmission rate of 16GT / s per lane, significantly improving data transmission efficiency and throughput, meeting the demands of modern data centers and enterprise applications for large-scale data transmission. Second, PCIe 5.0 features low communication latency, enabling rapid response and real-time data exchange, making it suitable for applications with strict communication timing requirements. Furthermore, the maturity and widespread adoption of the PCIe 5.0 communication standard bring advantages in hardware compatibility and standardization, ensuring compatibility with various hardware devices and system platforms, reducing the complexity of system design and integration, and improving system maintainability and scalability.

[0090] High efficiency: The PCIe 5.0 interface features high bandwidth and low latency, enabling fast data transmission, thereby improving the efficiency and response speed of communication between the BMC and BIOS.

[0091] Reliability: The PCIe 5.0 interface uses differential signal transmission and clock synchronization mechanism to ensure the stability and reliability of data transmission, and reduce the bit error rate and loss rate during data transmission.

[0092] Flexibility: The PCIe 5.0 interface is a highly flexible solution for communication, supporting multiple data formats and communication protocols to adapt to different application scenarios and needs.

[0093] Scalability: The PCIe 5.0 interface has high scalability, supporting the connection and data transmission of multiple devices, which facilitates system expansion and upgrades.

[0094] Compatibility: The PCIe 5.0 interface is an industry standard interface with good compatibility with existing hardware and software environments. It can be seamlessly integrated with existing systems, reducing the cost and risk of system upgrades and migrations.

[0095] The communication method between the BMC and BIOS provided in this invention constructs a data transmission channel between the BMC and BIOS by dividing the PCIe 5.0 bus channel between them into multiple parallel virtual communication channels. The multiple parallel virtual communication channels constructed after dividing the PCIe 5.0 bus channel offer higher bandwidth, lower latency, and stronger signal integrity, providing advantages such as high-speed data transmission, low-latency communication, stable reliability, and hardware standardization compatibility, thereby improving the communication efficiency between the BMC and BIOS.

[0096] In one embodiment, before the Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on the target data channel, the method further includes: the BMC initializing the PCIe 5.0 bus channel between the BMC and the BIOS; the initialization includes: the BMC identifying the device where the BIOS is located based on the PCIe 5.0 bus channel between the BMC and the BIOS; the BMC configuring the plurality of parallel virtual communication channels based on a multi-channel communication protocol, the multi-channel communication protocol being used to manage the plurality of parallel virtual communication channels, define the data packet format in the plurality of parallel virtual communication channels, define the error handling mechanism of the plurality of parallel virtual communication channels, and determine the adaptation of the plurality of parallel virtual communication channels to the underlying protocol; and the BMC performing link state training on the PCIe 5.0 bus channel between the BMC and the BIOS based on a link training state machine to perform state management of the PCIe 5.0 bus channel between the BMC and the BIOS.

[0097] The initialization process of the PCIe 5.0 bus channels by the BMC before sending the request message to the BIOS is as follows:

[0098] The BMC first identifies the device where the BIOS resides via the PCIe 5.0 bus channel. This typically involves enumerating and probing the devices on the bus to determine the specific location and identifier of the BIOS system.

[0099] BMC configures multiple parallel virtual communication channels based on a multi-channel communication protocol. This step aims to create multiple independent logical channels on the PCIe 5.0 physical channel through software, thereby improving communication flexibility and efficiency. The multi-channel communication protocol is responsible for managing these virtual channels, defining packet formats, error handling mechanisms, and determining their adaptation to the underlying PCIe protocol.

[0100] In multichannel communication protocols, packet format is fundamental to communication. The BMC and BIOS must adhere to the same packet format specifications to ensure the correctness and integrity of data during transmission.

[0101] The multichannel communication protocol also defines an error handling mechanism to detect and handle errors that may occur during communication.

[0102] Multi-channel communication protocols need to determine their compatibility with the underlying PCIe 5.0 protocol, adapting it to the characteristics of IPMI or other underlying protocols. In this way, the DVC mechanism originally on the PCIe bus can be mapped to the communication link between the BIOS and BMC, enabling efficient transmission of different types of data through independent virtual channels.

[0103] After configuring the virtual channel, the BMC performs link state training on the PCIe 5.0 bus channel based on the link training state machine. Link training is a crucial part of the PCIe protocol, used to ensure the quality and stability of the communication link. The link training state machine defines the various stages and processes of training, including physical layer training and data link layer training. Through this process, the BMC can detect and fix potential problems in the link, improving the reliability and stability of communication.

[0104] After link training is complete, the BMC can perform status management on the PCIe 5.0 bus channels. This includes monitoring the channel's operational status, handling anomalies, and optimizing performance. Through continuous status management, the BMC can ensure that communication with the BIOS remains optimal at all times.

[0105] In one embodiment, the method further includes: the BMC determining the historical communication load of each virtual communication channel based on historical communication data of multiple virtual communication channels; and adjusting the resource scheduling of multiple virtual communication channels in the target data channel in real time based on the historical communication load.

[0106] BMC continuously monitors and records data transmitted through each virtual communication channel. This data includes key metrics such as data transmission volume, transmission frequency, transmission latency, and error rate. By collecting and analyzing this historical communication data, BMC can understand the communication load of each virtual communication channel.

[0107] Based on the collected historical communication data, BMC can calculate the historical communication load of each virtual communication channel. The historical communication load can be a comprehensive indicator that reflects multiple dimensions such as the channel's average data transmission volume, maximum data transmission volume, and data transmission fluctuations over a period of time.

[0108] BMC not only determines current communication load based on historical data, but also uses advanced algorithms (such as machine learning algorithms) to predict future communication load. This real-time assessment and prediction capability enables BMC to make adjustments in advance to adapt to possible changes.

[0109] Specifically, BMC can predict future communication loads based on time series forecasting.

[0110] BMC needs to collect historical communication load data, which typically includes communication load values ​​at different points in time, forming time-series data. The collected data undergoes preprocessing steps such as cleaning, missing value imputation, and outlier handling to ensure accuracy and consistency.

[0111] An autoregressive moving average (ARMA) model can be selected: suitable for forecasting stationary time series data. Time series are modeled and predicted by selecting appropriate autoregressive and moving average terms.

[0112] The preprocessed data is divided into training, validation, and test sets. The selected time series prediction model is trained using the training set. The model's performance is evaluated on the validation set, and the model parameters are adjusted to achieve optimal prediction results. The model is then tested using the test set to verify its generalization ability.

[0113] The trained model is deployed to BMC for real-time prediction of future communication loads. Based on real-world application scenarios, the model is continuously optimized, such as by adjusting model parameters and adding new features, to improve prediction accuracy.

[0114] Based on real-time assessment and prediction of historical communication load, BMC can adjust the resource scheduling of multiple virtual communication channels in the target data channel in real time. Resource scheduling optimization can include the following aspects:

[0115] Bandwidth allocation: The bandwidth allocation of each channel is dynamically adjusted according to the load of each channel to ensure that high-load channels can obtain sufficient bandwidth resources, while low-load channels do not waste bandwidth.

[0116] Priority settings: Allocate more resources, such as higher bandwidth and lower latency, to high-priority data transmission to ensure timely transmission of important data.

[0117] Fault recovery: When a channel fails or experiences abnormal load, data transmission can be quickly switched to other channels to ensure the continuity and reliability of communication.

[0118] Load balancing: By balancing the load of each channel, it avoids situations where one channel is overloaded while other channels are idle, thereby improving overall communication efficiency.

[0119] In one embodiment, sending the request message to the Basic Input / Output BIOS system further includes: when the request message is multiple messages, the BMC sends the multiple messages to the BIOS system in parallel based on multiple parallel virtual communication channels in the target data channel.

[0120] Understandably, there are frequent situations where multiple messages need to be transmitted simultaneously between the BMC and BIOS. When there are multiple request messages, the BMC can use multiple parallel virtual communication channels to transmit multiple messages to the BIOS system in parallel, thus improving data transmission efficiency.

[0121] In one embodiment, the method further includes: the BMC allocating bandwidth to each virtual communication channel by dividing the bandwidth of the PCIe 5.0 bus channel between the BMC and the BIOS based on the characteristics of data transmitted in the plurality of parallel virtual communication channels and the priority of each virtual communication channel.

[0122] BMC first analyzes the characteristics of the data transmitted through each virtual communication channel. These characteristics may include data type, data size, transmission frequency, real-time requirements, etc. Specifically, the resulting virtual channels can be: firmware update channel, monitoring channel, emergency alarm channel, and sensor data channel, etc.

[0123] BMC prioritizes each virtual communication channel based on business needs and application scenarios. Priorities may be based on factors such as data importance, real-time requirements, and application sensitivity. For example, real-time control data may require higher priority to ensure its timely and accurate transmission.

[0124] Based on the characteristics of the transmitted data and channel priorities, the BMC formulates a bandwidth allocation strategy. This strategy aims to meet the transmission needs of each channel while ensuring efficient utilization of overall bandwidth.

[0125] The BMC allocates bandwidth for the PCIe 5.0 bus channels according to the established bandwidth allocation strategy and distributes corresponding bandwidth resources to each virtual communication channel. Simultaneously, the BMC continuously monitors the bandwidth usage of each virtual communication channel and dynamically adjusts it based on actual conditions. For example, when the transmission demand of a channel increases, the BMC can dynamically increase its bandwidth allocation; when the transmission demand of a channel decreases, it can allocate its excess bandwidth to other channels that require it.

[0126] In one embodiment, the BMC further includes: adjusting the QoS policy of each virtual channel based on the software-defined network (SDN) controller, and adjusting the bandwidth allocation and priority of each virtual channel according to the real-time network status and application requirements.

[0127] Building upon virtual channel isolation, the concept of Software Defined Networking (SDN) is integrated to achieve software-defined traffic management. The SDN controller dynamically adjusts the Quality of Service (QoS) policies for each virtual channel, automatically optimizing bandwidth allocation and prioritization based on real-time network conditions and application requirements. This ensures that critical services maintain minimal latency and maximum stability even in highly dynamic environments.

[0128] Based on SDN-based automation strategies, the system automatically releases additional resources previously allocated to firmware update channels, including restoring previously merged monitoring channels for routine monitoring. During resource reallocation, non-essential channels are kept in a low-power state to reduce overall system energy consumption. After resource reallocation, the BMC and BIOS exchange information through low-priority system status channels to confirm their respective statuses and prepare for the next task (such as system health checks or routine maintenance), ensuring continuous and efficient system operation.

[0129] In one embodiment, the method further includes: acquiring error data during transmission of the target data channel based on the BMC; classifying the error data based on the error type; and determining the priority of error data processing based on the category of the error data.

[0130] Optionally, the following mechanisms can be added to ensure reliability and handle exceptions during data transmission:

[0131] Adaptive error handling strategy:

[0132] Error type classification: First, it is necessary to classify and summarize the types of errors that may occur in communication. Common error types include transmission errors, packet loss errors, and timing errors. Based on the different error types, corresponding error handling strategies should be developed.

[0133] In this process, we maintain and record the problems encountered in each iteration. When a problem meets certain conditions, a solution is triggered, and the trigger time, process, and result are recorded in the corresponding MAINTENCE log. For example, during the interaction and transmission between the BMC and BIOS, it is discovered that the BMC receives data on the device components transmitted from the BIOS. The missing information will cause the BMC web interface to display missing components. When the BMC detects missing data in the returned information, it will switch to the adaptive error handling process. According to the data loss policy, it will compare the data and transfer it to the relevant thread. At the same time, it will resend the missing data signal to the BIOS and wait for the BIOS to return the data. After the data is returned, it will compare it again and end the current processing flow.

[0134] Strategy formulation and priority determination: For each error type, a corresponding error handling strategy is formulated, and the processing priority (warning / critical) is determined. For example, for critical transmission errors, a strategy of immediately interrupting communication and performing error recovery can be adopted; for minor packet loss errors (warnings), a strategy of delayed processing or automatic retry can be adopted.

[0135] Parameters are dynamically adjusted during communication based on real-time communication conditions and error feedback. The execution method and priority of the error handling strategy can be adjusted in real time according to factors such as communication load, communication environment, and system status to maximize communication stability and reliability.

[0136] Figure 3 This is a schematic diagram of the communication device between the BMC and BIOS provided by the present invention, as shown below. Figure 3 As shown, the device includes:

[0137] Data transmission module 310 is used for the baseboard management controller (BMC) to send a request message to the basic input / output BIOS system based on the target data channel, so that the BIOS can execute a corresponding response based on the request message after receiving the request message;

[0138] The construction process of the target data channel includes:

[0139] The BMC uses distributed virtual channel technology to divide the PCIe 5.0 bus channel between the BMC and the BIOS into multiple parallel virtual communication channels, and constructs the target data channel based on these multiple parallel virtual communication channels.

[0140] The communication device between the BMC and BIOS provided by this invention divides the PCIe 5.0 bus channel constructed between the BMC and the BIOS into multiple parallel virtual communication channels, thereby realizing the construction of a data transmission channel between the BMC and the BIOS. The multiple parallel virtual communication channels constructed based on the PCIe 5.0 bus channel division have higher bandwidth, lower latency, and stronger signal integrity, enabling high-speed data transmission, low-latency communication, stable reliability, and hardware standardization compatibility, thus improving the communication efficiency between the BMC and the BIOS.

[0141] In one embodiment, the data transmission module 310 is specifically used for:

[0142] Before the Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on the target data channel, it also includes:

[0143] The BMC initializes the PCIe 5.0 bus channel between the BMC and the BIOS;

[0144] The initialization includes:

[0145] The BMC identifies the device where the BIOS is located based on the PCIe 5.0 bus channel between the BMC and the BIOS;

[0146] The BMC is based on a multi-channel communication protocol and configures the multiple parallel virtual communication channels. The multi-channel communication protocol is used to manage the multiple parallel virtual communication channels, define the data packet format in the multiple parallel virtual communication channels, define the error handling mechanism of the multiple parallel virtual communication channels, and determine the adaptation of the multiple parallel virtual communication channels to the underlying protocol.

[0147] The BMC performs link state training on the PCIe 5.0 bus channel between the BMC and the BIOS based on the link training state machine, so as to manage the state of the PCIe 5.0 bus channel between the BMC and the BIOS.

[0148] In one embodiment, the data transmission module 310 is further configured to:

[0149] Also includes:

[0150] The BMC determines the historical communication load of each virtual communication channel based on the historical communication data of the multiple virtual communication channels.

[0151] Based on the historical communication load, the resource scheduling of multiple virtual communication channels in the target data channel is adjusted in real time.

[0152] In one embodiment, the data transmission module 310 is further configured to:

[0153] Sending the request message to the Basic Input / Output BIOS system further includes:

[0154] When the request message consists of multiple messages, the BMC sends the multiple messages to the BIOS system in parallel based on multiple parallel virtual communication channels in the target data channel.

[0155] In one embodiment, the data transmission module 310 is further configured to:

[0156] Also includes:

[0157] Based on the characteristics of data transmission in the multiple parallel virtual communication channels and the priority of each virtual communication channel, the BMC divides the bandwidth of the PCIe 5.0 bus channel between the BMC and the BIOS to allocate bandwidth to each virtual communication channel.

[0158] In one embodiment, the data transmission module 310 is further configured to:

[0159] Also includes:

[0160] The BMC, based on a software-defined networking (SDN) controller, adjusts the QoS (Quality of Service) policy of each virtual channel and adjusts the bandwidth allocation and priority of each virtual channel according to real-time network status and application requirements.

[0161] In one embodiment, the data transmission module 310 is further configured to:

[0162] Also includes:

[0163] Error data during transmission of the target data channel is obtained based on BMC;

[0164] The error data is categorized based on its error type, and the priority of processing the error data is determined based on the category of the error data.

[0165] Figure 4 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 4As shown, the electronic device may include: a processor 410, a communication interface 420, a memory 430, and a communication bus 440, wherein the processor 410, the communication interface 420, and the memory 430 communicate with each other through the communication bus 440. The processor 410 can call logical instructions in the memory 430 to execute a communication method between the BMC and the BIOS, the method including:

[0166] The Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on the target data channel, so that the BIOS, upon receiving the request message, executes the corresponding response based on the request message.

[0167] The construction process of the target data channel includes:

[0168] The BMC uses distributed virtual channel technology to divide the PCIe 5.0 bus channel between the BMC and the BIOS into multiple parallel virtual communication channels, and constructs the target data channel based on these multiple parallel virtual communication channels.

[0169] Furthermore, the logical instructions in the aforementioned memory 430 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0170] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, wherein when the program instructions are executed by a computer, the computer is able to execute the BMC-BIOS communication method provided by the above methods, the method comprising:

[0171] The Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on the target data channel, so that the BIOS, upon receiving the request message, executes the corresponding response based on the request message.

[0172] The construction process of the target data channel includes:

[0173] The BMC uses distributed virtual channel technology to divide the PCIe 5.0 bus channel between the BMC and the BIOS into multiple parallel virtual communication channels, and constructs the target data channel based on these multiple parallel virtual communication channels.

[0174] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the communication method between the BMC and BIOS provided by the methods described above, the method comprising:

[0175] The Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on the target data channel, so that the BIOS, upon receiving the request message, executes the corresponding response based on the request message.

[0176] The construction process of the target data channel includes:

[0177] The BMC uses distributed virtual channel technology to divide the PCIe 5.0 bus channel between the BMC and the BIOS into multiple parallel virtual communication channels, and constructs the target data channel based on these multiple parallel virtual communication channels.

[0178] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0179] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A communication method between BMC and BIOS, characterized in that, The method includes: The Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on the target data channel, so that the BIOS, upon receiving the request message, executes the corresponding response based on the request message. The construction process of the target data channel includes: The BMC uses distributed virtual channel technology to divide the PCIe 5.0 bus channel between the BMC and the BIOS into multiple parallel virtual communication channels, and constructs the target data channel based on these multiple parallel virtual communication channels. Before the Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on the target data channel, it also includes: The BMC initializes the PCIe 5.0 bus channel between the BMC and the BIOS; The initialization includes: The BMC identifies the device where the BIOS is located based on the PCIe 5.0 bus channel between the BMC and the BIOS; The BMC is based on a multi-channel communication protocol and configures the multiple parallel virtual communication channels. The multi-channel communication protocol is used to manage the multiple parallel virtual communication channels, define the data packet format in the multiple parallel virtual communication channels, define the error handling mechanism of the multiple parallel virtual communication channels, and determine the adaptation of the multiple parallel virtual communication channels to the underlying protocol. The BMC performs link state training on the PCIe 5.0 bus channel between the BMC and the BIOS based on the link training state machine, so as to manage the state of the PCIe 5.0 bus channel between the BMC and the BIOS.

2. The communication method between BMC and BIOS according to claim 1, characterized in that, Also includes: The BMC determines the historical communication load of each virtual communication channel based on historical communication data from multiple virtual communication channels. Based on the historical communication load, the resource scheduling of multiple virtual communication channels in the target data channel is adjusted in real time.

3. The communication method between BMC and BIOS according to claim 1, characterized in that, Sending the request message to the Basic Input / Output BIOS system further includes: When the request message consists of multiple messages, the BMC sends the multiple messages to the BIOS system in parallel based on multiple parallel virtual communication channels in the target data channel.

4. The communication method between BMC and BIOS according to claim 1, characterized in that, Also includes: Based on the characteristics of data transmission in the multiple parallel virtual communication channels and the priority of each virtual communication channel, the BMC divides the bandwidth of the PCIe 5.0 bus channel between the BMC and the BIOS to allocate bandwidth to each virtual communication channel.

5. The communication method between BMC and BIOS according to claim 1, characterized in that, Also includes: The BMC is based on a software-defined networking (SDN) controller, which adjusts the QoS policy of each virtual channel and adjusts the bandwidth allocation and priority of each virtual channel according to real-time network status and application requirements.

6. The communication method between BMC and BIOS according to claim 1, characterized in that, Also includes: Error data during transmission of the target data channel is obtained based on BMC; The error data is categorized based on its error type, and the priority of processing the error data is determined based on the category of the error data.

7. A communication device between a BMC and a BIOS, characterized in that, include: The data transmission module is used for the Baseboard Management Controller (BMC) to send a request message to the Basic Input / Output BIOS system based on the target data channel, so that the BIOS can execute a corresponding response based on the request message after receiving it. The construction process of the target data channel includes: The BMC uses distributed virtual channel technology to divide the PCIe 5.0 bus channel between the BMC and the BIOS into multiple parallel virtual communication channels, and constructs the target data channel based on these multiple parallel virtual communication channels. Before the Baseboard Management Controller (BMC) sends a request message to the Basic Input / Output BIOS system based on the target data channel, it also includes: The BMC initializes the PCIe 5.0 bus channel between the BMC and the BIOS; The initialization includes: The BMC identifies the device where the BIOS is located based on the PCIe 5.0 bus channel between the BMC and the BIOS; The BMC is based on a multi-channel communication protocol and configures the multiple parallel virtual communication channels. The multi-channel communication protocol is used to manage the multiple parallel virtual communication channels, define the data packet format in the multiple parallel virtual communication channels, define the error handling mechanism of the multiple parallel virtual communication channels, and determine the adaptation of the multiple parallel virtual communication channels to the underlying protocol. The BMC performs link state training on the PCIe 5.0 bus channel between the BMC and the BIOS based on the link training state machine, so as to manage the state of the PCIe 5.0 bus channel between the BMC and the BIOS.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the communication method between the BMC and the BIOS as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the communication method between the BMC and the BIOS as described in any one of claims 1 to 6.

Images