Gate driving circuit, display panel and display device

Abstract

The application provides a gate drive circuit, a display panel and a display device. The gate drive circuit comprises a starting signal circuit, a drive output circuit, a noise reduction signal circuit, a noise reduction circuit, a first reset circuit and a second reset circuit. The starting signal circuit is connected with a first output signal line and a second output signal line, and is connected with the drive output circuit through a first node. The drive output circuit is connected with a clock signal line and the starting signal circuit. The noise reduction signal circuit is connected with the noise reduction circuit, a voltage signal line, a power supply end, the second output signal line and the first node. The noise reduction circuit is connected with the drive output circuit, the noise reduction signal circuit and the voltage signal line. The first reset circuit is connected with the voltage signal line, the first node and a global reset signal line. The second reset circuit is connected with the voltage signal line, the drive output circuit and a third output signal line.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] Thin Film Transistor-Liquid Crystal Display (TFT-LCD) features small size, low power consumption, high image quality, no radiation, and portability. It has developed rapidly in recent years and has gradually replaced traditional cathode ray tube display (CRT) devices, occupying a dominant position in the current flat panel display market.

[0003] In the GOA (Gate On Array) circuit of an LCD, individual TFTs need to be designed with their gate and drain connected. However, with this design, these TFTs are easily turned on if static electricity occurs, which can damage the circuit. Summary of the Invention

[0004] In view of this, this application proposes a gate driving circuit, a display panel, and a display device to solve or partially solve the above-mentioned problems.

[0005] To achieve the above objectives, this application provides a gate driving circuit, wherein the gate driving circuit is one of any row in an array of gate driving circuits, and the gate driving circuit includes: a start signal circuit, a drive output circuit, a noise reduction signal circuit, a noise reduction circuit, a first reset circuit, and a second reset circuit.

[0006] The start signal circuit is connected to the first output signal line and the second output signal line, and is connected to the drive output circuit through the first node. It is configured to provide a control signal to the drive output circuit. The first output signal line and the second output signal line are two output signal lines of the drive output circuit of another gate drive circuit of the first set row.

[0007] The drive output circuit is connected to the clock signal line and the start signal circuit, and is configured to receive the control signal, generate an output signal, and output the output signal through the corresponding output signal line.

[0008] The noise reduction signal circuit is connected to the noise reduction circuit, the voltage signal line, the power supply terminal, the second output signal line and the first node, and is configured to generate and output the noise reduction control signal of the noise reduction circuit.

[0009] The noise reduction circuit is connected to the drive output circuit, the noise reduction signal circuit and the voltage signal line, and is configured to reduce noise in the control signal and the output signal according to the noise reduction control signal.

[0010] The first reset circuit, connected to the voltage signal line, the first node, and the global reset signal line, is configured to perform an initial reset of the circuit.

[0011] The second reset circuit, connected to the voltage signal line, the drive output circuit, and the third output signal line, is configured to reset the output signal; wherein the third output signal line is an output signal line of the drive output circuit of another gate drive circuit of the second set row.

[0012] In some exemplary embodiments, the activation signal circuit includes:

[0013] The first transistor has its control electrode connected to the first output signal line, its first electrode connected to the second output signal line, and its second electrode connected to the first node.

[0014] In some exemplary embodiments, the activation signal circuit includes:

[0015] The first transistor has its control electrode connected to the second output signal line, its first electrode connected to the first output signal line, and its second electrode connected to the first node.

[0016] In some exemplary embodiments, when the gate driving circuit is a gate driving circuit in a first preset row of the set of gate driving circuits, the first transistor has its control electrode connected to a first start frame signal line, its first electrode connected to a second start frame signal line, and its second electrode connected to the first node.

[0017] In some exemplary embodiments, the drive output circuit includes:

[0018] The second transistor has its control electrode connected to the first node, its first electrode connected to the clock signal line, and its second electrode connected to the fifth output signal line.

[0019] The third transistor has its control electrode connected to the first node, its first electrode connected to the clock signal line, and its second electrode connected to the sixth output signal line.

[0020] In some exemplary embodiments, the noise reduction signal circuit includes: a signal generation circuit and a first control circuit;

[0021] The signal generation circuit, along with the power supply and the first control circuit, is configured to generate the noise reduction control signal.

[0022] The first control circuit is connected to the signal generation circuit, the voltage signal line and the noise reduction circuit, and is configured to control the noise reduction control signal.

[0023] In some exemplary embodiments, the power supply terminal includes a first power supply terminal and a second power supply terminal, and the signal generation circuit includes:

[0024] The fourth transistor has its control electrode connected to the first power supply terminal, its first electrode connected to the second power supply terminal, and its second electrode connected to the noise reduction circuit.

[0025] In some exemplary embodiments, the first control circuit includes:

[0026] The fifth transistor has its control electrode connected to the second output signal line, its first electrode connected to the voltage signal line, and its second electrode connected to the second electrode of the fourth transistor.

[0027] The sixth transistor has its control electrode connected to the first node, its first electrode connected to the voltage signal line, and its second electrode connected to the second electrode of the fourth transistor.

[0028] In some exemplary embodiments, the noise reduction circuit includes:

[0029] The seventh transistor has its control electrode connected to the second electrode of the fourth transistor, its first electrode connected to the voltage signal line, and its second electrode connected to the first node;

[0030] The eighth transistor has its control electrode connected to the second electrode of the fourth transistor, its first electrode connected to the voltage signal line, and its second electrode connected to the fifth output signal line.

[0031] The ninth transistor has its control electrode connected to the second electrode of the fourth transistor, its first electrode connected to the voltage signal line, and its second electrode connected to the sixth output signal line.

[0032] In some exemplary embodiments, the first reset circuit includes:

[0033] The tenth transistor has its control electrode connected to the global reset signal line, its first electrode connected to the voltage signal line, and its second electrode connected to the first node.

[0034] In some exemplary embodiments, the second reset circuit includes:

[0035] The eleventh transistor has its control electrode connected to the third output signal line, its first electrode connected to the voltage signal line, and its second electrode connected to the sixth output signal line.

[0036] In some exemplary embodiments, the gate driving circuit further includes:

[0037] The second control circuit, connected to the voltage signal line, the first node, and the fourth output signal line, is configured to control the potential of the first node; wherein the fourth output signal line is another output signal line of the drive output circuit of another gate drive circuit of the second set row.

[0038] In some exemplary embodiments, the second control circuit includes:

[0039] The twelfth transistor has its control electrode connected to the fourth output signal line, its first electrode connected to the voltage signal line, and its second electrode connected to the first node.

[0040] In some exemplary embodiments, when the gate driving circuit is a gate driving circuit in the second preset row of the set of gate driving circuits, the eleventh transistor has its control electrode connected to the global reset signal line; the twelfth transistor has its control electrode connected to the global reset signal line.

[0041] In some exemplary embodiments, the gate driving circuit further includes:

[0042] A storage capacitor, the first end of which is connected to the first node, and the second end of which is connected to the sixth output signal line.

[0043] Based on the same concept, this application also provides a display panel including the gate driving circuit as described in any of the preceding claims.

[0044] Based on the same concept, this application also provides a display device, including the display panel as described above.

[0045] As can be seen from the above description, the gate driving circuit, display panel, and display device provided in this application include: a startup signal circuit, a drive output circuit, a noise reduction signal circuit, a noise reduction circuit, a first reset circuit, and a second reset circuit; the startup signal circuit is connected to the first output signal line and the second output signal line, and is connected to the drive output circuit through a first node; the drive output circuit is connected to the clock signal line and the startup signal circuit; the noise reduction signal circuit is connected to the noise reduction circuit, the voltage signal line, the power supply terminal, the second output signal line, and the first node; the noise reduction circuit is connected to the drive output circuit, the noise reduction signal circuit, and the voltage signal line; the first reset circuit is connected to the voltage signal line, the first node, and the global reset signal line; the second reset circuit is connected to the voltage signal line, the drive output circuit, and the third output signal line. This application transforms a single output signal line originally connected to the start signal circuit into two completely independent output signal lines with essentially the same signal. This allows the relevant TFTs in the start signal circuit to function as transistor TFTs when not powered on, effectively preventing static electricity. When powered on, since the two output signal lines have essentially the same signal, they can still be considered as the original diode TFTs. This method eliminates the generation of static electricity, prevents the TFTs from being turned on, and avoids damage to the circuit. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of an exemplary GOA circuit provided in an embodiment of this application.

[0048] Figure 2 A schematic diagram of the layout design of the first transistor M1 and the fourth transistor M4 of the exemplary GOA circuit provided in the embodiments of this application.

[0049] Figure 3 This is a structural block diagram of an exemplary gate drive circuit provided in an embodiment of this application.

[0050] Figure 4 This is a schematic diagram of a first circuit structure of an exemplary gate drive circuit provided in an embodiment of this application.

[0051] Figure 5 This is a schematic diagram of a second circuit structure for an exemplary gate drive circuit provided in an embodiment of this application.

[0052] Figure 6A schematic diagram of the layout design of the first transistor M1 and the fourth transistor M4 of the exemplary gate drive circuit provided in an embodiment of this application.

[0053] Figure 7 for Figure 6 A schematic diagram of the cross-sectional structure along lines AA' and BB'.

[0054] Figure 8 This is a schematic diagram of the waveforms of each signal line when VDD of the exemplary gate drive circuit provided in the embodiments of this application is DC.

[0055] Figure 9 The exemplary gate drive circuit provided in this application provides a schematic diagram of the waveforms of each signal line when VDD is AC. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this specification clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0057] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element, object, or method step preceding the term covers the element, object, or method step listed after the term and its equivalents, without excluding other elements, objects, or method steps. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0058] This application provides a display device, which can be a mobile phone, computer, television, monitor, vehicle display device, touch screen all-in-one machine or conference screen, etc., that needs to display content. The display device includes a liquid crystal display panel.

[0059] A liquid crystal display (LCD) panel includes an array substrate, a color filter substrate (CF), and a liquid crystal layer (LC). After the array substrate and CF are assembled into cells, the liquid crystal layer fills the space between the array substrate and the CF. The LCD panel includes a display area (Active Area, or AA area) and a non-display area. The display area is the region used for display, containing multiple pixel units arranged in an array; the non-display area is located around the perimeter of the display area.

[0060] The array substrate has pixel circuits within the display area for controlling the display of pixel units. The pixel circuits include multiple vertically intersecting gate lines and multiple data lines, as well as thin-film transistors (TFTs) connected between the gate lines and data lines. These TFTs are positioned corresponding to the pixel units; therefore, they are referred to herein as pixel transistors. The pixel transistors conduct when a second conduction level is input. Pixel transistors located in the same row of pixel units are connected to the same gate line, and pixel transistors located in the same column of pixel units are connected to the same data line.

[0061] The array substrate has a gate driving circuit connected to the gate lines and a data driving circuit connected to the data lines in the non-display area. The gate driving circuit includes multiple cascaded shift register units. During the display process of the liquid crystal display panel, the gate driving circuit outputs a gate scan signal to scan and access each pixel unit in the pixel array line by line. The data driving circuit converts the display data to be displayed into data voltage signals. While each row of gate lines is scanned, the data driving circuit writes the data voltage signals into the pixel circuit of that row through each data line to illuminate the pixel units in that row, ultimately realizing the display of the entire display area.

[0062] As described in the background section, in such Figure 1 In the gate drive circuit shown, some of the transistor TFTs are designed with their gates (G, control electrode) and drains (Drain, first electrode) connected, such as the first transistor M1 and the fourth transistor M4. Then, as... Figure 2 The diagram shows the layout design of the first transistor M1 and the fourth transistor M4. It can be seen that the gate and drain of the first transistor M1 are connected to the same signal line, and similarly, the gate and drain of the fourth transistor M4 are also connected to the same signal line. During the manufacturing process, if static electricity occurs, the gate and drain of the existing TFT design are connected together and carry the same charge. Compared to a transistor TFT where the gate and drain are not connected, this design is more susceptible to static electricity conduction, is more affected by static electricity, and is more prone to TFT damage.

[0063] In light of the above-mentioned practical situation, this application provides a gate driving circuit. This application transforms a single output signal line originally connected to the startup signal circuit into two completely independent output signal lines with essentially the same signal. This allows the relevant TFTs in the startup signal circuit to function as transistor TFTs when not powered, effectively preventing static electricity. Only when powered on, since the two output signal lines essentially have the same signal, they can still be considered as original diode TFTs. This method eliminates the generation of static electricity, preventing the TFTs from being turned on and causing damage to the circuit.

[0064] after, Figure 3 A structural block diagram of an exemplary gate drive circuit provided in an embodiment of this application is shown.

[0065] like Figure 3 As shown, the gate drive circuit exemplarily proposed in this application includes: a start signal circuit 310, a drive output circuit 320, a noise reduction signal circuit 330, a noise reduction circuit 340, a first reset circuit 350, and a second reset circuit 360.

[0066] The start signal circuit 310 is used to provide a start signal to the gate driving circuit of the current row. It should be noted that the gate driving circuit in this embodiment is one of the gate driving circuits in any row of a gate driving circuit set composed of multiple gate driving circuits arranged in an array in the display panel, and each row may include at least one gate driving circuit. Furthermore, in the display panel obtained in this application, the gate driving circuits in the gate driving circuit set are generally grouped, and each group is controlled uniformly. For example, in some embodiments, four or five rows of gate driving circuits can be controlled uniformly as a group. Taking four rows as an example, the gate driving circuits from the first to the fourth row form the first group, the gate driving circuits from the fifth to the eighth row form the second group, and so on.

[0067] Next, the start signal circuit 310 will be further described. In this embodiment, the start signal circuit 310 is connected to the first output signal line G(nx) and the second output signal line C(nx), and is connected to the drive output circuit 320 through the first node PU. The first output signal line G(nx) and the second output signal line C(nx) are two output signal lines of the drive output circuit of another gate drive circuit in the first set row. As can be seen from the aforementioned grouping, the first set row here is the row corresponding to the row where the current gate drive circuit is located in the previous group. For example, in an embodiment where 4 rows are grouped together, the first output signal line and the second output signal line are G(n-4) and C(n-4). It should be noted beforehand that the drive output circuit 320 of the gate drive circuit in this embodiment generally has two output signal lines, namely the fifth output signal line Cn and the sixth output signal line Gn. The fifth output signal line Cn of the current gate drive circuit is the second output signal line of the corresponding start signal circuit in the next group, and similarly, the sixth output signal line Gn is the first output signal line of the corresponding start signal circuit in the next group. The correspondence here depends on the number of rows in each group. If each group includes four rows, then the Cn and Gn of the current gate drive circuit are the second and first output signal lines of the gate drive circuit in the fourth row. In specific implementation scenarios, the output of Cn is generally a capacitor output signal, and the output of Gn is generally a voltage output signal. The first node PU can be understood as a pull-up node; after startup, keeping the potential of this point high enables the drive output circuit to perform the corresponding output.

[0068] In some embodiments, such as Figure 4 As shown, the start signal circuit 310 may further include: a first transistor M1, whose control electrode is connected to the first output signal line G(nx), its first electrode is connected to the second output signal line C(nx), and its second electrode is connected to the first node PU.

[0069] It should also be noted that in the transistor structures appearing in this embodiment and subsequent embodiments, the control electrode generally corresponds to the gate (G) of the transistor, while the first and second electrodes correspond to the source (S) and drain (D) of the transistor. Furthermore, the transistors used in the embodiments of this application can all be thin-film transistors, field-effect transistors, or other devices with similar characteristics; thin-film transistors can be oxide semiconductor transistors. Based on their function in the circuit, the transistors used in the embodiments of this application are mainly switching transistors. Since the source and drain of a switching transistor are symmetrical, they are interchangeable. Therefore, in this scheme, one of the source and drain is called the first electrode, the other is called the second electrode, and the gate is called the control electrode.

[0070] and Figure 1 In contrast, in this embodiment, the control electrode and the first electrode of the first transistor M1, which were originally connected to the same output signal line, are separated so that they are connected to two separate output signal lines. Although the actual signal waveforms of these two signal lines may be the same or similar, since they are signals output from two output nodes, the control electrode and the first electrode of the first transistor M1 can be separated so that the transistor TFT structure can be maintained when it is not powered on, thereby preventing static electricity from occurring.

[0071] Subsequently, in some other embodiments, since the first output signal line G(nx), or the output signal of Gn of each gate drive circuit, is connected to the AA area (display area) of the display panel for pixel display control, these pixels may affect the signal of Gn, for example, causing insufficient waveform amplitude, i.e., voltage instability. Furthermore, if the first output signal line G(nx) is connected to the control electrode of the first transistor M1, there is a small probability that the first and second electrodes of the first transistor M1 may fail to conduct. Therefore, to reduce the occurrence of the above situations and for a more reliable design, in some embodiments, such as... Figure 5 As shown, the start signal circuit 310 may further include: a first transistor M1, whose control electrode is connected to the second output signal line C(nx), its first electrode is connected to the first output signal line G(nx), and its second electrode is connected to the first node PU. That is, in Figure 4 Based on the first transistor M1 shown, the wires connecting the control electrode and the first electrode are swapped.

[0072] It should be noted here that, with Figure 1 Compared to the illustrated embodiment, the startup signal circuit 310 in this embodiment adds a first output signal line G(nx) to the original second output signal line C(nx). In specific application scenarios, a signal line can be added from the Gn line of each row of the gate drive circuit and eventually run parallel to the original Cn line. Similarly, it only requires a slight increase in the border width.

[0073] Furthermore, as mentioned above, gate drive circuits generally appear in groups. Therefore, for the gate drive circuits within the first group, for example, in a scenario where four rows form a group, the first four rows of gate drive circuits do not actually have a first output signal line G(nx) and a second output signal line C(nx). Consequently, in order to provide signals to the gate drive circuits of these rows, in some embodiments, the control electrode and the first electrode of the first transistor M1 in the first preset row can be connected to two start frame signal lines STV respectively. That is, in some embodiments, such as... Figure 4 or Figure 5As shown, when the gate driving circuit is a gate driving circuit within the first preset row of the gate driving circuit set, the first transistor M1 has its control electrode connected to the first start frame signal line STV1, its first electrode connected to the second start frame signal line STV2, and its second electrode connected to the first node PU. The first preset row is determined based on the grouping of the gate driving circuit set in a specific application scenario. For example, if there are 4 rows as a group, then the first preset row is the first 4 rows; if there are 5 rows as a group, then the first preset row is the first 5 rows. Although the first start frame signal line STV1 and the second start frame signal line STV2 have the same signal, they are not branches of the same STV bus. This does not prevent the generation of static electricity. They are at least led out from two pins of the corresponding IC (integrated circuit). For example, two start frame signals are led out from two pins of the same FPC, namely the first start frame signal line STV1 and the second start frame signal line STV2. These two start frame signal lines can be arranged side by side on the same layer (of course, they can also be set on different layers in different embodiments). Since there is a start frame signal line STV in the original design, it is only necessary to add a trace width and position next to it to solve the corresponding trace problem.

[0074] like Figure 3 As shown, the drive output circuit 320 is connected to the clock signal line CKm and the start signal circuit 310, and is configured to receive the control signal, generate the output signal, and output the output signal through the corresponding output signal line.

[0075] Specifically, such as Figure 4 or Figure 5 As shown, the drive output circuit 320 may include: a second transistor M2, whose control electrode is connected to the first node PU, whose first electrode is connected to the clock signal line CKm, and whose second electrode is connected to the fifth output signal line Cn; and a third transistor M3, whose control electrode is connected to the first node PU, whose first electrode is connected to the clock signal line CKm, and whose second electrode is connected to the sixth output signal line Gn.

[0076] The clock signal line CKm (where m is an integer greater than 0) is used to provide a synchronization signal source for the gate drive circuit. The fifth output signal line Cn and the sixth output signal line Gn have been described in the foregoing embodiments.

[0077] like Figure 3 As shown, the noise reduction signal circuit 330 is connected to the noise reduction circuit 340, the voltage signal line VGL, the power supply terminal VDD, the second output signal line C(nx), and the first node PU, and is configured to generate and output the noise reduction control signal of the noise reduction circuit 340.

[0078] Specifically, the noise reduction signal circuit 330 can be further divided into a signal generation circuit 331 and a first control circuit 332. The signal generation circuit 331, connected to the power supply terminal VDD and the first control circuit 332, is configured to generate the noise reduction control signal. The first control circuit 332, connected to the signal generation circuit 331, the voltage signal line VGL, and the noise reduction circuit 340, is configured to control the noise reduction control signal.

[0079] In some embodiments, such as Figure 1 As shown, the gate and drain of M4, corresponding to the signal generation circuit 331, are also connected together. To prevent electrostatic damage to the signal generation circuit 331, the power supply terminal VDD can be divided into two lines: a first power supply terminal VDD1 and a second power supply terminal VDD2. The configuration of these two power supply terminals is similar to that of the aforementioned first start frame signal line STV1 and second start frame signal line STV2; they both originate from the same control IC, but are led out from two pins of that IC, and the two lines are arranged in parallel on the same or different layers. Furthermore, the first power supply terminal VDD1 and the second power supply terminal VDD2 can be either DC power supplies or AC power supplies.

[0080] Furthermore, for the signal generation circuit 331, such as Figure 4 or Figure 5 As shown, in some embodiments, the signal generation circuit 331 may include: a fourth transistor M4, whose control terminal is connected to the first power supply terminal VDD1, its first terminal is connected to the second power supply terminal VDD2, and its second terminal is connected to the noise reduction circuit 340.

[0081] Subsequently, the noise reduction control signal generated by the signal generation circuit 331 needs further control. Therefore, in some embodiments, such as... Figure 4 or Figure 5 As shown, the first control circuit 332 may include: a fifth transistor M5, whose control electrode is connected to the second output signal line C(nx), its first electrode is connected to the voltage signal line VGL, and its second electrode is connected to the second electrode of the fourth transistor M4; and a sixth transistor M6, whose control electrode is connected to the first node PU, its first electrode is connected to the voltage signal line, and its second electrode is connected to the second electrode of the fourth transistor M4. As with the aforementioned case, the control electrode of the fifth transistor M5 can be connected to either STV1 or STV2 for the gate drive circuit within the first preset row.

[0082] like Figure 3As shown, the noise reduction circuit 340 is connected to the drive output circuit 320, the noise reduction signal circuit 330 and the voltage signal line VGL, and is configured to reduce noise on the control signal and the output signal according to the noise reduction control signal.

[0083] In some embodiments, such as Figure 4 or Figure 5 As shown, to achieve noise reduction for the first node PU, the noise reduction circuit 340 may include: a seventh transistor M7, whose control electrode is connected to the second electrode of the fourth transistor M4, its first electrode is connected to the voltage signal line VGL, and its second electrode is connected to the first node PU. Next, to achieve noise reduction for the output signal of the fifth output signal line Cn, the noise reduction circuit 340 may include: an eighth transistor M8, whose control electrode is connected to the second electrode of the fourth transistor M4, its first electrode is connected to the voltage signal line VGL, and its second electrode is connected to the fifth output signal line Cn. Similarly, to achieve noise reduction for the output signal of the sixth output signal line Gn, the noise reduction circuit 340 may include: a ninth transistor M9, whose control electrode is connected to the second electrode of the fourth transistor M4, its first electrode is connected to the voltage signal line VGL, and its second electrode is connected to the sixth output signal line Gn.

[0084] Subsequently, in some embodiments, the gate drive circuit may further include a first reset circuit 350. For example... Figure 3 As shown, the first reset circuit 350, connected to the voltage signal line VGL, the first node PU, and the global reset signal line TRST, is configured to perform an initial reset of the circuit. Specifically, as... Figure 4 or Figure 5 As shown, the first reset circuit 350 may include: a tenth transistor M10, whose control electrode is connected to the global reset signal line TRST, its first electrode is connected to the voltage signal line VGL, and its second electrode is connected to the first node PU.

[0085] In this embodiment, the main function of the first reset circuit 350, namely the tenth transistor M10, is to reset the potential of each node of the entire gate drive circuit at the beginning of each cycle or each frame, which is equivalent to an initialization function.

[0086] In some embodiments, such as Figure 3 As shown, the gate drive circuit may further include a second reset circuit 360, connected to the voltage signal line VGL, the drive output circuit 320, and the third output signal line G(n+x), and configured to reset the output signal; wherein, the third output signal line G(n+x) is an output signal line of the drive output circuit of another gate drive circuit in the second set row. Specifically, as... Figure 4 or Figure 5 As shown, the second reset circuit 360 may include: an eleventh transistor M11, whose control terminal is connected to the third output signal line G(n+x), whose first terminal is connected to the voltage signal line VGL, and whose second terminal is connected to the sixth output signal line Gn.

[0087] Similar to the first output signal line G(nx) and the second output signal line C(nx), the second setting row for the third output signal line G(n+x) is the row in the next group corresponding to the row where the current gate driving circuit is located. For example, in an embodiment where 4 rows are grouped together, the third output signal line is G(n+4). The second reset circuit 360 or the eleventh transistor M11 mainly functions to reset and initialize the voltage signal output terminal of the current gate driving circuit, i.e., the sixth output signal line Gn.

[0088] In some embodiments, such as Figure 3 As shown, the gate drive circuit may further include a second control circuit 370, connected to the voltage signal line VGL, the first node PU, and the fourth output signal line C(n+x), and configured to control the potential of the first node PU; wherein, the fourth output signal line C(n+x) is another output signal line of the drive output circuit of another gate drive circuit in the second set row. Specifically, as... Figure 4 or Figure 5 As shown, the second control circuit 370 may include: a twelfth transistor M12, whose control electrode is connected to the fourth output signal line C(n+x), whose first electrode is connected to the voltage signal line VGL, and whose second electrode is connected to the first node PU.

[0089] Here, the fourth output signal line C(n+x) is configured similarly to the third output signal line G(n+x).

[0090] Subsequently, for the third output signal line G(n+x) and the fourth output signal line C(n+x), similar to the first output signal line G(nx) and the second output signal line C(nx), the gate drive circuits generally appear in groups. Therefore, for the gate drive circuits in the last group, for example, in a scenario where four rows form a group, the gate drive circuits in the last four rows do not actually have the third output signal line G(n+x) and the fourth output signal line C(n+x). To provide signals to the gate drive circuits in these rows, in some embodiments, the control electrode of the eleventh transistor M11 in the last preset row can be connected to the global reset signal line TRST; the control electrode of the twelfth transistor M12 can also be connected to the global reset signal line TRST. That is, in some embodiments, such as... Figure 4 or Figure 5As shown, when the gate driving circuit is a gate driving circuit within the second preset row of the gate driving circuit set, the control electrode of the eleventh transistor M11 is connected to the global reset signal line TRST; the control electrode of the twelfth transistor M12 is also connected to the global reset signal line TRST. The second preset row is determined based on the grouping of the gate driving circuit set in a specific application scenario. For example, if there are 4 rows as a group, then the second preset row is the last 4 rows; if there are 5 rows as a group, then the second preset row is the last 5 rows.

[0091] Finally, in some embodiments, such as Figure 4 or Figure 5 As shown, the gate driving circuit further includes a storage capacitor C, the first end of which is connected to the first node PU, and the second end of which is connected to the sixth output signal line Gn.

[0092] Then, in specific application scenarios, such as Figure 6 The diagram shown is a layout design schematic of the first transistor M1 and the fourth transistor M4 in this embodiment; as shown... Figure 7 As shown, Figure 6 A schematic diagram of the cross-sectional structure along lines AA' and BB'. Among them, in... Figure 6 The example shown is a scenario where the control electrode of the first transistor M1 is connected to the first output signal line G(nx), and the first electrode is connected to the second output signal line C(nx). Meanwhile, in... Figure 7 In this diagram, GE represents the gate metal layer, SD represents the source / drain metal layer, ACT represents the active layer, GI represents the gate insulating layer, buffer represents the buffer layer, ILD represents the interlayer insulating layer, and LS represents the light-shielding layer. Figure 6 , Figure 7 It can be seen that on the array glass substrate, the first start frame signal line STV1 and the second start frame signal line STV2 are not connected, and the first output signal line G(nx) and the second output signal line C(nx) are not connected. Furthermore, combined with... Figure 8 and Figure 9 ,in, Figure 8 This is a schematic diagram of the waveforms of each signal line when VDD is DC. Figure 9The diagram shows the waveforms of each signal line when VDD is AC. It can be seen that when no power is applied, the first transistor M1 is a transistor TFT. Subsequently, since the waveforms of the first start frame signal line STV1 and the second start frame signal line STV2 are the same, and the waveforms of the first output signal line G(nx) and the second output signal line C(nx) are the same, when power is applied, the first transistor M1 can be equivalent to a diode TFT, thus not affecting the corresponding function. Next, the control electrode of the fourth transistor M4 is connected to the first power supply terminal VDD1, and the first electrode is connected to the second power supply terminal VDD2. On the array glass substrate, the first power supply terminal VDD1 and the second power supply terminal VDD2 are not connected, so when no power is applied, the fourth transistor M4 is a transistor TFT. Subsequently, since the waveforms of the first power supply terminal VDD1 and the second power supply terminal VDD2 are the same, both of which can be DC signals VGH or AC signals, when power is applied, the fourth transistor M4 can be equivalent to a diode TFT, thus not affecting the corresponding function.

[0093] Finally, it should be noted that transistors can be classified into N-type and P-type according to their characteristics. P-type transistors conduct when the gate is low and are cut off when the gate is high; N-type transistors conduct when the gate is high and are cut off when the gate is low.

[0094] In this document, transistors are described using N-type transistors as an example. That is, in the above embodiments, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are all N-type transistors. This is a preferred embodiment for ease of implementation and does not limit the technical solution of the present invention. Those skilled in the art should understand that simply changing the type of each transistor (N-type or P-type) and changing the polarity of the output voltage of each power supply terminal and control signal line to achieve the same conduction or cutoff operation as in this embodiment is within the scope of protection of this application. Specific examples are not provided here.

[0095] As can be seen from the above description, the gate driving circuit provided in this application includes: a startup signal circuit, a drive output circuit, a noise reduction signal circuit, a noise reduction circuit, a first reset circuit, and a second reset circuit; the startup signal circuit is connected to the first output signal line and the second output signal line, and is connected to the drive output circuit through a first node; the drive output circuit is connected to the clock signal line and the startup signal circuit; the noise reduction signal circuit is connected to the noise reduction circuit, the voltage signal line, the power supply terminal, the second output signal line, and the first node; the noise reduction circuit is connected to the drive output circuit, the noise reduction signal circuit, and the voltage signal line; the first reset circuit is connected to the voltage signal line, the first node, and the global reset signal line; the second reset circuit is connected to the voltage signal line, the drive output circuit, and the third output signal line. This application transforms a single output signal line originally connected to the start signal circuit into two completely independent output signal lines with essentially the same signal. This allows the relevant TFTs in the start signal circuit to function as transistor TFTs when not powered on, effectively preventing static electricity. When powered on, since the two output signal lines have essentially the same signal, they can still be considered as the original diode TFTs. This method eliminates the generation of static electricity, prevents the TFTs from being turned on, and avoids damage to the circuit.

[0096] Based on the same concept, this application also provides a display panel, including the gate driving circuit as described in any of the foregoing embodiments.

[0097] The display panel of the above embodiments is used to apply the corresponding gate driving circuit in the foregoing embodiments, and the beneficial effects of the embodiments with the corresponding gate driving circuit will not be repeated here.

[0098] Meanwhile, the display panel can also be applied to the display device provided in the embodiments of this application, so that the corresponding display device has the same or similar beneficial effects as the corresponding gate driving circuit embodiments, which will not be described again here.

[0099] Understandably, in specific applications, the display device is a product with image display capabilities, and it is generally driven by multiple driving circuits. Examples include: monitors, televisions, billboards, digital photo frames, laser printers with display capabilities, telephones, mobile phones, tablets, watches, personal digital assistants (PDAs), digital cameras, portable camcorders, viewfinders, navigators, vehicles, large-area walls, home appliances, and information query devices (such as e-government, banking, hospital, and power sector business query devices, monitors, etc.).

[0100] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0101] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this disclosure, the provided drawings may or may not show well-known power / ground connections to integrated circuit (IC) chips and other components. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this disclosure, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this disclosure will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuitry) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that the embodiments of this disclosure may be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0102] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0103] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A gate drive circuit characterized by comprising: The gate drive circuit is one of any row in a set of array-arranged gate drive circuits, and the gate drive circuit comprises a start signal circuit, a drive output circuit, a noise reduction signal circuit, a noise reduction circuit, a first reset circuit and a second reset circuit; The start signal circuit is connected with a first output signal line and a second output signal line, and is connected with the drive output circuit through a first node, and is configured to provide a control signal for the drive output circuit; wherein the first output signal line and the second output signal line are two output signal lines of the drive output circuit of another gate drive circuit of a first set row; The drive output circuit is connected with a clock signal line and the start signal circuit, and is configured to receive the control signal, generate an output signal, and output the output signal through a corresponding output signal line; The noise reduction signal circuit is connected with the noise reduction circuit, a voltage signal line, a power supply end, the second output signal line and the first node, and is configured to generate and output a noise reduction control signal of the noise reduction circuit; The noise reduction circuit is connected with the drive output circuit, the noise reduction signal circuit and the voltage signal line, and is configured to reduce noise of the control signal and the output signal according to the noise reduction control signal; The first reset circuit is connected with the voltage signal line, the first node and a global reset signal line, and is configured to perform initial reset of the circuit; The second reset circuit is connected with the voltage signal line, the drive output circuit and a third output signal line, and is configured to reset the output signal; wherein the third output signal line is one output signal line of the drive output circuit of another gate drive circuit of a second set row.

2. The gate drive circuit according to claim 1, characterized by The start signal circuit comprises: A first transistor, whose control electrode is connected with the first output signal line, whose first electrode is connected with the second output signal line, and whose second electrode is connected with the first node.

3. The gate drive circuit according to claim 1, characterized by The start signal circuit comprises: A first transistor, whose control electrode is connected with the second output signal line, whose first electrode is connected with the first output signal line, and whose second electrode is connected with the first node.

4. The gate drive circuit according to claim 2 or 3, characterized in that, When the gate drive circuit is a gate drive circuit in a first preset row in the set of gate drive circuits, the first transistor, whose control electrode is connected with a first start frame signal line, whose first electrode is connected with a second start frame signal line, and whose second electrode is connected with the first node.

5. The gate drive circuit according to claim 1, characterized by The drive output circuit comprises: A second transistor, whose control electrode is connected with the first node, whose first electrode is connected with the clock signal line, and whose second electrode is connected with a fifth output signal line; A third transistor, whose control electrode is connected with the first node, whose first electrode is connected with the clock signal line, and whose second electrode is connected with a sixth output signal line.

6. The gate drive circuit according to claim 5, characterized by The noise reduction signal circuit comprises a signal generation circuit and a first control circuit; The signal generation circuit is connected with a power supply end and the first control circuit, and is configured to generate the noise reduction control signal; The first control circuit is connected with the signal generation circuit, the voltage signal line and the noise reduction circuit, and is configured to control the noise reduction control signal.

7. The gate drive circuit according to claim 6, characterized by The signal generation circuit includes: A fourth transistor, whose control electrode is connected with the first power supply end, whose first electrode is connected with the second power supply end, and whose second electrode is connected with the noise reduction circuit.

8. The gate drive circuit according to claim 7, characterized by The first control circuit includes: A fifth transistor, whose control electrode is connected with the second output signal line, whose first electrode is connected with the voltage signal line, and whose second electrode is connected with the second electrode of the fourth transistor; A sixth transistor, whose control electrode is connected with the first node, whose first electrode is connected with the voltage signal line, and whose second electrode is connected with the second electrode of the fourth transistor.

9. The gate drive circuit according to claim 7, characterized by The noise reduction circuit includes: A seventh transistor, whose control electrode is connected with the second electrode of the fourth transistor, whose first electrode is connected with the voltage signal line, and whose second electrode is connected with the first node; An eighth transistor, whose control electrode is connected with the second electrode of the fourth transistor, whose first electrode is connected with the voltage signal line, and whose second electrode is connected with the fifth output signal line; A ninth transistor, whose control electrode is connected with the second electrode of the fourth transistor, whose first electrode is connected with the voltage signal line, and whose second electrode is connected with the sixth output signal line.

10. The gate drive circuit according to claim 1, characterized by The first reset circuit includes: A tenth transistor, whose control electrode is connected with the global reset signal line, whose first electrode is connected with the voltage signal line, and whose second electrode is connected with the first node.

11. The gate drive circuit according to claim 5, characterized by The second reset circuit includes: An eleventh transistor, whose control electrode is connected with the third output signal line, whose first electrode is connected with the voltage signal line, and whose second electrode is connected with the sixth output signal line.

12. The gate drive circuit according to claim 1, characterized by Further includes: A second control circuit, connected with the voltage signal line, the first node and a fourth output signal line, and configured to control the potential of the first node; wherein the fourth output signal line is another output signal line of a driving output circuit of another gate drive circuit of a second set row.

13. The gate drive circuit according to claim 12, characterized by The second control circuit includes: A twelfth transistor, whose control electrode is connected with the fourth output signal line, whose first electrode is connected with the voltage signal line, and whose second electrode is connected with the first node.

14. The gate drive circuit of claim 11, wherein, When the gate drive circuit is a gate drive circuit in a second preset row in the set of gate drive circuits, the eleventh transistor has its control electrode connected with the global reset signal line.

15. The gate drive circuit of claim 13, wherein, When the gate drive circuit is a gate drive circuit in a second preset row in the set of gate drive circuits, the twelfth transistor has its control electrode connected with the global reset signal line.

16. The gate drive circuit according to claim 5, wherein The gate drive circuit further includes: A storage capacitor, whose first end is connected with the first node, and whose second end is connected with the sixth output signal line.

17. A display panel, characterized by A display panel including the gate drive circuit according to any one of claims 1 to 16.

18. A display device comprising: A display panel including the gate drive circuit according to claim 17.

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