Semiconductor device and method of manufacturing the same

Abstract

Disclosed are semiconductor devices and methods of making the same. The semiconductor devices include a substrate, a shallow trench isolation, and a plurality of bit line structures. The substrate includes a plurality of active regions. The shallow trench isolation is disposed in the substrate and includes a first insulating layer higher than a surface of the substrate and a second insulating layer lower than the surface of the substrate. The bit line structures are disposed on the substrate and include at least a conductive layer. At least one of the bit line structures spans the active regions and the first and second insulating layers of the shallow trench isolation and has a first insulating stack, a second insulating stack, and a third insulating stack, respectively. The first, second, and third insulating stacks include top surfaces coplanar with each other and different stack materials. As such, the component performance of the bit line structures is improved, thereby optimizing the operational performance of the semiconductor devices.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device with a bit line structure and a method of fabricating the same. BACKGROUND

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, because it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally, dynamic random access memory with a recessed gate structure is formed by a large number of memory cells gathered to form an array region for storing information, and each memory cell can be composed of a transistor component and a capacitor component in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product demand, the density of memory cells in the array region must continue to increase, resulting in increasing difficulty and complexity of related manufacturing processes and designs. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of the related memory device. SUMMARY

[0003] One purpose of the present application is to provide a semiconductor device, by providing an insulating stack structure with different stack materials and the same top surface on the conductive layer of the bit line structure, so that the bit line structure can achieve different insulation effects in the corresponding extension area. Thus, the semiconductor device of the present application has a more optimized component structure and performance, thereby improving the operation performance of the semiconductor device.

[0004] One purpose of the present application is to provide a method of fabricating a semiconductor device, by forming an insulating stack structure with different stack materials and the same top surface on the conductive layer of the bit line structure that simultaneously extends over the active region and the shallow trench isolation, so that the bit line structure can achieve different insulation effects in the corresponding extension area. Thus, the method of the present application can form a semiconductor device with a more optimized structure and performance.

[0005] To achieve the above objectives, one embodiment of this application provides a semiconductor device including a substrate, a shallow trench isolation layer, and a plurality of bit line structures. The substrate includes a plurality of active regions. The shallow trench isolation layer is disposed in the substrate and includes a first insulating layer above the surface of the substrate and a second insulating layer below the surface of the substrate, the second insulating layer being located on the first insulating layer. The bit line structures are disposed on the substrate, extending in a first direction and arranged in a second direction perpendicular to the first direction, each bit line structure including at least a conductive layer disposed on the substrate. At least one bit line structure spans the active regions and the first and second insulating layers of the shallow trench isolation layer in the first direction. The at least one bit line structure has a first insulating stack structure, a second insulating stack structure, and a third insulating stack structure respectively on the active regions and the first and second insulating layers of the shallow trench isolation layer. The first, second, and third insulating stack structures include top surfaces on the same horizontal plane and different stacking materials.

[0006] To achieve the above objectives, another embodiment of this application provides a method for fabricating a semiconductor device, comprising the following steps: A substrate is provided, the substrate including a plurality of active regions. A shallow trench isolation is formed in the substrate, the shallow trench isolation including a first insulating layer above the surface of the substrate and a second insulating layer below the surface of the substrate, the second insulating layer being located on the first insulating layer. A plurality of bit line structures are formed on the substrate, the bit line structures extending in a first direction and arranged in a second direction perpendicular to the first direction, each bit line structure including at least a conductive layer disposed on the substrate. At least one bit line structure traverses the active regions, and the first and second insulating layers of the shallow trench isolation in the first direction. The at least one bit line structure has a first insulating stack structure, a second insulating stack structure, and a third insulating stack structure respectively on the active regions, and the first and second insulating layers of the shallow trench isolation. The first, second, and third insulating stack structures include top surfaces on the same horizontal plane and different stacking materials.

[0007] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor devices and their manufacturing methods provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description

[0008] The accompanying drawings provide a more in-depth understanding of embodiments of this application and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams and are for illustrative and drawing convenience, and relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figure 1 A top view schematic diagram of a semiconductor device provided in an embodiment of this application;

[0010] Figure 2 for Figure 1 A schematic diagram of cross-sections taken along section lines A-A' and B-B';

[0011] Figure 3 for Figure 1 A schematic diagram of a cross-section taken along section line C-C';

[0012] Figure 4 for Figure 1 A schematic diagram of a cross-section taken along section line D-D';

[0013] Figure 5 for Figure 1 A schematic diagram of a cross-section taken along section line E-E';

[0014] Figure 6 A cross-sectional schematic diagram of the semiconductor device fabrication method provided in the embodiments of this application after the formation of the spacer wall layer;

[0015] Figure 7 A cross-sectional view of the method for fabricating a semiconductor device according to an embodiment of this application after forming the first cover material layer;

[0016] Figure 8 A cross-sectional schematic diagram of the method for fabricating a semiconductor device provided in the embodiments of this application after performing a first planarization process;

[0017] Figure 9 This is a cross-sectional view of the semiconductor device fabrication method provided in this application embodiment after the formation of the second cover material layer.

[0018] The reference numerals in the attached figures are explained as follows:

[0019] 10 Semiconductor Devices

[0020] 100 substrate

[0021] 100A Unit Area

[0022] 100B Surrounding Area

[0023] 100s surface

[0024] 102 Shallow Trench Isolation

[0025] 104 Third Insulation Layer

[0026] 104t top surface

[0027] 106 First Insulation Layer

[0028] 106t top surface

[0029] 108 Second Insulation Layer

[0030] 108t top surface

[0031] 110 active area

[0032] 114 insulation layer

[0033] 116 semiconductor layer

[0034] 118 metal layer

[0035] 120 conductive layer

[0036] 122 First cap layer

[0037] 124 gap wall layer

[0038] 126 barrier layers

[0039] 128 oxide layer

[0040] 130 Second cap layer

[0041] 140-bit line structure

[0042] 140c bit line plug

[0043] 140t top surface

[0044] 142 Second Insulation Stack Structure

[0045] 144 Third Insulation Stack Structure

[0046] 146 Fourth Insulation Stack Structure

[0047] 148 First Insulating Stack Structure

[0048] 214 gate dielectric layer

[0049] 216 doped region

[0050] 220 conductive layer

[0051] 222 cap layer

[0052] 224 gap wall layer

[0053] 226 First Covering Layer

[0054] 228 Second Covering Layer

[0055] 230 Third Covering Layer

[0056] 230t flat top surface

[0057] 240 gate structure

[0058] 326 barrier material layer

[0059] 328 oxide material layer

[0060] 330 Second Covering Material Layer

[0061] t1, t2, t3, t4, t5 Top surface

[0062] t4 Top surface

[0063] t5 concave top surface Detailed Implementation

[0064] To enable those skilled in the art to further understand this application, preferred embodiments of the application are described below, along with accompanying drawings, to explain in detail the composition and desired effects of the application. It should be understood that the following embodiments can be modified by substituting, recombining, or mixing features from several different embodiments to achieve other embodiments without departing from the spirit of this application.

[0065] Please refer to Figure 1 and Figure 5 As shown, the illustration is a schematic diagram of the semiconductor device 10 according to the first embodiment of this application. First, as... Figure 1 and Figure 2As shown, the semiconductor device 10 includes a substrate 100, a shallow trench isolation 102, and a plurality of bit line structures 140. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, and the substrate 100 simultaneously includes a cell region 100A with a relatively high component density and a peripheral region 100B with a relatively low component density. The cell region 100A and the peripheral region 100B are, for example, adjacent to each other, but are not limited thereto. The shallow trench isolation 102 is further disposed within the substrate 100 to define a plurality of active regions 110 extending in the same direction D1 on the substrate 100. The shallow trench isolation 102 includes a composite structure, such as a third insulating layer 104, a first insulating layer 106, and a second insulating layer 108 sequentially disposed. The top surface 106t of the first insulating layer 106 is higher than the surface 100s of the substrate 100, and the top surfaces 104t and 108t of the third insulating layer 104 and the second insulating layer 108 are higher than the surface 100s of the substrate 100, but this is not a limitation. A bitline structure 140 is disposed on the substrate 100, and includes a conductive layer 120 and an insulating stack structure sequentially disposed on the substrate 100. The conductive layer 120 of each bit line structure 140 extends within the cell region 100A along the first direction D2 and is arranged parallel to each other in the second direction D3 perpendicular to the first direction D2, and can simultaneously span the active region 110 and the shallow trench isolation 102 of the substrate 100. Thus, those skilled in the art can easily understand the bit line structure 140 as a strip structure extending in the first direction D2 and arranged in the second direction D3, while in this embodiment... Figure 1 To clearly show the strip structure, the illustration of the insulating stacked layers (such as the second cover layer 130, the second cover layer 228, etc.) set above are omitted.

[0066] It should be noted that, for example, Figure 1 and Figure 2As shown, each bit line structure 140 simultaneously spans the active region 110 and the shallow trench isolation 102 of the substrate 100, such that the conductive layer 120 and its above insulating stack conformally cover the third insulating layer 104, the first insulating layer 106, and the second insulating layer 108 of the active region 110 and the shallow trench isolation 102. The portions of the bit line structure 140 on the active region 110 and the first insulating layer 106 and the second insulating layer 108 of the shallow trench isolation 102 have different insulating stack structures. Specifically, the portion of the bit line structure 140 on the active region 110 has a first insulating stack structure 148, the portion of the bit line structure 140 on the first insulating layer 106 has a second insulating stack structure 142, and the portion of the bit line structure 140 on the second insulating layer 108 has a third insulating stack structure 144. Figure 2 As shown, the top surfaces of the first insulating stack structure 148, the second insulating stack structure 142, and the third insulating stack structure 144 are located on the same plane 140t, and include different numbers of stacked layers and stacked materials. Therefore, by providing different first insulating stack structures 148, second insulating stack structures 142, and third insulating stack structures 144 on the conductive layer 120, the bit line structure 140 achieves different insulation effects in the corresponding extended regions. Thus, the semiconductor device of this application can have a more optimized component structure and performance, thereby improving the operational performance of the semiconductor device.

[0067] like Figure 2 and Figure 3 As shown, the conductive layer 120 further includes, from bottom to top, a semiconductor layer 116 (e.g., including doped polycrystalline silicon, doped amorphous silicon, or other semiconductor materials), a barrier layer (not shown, e.g., including titanium and / or titanium nitride, tantalum and / or tantalum oxide, or other conductive and resistive barrier materials), and a metal layer 118 (e.g., including tungsten, aluminum, or copper, or other low-resistance metal materials) disposed on the substrate 100. Each bit line structure 140 is, in principle, located on an insulating layer 114 (e.g., including sequentially stacked oxide-nitride-oxide structures) disposed above the substrate 100, while a portion of the semiconductor layer 116 extends into the substrate 100 to form a bit line contact (BLC) 140c, allowing each bit line structure 140 to be electrically connected to the active region 112 via the integrally formed bit line contact 140c.

[0068] Specifically, the first insulating stack structure 148 located on the active region 110 includes a first capping layer 122, a barrier layer 126, and a second capping layer 130 sequentially disposed on the conductive layer 120 from bottom to top, wherein the first capping layer 122, the barrier layer 126, and the second capping layer 130 are in physical contact with each other. In one embodiment, the first capping layer 122, the barrier layer 126, and the second capping layer 130 respectively comprise insulating materials such as silicon nitride, silicon carbonitride, or silicon oxynitride, or combinations thereof, and the first capping layer 122, the barrier layer 126, and the second capping layer 130 preferably comprise different insulating materials, but are not limited thereto. On the other hand, the third insulating stack structure 144 located on the second insulating layer 108 includes a first capping layer 122, a barrier layer 126, an oxide layer 128, and a second capping layer 130 sequentially disposed on the conductive layer 120 from bottom to top. In other words, an oxide layer 128 is additionally disposed between the barrier layer 126 and the second capping layer 130 in the third insulating stack structure 144. The oxide layer 128 includes insulating materials such as silicon oxide and physically contacts the upper second capping layer 130 and the lower barrier layer 126.

[0069] like Figure 2 and Figure 4 As shown, the second insulating stack structure 142 located on the first insulating layer 106 includes, for example, a first capping layer 122 and a second capping layer 130 sequentially disposed on the conductive layer 120 from bottom to top. That is, no barrier layer 126 is disposed between the first capping layer 122 and the second capping layer 130 in the second insulating stack structure 142, and they are in physical contact with each other. The top surface t1 of the first capping layer 122 in the first insulating stack structure 148 is higher than the top surface t3 of the first capping layer 122 in the third insulating stack structure 144, and lower than the top surface t2 of the first capping layer 122 in the second insulating stack structure 142, but is not limited thereto.

[0070] like Figure 2 and Figure 5As shown, each bit line structure 140 also has a fourth insulating stack structure 146 at its end. Depending on the extension area of ​​each bit line structure 140, the fourth insulating stack structure 146 can be selectively disposed on the active region 110 and / or the shallow trench isolation 102, and includes different stacked layers. Its top surface is also on the same plane 140t as the top surfaces of the first insulating stack structure 148, the second insulating stack structure 142, and the third insulating stack structure 144. Specifically, when the end of the bit line structure 140 spans the active region 110, the fourth insulating stack structure 146 includes a spacer layer 124, a barrier layer 126, and a second capping layer 130 sequentially disposed from bottom to top on the conductive layer 120. Furthermore, the spacer layer 124 in the fourth insulating stack structure 146 has a relatively high top surface t4. On the other hand, when the end of the bit line structure 140 spans the shallow trench isolation 102, the fourth insulating stack structure 146 includes a spacer layer 124, a barrier layer 126, an oxide layer 128, and a second capping layer 130 sequentially disposed on the conductive layer 120 from bottom to top. The spacer layer 124 in the fourth insulating stack structure 146 has a relatively low recessed top surface t5, but is not limited thereto. In one embodiment, the spacer layer 124 may include insulating materials such as silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride, preferably including insulating materials different from the barrier layer 126, but is not limited thereto. In another embodiment, the spacer layer 124 may also selectively include a composite layer structure, such as a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer sequentially disposed on the sidewalls of each bit line structure 140, but is not limited thereto.

[0071] For example Figure 1 and Figure 2As shown, the semiconductor device 10 also includes a gate structure 240 disposed on the substrate 100. Specifically, the gate structure 240 extends within the peripheral region 100B along a second direction D3 and is arranged along a first direction D2, and can simultaneously span the active region 110 and the shallow trench isolation 102 of the substrate 100. Each gate structure 240 includes, in detail, a gate dielectric layer 214, a conductive layer 220, a capping layer 222, and a spacer layer 224 disposed sequentially on the sidewalls of the gate dielectric layer 214, the conductive layer 220, and the capping layer 222. The conductive layer 220 of the gate structure 240 also includes, from bottom to top, a semiconductor layer 116 (e.g., doped polycrystalline silicon, doped amorphous silicon, or other semiconductor materials), a barrier layer (not shown, e.g., titanium and / or titanium nitride, tantalum and / or tantalum oxide, or other conductive and resistive barrier materials), and a metal layer 118 (e.g., tungsten, aluminum, or copper, or other low-resistance metal materials). In a preferred embodiment, the conductive layer 220 of the gate structure 240 may include, for example, the same material as the conductive layer 120 in the bit line structure 140, the capping layer 222 of the gate structure 240 may include, for example, the same material as the first capping layer 122 in the bit line structure 140, and the spacer layer 224 of the gate structure 240 may include, for example, the same material as the spacer layer 124 in the bit line structure 140, but is not limited thereto.

[0072] Furthermore, a first cover layer 226, a second cover layer 228, and a third cover layer 230 are sequentially disposed above the gate structure 240. The first cover layer 226 conformally covers the spacer wall layer 224, the gate structure 240, and the substrate 100. The second cover layer 228 covers the first cover layer 226 and is flush with the first cover layer 226 disposed directly above the gate structure 240. The third cover layer 230 integrally covers the second cover layer 228 and the first cover layer 226 and has a flat top surface 230t. Preferably, the flat top surface 230t of the third cover layer 230 in the peripheral region 100B is flush with the top surfaces (i.e., planes 140t) of the first insulating stack structure 148, the second insulating stack structure 142, the third insulating stack structure 144, and the fourth insulating stack structure 146 in the unit region 100A, but is not limited thereto. In one embodiment, the first cover layer 226, the second cover layer 228, and the third cover layer 230 each contain different insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride. The first cover layer 226 in the peripheral region 100B contains, for example, the same material as the barrier layer 126 in the unit region 100A. The second cover layer 228 in the peripheral region 100B contains, for example, the same material as the oxide layer 128 in the unit region 100A. The third cover layer 230 in the peripheral region 100B contains, for example, the same material as the second capping layer 130 in the unit region 100A, but is not limited thereto.

[0073] In this configuration, the gate structure 240 located in the peripheral region 100B and the doped regions 216 in the substrates 100 on both sides together form a transistor assembly. The bit line structure 140 located in the cell region 100A, together with another transistor assembly (not shown), a capacitor (not shown), and a word line structure also located in the cell region 100A, forms a dynamic random access memory (DRAM). Voltage information from the substrate 100 is received through the bit line structure 140 and the word line structure. Furthermore, since the bit line structure 140 has different insulating stacking structures in different extension regions, different insulation effects can be achieved in the corresponding extension regions, thereby improving the operational performance of the DRAM.

[0074] According to the semiconductor device of this embodiment, an insulating stacked structure with a flush top surface and including different stacked layers and stacked materials is provided on the conductive layer of the bit line structure. This allows the bit line structure to have different insulating stacked structures in different regions, thereby achieving different insulation effects in the corresponding extended regions. Therefore, the semiconductor device of this embodiment has a more optimized component structure and performance, thereby improving the operational performance of the semiconductor device.

[0075] In order to enable those skilled in the art to easily understand the semiconductor device 10 of this application, the manufacturing method of the semiconductor device 10 of this application will be further described below.

[0076] Please see Figures 6 to 9 The diagram shown illustrates a method for fabricating the semiconductor device 10 in a preferred embodiment of this application. First, as... Figure 6 As shown, a substrate 100 is provided, and shallow trench isolation 102 is formed in the cell region 100A and the peripheral region 100B of the substrate 100, while an active region 110 is defined simultaneously. In one embodiment, the shallow trench isolation 102 is formed, for example, by first forming a plurality of trenches (not shown) in the substrate 100 using an etching process, and then sequentially forming a third insulating layer 104, a first insulating layer 106, and a second insulating layer 108 in the trenches. The top surface 106t of the first insulating layer 106 is higher than the surface 100s of the substrate 100, and the top surfaces 104t and 108t of the third insulating layer 104 and the second insulating layer 108 are higher than the surface 100s of the substrate 100, but this is not a limitation.

[0077] Next, an insulating layer 114 is formed on the substrate 100, conformally covering the third insulating layer 104, the first insulating layer 106, and the second insulating layer 108 of the active region 110 and the shallow trench isolation 102. Then, after removing the insulating layer 114 in the peripheral region 100B, a conductive layer 120 and a first capping layer 122 of the bit line structure 140 are formed in the cell region 100A, and a gate structure 240 is formed in the peripheral region 100B. In one embodiment, the formation of the gate structure 240 may be integrated into the fabrication process of the conductive layer 120 and the first capping layer 122, for example, including but not limited to the following steps. First, multiple openings penetrating the insulating layer 114 are formed in cell region 100A through a mask layer (not shown). Then, chemical vapor deposition (CVD) is performed simultaneously in cell region 100A and peripheral region 100B to form a semiconductor material layer (not shown, such as doped silicon, doped phosphorus, or silicon-phosphorus semiconductor materials) that fills the openings and integrally covers the substrate 100. Then, barrier material layer (not shown, such as tantalum and / or tantalum nitride, titanium and / or titanium nitride conductive barrier materials), metal material layer (not shown, such as low-resistivity metal materials such as aluminum, titanium, copper, or tungsten), and first cover material layer (not shown, such as insulating materials such as silicon nitride, silicon carbonitride, or silicon oxynitride) are deposited sequentially to integrally cover the substrate 100. It should be noted that, due to the uneven height of the top surfaces of the third insulating layer 104, the first insulating layer 106, and the second insulating layer 108 of the shallow trench isolation 102, the first cover material layer, the metal material layer, the barrier material layer, the semiconductor material layer, and the insulating layer 114 formed thereon have correspondingly different contours, such as... Figure 6 As shown.

[0078] Then, at least one photolithography process is performed to pattern the first cover material layer and the underlying stacked conductive material layers (including metal material layers, barrier material layers, and metal material layers). A conductive layer 120 extending along the first direction D2 and a first capping layer 122 thereon are formed in the cell region 100A, and a gate structure 240 extending along the second direction D3 is formed in the peripheral region 100B. Thus, the conductive layer 220 and capping layer 222 of the gate structure 240 may preferably comprise the same material as the conductive layer 120 and first capping layer 122 of the bit line structure 140, but are not limited thereto. Then, using the same process, spacer walls 124 are formed on the sidewalls of the conductive layer 120 and first capping layer 122 of the bit line structure 140, and spacer walls 224 are formed on the sidewalls of the conductive layer 220 and capping layer 222 of the gate structure 240. In one embodiment, the formation of the spacer layer 224 can also be integrated into the fabrication process of the spacer layer 124 in the unit region 100A, so that the spacer layer 224 in the peripheral region 100B and the spacer layer 124 in the unit region 100A can include the same material, but is not limited thereto.

[0079] like Figure 7 As shown, a chemical vapor deposition process is simultaneously performed again within the unit region 100A and the peripheral region 100B to sequentially form a barrier material layer 326 and an oxide material layer 328. The barrier material layer 326 conformally covers the substrate 100 in the unit region 100A, the conductive layer 120 of the bit line structure 140, and the first capping layer 122, as well as the substrate 100 and the gate structure 240 in the peripheral region 100B, and also has varying contours. The oxide material layer 328 is integrally covered over the barrier material layer 326 and has a flat top surface. In one embodiment, the barrier material layer 326 may include insulating materials such as silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride, preferably including insulating materials different from those in the spacer layer 124 or spacer layer 224. The oxide material layer 328 may include insulating materials such as silicon oxide or silicon oxynitride, but is not limited thereto.

[0080] like Figure 8 As shown, a first planarization process is performed, partially removing the oxide material layer 328, and simultaneously forming an oxide layer 128 in the cell region 100A and a second capping layer 228 in the peripheral region 100B. It should be noted that during the first planarization process, the barrier material layer 326 located above the gate structure 240 in the peripheral region 100B serves as a stop layer. Furthermore, since the barrier material layer 326 in the cell region 100A has varying contours, during the first planarization process, the barrier material layer 326 and the portion of the first capping layer 122 below it in the cell region 100A are also removed, resulting in the formation of a barrier layer 126 in the cell region 100A and a first capping layer 226 in the peripheral region 100B. In other words, after the first planarization process, the barrier material layer 326 covering the first insulating layer 106 of the shallow trench isolation 102 in the cell region 100A is removed, directly exposing the underlying first capping layer 122.

[0081] like Figure 9 As shown, a chemical vapor deposition process is simultaneously performed again within the unit region 100A and the peripheral region 100B to form a second cover material layer 330. This layer entirely covers the barrier layer 126 and oxide layer 128 within the unit region 100A and the second cover layer 228 within the peripheral region 100B, and has a flat top surface. In one embodiment, the second cover material layer 330 includes, for example, an insulating material such as silicon nitride, silicon carbonitride, or silicon oxynitride, or a combination of these insulating materials. Preferably, it includes an insulating material different from the oxide material layer 328, but is not limited thereto. Then, a second planarization process is performed to partially remove the second cover material layer 330 within the unit region 100A and the peripheral region 100B, thereby forming a layer such as... Figure 2The second cover layer 130 is shown, and a shape is formed within the peripheral region 100B as shown. Figure 2 The third capping layer 230 is shown. Thus, the first capping layer 122, the barrier layer 126, and the second capping layer 130, sequentially stacked on the conductive layer 120 above the active region 110 within the cell region 100A, are formed as shown. Figure 2 The first insulating stack structure 148 shown is formed by first capping layer 122 and second capping layer 130 sequentially stacked on conductive layer 120 above first insulating layer 106 of shallow trench isolation 102. Figure 2 The second insulating stack structure 142 shown is formed by the first capping layer 122, the barrier layer 126, the oxide layer 128, and the second capping layer 130 sequentially stacked on the conductive layer 120 above the second insulating layer 108 of the shallow trench isolation 102. Figure 2 The third insulating stack structure 144 is shown. Furthermore, the spacer layer 124, barrier layer 126, oxide layer 128, and second capping layer 130, sequentially stacked on the conductive layer 120 above the second insulating layer 108 of the shallow trench isolation 102, form the fourth insulating stack structure 146, located at the end of each bit line structure 140. Thus, the fabrication of the semiconductor device 10 in this embodiment is completed. With a simplified process, insulating stack structures with equal top surface height and different stacking materials can be formed above the conductive layer 120 of the bit line structure 140 to achieve different insulation effects in the corresponding extended regions.

[0082] According to the fabrication method of this embodiment, a shallow trench isolation layer with uneven top surface height is pre-formed before fabricating the conductive layer of the bitline structure. This results in the conductive layer spanning the active region and the shallow trench isolation layer having correspondingly varying contours. This operation allows for the formation of an insulating stack structure with equal top surface height and different stacking materials on the conductive layer spanning both the active region and the shallow trench isolation layer. This enables the bitline structure to achieve different insulation effects in its respective extended regions. Therefore, the fabrication method of this embodiment facilitates the formation of semiconductor devices with more optimized structure and performance.

[0083] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes multiple active regions; Shallow trench isolation is disposed in the substrate; the shallow trench isolation includes a first insulating layer above the surface of the substrate and a second insulating layer below the surface of the substrate, the second insulating layer being located on the first insulating layer; as well as Multiple bit line structures are disposed on the substrate. The bit line structures extend in a first direction and are arranged in a second direction perpendicular to the first direction. Each bit line structure includes at least a conductive layer disposed on the substrate. The conductive layer includes a semiconductor layer, a barrier layer and a metal layer disposed sequentially on the substrate from bottom to top. Wherein, at least one of the bit line structures spans the active region and the first and second insulating layers isolated by the shallow trench in the first direction. The at least one bit line structure has a first insulating stack structure, a second insulating stack structure, and a third insulating stack structure on the active region and the first and second insulating layers isolated by the shallow trench, respectively. The first insulating stack structure, the second insulating stack structure, and the third insulating stack structure include top surfaces that are on the same horizontal plane and different stacking materials.

2. The semiconductor device according to claim 1, characterized in that, The second insulating stack structure includes a first cap layer and a second cap layer that are physically in contact with each other and are sequentially disposed on the conductive layer from bottom to top. The third insulating stack structure includes a first cap layer, a barrier layer, an oxide layer and a second cap layer that are physically in contact with each other and are sequentially disposed on the conductive layer from bottom to top.

3. The semiconductor device according to claim 2, characterized in that, The top surface of the first cover layer of the second insulating stack structure is higher than the top surface of the first cover layer of the third insulating stack structure.

4. The semiconductor device according to claim 2, characterized in that, The first insulating stack structure includes a first capping layer, a barrier layer, and a second capping layer that are physically in contact with each other and are sequentially disposed on the conductive layer from bottom to top.

5. The semiconductor device according to claim 2, characterized in that, The top surface of the first cover layer of the first insulating stack structure is higher than the top surface of the first cover layer of the third insulating stack structure, and lower than the top surface of the first cover layer of the second insulating stack structure.

6. The semiconductor device according to claim 2, characterized in that, The shallow trench isolation further includes a third insulating layer, the top surface of which is lower than the surface of the substrate and the top surface of the first insulating layer, the top surface of which is higher than the top surface of the second insulating layer, and the first insulating layer is located on the third insulating layer.

7. The semiconductor device according to claim 6, characterized in that, At least one of the bit line structures further includes a fourth insulating stack structure disposed on the second insulating layer, wherein the fourth insulating stack structure includes a spacer wall layer, the barrier layer, the oxide layer and the second capping layer.

8. The semiconductor device according to claim 7, characterized in that, The top surface of the fourth insulating stack structure, the top surface of the first insulating stack structure, the top surface of the second insulating stack structure, and the top surface of the third insulating stack structure are located on the same plane.

9. The semiconductor device according to claim 7, characterized in that, Also includes: At least one gate structure is disposed on the substrate, and includes at least another conductive layer and another spacer layer, wherein the other conductive layer of the at least one gate structure and the conductive layer of the at least one bit line structure comprise the same conductive material; A first cover layer is disposed on the at least one gate structure; A second cover layer is disposed on the first cover layer; as well as A third overlay layer is disposed on the second overlay layer.

10. The semiconductor device according to claim 9, characterized in that, The first cover layer and the barrier layer are made of the same material, the second cover layer and the oxide layer are made of the same material, and the third cover layer and the second capping layer are made of the same material.

11. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising a plurality of active regions; Shallow trench isolation is formed in the substrate, the shallow trench isolation including a first insulating layer above the surface of the substrate and a second insulating layer below the surface of the substrate, the second insulating layer being located on the first insulating layer; as well as A plurality of bit line structures are formed on the substrate, the bit line structures extending in a first direction and arranged in a second direction perpendicular to the first direction, and each bit line structure includes at least a conductive layer disposed on the substrate; Wherein, at least one of the bit line structures spans the active region and the first and second insulating layers isolated by the shallow trench in the first direction. The at least one bit line structure has a first insulating stack structure, a second insulating stack structure, and a third insulating stack structure on the active region and the first and second insulating layers isolated by the shallow trench, respectively. The first insulating stack structure, the second insulating stack structure, and the third insulating stack structure include top surfaces that are on the same plane and different stacking materials.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, Also includes: A conductive material layer and a first cover material layer are formed on the substrate in sequence; Patterning the first cover material layer and the conductive material layer to form a first capping layer and the conductive layer partially located on the shallow trench isolation and partially located on the active region; as well as A gap wall layer is formed on the sidewalls of the first capping layer and the conductive layer.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, Also includes: A barrier material layer and an oxide material layer are applied to the first capping layer and the spacer wall layer; A first planarization process is performed to partially remove the oxide material layer, the barrier material layer, and the first capping layer to form an oxide layer and a barrier layer; A second covering material layer is formed on the oxide layer; as well as A second planarization process is performed to partially remove the second cover material layer, forming a second cover layer that partially physically contacts the barrier layer, the first cover layer, and the oxide layer, and forming the bit line structure.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The first capping layer and the second capping layer formed on the conductive layer above the first insulating layer isolated by the shallow trench together form the second insulating stack structure. The first capping layer, the barrier layer, the oxide layer and the second capping layer formed on the conductive layer above the second insulating layer isolated by the shallow trench together form the third insulating stack structure. The top surface of the first capping layer of the second insulating stack structure is higher than the top surface of the first capping layer of the third insulating stack structure.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The spacer layer, the barrier layer, the oxide layer, and the second capping layer formed above the second insulating layer together form a fourth insulating stack structure.

16. The method for fabricating a semiconductor device according to claim 15, characterized in that, The top surface of the fourth insulating stack structure, the top surface of the first insulating stack structure, the top surface of the second insulating stack structure, and the top surface of the third insulating stack structure are located on the same plane.

17. The method for fabricating a semiconductor device according to claim 14, characterized in that, The first capping layer, the barrier layer, and the second capping layer formed on the conductive layer above the active region together form a first insulating stack structure.

18. The method for fabricating a semiconductor device according to claim 17, characterized in that, The top surface of the first cover layer of the first insulating stack structure is higher than the top surface of the first cover layer of the third insulating stack structure, and lower than the top surface of the first cover layer of the second insulating stack structure.

19. The method for fabricating a semiconductor device according to claim 11, characterized in that, Also includes: At least one gate structure is formed on the substrate, comprising at least another conductive layer and a spacer layer, wherein the other conductive layer of the at least one gate structure and the conductive layer of the at least one bit line structure comprise the same conductive material; A first capping layer is formed on the at least one gate structure; A second cover layer is formed on the first cover layer; as well as A third cover layer is formed on the second cover layer.

20. The method for fabricating a semiconductor device according to claim 19, characterized in that, The first cover layer and the barrier layer are made of the same material, the second cover layer and the oxide layer are made of the same material, and the third cover layer and the second capping layer are made of the same material.

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