Parallelized distributed optical fiber audio acquisition restoration method

Abstract

The present application relates to the field of distributed optical fiber sensing, and particularly relates to a parallelized distributed optical fiber audio acquisition and restoration method. The present application performs each calculation step (phase demodulation, fading suppression, phase unwrapping, audio conversion) in parallel through FPGA; FPGA takes clock cycle as the basic time unit, collects data on one side, calculates data on the other side, and outputs data at the same time, which reduces the calculation delay, guarantees the consistency of each calculation delay, and the calculation delay is irrelevant to the number of restored spatial points; in addition, FPGA directly outputs data to CPU after calculation, which reduces data transmission time and reduces the data transfer pressure of CPU; furthermore, the power consumption level of FPGA is much lower than that of GPU. Finally, the present application restores audio information on each spatial point in real time and parallel, and the audio signal sampling rate is as high as 50Khz, while having the advantages of low power consumption, easy deployment on edge and portable devices.

Description

Technical Field

[0001] This invention relates to the field of distributed optical fiber sensing, and in particular to a parallelized distributed optical fiber audio acquisition and reconstruction method. Background Technology

[0002] Heterodyne distributed optical fiber acoustic sensing (DAS) based on Φ-OTDR (Phi-Optical Time Domain Reflectometer) has great application value in security monitoring, railway track monitoring, oil and gas pipeline monitoring, and seismic exploration, due to its advantages of dense sensing points, long sensing distance, and high response speed.

[0003] Currently, the application of heterodyne distributed fiber optic acoustic wave sensing technology in voice detection and security monitoring faces major technical challenges: the amount of data from distributed fiber optic sensing is enormous, and the audio sampling rate of CPU-based heterodyne distributed fiber optic acoustic wave sensing devices at each spatial point is difficult to reach professional audio level (48kHz), making it difficult to reproduce rich and clear audio signals in real time.

[0004] Many researchers have adopted a heterogeneous computing approach using CPU+GPU to address this challenge. While the parallel computing capabilities of GPUs can enable real-time reconstruction of high-sampling-rate audio signals, they also have several drawbacks:

[0005] (1) For high sampling rate audio signal restoration, although the GPU computation latency can reach hundreds of milliseconds, this is related to the amount of data demodulated. The number of computation threads needs to be increased with the increase of the number of restoration space points to ensure that the computation latency is low enough, which leads to low device application flexibility.

[0006] (2) Since the GPU cannot work independently, the raw data needs to be transferred from the CPU to the GPU for calculation. After the GPU completes the calculation, the data is transferred back to the CPU. Although the calculation time is reduced, the data transfer time is increased, which also increases the pressure on the CPU to move data.

[0007] (3) The power consumption of mainstream GPUs on the market is around 350W, which greatly increases the overall power consumption and size of heterodyne distributed fiber optic acoustic wave sensing devices, making them more difficult to deploy.

[0008] (4) Using GPUs relies on the multi-threading function of the operating system. The time of each thread is not completely synchronized, so it cannot be applied to scenarios that require precise latency. Summary of the Invention

[0009] In view of the above problems or deficiencies, in order to solve the problems that the existing heterodyne distributed optical fiber acoustic wave sensing technology is difficult to balance the calculation delay, data transmission complexity and power consumption when restoring the information-rich and clear audio signal in real time, the application provides a parallel distributed optical fiber audio acquisition and restoration method, which is realized by FPGA, and the calculation delay is lower than that of GPU, which can reach the order of ten microseconds, and is independent of the number of restored spatial points; the data after calculation is transmitted to CPU, the data carrying pressure of CPU is small, and the data transmission delay is low; the power consumption of the implementation circuit of the application is only 3.5W, which provides a basis for the miniaturization of the device; and the minimum time unit is the clock cycle, and the calculation delay is consistent each time.

[0010] A parallel distributed optical fiber audio acquisition and restoration method, the specific steps are as follows:

[0011] Step 1, the digital-analog conversion chip converts the back Rayleigh scattering signal output by the photoelectric balance detector from an analog signal to a digital signal and outputs it to the FPGA.

[0012] Step 2, the digital signal output by step 1 is phase demodulated.

[0013] The FPGA divides the input digital signal into 3 paths and simultaneously performs FIR band-pass filtering; then each path of the filtered signal is mixed with the cosine signal and the sine signal generated by the signal generator to generate 3 paths of in-phase signal I i and 3 paths of quadrature signal Q i , wherein i=1, 2, 3, representing the path number; finally, each path of the signal passes through a 6-channel parallel FIR low-pass filter to obtain 3 paths of I / Q signals after phase demodulation.

[0014] Step 3, the I / Q signal output by step 2 is subjected to fading suppression.

[0015] The FPGA calculates the argument of each path of the 3 paths of I / Q signals obtained in step 2 according to the trace cyclic index, and simultaneously stores the argument value in the RAM memory in the FPGA.

[0016] Then, the traces with index numbers 2 to L1 are rotated in the complex domain according to the corresponding signal path argument values stored in the RAM memory, wherein L1EN + , L1>=3, N + is a positive integer; then, the 3 paths of rotated I' / Q' signals are summed to obtain I sum and Q sum ; finally, the argument of the complex number I sum +jQ sum is calculated, j is the imaginary unit, and the phase signal θ after fading suppression is obtained.

[0017] Step 4, phase unwrapping is performed on the phase signal output in step 3.

[0018] The FPGA calculates the 3rd order backward difference value of the spatial point according to the phase signal obtained in step 3, and obtains the phase difference signal d ; then, the phase difference signal d is randomly sampled in space in the form of loop index; finally, according to the trace index, if the 1st order backward difference value diff of the phase d at the same spatial point of the previous trace and the current trace exceeds the predetermined threshold range, phase unwrapping is performed by adding or subtracting a predetermined compensation value, and the unwrapped phase signal is output.

[0019] Step 5, audio conversion is performed on the unwrapped phase signal output in step 4.

[0020] The FPGA calculates the 1st order backward difference value of the same spatial point of the previous trace and the current trace according to the unwrapped phase signal obtained in step 4; then, it is judged whether the backward difference value is less than 1: if the difference value is less than 1, the difference value is the audio amplitude at this spatial point; otherwise, the difference value is reduced to S as the audio amplitude at this spatial point, where -1

[0021] Further, the step 2 is specifically as follows:

[0022] Step 2.1, the data type of the digital signal is signed number fix16_15, which is divided into 3 parallel signals and simultaneously passes through 3 FIR bandpass filters BP1, BP2, BP3, the passband range of the 3 filters is 10Mhz to 20Mhz, 15Mhz to 25Mhz, 20Mhz to 30Mhz, and the format of the data output by the filter is fix32_30.

[0023] Step 2.2, the sine signal and cosine signal generated by the signal generator instantiated in the FPGA are output to the multiplier input port of the multipliers M1, M2, M3 and the multipliers M4, M5, M6, respectively; the output data of the bandpass filter BP1 is output to the other multiplier input port of the multipliers M1 and M4; the output data of the bandpass filter BP2 is output to the other multiplier input port of the multipliers M2 and M5; the output data of the bandpass filter BP3 is output to the other multiplier input port of the multipliers M3 and M6; in this way, the mixing is completed, and the multipliers M1, M2, M3 output the quadrature signals Q1, Q2, Q3, and the multipliers M4, M5, M6 output the in-phase signals I1, I2, I3.

[0024] Step 2.3, 6-channel parallel FIR low-pass filter LP1 filters 3 Q signals and 3 I signals simultaneously, and outputs I / Q signals after phase demodulation. The cut-off frequency of the low-pass filter is 10 Mhz.

[0025] Further, the step 3 is specifically as follows:

[0026] Step 3.1, the FIR low-pass filter is self-increased by 1 for the spatial point index cnt_sample defined by the logic controller every time an effective data is output, and is self-cleared when cnt_sample is increased to N1, at which time the trace index cnt_trace is self-increased by 1, and is self-cleared when cnt_trace is increased to L1. The index is continuously looped, wherein N1∈N + ,N1>1.

[0027] Step 3.2, when the index trace number is 1, the filtered I / Q signals are output to the arc tangent calculation modules ARC1, ARC2, ARC3 through the logic controller; wherein filtered I1 and Q1 are output to the real part input port and the imaginary part input port of ARC1, filtered I2 and Q2 are output to the real part input port and the imaginary part input port of ARC2, and filtered I3 and Q3 are output to the real part input port and the imaginary part input port of ARC3. The three arc tangent calculation modules calculate the argument of the I / Q signal and simultaneously store it in the three one-to-one corresponding memories RAM1, RAM2, RAM3. One-to-one correspondence means that the arc tangent calculation module and the memory have the same number to form a corresponding relationship.

[0028] When the index trace number is 2 to L1, the filtered I / Q signals are output to the vector rotators VT1, VT2, VT3 through the logic controller; wherein filtered I1 and Q1 are output to the real part input port and the imaginary part input port of VT1, filtered I2 and Q2 are output to the real part input port and the imaginary part input port of VT2, and filtered I3 and Q3 are output to the real part input port and the imaginary part input port of VT3. At the same time, the argument value cached in each RAM is read and output to the angle input port of the vector rotator one-to-one corresponding, and one-to-one correspondence means that the memory and the vector rotator have the same number to form a corresponding relationship. The calculation formula is wherein I' and Q' are the signals after vector rotation, and is the argument value cached in the RAM.

[0029] Step 3.3, the three vector rotators synchronously output 3 I' / Q' signals to the parallel complex adder to perform summation operation of the signals. The calculation formula is I sum =I1'+I2'+I3', Q sum =Q1'+Q2'+Q3'.

[0030] Step 3.4, complex adder output I sum , Q sum signal to arctangent calculation module ARC4 to perform arctangent operation on the signal, and the calculation formula is θ = atan(Q sum / I sum ), wherein θ is the phase signal after fading suppression.

[0031] Further, the step 4 is specifically as follows:

[0032] Step 4.1, the phase unwrapper uses the phase signal θ output by step 3 to calculate the phase difference signal θ d , and the calculation formula is θ d = θ n - θ n-3 , wherein θ n is the current input value, and θ n-3 is the input value three clock periods ago.

[0033] Step 4.2, in a loop index manner, after calculating 10 data, one is randomly reserved as valid data, and data extraction is completed. The loop index refers to the sequence number of the valid data reserved in the subsequent 10 data being the same as the first time.

[0034] Step 4.3, after calculating one valid data, the space point indexer cnt_sample_1 defined in the phase unwrapper is automatically increased by 1, and when cnt_sample_1 is automatically increased to N2, it is automatically cleared, at this time, the trace indexer cnt_trace_1 is automatically increased by 1, and when cnt_trace_1 is automatically increased to L2, it is automatically cleared, and the index is continuously looped, wherein N2 ∈ N + , N2 > 1.

[0035] Step 4.4, when the index trace number is 1, the phase unwrapper will write the valid data into the memory RAM_phi at the same time, and initialize the offset variable k to 0 and write it into the memory RAM_k.

[0036] When the index trace number is 2 to L2, the unwrapper calculates the first order backward difference value of the current phase difference signal θ d and the corresponding space point signal in the memory RAM_phi, and the calculation formula is diff = θ d - θ d_RAM , θ d_RAM is the signal with the same space position as θ d in the previous trace.

[0037] If π-2kπ ≤ diff ≤ 3π-2kπ, update the k value of the corresponding space point in the memory RAM_phi k = k-1, and output the unwrapped phase signal θ unwarp= θ d + 2kπ.

[0038] If 3π - 2kπ≤ diff≤ 5π - 2kπ, update the k value of the corresponding spatial point in the memory RAM_phi k = k - 2, and output the unwrapped phase signal θ unwarp = θ d + 2kπ.

[0039] If -π - 2kπ≤ diff≤ -3π - 2kπ, update the k value of the corresponding spatial point in the memory RAM_phi k = k + 1, and output the unwrapped phase signal θ unwarp = θ d + 2kπ.

[0040] If -3π - 2kπ≤ diff≤ -5π - 2kπ, update the k value of the corresponding spatial point in the memory RAM_phi k = k + 2, and output the unwrapped phase signal θ unwarp = θ d + 2kπ.

[0041] If -π - 2kπ≤ diff≤ π - 2kπ, directly output the unwrapped phase signal θ unwarp = θ d + 2kπ.

[0042] Wherein, the upper and lower limits of the judgment are the predetermined threshold values, and 2kπ is a predetermined compensation value.

[0043] Further, the step 5 is specifically as follows:

[0044] Step 5.1, the audio converter writes the first received unwrapped phase signal θ unwarp into the memory RAM_phi_unwrap;

[0045] Step 5.2, when the audio converter receives a non-first trace, the audio signal sound is obtained by calculating the 1st order backward difference value of the current input signal and the signal of the corresponding spatial point in the memory RAM_phi, and the calculation formula is sound = θ unwrap - θ unwrap_RAM , wherein θ unwrap is the current unwrapped phase signal, θ unwrap_RAM is the unwrapped phase signal of the same spatial position as θ unwrap in the previous trace, and θ unwrap is used to update the cache value in the memory RAM_phi_unwrap;

[0046] Step 5.3, if the value of the audio signal sound≥1, it is reduced to S output, wherein -1

[0047] The present application can achieve lower calculation delay and accurate delay mainly by the parallel execution of each calculation step of the FPGA. The FPGA takes the clock cycle as the basic time unit, collects data, calculates data, and outputs data at the same time. This full-pipelined data processing method can reduce the calculation delay while ensuring the consistency of each calculation delay, and the calculation delay is irrelevant to the number of restored spatial points. The GPU caches a large amount of data, performs multi-thread parallel calculation by operating system in an instruction cycle unit, outputs a large amount of data after calculation, and cannot achieve full-pipelined data processing. Moreover, the calculation time of each thread is not fixed, and the consistency of the calculation delay cannot be maintained. In addition, the GPU needs to obtain data from the CPU, and after the calculation is completed, the data is transmitted back to the CPU by relying on a high-bandwidth transmission protocol. The FPGA directly outputs data to the CPU after calculation, reduces the data transmission time, and reduces the data transfer pressure of the CPU. Furthermore, the power consumption level of the FPGA is much lower than that of the GPU. The power consumption of the mainstream GPU product on the market is about 350W, and the power consumption of the circuit realized by the present application on the FPGA is only 3.5W. Therefore, the present application has advantages in calculation delay, data transmission complexity, and power consumption.

[0048] In summary, the present application takes into account the calculation delay, data transmission complexity, and power consumption when restoring the information-rich and clear audio signal in real time. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 The system working schematic diagram of the embodiment;

[0050] Figure 2 The data processing board card architecture diagram of the embodiment;

[0051] Figure 3 The architecture diagram of the present application;

[0052] Figure 4 The architecture diagram of the phase demodulator in the embodiment;

[0053] Figure 5 The architecture diagram of the fading suppressor in the embodiment;

[0054] Figure 6 The architecture diagram of the de-roller in the embodiment;

[0055] Figure 7 The architecture diagram of the audio converter in the embodiment;

[0056] Figure 8 The audio restoration effect diagram of the embodiment. DETAILED DESCRIPTION

[0057] The application will be further described in detail below with reference to the accompanying drawings and examples.

[0058] The system connection structure of the embodiment is shown in Figure 1 The laser emits a laser pulse signal with a width of 100 ns, which first passes through an isolator to prevent the light from reversing into the laser and damaging the laser. Then, the signal light with a power ratio of 97:3 passes through a 97:3 coupler, 97% of the power of the signal light passes through a 100M acousto-optic modulator and is modulated into a high-coherence laser pulse signal, and then the signal is amplified through an EDFA and enters the sensing optical fiber through a circulator. The backscattering signal in the optical fiber interferes with the 3% power local light passing through an 80M acousto-optic modulator in a 2*2 coupler, and then the interference signal enters the photodetector. Then, the photodetector converts the optical signal into an analog electrical signal, which is output to the data processing board card. Finally, the audio data is transmitted to the host computer for display and playback after being processed by the data processing board card. The FPGA on the data processing board card selects the ZYNQ-XC7Z35 chip produced by XILINX, the digital-to-analog conversion chip selects the AD9643 produced by ADI, and the DAS audio restorer is deployed in the FPGA of the data processing board card.

[0059] The architecture of the data processing board card in the embodiment is shown in Figure 2 The digital-to-analog conversion chip collects the backscattering signal (raw data) output by the photoelectric balance detector at a rate of 100MSPS; then the signal is transmitted to the DAS audio restorer, and the restored audio signal is written into the on-board DDR3 chip through DMA; then the PS end of the ZYNQ-XC7Z35 chip reads the data in the DDR3 and transmits the data to the host computer through the TCP / IP protocol; finally, the host computer plays and displays the audio signal through the Labview software.

[0060] A parallelized distributed optical fiber audio acquisition and restoration method, the specific steps are as follows:

[0061] Step 1, the digital-to-analog conversion chip converts the backscattering signal output by the photoelectric balance detector into a digital signal at a sampling rate of 100MSPS, and outputs it to the FPGA.

[0062] Step 2, the digital signal output in step 1 is phase demodulated; the architecture diagram of the phase demodulator used in the embodiment is shown in Figure 4

[0063] The FPGA divides the original signal into three paths and performs FIR band-pass filtering simultaneously; then each filtered signal is mixed with the cosine signal and the sine signal generated by the signal generator to generate three in-phase signals I i ​and 3 orthogonal signals Q i , where i = 1, 2, 3, represents the path number; finally, each signal passes through a 6-channel parallel FIR low-pass filter to obtain the I / Q signals after phase demodulation.

[0064] Step 2.1, the data type of the digital signal is signed fix16_15, which is divided into 3 parallel signals and simultaneously passes through 3 18-order FIR band-pass filters BP1, BP2, BP3 with a sampling rate of 100Mhz; the passband ranges of the 3 filters are 10Mhz to 20Mhz, 15Mhz to 25Mhz, and 20Mhz to 30Mhz; the format of the data output by the filters is fix32_30;

[0065] Step 2.2, the sine and cosine signals generated by the signal generator instantiated in the FPGA are output to the multiplier input ports of the multipliers M1, M2, M3 and M4, M5, M6, respectively; the single period values of the two sequences are [0.296875, 0.984375, 0.296875, 0.796875, 0.796875] and [-0.9375, -0.015625, 0.9375, 0.578125, -0.578125], respectively; the output data of the band-pass filter BP1 is output to the other multiplier input ports of the multipliers M1 and M4; the output data of the band-pass filter BP2 is output to the other multiplier input ports of the multipliers M2 and M5; the output data of the band-pass filter BP3 is output to the other multiplier input ports of the multipliers M3 and M6; in this way, the mixing is completed, and the multipliers M1, M2, M3 output the orthogonal signals Q1, Q2, Q3, and the multipliers M4, M5, M6 output the in-phase signals I1, I2, I3;

[0066] Step 2.3, the 6-channel parallel 18-order FIR low-pass filter LP1 simultaneously filters the 3 Q signals and the 3 I signals, and outputs the I / Q signals after phase demodulation; the sampling rate of the filter is 100Mhz, and the cutoff frequency is 10Mhz;

[0067] Step 3, the I / Q signals output in step 2 are subjected to fading suppression; the architecture diagram of the fading suppressor used in this embodiment is shown in Figure 5

[0068] The FPGA calculates the argument using the trace loop index for each of the 3 I / Q signals obtained in step 2, and stores the argument value in the RAM memory inside the FPGA; then, the traces with index numbers 2 to 5001 are rotated in the complex domain in the opposite direction at the same angle; again, the 3 rotated I / Q signals are summed to obtain I sum and Q sum ; finally, the complex number I​sum + jQ sum , where j is the imaginary unit, and θ is the phase signal after fading suppression.

[0069] Step 3.1, the low-pass filter LP1 outputs one valid data, the space point index cnt_sample defined in the logic controller is incremented by 1, when cnt_sample is incremented to 1500, it is cleared, at this time, the trace index cnt_trace is incremented by 1, when cnt_trace is incremented to 5001, it is cleared, and the index is continuously looped.

[0070] Step 3.2, when the index trace number is 1, the filtered I / Q signals are output to the arc tangent calculation modules ARC1, ARC2, ARC3 through the logic controller; wherein the filtered I1 and Q1 are output to the real and imaginary input ports of ARC1, the filtered I2 and Q2 are output to the real and imaginary input ports of ARC2, and the filtered I3 and Q3 are output to the real and imaginary input ports of ARC3, the three arc tangent calculation modules calculate the radian of the I / Q signal and simultaneously store them in the three one-to-one corresponding memories RAM1, RAM2, RAM3, and the one-to-one correspondence means that the arc tangent calculation module and the memory have the same number to form a corresponding relationship.

[0071] When the index trace number is 2 to 5001, the filtered I / Q signals are output to the vector rotators VT1, VT2, VT3 through the logic controller; wherein the filtered I1 and Q1 are output to the real and imaginary input ports of VT1, the filtered I2 and Q2 are output to the real and imaginary input ports of VT2, and the filtered I3 and Q3 are output to the real and imaginary input ports of VT3, and the radian values cached in each RAM are read and output to the angle input ports of the vector rotators one-to-one corresponding, and the one-to-one correspondence means that the memory and the vector rotator have the same number to form a corresponding relationship, and the calculation formula is where I' and Q' are the signals after vector rotation, is the radian value cached in the RAM;

[0072] Step 3.3, the three vector rotators synchronously output three I' / Q' signals to the parallel complex adder to perform summation operation of the signals, and the calculation formula is I sum = I1' + I2' + I3', Q sum = Q1' + Q2' + Q3';

[0073] Step 3.4, the complex adder outputs I sum , Q sumThe signal is input into an arctangent calculation module ARC4 to perform an arctangent operation on the signal, and the calculation formula is θ = atan(Q sum / I sum ), where θ is the phase signal after fading suppression.

[0074] Step 4, the phase unwrapping is performed on the phase signal output in step 3, and the architecture diagram of the unwrapper used in step 4 is shown in Figure 6 .

[0075] The FPGA calculates the third-order backward difference value of the spatial point according to the phase signal θ obtained in step 3, and obtains the phase difference signal θ d ; then, the phase difference signal is spatially decimated; finally, according to the trace index, if the first-order backward difference value diff of θ d at the same spatial point of the previous trace and the current trace exceeds the predetermined threshold range, the phase unwrapping is performed by adding or subtracting a predetermined compensation value, and the unwrapped phase signal is output.

[0076] Step 4.1, the phase signal θ output by the arctangent calculation module is input into the phase unwrapper, and the phase difference signal θ d is calculated, and the calculation formula is θ d = θ n - θ n-3 , where θ n is the current input value, and θ n-3 is the input value three clock cycles ago.

[0077] Step 4.2, in the form of loop index, after calculating 10 data, 1 is randomly reserved as valid data to complete data decimation; the loop index means that the serial number of the valid data reserved in the subsequent 10 data is the same as the first time.

[0078] Step 4.3, after calculating 1 valid data, the spatial point index cnt_sample_1 defined in the unwrapper is automatically incremented by 1, and when cnt_sample_1 is incremented to 150, it is automatically cleared, at this time, the trace index cnt_trace_1 is automatically incremented by 1, and when cnt_trace_1 is incremented to 5000, it is automatically cleared, and the index is continuously looped.

[0079] Step 4.4, when the index trace number is 1, the unwrapper will write the valid data into the memory RAM_phi, and initialize the offset variable k to 0 and write it into the memory RAM_k.

[0080] When the index trace number is 2 to 5000, the unwrapper calculates the first-order backward difference value of the current difference signal and the corresponding spatial point signal in the memory RAM_phi, and the calculation formula is diff = θ d - θd_RAM where θ d is the current phase difference signal, θ d_RAM is the signal at the same spatial position in the previous trace; d

[0081] If π-2kπ≤diff≤3π-2kπ, update the k value of the corresponding spatial point in the memory RAM_phi, k=k-1, and output the unwrapped phase signal θ unwarp = θ d +2kπ;

[0082] If 3π-2kπ≤diff≤5π-2kπ, update the k value of the corresponding spatial point in the memory RAM_phi, k=k-2, and output the unwrapped phase signal θ unwarp = θ d +2kπ;

[0083] If -π-2kπ≤diff≤-3π-2kπ, update the k value of the corresponding spatial point in the memory RAM_phi, k=k+1, and output the unwrapped phase signal θ unwarp = θ d +2kπ;

[0084] If -3π-2kπ≤diff≤-5π-2kπ, update the k value of the corresponding spatial point in the memory RAM_phi, k=k+2, and output the unwrapped phase signal θ unwarp = θ d +2kπ;

[0085] If -π-2kπ≤diff≤π-2kπ, directly output the unwrapped phase signal θ unwarp = θ d +2kπ;

[0086] Step 5, audio conversion is performed on the unwrapped phase signal output in step 4, and the architecture diagram of the audio converter used in the embodiment is shown in Figure 7

[0087] The FPGA calculates the 1st order backward difference value of the same spatial point in the previous trace and the current trace according to the unwrapped phase signal obtained in step 4 according to the trace index. Then, it is determined whether the difference value is less than 1. Finally, if the difference value is less than 1, the difference value is the audio amplitude at the spatial point; otherwise, the difference value is reduced to 0.2 as the audio amplitude at the spatial point. The value greater than 1 is a jump value caused by the beginning and end of the index loop in the calculation process, so it is reasonable to reduce it to a smaller value of 0.2.

[0088] Step 5.1, the audio converter receives the first unwrapped phase signal θ unwarp ​​Write memory RAM_phi_unwrap;

[0089] Step 5.2, when the audio converter receives a non-first trace line, the audio signal sound is obtained by calculating the first-order backward difference value of the current input signal and the corresponding spatial point signal in the memory RAM_phi, and the calculation formula is sound = θ unwrap -θ unwrap_RAM , wherein θ unwrap is the current unwrapped phase signal, θ unwrap_RAM is the phase signal at the same spatial position as θ unwrap in the previous trace line, and θ unwrap is used to update the cache value in the memory RAM_phi_unwrap;

[0090] Step 5.3, if the value of the audio signal sound is greater than or equal to 1, it is reduced to 0.2 for output; if the value of the audio signal sound is less than 1, it is directly output.

[0091] The number of audio restored spatial points in the embodiment is 150, the spatial point interval is 10 meters, and the audio sampling rate of each spatial point is 50Khz. Figure 8 (a) is an audio intensity rendering diagram of all spatial points on the distributed optical fiber at a certain moment, wherein the middle section is the effective area of the audio signal, the front section does not exist effective signal due to the inherent signal transmission delay of the optical system, and the rear section does not exist effective signal due to the sensing optical fiber length of the access system being only 1.05 kilometers. Figure 8 (b) is an audio waveform diagram restored at a spatial point 450 meters away from the starting position of the optical fiber at the same moment. Figure 8 (c) is a power spectral density diagram of the audio signal in figure (b).

[0092] As can be seen from the above embodiment, the FPGA parallelizes the execution of each calculation step, the FPGA takes the clock cycle as the basic time unit, collects data on one side, calculates data on the other side, and outputs data at the same time, this full-pipelined data processing method can reduce the calculation delay while ensuring the consistency of each calculation delay, and the calculation delay is irrelevant to the number of restored spatial points; after the FPGA calculation is completed, the data is directly output to the CPU, which reduces the data transmission time and relieves the data transfer pressure of the CPU. Moreover, the power consumption level of the FPGA is much lower than that of the GPU, and the power consumption of the mainstream GPU products on the market is about 350W, while the circuit power consumption of the FPGA after the implementation of the present application is only 3.5W. Finally, the present application restores the audio information at each spatial point in real time and parallel, and the audio signal sampling rate is as high as 50Khz, while having the advantages of low power consumption, easy deployment on the edge and portable devices.

Claims

1. A parallelized distributed optical fiber audio acquisition restoration method, characterized in that, The specific steps are as follows: Step 1, the digital-analog conversion chip converts the backscattering signal output by the photoelectric balance detector from an analog signal to a digital signal and outputs to the FPGA; Step 2, the digital signal output by step 1 is phase demodulated; The FPGA divides the input digital signal into three paths for FIR band-pass filtering simultaneously; then the filtered signals of each path are mixed with the cosine signal and the sine signal generated by the signal generator respectively to generate three paths of in-phase signals I i and three paths of quadrature signals Q i , wherein i=1, 2, 3, represents the path number; finally, each path of signals passes through six-channel parallel FIR low-pass filters simultaneously to obtain three paths of I / Q signals after phase demodulation; Step 3, the I / Q signal output by step 2 is subjected to fading suppression; The FPGA calculates the argument of each trace using the trace index number 1 according to the 3-channel I / Q signal obtained in step 2, and simultaneously stores the argument value in the RAM memory in the FPGA; Then, the traces with index numbers 2 to L1 are rotated in the complex domain in the opposite direction by the corresponding signal path angle values stored in the RAM memory, where L1 ∈ N + , L1 ≥ 3, N + is a positive integer; then, the 3-way rotated I' / Q' signals are summed to obtain I sum and Q sum , respectively; finally, the angle of the complex number I sum +jQ sum is calculated, j being the imaginary unit, i.e. the phase signal θ after fading suppression is obtained; Step 4, the phase signal output by step 3 is subjected to phase unwrapping; The FPGA calculates the 3rd order backward difference value of the spatial point according to the phase signal θ obtained in step 3 and the spatial point index, and obtains a phase difference signal θ d ; then, the phase difference signal θ d is extracted in the spatial domain in a cyclic index manner; finally, if the 1st order backward difference value diff of θ d at the same spatial point of the previous trace and the current trace exceeds a predetermined threshold range, the phase unwrapping is performed by adding or subtracting a predetermined compensation value, and an unwrapped phase signal is output. Step 5, the unwrapped phase signal output by step 4 is subjected to audio conversion; The FPGA calculates the first-order backward difference value at the same spatial point of the previous trace and the current trace according to the unwrapped phase signal obtained in step 4 according to the trace index; Then, it is judged whether the difference value is less than 1: if the difference value is less than 1, the difference value is the audio amplitude at this spatial point; Otherwise, the difference value is reduced to S as the audio amplitude at this spatial point, where -1 < S < 1.

2. The parallelized distributed optical fiber audio collection reduction method of claim 1, wherein, The step 2 is specifically as follows: Step 2.1, the data type of the digital signal is signed fix16_15, which is divided into 3 parallel signals and simultaneously passes through 3 FIR bandpass filters BP1, BP2 and BP3, the passband range of the 3 filters is 10Mhz to 20Mhz, 15Mhz to 25Mhz and 20Mhz to 30Mhz, and the format of the data output by the filter is fix32_30; Step 2.2, the sine signal and cosine signal generated by the signal generator instantiated in the FPGA are output to the multiplier input port of the multipliers M1, M2, M3 and M4, M5, M6 respectively; the output data of the bandpass filter BP1 is output to the other multiplier input port of the multipliers M1 and M4; the output data of the bandpass filter BP2 is output to the other multiplier input port of the multipliers M2 and M5; the output data of the bandpass filter BP3 is output to the other multiplier input port of the multipliers M3 and M6; in this way, the mixing is completed, and the multipliers M1, M2, M3 output the quadrature signals Q1, Q2, Q3, and the multipliers M4, M5, M6 output the in-phase signals I1, I2, I3; Step 2.3, the 6-channel parallel FIR low-pass filter LP1 simultaneously filters the 3-channel Q signals and 3-channel I signals, outputs the I / Q signals after phase demodulation, and the cut-off frequency of the low-pass filter is 10Mhz.

3. The parallelized distributed optical fiber audio collection reduction method of claim 1, wherein, The step 3 is specifically as follows: Step 3.1, the space point index cnt_sample defined by the logic controller is increased by 1 every time an effective data is outputted by the FIR low-pass filter, and is cleared when it is increased to N1, at which time the trace index cnt_trace is increased by 1, and is cleared when it is increased to L1, and the indexes are continuously cycled, wherein N1∈N + N1>1; Step 3.2, when the index trace number is 1, the filtered I / Q signals are output to the arctangent calculation modules ARC1, ARC2, ARC3 by the logic controller; wherein filtered I1 and Q1 are output to the real and imaginary input ports of ARC1, filtered I2 and Q2 are output to the real and imaginary input ports of ARC2, and filtered I3 and Q3 are output to the real and imaginary input ports of ARC3; the three arctangent calculation modules calculate the arguments of the I / Q signals and simultaneously store them in the three one-to-one corresponding memories RAM1, RAM2, RAM3; one-to-one correspondence means that the arctangent calculation modules and the memories have the same number and form a corresponding relationship; When the index trace number is 2 to L1, the filtered I / Q signals are output to the vector rotators VT1, VT2, VT3 by the logic controller; wherein the filtered I1 and Q1 are output to the real and imaginary input ports of VT1, the filtered I2 and Q2 are output to the real and imaginary input ports of VT2, and the filtered I3 and Q3 are output to the real and imaginary input ports of VT3, while reading the radian values cached in each RAM and output to the angle input ports of the vector rotators one by one, which means that the memory and the vector rotator have the same number and form a corresponding relationship, and the calculation formula is wherein I' and Q' are the signals after vector rotation, is the radian value cached in the RAM. Step 3. The 3 vector rotators synchronously output 3 I' / Q' signals to the parallel complex adder to perform summation operation of the signals, and the calculation formula is I sum = I1' + I2' + I3', Q sum = Q1' + Q2' + Q3'. Step 3.4, complex adder output I sum , Q sum signal to arctangent calculation module ARC4, to perform arctangent operation on the signal, with the formula θ = atan(Q sum / I sum ), where θ is the phase signal after fading suppression.

4. The parallelized distributed optical fiber audio collection reduction method of claim 1, wherein, The step 4 is specifically as follows: Step 4.1: The phase uncoiler uses the phase signal θ output in step 3 to calculate the phase difference signal θ. d The calculation formula is θ d =θ n -θ n-3 , where θ n θ is the current input value. n-3 The input value was obtained 3 clock cycles ago; Step 4.2, in a cyclic index manner, after 10 data are calculated, 1 is randomly reserved as valid data to complete data extraction; cyclic index means that the valid data serial number of every 10 data in the subsequent is the same as the first time; Step 4.3, for each valid data calculated, the phase unwrapping internal self-defined space point indexer cnt_sample_1 is incremented by 1, and when cnt_sample_1 is incremented to N2, it is cleared, at this time the self-defined trace indexer cnt_trace_1 is incremented by 1, and when cnt_trace_1 is incremented to L2, it is cleared, the index is continuously looped, wherein N2∈N + N2>1; Step 4.4, when the index trace number is 1, the phase unwrapper simultaneously writes the valid data into the memory RAM_phi and initializes the offset variable k to 0 and writes it into the memory RAM_k; When the index trace number is 2 to L2, the unwrapper calculates the current phase difference signal θ d and the 1st order backward difference value of the corresponding spatial point signal in the memory RAM_phi, the calculation formula is diff=θ d -θ d_RAM , θ d_RAM is the signal in the previous trace with the same spatial position as θ d ; If π - 2kπ ≤ diff ≤ 3π - 2kπ, then update the k value k = k - 1 of the corresponding spatial point in the memory RAM_phi, and output the unwrapped phase signal θ unwarp = θ d + 2kπ; If 3π - 2kπ ≤ diff ≤ 5π - 2kπ, then update the k value k = k - 2 of the corresponding spatial point in the memory RAM_phi, and output the unwrapped phase signal θ unwarp = θ d + 2kπ; If -π - 2kπ ≤ diff ≤ -3π - 2kπ, update the k value of the corresponding spatial point in the memory RAM_phi, k = k + 1, and output the unwrapped phase signal θ unwarp = θ d + 2kπ; If -3π - 2kπ ≤ diff ≤ -5π - 2kπ, update the k value k = k + 2 of the corresponding spatial point in the memory RAM_phi, and output the unwrapped phase signal θ unwarp = θ d + 2kπ; If -π - 2kπ < diff < π - 2kπ, directly output the unwrapped phase signal θ unwarp = θ d + 2kπ; Wherein, the upper and lower limits of the judgment are the predetermined threshold, and 2kπ is the predetermined compensation value.

5. The parallelized distributed optical fiber audio collection reduction method of claim 1, wherein, The step 5 is specifically as follows: Step 5.

1. The audio converter will receive the first unwrapped phase signal θ unwarp Write to memory RAM_phi_unwrap; Step 5.2, when the audio converter receives the non-first trace, the audio signal sound is obtained by calculating the 1st order backward difference value of the current input signal and the corresponding spatial point signal in the memory RAM_phi, the calculation formula is sound = θ unwrap - θ unwrap_RAM , wherein θ unwrap is the current unwrapped phase signal, θ unwrap_RAM is the unwrapped phase signal in the previous trace with the same spatial position as θ unwrap , and the cache value in the memory RAM_phi_unwrap is updated using θ unwrap ; Step 5.3, if the audio signal sound value is greater than or equal to 1, it is reduced to S output, wherein -1<S<1; if the value of the audio signal sound is less than 1, it is directly output.

6. The parallelized distributed optical fiber audio collection reduction method of claim 1, wherein, The S=0.2.

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