A joint compilation optimization method, device and medium for heterogeneous computing

Abstract

The present application discloses a joint compilation optimization method, device and medium for heterogeneous computing, which relates to the field of data compilation. The method includes: obtaining source code; cutting the source code based on keywords to obtain code modules corresponding to the host side and the device side respectively, and mapping the code modules to obtain corresponding intermediate representations; independently optimizing the corresponding intermediate representations according to the compilation optimization stage set in the compiler; jointly compiling the independent optimization results; running the code based on the joint compilation results, and automatically tuning based on the feedback running results until the final executable file is generated. A cost evaluation model is established through multiple dimensions, and nonlinear factors are introduced to characterize the influence of bandwidth and computing resources, which more realistically reflects the influence of various factors on cost. A greedy algorithm is used for iterative search to ensure the optimization of the final program performance.

Description

Technical Field

[0001] The present application relates to the field of data compilation, and specifically to a joint compilation optimization method, device and medium for heterogeneous computing. Background Art

[0002] As computing demands grow, heterogeneous computing systems are becoming increasingly important because they can integrate different types of processors. However, traditional compilation techniques often require separate compilation and optimization for different hardware platforms, which not only increases development costs but also limits application performance.

[0003] For example, as a standard for general heterogeneous computing programming framework, OpenCL also adopts the design concept of separating host-side code and device-side code in traditional compilation technology, which to a certain extent limits the performance improvement of code written in OpenCL. Summary of the invention

[0004] In order to solve the above problems, this application proposes a joint compilation optimization method for heterogeneous computing, including:

[0005] Obtaining source code and preprocessing the source code;

[0006] The source code is segmented based on keywords to obtain code modules corresponding to the host side and the device side, respectively, and the code modules are mapped to obtain corresponding intermediate representations;

[0007] For either the host side or the device side, independently optimizing the intermediate representation corresponding to itself according to the compilation optimization stage set in the compiler;

[0008] Obtaining independent optimization results of the host side and the device side, and jointly compiling the independent optimization results;

[0009] The code is run based on the joint compilation results, and automatic tuning is performed based on the feedback of the running results until the final executable file is generated.

[0010] On the other hand, the present application also proposes a joint compilation optimization device for heterogeneous computing, including:

[0011] at least one processor; and,

[0012] a memory communicatively connected to the at least one processor; wherein,

[0013] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the joint compilation optimization method for heterogeneous computing as described in the above example.

[0014] On the other hand, the present application also proposes a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured as: the joint compilation optimization method for heterogeneous computing described in the above example.

[0015] The joint compilation optimization method for heterogeneous computing proposed in this application can bring the following beneficial effects:

[0016] By combining the host-side and device-side program codes through joint compilation technology, the program can be optimized from a global perspective, improving the compilation efficiency and application performance in heterogeneous computing environments. In view of the impact of different optimization strategies on performance when jointly compiling the host-side and device-side codes, a cost evaluation model is established through multiple dimensions, and nonlinear factors are introduced to characterize the impact of bandwidth and computing resources on the cost evaluation model, which more realistically reflects the impact of various factors on the cost. A greedy algorithm is used for iterative search to ensure the optimization of the final program performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 It is a flowchart of a joint compilation optimization method for heterogeneous computing in an embodiment of the present application;

[0019] Figure 2 A hardware structure topology diagram in one case in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of a compilation process in one scenario in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of a joint compilation data flow in one scenario in an embodiment of the present application;

[0022] Figure 5 This is a schematic diagram of the automatic tuning process in one scenario in an embodiment of the present application;

[0023] Figure 6 It is a schematic diagram of a joint compilation optimization device for heterogeneous computing in an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0025] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0026] like Figure 1 As shown, the embodiment of the present application provides a joint compilation optimization method for heterogeneous computing, including:

[0027] S101: Obtain source code and preprocess the source code.

[0028] Since the compilation process involves multiple sides, including the host side and the device side, the compilation framework can be unified in advance to create a compilation framework that can process both the host side and the device side code at the same time to ensure consistency and synchronization during the compilation process.

[0029] Considering the universality of the compilation framework and the activeness of the community, compiler frameworks such as GCC (GNU Compiler Collection), ICC (Intel Compiler), and LLVM (Low Level Virtual Machine) can be used as a unified compilation framework for implementing heterogeneous computing. In the embodiments of the present application, the LLVM compiler is used as an example for explanation.

[0030] like Figure 2 As shown in the hardware structure topology diagram, the host side (CPU) and the device side (GPU) are connected through a bus (PCIE).

[0031] like Figure 3 and Figure 4 As shown, after the source code is input, the source code is preprocessed, including syntax checking, macro expansion, and using static analysis tools to analyze the code structure and performance bottlenecks, so as to facilitate subsequent analysis and processing of the code.

[0032] S102: Slice the source code based on keywords to obtain code modules corresponding to the host side and the device side respectively, and map the code modules to obtain corresponding intermediate representations.

[0033] Specifically, the source code is input into a compiler (e.g., Clang), and the reserved keywords (e.g., Host, Device, Global, and Kernel) in the compiler are used to split the code modules corresponding to the host side and the device side. For example, the code module modified by the Host keyword is the host side code module, and the code module modified by Device and Kernel is the device side code module.

[0034] The compiler performs syntax analysis on each code module to establish a corresponding abstract syntax tree, and maps the code module to a corresponding intermediate representation (IR) through a language conversion module (eg, CodeGen module) based on the abstract syntax tree.

[0035] Different processor architectures support different instruction sets. For LLVM, its backend can adapt to various custom instruction sets, so it can use the characteristics of different processor architectures to achieve better resource allocation. LLVM-based front-end compilers (such as Clang) automatically divide the code modules (also called code programs) on the host side and the device side according to the reserved keywords of the host side and device side codes written by users.

[0036] S103: For either the host side or the device side, independently optimize the intermediate representation corresponding to itself according to the compilation optimization stage set in the compiler.

[0037] like Figure 3 and Figure 4 As shown in the figure, by designing an optimization strategy, the characteristics of the target hardware (including the hardware on the host side and the device side) can be taken into account during compilation, and appropriate optimization techniques can be automatically applied. Specific independent optimizations are applied to the host side code module and the device side code module after code segmentation.

[0038] Specifically, for either the host side or the device side, the compiler manager (also called the optimizer) is determined, and based on the compilation optimization stage set in the compiler manager, the corresponding intermediate representation is optimized independently. Taking the LLVM compiler as an example, a Pass manager is set as the compilation manager to manage each optimization Pass, that is, each compilation optimization stage, so as to independently optimize the intermediate representation (LLVM-IR).

[0039] Among them, independent optimization includes one or more optimization strategies of constant folding, dead code elimination, loop unrolling, loop merging, branch elimination, and data partitioning. Independent optimization can select any one of these optimization strategies, or combine multiple optimization strategies as a senior independent optimization.

[0040] S104: Obtain independent optimization results of the host side and the device side, and jointly compile the independent optimization results.

[0041] The joint optimizer under the unified compilation framework obtains independent optimization results on the host side and the device side, and integrates the independent optimization results. According to the calling relationship between the host-side code modules and the device-side code modules after independent optimization, the associated host-side code modules and device-side code modules are grouped, and a joint compilation method is adopted for each group of host-device side codes. The joint optimization pass is applied to fully explore the hotspots of performance optimization and improvement from a global perspective.

[0042] Specifically, based on the compiler's source code segmentation stage, the calling relationship of the code module quality inspection on the host side and the device side is obtained. Generally speaking, the host side function implements the encapsulation and calling of the device side function. The code block parsed in the source code segmentation stage (that is, the Clang stage) retains the calling relationship between the host side and the device side code segments, so the corresponding calling relationship can be obtained. Here, the dependency relationship between the code blocks can also be obtained based on the calling relationship.

[0043] According to the calling relationship, the independent optimization results of the host side and the device side are grouped, and according to the grouping results, the independent optimization results of the host side and the device side are jointly compiled. The host side and the device side functions are grouped according to the existing calling dependencies, and for the grouped code blocks, the Pass corresponding to the joint compilation is selected from the stage set (Pass set) and applied. The selected Pass is used to perform an overall analysis of the entire code block on the host side and the device side, and the joint compilation is achieved by comprehensively considering the front-to-back dependencies of the host side and the device side codes.

[0044] S105: Run the code based on the joint compilation result, and perform automatic tuning based on the feedback of the running result until a final executable file is generated.

[0045] Run the jointly compiled code, collect performance data based on the feedback of the running results, and perform tuning based on the feedback, so as to finally compile the output and generate the final executable file through the linker.

[0046] Specifically, for each combination of optimization passes, that is, the combination of optimization strategies adopted by each independent optimization and joint compilation, a cost evaluation model for evaluation is determined, and the data transmission time, computing time, memory usage, bandwidth occupancy, and computing resource utilization of the optimized program are used as the basis for decision-making. The shorter the data transmission time and computing time of the optimized program, the lower the memory usage, the lower the bandwidth occupancy and the lower the resource utilization, the lower the combination cost of the corresponding situation, and the higher the performance benefit brought by adopting this situation.

[0047] Based on this, the code is run based on the joint compilation result, and the code running result is obtained based on the preset dimension feedback; wherein the preset dimension includes at least one of program data transmission time, calculation time, memory usage, bandwidth occupancy, and computing resource utilization.

[0048] Determine a pre-generated cost evaluation model, input the code running results into the cost evaluation model, output the evaluation optimization cost, and iteratively tune the independent optimization on the host side and / or device side according to the evaluation optimization cost until the output evaluation optimization cost meets expectations, or the number of iterations reaches a preset upper limit.

[0049] Furthermore, in the cost evaluation model, the total cost is obtained based on the weighted sum of transmission cost, computing cost, memory cost, bandwidth cost, and computing resource cost.

[0050] Among them, the transmission cost is based on the transmission cost per unit time and the data transmission time; the computing cost is based on the cost per unit computing time and the computing time, and the computing time is obtained by summing up the sub-computing times corresponding to the host side and the device side respectively; the memory cost is based on the cost per unit memory usage and the memory usage, and the memory usage is obtained by summing up the sub-memory usages corresponding to the host side and the device side respectively; the bandwidth cost is based on the cost per unit bandwidth usage and the bandwidth occupancy; the computing resource cost is based on the cost per unit computing resource usage and the computing resource usage, and the computing resource usage is obtained by summing up the sub-computing resource usages corresponding to the host side and the device side respectively.

[0051] Among them, the cost of transmission per unit time, the cost per unit computing time, the cost per unit memory usage, the cost per unit bandwidth usage, the cost per unit computing resource usage, etc. can be called cost factors. Each cost factor can be obtained through experiments and expert experience data, and can reflect the proportion of each cost more truly and objectively.

[0052] Here, each cost can be weighted and summed in a linear manner to obtain the total cost, as shown in Formula 1.

[0053] Formula 1;

[0054] in, is the total cost, is the transmission cost per unit time, is the cost per unit of computing time, is the cost per unit of memory usage, is the cost per unit of bandwidth used, is the cost per unit of computing resource usage, is the data transmission time, , To calculate the time, , are the sub-computation times corresponding to the host side and the device side respectively, , is the memory usage, , They are the corresponding sub-memory usage on the host side and the device side, is the bandwidth usage, , To calculate resource usage, , They are the usage of sub-computing resources on the host side and the device side respectively.

[0055] In order to more realistically characterize the relationship between cost and the usage of each resource, nonlinearity is introduced into the cost model. Considering the impact of bandwidth and computing resource usage on the results, the transmission cost, computing cost, and memory cost are set to be calculated based on linear functions, and the bandwidth cost and computing resource cost are calculated using exponential functions.

[0056] The bandwidth cost and computing resource cost are shown in Formula 2.

[0057] Formula 2: Wherein, Y corresponds to bandwidth cost or computing resources, C corresponds to the cost per unit of bandwidth usage or the cost per unit of computing resources usage, and X corresponds to the bandwidth occupancy or computing resource usage. is an exponential function.

[0058] Based on this, according to the expression of Formula 2, Formula 1 is adjusted to be as shown in Formula 3.

[0059] Formula three.

[0060] Corresponding to Formula 2 , which is an exponential function, and its expression is shown in Formula 4.

[0061] Formula 4: is the preset constant, is the initial value corresponding to the bandwidth cost or computing resource cost.

[0062] Based on this, the bandwidth cost and computing resource cost are described by formula 4, and formulas 5 and 6 corresponding to the bandwidth cost and computing resource cost are obtained respectively.

[0063] Formula 5; where B>0, is the initial value of bandwidth cost.

[0064] Formula 6: Where R>0, It is the initial value of computing resource cost.

[0065] The preset constants are 1.2 and 1.7, which are obtained by combining experiments and expert experience. In actual work, the values ​​can be adjusted based on different on-site environments. Generally speaking, the preset constants of bandwidth cost range from 1.0 to 1.4, and the preset constants of computing resource cost range from 1.5 to 1.9.

[0066] The reason for considering using the exponential function is that the exponential function can better reflect the characteristics that with the increase of bandwidth and the utilization of computing resources, the bandwidth cost and computing resource cost increase at an increasingly faster rate. This calculation method simulates the increase of per unit bandwidth cost with the increase of bandwidth and the increase of per unit computing resource usage cost with the increase of computing resource utilization. Compared with the linear function method, it can better fit the actual situation.

[0067] like Figure 5 As shown, after the cost evaluation model is determined, each optimization combination is automatically tuned based on the cost evaluation model. Here, a greedy algorithm can be used for automatic tuning, and a new set of optimization combinations is reselected. The above process is iterated again until a set that meets the requirements is found or the upper limit of the number of iterations is reached. The iteration is exited and the best set of all current situations, that is, the set with the lowest evaluated optimization cost, is taken as the final result.

[0068] Specifically, all optimization combinations that can be formed by the optimization strategies in the independent optimization on the host side and the device side are obtained, and a search space is formed according to all the optimization combinations.

[0069] The optimal combination of the optimization strategies of the current independent optimizations on the host side and the device side is taken as an initial candidate solution, and the optimization strategies in the initial candidate solution are adjusted to search for a new optimal combination in the search space.

[0070] The adjustments may include adding, deleting, replacing, changing specific parameters, adjusting the order of strategies, etc., and the adjustment direction (that is, which optimization strategies are adjusted first and how to adjust them) may be random or manually specified.

[0071] If the new optimization combination has a higher evaluation optimization cost than the initial candidate solution, it means that the search direction is wrong. Change the search direction and perform a reverse search (for example, if the original search direction is to increase a certain value, then the reverse search direction is to reduce a certain value, or if the original search direction is to add a certain optimization strategy, then the reverse search direction is to delete a certain optimization strategy), and update the search space. Consider that the new optimization combination is a cross combination and exclude the new optimization combination.

[0072] If the new optimization combination has a lower evaluation optimization cost than the initial candidate solution, the current search direction is considered to be the correct search direction, and the search is continued in the current search direction until the evaluation optimization cost of the local optimal solution found meets expectations (usually the evaluation optimization cost is the lowest, or lower than the preset value), or the number of search iterations reaches the preset upper limit. Of course, different local optimal solutions may be generated for different initial candidate solutions. Here, new initial candidate solutions can be created based on demand to generate multiple local optimal solutions for comparison.

[0073] By combining the host-side and device-side program codes through joint compilation technology, the program can be optimized from a global perspective, improving the compilation efficiency and application performance in heterogeneous computing environments. In view of the impact of different optimization strategies on performance when jointly compiling the host-side and device-side codes, a cost evaluation model is established through multiple dimensions, and nonlinear factors are introduced to characterize the impact of bandwidth and computing resources on the cost evaluation model, which more realistically reflects the impact of various factors on the cost. A greedy algorithm is used for iterative search to ensure the optimization of the final program performance.

[0074] like Figure 6 As shown, the embodiment of the present application also proposes a joint compilation optimization device for heterogeneous computing, including:

[0075] at least one processor; and,

[0076] a memory communicatively connected to the at least one processor; wherein,

[0077] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the joint compilation optimization method for heterogeneous computing as described in any of the above embodiments.

[0078] The embodiment of the present application further proposes a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured as: the joint compilation optimization method for heterogeneous computing described in any of the above embodiments.

[0079] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0080] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0081] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0082] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0083] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0084] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0085] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0086] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0087] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0088] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0089] The above is only the embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the present application.

Claims

1. A joint compilation optimization method for heterogeneous computing, characterized in that: include: Obtaining source code and preprocessing the source code; The source code is segmented based on keywords to obtain code modules corresponding to the host side and the device side, respectively, and the code modules are mapped to obtain corresponding intermediate representations; For either the host side or the device side, independently optimizing the intermediate representation corresponding to itself according to the compilation optimization stage set in the compiler; Obtaining independent optimization results of the host side and the device side, and jointly compiling the independent optimization results; Run the code based on the joint compilation results, and automatically tune based on the feedback results until the final executable file is generated; Run the code based on the joint compilation results, and automatically tune based on the feedback results until the final executable file is generated, including: The code is run based on the joint compilation result, and the code running result is obtained based on the preset dimension feedback; wherein the preset dimension includes at least one of program data transmission time, computing time, memory usage, bandwidth occupancy, and computing resource utilization; Determine a pre-generated cost evaluation model, input the code running result into the cost evaluation model, and output the evaluation optimization cost; According to the evaluation optimization cost, iteratively tune the independent optimization of the host side and / or the device side until the output evaluation optimization cost meets expectations, or the number of iterations reaches a preset upper limit; In the cost evaluation model, the total cost is obtained based on the weighted sum of transmission cost, computing cost, memory cost, bandwidth cost, and computing resource cost; The transmission cost is obtained based on the transmission cost per unit time and the data transmission time; The computing cost is obtained based on the cost per unit computing time and the computing time; the computing time is obtained by summing up the sub-computing times corresponding to the host side and the device side respectively; The memory cost is obtained based on the cost per unit of memory usage and the memory usage; the memory usage is obtained by summing the sub-memory usages corresponding to the host side and the device side respectively; Bandwidth cost is obtained based on the cost per unit of bandwidth used and the bandwidth usage; The computing resource cost is obtained based on the cost per unit of computing resource usage and the computing resource usage; the computing resource usage is obtained by summing the sub-computing resource usages corresponding to the host side and the device side respectively; The transmission cost, the computing cost, and the memory cost are calculated based on a linear function; The bandwidth cost and the computing resource cost are calculated by using an exponential function; The calculation expressions of the bandwidth cost and the computing resource cost are: , where Y corresponds to bandwidth cost or computing resources, C corresponds to the cost per unit of bandwidth usage or the cost per unit of computing resources usage, and X corresponds to the bandwidth usage or computing resource usage. is an exponential function; ,in, is the preset constant, is the initial value corresponding to the bandwidth cost or computing resource cost.

2. The method according to claim 1, characterized in that The source code is segmented based on keywords to obtain code modules corresponding to the host side and the device side, respectively, and the code modules are mapped to obtain corresponding intermediate representations, specifically including: Input the source code into a front-end compiler, and split it by reserved keywords in the compiler to obtain code modules corresponding to the host side and the device side respectively; Perform syntax analysis on each code module to build the corresponding abstract syntax tree; According to the abstract syntax tree, the code module is mapped into a corresponding intermediate representation through a language conversion module.

3. The method according to claim 1, characterized in that For either the host side or the device side, according to the compilation optimization stage set in the compiler, the intermediate representation corresponding to the device side is independently optimized, specifically including: For any one of the host side and the device side, determine the compile manager of the compile manager, and independently optimize the intermediate representation corresponding to the compile manager based on the compile optimization stage set in the compile manager; The independent optimization includes one or more optimization strategies of constant folding, dead code elimination, loop unrolling, loop merging, branch elimination, and data blocking.

4. The method according to claim 1, characterized in that: The independent optimization results are jointly compiled, specifically including: Based on the compiler in the cutting stage of the source code, the calling relationship of the code module quality inspection on the host side and the device side is obtained; The independent optimization results of the host side and the device side are grouped according to the calling relationship, and the independent optimization results of the host side and the device side are jointly compiled according to the grouping result.

5. A joint compilation optimization device for heterogeneous computing, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the joint compilation optimization method for heterogeneous computing as described in any one of claims 1 to 4.

6. A non-volatile computer storage medium storing computer executable instructions, characterized in that: The computer executable instructions are configured as a joint compilation optimization method for heterogeneous computing as described in any one of claims 1 to 4.

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