CXL-based ddr4 / 5 memory expansion controller error checking and correction method

Abstract

The application discloses a CXL-based DDR4 / 5 memory expansion controller error checking and correction method, comprising the following steps: configuring a CXL protocol in a CPU; reading and writing 64-byte data of a memory by the CPU through a CXL from a memory controller; generating N groups of 8-bit Side-Band ECC according to the front and rear halves of each N burst; and checking and correcting according to error results, so that the application has the opportunity to correct the error, and solves the problem that the existing MC error checking and correction method cannot guarantee accurate error correction when two or more errors occur in each burst.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer storage, and in particular to a CXL-based DDR4 / 5 memory expansion controller error checking and correction method. BACKGROUND

[0002] CXL (Compute Express Link) technology is an open standard for high-speed, high-capacity CPU-to-device and CPU-to-memory connections, designed for high-performance data center computers. It is built on the serial PCI Express (PCIe) physical and electrical interface, including a PCIe-based block input / output protocol (CXL.io) and a new cache coherency protocol for accessing system memory (CXL.cache) and device memory (CXL.mem). Serial communication and pool functions enable CXL memory to overcome the performance and socket packaging limitations of common DRAM DIMM memory when achieving high storage capacity.

[0003] The CXL memory expansion controller chip is a CXL DRAM memory controller, which belongs to the third type of device defined by the CXL protocol. The chip supports JEDEC DDR4 / 5 standards and also complies with CXL 1.1 / 2.0 specifications, supporting PCIe 5.0 rates. The chip provides a high-bandwidth, low-latency high-speed interconnection solution for CPU and CXL protocol-based device memory, enabling memory sharing between CPU and various CXL device memories, significantly reducing software stack complexity and total cost of ownership (TCO) of data centers while greatly improving system performance.

[0004] In the prior art, as memory rates, grain densities, and application numbers increase, memory failure rates also increase, and RAS features of the memory become particularly important. DDR5 introduces a new function, On-Die ECC, to enhance the RAS features of the memory relative to DDR4.

[0005] Error checking and correction of the memory controller (MC) is achieved by adding additional ECC grains (referred to as Side-Band ECC) to the memory, and the process is implemented by the MC, which only allows one error per burst of data (DDR4 64 bits or DDR5 32 bits). When two or more errors occur per burst, accurate error correction cannot be guaranteed. SUMMARY

[0006] This section is intended to introduce the reader to various aspects of the present embodiments of the present invention, which are described below, and which have a bearing on fully understanding the application. This section is not intended to limit the scope of the application in any way.

[0007] In view of the problems existing in the prior art MC error checking and correction method, the present application is proposed.

[0008] Therefore, the present application solves the technical problem that the prior art MC error checking and correction method cannot guarantee accurate error correction when 2 or more errors occur in each burst.

[0009] To solve the above technical problems, the present application provides the following technical solutions: a CXL-based DDR4 / 5 memory expansion controller error checking and correction method, comprising the following steps: S1: configuring a CXL protocol in a CPU; S2: the CPU reads and writes 64-byte data from a memory controller through CXL, and the amount of data read and written each time is 64 bytes, i.e. 8 64-bit bursts; S3: generating 8 reorganized 64-bit bursts from the front and back halves of the original 8 64-bit bursts, respectively, and then generating 8 groups of 8-bit Side-Band ECC from the 8 reorganized 64-bit bursts, and performing checking and correction according to the error results.

[0010] As a preferred scheme of the CXL-based DDR4 / 5 memory expansion controller error checking and correction method, when 2 or more errors occur in each original 64-bit burst, the 8 groups of 8-bit Side-Band ECC generated by the 8 reorganized 64-bit bursts complete accurate error correction.

[0011] As a preferred scheme of the CXL-based DDR4 / 5 memory expansion controller error checking and correction method, the particle width of the DDR4 / 5 DRAM includes 4 bits, 8 bits, and 16 bits; each original burst and each reorganized burst is a 64-bit burst; each reorganized 64-bit burst generates a group of 8-bit Side-Band ECC, and 8 reorganized 64-bit bursts generate 8 groups of 8-bit Side-Band ECC; each reorganized 64-bit burst can generate 2 errors that may occur in the original 64-bit burst according to the front and back halves of the original 8 64-bit bursts to complete accurate error correction.

[0012] The application provides a CXL-based DDR4 / 5 memory expansion controller error checking and correction method. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings. Among them:

[0014] Figure 1 The overall method flowchart of the CXL-based DDR4 / 5 memory expansion controller error checking and correction method provided by the present application.

[0015] Figure 2 The functional block diagram of the CXL DDR4 / 5 applied to the PC host.

[0016] Figure 3 The chip module diagram of the communication protocol between the PC host CPU and the DDR4 / 5 CXL memory controller.

[0017] Figure 4 The first chip display diagram of the CXL interface DDR4 / 5 memory which is already commercially available on the market and is related to the present application.

[0018] Figure 5 The second chip display diagram of the CXL interface DDR4 / 5 memory which is already commercially available on the market and is related to the present application.

[0019] Figure 6 The grain diagram of the DDR5 DRAM x4 used in the present application.

[0020] Figure 7 The comparison diagram of the present application and the prior art. DETAILED DESCRIPTION

[0021] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the present application.

[0022] The CXL memory expansion controller chip is a CXLDRAM memory controller, which belongs to the third type of device defined in the CXL protocol. The chip supports the JEDEC DDR4 / 5 standard, and also meets the CXL 1.1 / 2.0 specification, and supports the rate of PCIe 5.0. The chip can provide a high-bandwidth, low-latency high-speed interconnection solution for CPU and CXL protocol-based device memory, thereby realizing memory sharing between CPU and each CXL device memory, greatly improving system performance, and significantly reducing software stack complexity and total cost of ownership (TCO) of data center.

[0023] As shown in Figure 2 , CXL DDR4 / 5 has been widely applied to PC host.

[0024] With the increase of memory rate, particle density and application quantity, the memory failure rate also increases, and the RAS characteristics of the memory are particularly important. DDR5 introduces a new function On-Die ECC to enhance the RAS characteristics of the memory compared with DDR4.

[0025] The error checking and correction of the memory controller Memory Controller (MC) is realized by adding an additional ECC particle (called Side-Band ECC) to the memory, and the process is realized by the MC, which only allows one error per burst of data (DDR464bit or DDR532bit). When two or more errors occur in each burst, accurate error correction cannot be guaranteed.

[0026] As shown in Figure 3 , it is the communication protocol between PC host CPU and DDR4 / 5 CXL memory controller.

[0027] As shown in Figure 4 , it is the DDR4 / 5 memory of the CXL interface that can be directly used DDR4 / 5 DIMM module.

[0028] As shown in Figure 5 , it is the DDR4 / 5 memory of the CXL interface that can be directly used DDR4 / 5 part particle.

[0029] In the prior art, with the increase of memory rate (i.e. DDR4 / 5 interface working rate), particle density (i.e. the capacity of DDR4 / 5 memory particles) and the number of applications, the memory failure rate also increases, and the RAS characteristics of the memory become particularly important. DDR5 introduces a new function On-Die ECC to enhance the RAS characteristics of the memory relative to DDR4.

[0030] The error checking and correction of the memory controller Memory Controller (MC) is realized by adding an additional ECC particle (referred to as Side-Band ECC) to the memory (such as 32 bits or 64 bits, which requires an additional 8 bits for ECC use), and the process is realized by the MC (ECC is automatically generated by the MC memory controller hardware), which only allows one error per burst of data (DDR464bit or DDR532bit) (whether more than one bit error occurs is automatically judged by the ECC algorithm), and when two or more errors occur per burst, accurate error correction cannot be guaranteed.

[0031] It should be noted that when two or more errors occur per burst (32 bits or 64 bits), the burst data error is defined.

[0032] It should be noted that the particle width of DDR4 / 5 DRAM is 4 bits, 8 bits, 16 bits.

[0033] Therefore, please refer to Figure 1 The present application provides a CXL-based DDR4 / 5 memory expansion controller error checking and correction method, comprising the following steps:

[0034] S1: configuring a CXL protocol in a CPU;

[0035] S2: The CPU reads and writes 64-byte data from the memory controller through the CXL, which is equivalent to multiple bursts (8x DDR464bit or 16x DDR532bit) of memory data. The amount of data read and written by the CPU through the CXL protocol each time is 64 bytes, which is equivalent to 8 groups of 64-bit bursts;

[0036] S3: According to the front and back half of each N burst, N groups of 8-bit Side-Band ECC are generated, and error checking and correction is performed according to the error result.

[0037] Further, when two errors occur in a certain burst during error checking and correction according to the error result, accurate error correction is completed.

[0038] wherein the condition for completing error correction is that when one of the bursts has 2 errors and the other burst has no error at all.

[0039] Specifically, the conventional memory error checking and correction is to generate a set of 8-bit Side-Band ECC (DDR4 64 bits -> 72 bits or DDR5 32 bits -> 40 bits) according to each burst, and the present application is to generate two sets of 8-bit Side-Band ECC according to the front and back halves of each two bursts, such as: DDR4 (1st burst 32 + 2nd burst 32) bits -> 72 bits or DDR5 (1st burst 16 + 2nd burst 16) bits -> 40 bits.

[0040] As shown in Figure 6 , it is indicated that the use of a grain of DDR5 DRAM x4, a total of 20, 20 x 4 = 80 bits, 8 bits of ECC will be generated every 32 bits, (32 + 8) x 2 = 80.

[0041] Compared with the prior art, if 2 errors are generated, even if ECC has been used, it cannot be corrected, and by using the present application, it has the opportunity to be corrected, which is the result of the principle of ECC plus the arrangement of data placement.

[0042] Please refer to Figure 7 , the existing method is to generate a set of 8-bit ECC for each set of burst 64 bits to correct 1-bit error, and the present application uses two sets of adjacent bursts of 64 bits each to take out 32 bits from each to form 64 bits to generate a set of 8-bit ECC, so there is a chance to correct 2-bit errors in a set of 64 bits.

[0043] The present application can also be extended to combine every 4 sets of 64 bits to correct up to 4-bit errors in a set of 64 bits, or combine every 8 sets of 64 bits to correct up to 8-bit errors in a set of 64 bits, or combine every 16 sets of 64 bits to correct up to 16-bit errors in a set of 64 bits, or combine every 32 sets of 64 bits to correct up to 32-bit errors in a set of 64 bits, or combine every 64 sets of 64 bits to correct up to 64-bit errors in a set of 64 bits.

[0044] If it is used to correct up to 4 bits errors in 1 group of 64 bits every 4 groups of 64 bits, 16 bits in each group of 64 bits are taken out to generate 8 bits ECC;

[0045] If it is used to correct up to 8 bits errors in 1 group of 64 bits every 8 groups of 64 bits, 8 bits in each group of 64 bits are taken out to generate 8 bits ECC;

[0046] If it is used to correct up to 16 bits errors in 1 group of 64 bits every 16 groups of 64 bits, 4 bits in each group of 64 bits are taken out to generate 8 bits ECC;

[0047] If it is used to correct up to 32 bits errors in 1 group of 64 bits every 32 groups of 64 bits, 2 bits in each group of 64 bits are taken out to generate 8 bits ECC;

[0048] If it is used to correct up to 64 bits errors in 1 group of 64 bits every 64 groups of 64 bits, 1 bit in each group of 64 bits is taken out to generate 8 bits ECC.

[0049] It should be noted that the present application is not limited to DDR4 / 5, and any DDR DRAM that needs to use ECC can be applicable.

[0050] In summary, the present application provides a CXL-based DDR4 / 5 memory expansion controller error checking and correction method. Compared with the prior art, if 2 errors are generated, even if ECC has been used, the present application can still correct the errors. The problem that the existing MC error checking and correction method cannot guarantee accurate error correction when 2 or more errors occur in each burst is solved.

[0051] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application, and they should be covered in the scope of the claims of the present application.

Claims

1. A method for error checking and correction for CXL-based DDR4 / 5 memory expansion controller, characterized in that, The method comprises the following steps: S1: configuring CXL protocol in CPU; S2: CPU reads and writes 64 bytes of data from the memory controller through CXL, and the data amount of each read and write is 64 bytes, i.e. 8 64 bits bursts; S3: 8 64 bits bursts are reorganized according to the front and back halves of the original 8 64 bits bursts, and 8 groups of 8 bit Side-Band ECC are generated from the reorganized 8 64 bits bursts, and error correction is performed according to the error result; Wherein, when 2 or more errors occur in each original 64 bits burst, 8 groups of 8 bit Side-Band ECC generated from the reorganized 8 64 bits bursts complete accurate error correction; Wherein, the grain width of DDR4 / 5 DRAM includes 4 bits, 8 bits and 16 bits; Wherein, each original burst and reorganized burst is 64 bits; Wherein, 1 group of 8 bit Side-Band ECC is generated from each reorganized 64 bits burst, and 8 groups of 8 bit Side-Band ECC are generated from 8 reorganized 64 bits bursts; Wherein, 2 errors that may occur in the original 64 bits burst to complete accurate error correction can be generated from each reorganized 64 bits burst according to the front and back halves of the original 8 64 bits bursts.

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