Display panel and display device

Abstract

The present application provides a display panel and a display device; the display panel is provided with at least one compensation signal line, so that the input module of the n+i-th level gate driving unit and the pull-down module of the n-j-th level gate driving unit are connected to the compensation signal line, the pulse width and amplitude of the effective pulse of the output signal of the compensation signal line are respectively equal to the pulse width and amplitude of the output signal of the output signal end of the n-j-th level gate driving unit, and the effective pulse of the output signal of the compensation signal line differs from the effective pulse of the output signal of the output signal end of the n-j-th level gate driving unit by j*m unit time lengths. When the output signal of the output signal end of the n-th level gate driving unit is abnormal, the abnormal level transmission signal can be repaired through the compensation signal line, so that the output signals of the subsequent levels of gate driving units are normal, thereby making the level transmission of the gate driving circuit normal and making the display panel display normally.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the requirements of display devices for low cost and high screen-to-body ratio have become higher. In order to reduce costs and increase screen-to-body ratio, existing display devices will adopt gate driver on array (GOA) technology to replace the technology of setting gate driver chips in the original display devices. Specifically, the gate driver circuit refers to the input of the thin film transistor control signal formed on the array substrate, thereby eliminating the cost and space occupied by the gate driver chip and realizing a narrow frame design. In the gate driver circuit, except for the first row of gate driver units that are turned on by the start signal, the gate driver units of other rows all use the output signal of the gate driver unit of the previous row as the start signal, which will cause the output signal of the gate driver unit of a certain row to be abnormal, resulting in a level transmission abnormality, which in turn causes the output signals of all subsequent rows of gate driver units to be abnormal, thereby causing display abnormality.

[0003] Therefore, the existing gate driving circuit has a technical problem that abnormal output signals of a row of gate driving units may lead to abnormal stage transmission. Summary of the Invention

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem in existing gate driving circuits where abnormal output signals of a row of gate driving units can lead to abnormal stage transmission.

[0005] An embodiment of the present application provides a display panel, comprising a display portion and a gate driving circuit located on at least one side of the display portion, wherein the gate driving circuit comprises a plurality of cascaded gate driving units, each of which comprises:

[0006] Input module;

[0007] an output module, comprising an output signal terminal, the output module being connected to the input module, and the output module being configured to control an output signal of the output signal terminal according to an output signal of the input module;

[0008] A pull-down module connected to the output module;

[0009] Wherein, the display panel further includes at least one compensation signal line, the input module of the n+i-th level gate driving unit is disconnected from the output signal end of the n-th level gate driving unit, the input module of the n+i-th level gate driving unit is connected to the compensation signal line, the pull-down module of the nj-th level gate driving unit is disconnected from the output signal end of the n-th level gate driving unit, the pull-down module of the nj-th level gate driving unit is connected to the compensation signal line, and the pulse width of the effective pulse of the output signal of the compensation signal line is the same as the output signal end of the nj-th level gate driving unit. The pulse widths of the effective pulses of the output signals of the signal terminals are equal, the amplitude of the effective pulses of the output signals of the compensation signal line is equal to the amplitude of the effective pulses of the output signals of the output signal terminals of the nj-th level gate driving units, the phase difference between the effective pulses of the output signals of the compensation signal line and the effective pulses of the output signals of the output signal terminals of the nj-th level gate driving units is j*m unit time lengths, n is greater than or equal to 2, n is less than the number of levels of the gate driving units, i is greater than or equal to 1, and i is less than n, j is greater than or equal to 1, and j is less than n, i, j, and n are all positive integers, and m is greater than 0.

[0010] In some embodiments, the input module includes an input transistor, wherein a gate of the input transistor is connected to a first electrode of the input transistor;

[0011] The output module includes an output transistor, the gate of the output transistor is connected to the second electrode of the input transistor, and the second electrode of the output transistor is connected to the output signal terminal;

[0012] The pull-down module includes a first pull-down transistor and a second pull-down transistor, wherein the gate of the first pull-down transistor is connected to the gate of the second pull-down transistor, the second electrode of the first pull-down transistor is connected to the second electrode of the input transistor, and the second electrode of the second pull-down transistor is connected to the output signal terminal;

[0013] In which, the display panel also includes a start signal line, a clock signal line and a low-potential signal line, the first electrode of the output transistor is connected to the clock signal line, the first electrode of the first pull-down transistor and the first electrode of the second pull-down transistor are connected to the low-potential signal line, the gate of the input transistor in the first-level gate driving unit is connected to the start signal line, the gate of the input transistor of the gate driving unit of other levels is connected to the output signal end of the gate driving unit of the previous level, the gate of the first pull-down transistor in the gate driving unit of the last level is connected to the start signal line, and the gate of the first pull-down transistor in the gate driving unit of other levels is connected to the output signal end of the gate driving unit of the next level.

[0014] In some embodiments, the display panel includes at least two compensation signal lines, one compensation signal line is connected to the input module of the n+i-th level gate driving unit and the pull-down module of the nj-th level gate driving unit, and the other compensation signal line is connected to other modules, and the timing of the two compensation signal lines is different.

[0015] In some embodiments, the display panel also includes a clock signal line, and the clock signal line includes a first clock signal line and a second clock signal line. In two adjacent levels of the gate driving units, the output module of one level of the gate driving unit is disconnected from the first clock signal line, and the output module of the gate driving unit is connected to the other compensation signal line, and the output module of the other level of the gate driving unit is connected to the second clock signal line.

[0016] In some embodiments, the display panel further includes a low-potential signal line, the pull-down modules of the gate driving units at each stage are disconnected from the low-potential signal line, and the pull-down modules of the gate driving units at each stage are connected to another compensation signal line.

[0017] In some embodiments, the output signal terminal of the last-stage gate driving unit is disconnected from the pull-down module of the previous-stage gate driving unit, and the pull-down module of the previous-stage gate driving unit is connected to another compensation signal line.

[0018] In some embodiments, the display panel also includes a start signal line, the input module of the first-level gate driving unit is disconnected from the start signal line, the pull-down module of the last-level gate driving unit is disconnected from the start signal line, the input module of the first-level gate driving unit is connected to another compensation signal line, and the pull-down module of the last-level gate driving unit is connected to another compensation signal line.

[0019] In some embodiments, the display panel includes a plurality of compensation signal lines arranged at intervals, the pull-down modules of the upper-level gate driving units of the multi-level gate driving units are respectively connected to the plurality of compensation signal lines, and the input modules of the lower-level gate driving units of the multi-level gate driving units are respectively connected to the plurality of compensation signal lines.

[0020] In some embodiments, the display portion is provided with a scan line, and the gate drive circuit is arranged on both sides of the display portion, the output signal end of the gate drive unit on one side is disconnected from the scan line, and the output signal end of the gate drive unit on the other side is connected to the scan line.

[0021] At the same time, an embodiment of the present application provides a display device, which includes the display panel as described in any of the above embodiments.

[0022] Beneficial effect: The present application provides a display panel and a display device; the display panel is provided with at least one compensation signal line, so that the input module of the n+i-th level gate driving unit and the pull-down module of the nj-th level gate driving unit are disconnected from the output signal end of the n-th level gate driving unit, and the input module of the n+i-th level gate driving unit and the pull-down module of the nj-th level gate driving unit are connected to the compensation signal line, the pulse width and amplitude of the effective pulse of the output signal of the compensation signal line are respectively equal to the pulse width and amplitude of the output signal of the output signal end of the nj-th level gate driving unit, and the effective pulse of the output signal of the compensation signal line differs from the effective pulse of the output signal of the output signal end of the nj-th level gate driving unit by j*m unit time lengths, so that when the output signal of the output signal end of the n-th level gate driving unit is abnormal, the abnormal level transmission signal can be repaired through the compensation signal line, so that the output signals of the subsequent levels of gate driving units are normal, thereby making the level transmission of the gate driving circuit normal and making the display panel display normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0024] Figure 1 A schematic diagram of a comparative gate drive circuit provided in an embodiment of the present application.

[0025] Figure 2 This is a circuit diagram and timing diagram of the comparative gate drive circuit provided in an embodiment of the present application when it is operating normally.

[0026] Figure 3 This is a circuit diagram of a comparison gate drive circuit provided in an embodiment of the present application when it operates abnormally.

[0027] Figure 4 A schematic diagram of a display panel provided in an embodiment of the present application.

[0028] Figure 5 A circuit diagram of a gate drive circuit provided in an embodiment of the present application.

[0029] Figure 6 for Figure 5 Timing diagram of the gate drive circuit in . DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0031] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0032] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0033] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0034] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0035] Figure 1 A schematic diagram of a comparative gate drive circuit provided in an embodiment of the present application; Figure 1 (a) is a schematic diagram of a comparative gate drive circuit provided in an embodiment of the present application when it is operating normally; Figure 1 (b) is a schematic diagram of the comparative gate drive circuit provided in an embodiment of the present application when it operates abnormally. Figure 2 A circuit diagram and a timing diagram of a comparative gate drive circuit provided in an embodiment of the present application during normal operation; Figure 2 (a) is a circuit diagram of a comparative gate drive circuit provided in an embodiment of the present application when it is operating normally; Figure 2 (b) is a timing diagram of the comparative gate drive circuit provided in an embodiment of the present application when it operates normally. Figure 3 This is a circuit diagram of a comparison gate drive circuit provided in an embodiment of the present application when it operates abnormally.

[0036] As an introduction to the embodiments of the present application, some comparative gate drive circuits are provided to illustrate the principles of the technical problems to be solved by the embodiments of the present application. Figure 1 As shown, the contrast gate driving circuit includes a plurality of cascaded contrast gate driving units 101, each contrast gate driving unit 101 is connected to the first clock line CK0 and the second clock line XCK0, the first-stage contrast gate driving unit 101 is connected to the initial signal line STV, and outputs a signal to the first row scan line through the first output signal terminal OUT1, and the output signal of the first output signal terminal OUT1 will also serve as the initial signal of the second-stage contrast gate driving unit 101, and accordingly, the output signals of the second output signal terminal OUT2, the third output signal terminal OUT3 and the fourth output signal terminal OUT4 will all serve as the output signals of the next-stage contrast gate driving unit 101.

[0037] like Figure 1 As shown in (a), when the output signals of the output signal terminals of the contrast gate driving units 101 at all levels are normal, the level transmission of the contrast gate driving circuit is normal, and the output signals of the contrast gate driving units 101 at all levels are normal, so that the display panel displays normally, as shown in FIG. Figure 1As shown in (b), taking the abnormal output signal of the second output terminal OUT2 of the second-level contrast gate driving unit 101 as an example, the symbol "×" (cross) in the drawings in the embodiments of the present application represents the routing and / or signal terminal with abnormal signals. The reason for the abnormal output signal of the second output terminal OUT2 may be that it is short-circuited with other signals in the display area or the circuit of the gate driving unit of this row is abnormal. The embodiment of the present application does not limit this. It is only necessary to determine that the signal terminal or routing is abnormal. It can be seen that since the output signal of the second output terminal OUT2 is used as the initial signal of the third-level contrast gate driving unit 101, the output signal of the third output terminal OUT3 will be abnormal, which will cause the output signal of the fourth output terminal OUT4 and the output signals of the subsequent levels of contrast gate driving units 101 to be abnormal, resulting in display abnormality.

[0038] Specifically, Figure 2 、 Figure 3 The circuit diagram and timing diagram of the comparative gate drive circuit are shown as follows. Figure 2 As shown, each comparison gate driving unit 101 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4 as an example. The gate and the first electrode of the first transistor T1 of the first-stage comparison gate driving unit 101 are connected to the initial signal line STV, the gate and the first electrode of the first transistor T1 of the other-stage comparison gate driving units 101 are connected to the output signal terminal of the previous-stage comparison gate driving unit 101, the second electrode of the first transistor T1 is connected to the gate of the second transistor T2, the first electrode of the second transistor T2 of the first-stage comparison gate driving unit 101 is connected to the first clock line CK0, and the second transistor T2 of the other-stage comparison gate driving unit 101 is connected to the first clock line CK0. The first electrode of T2 is connected to the second clock line XCK0, the second electrode of the second transistor T2 is connected to the output signal terminal, the gates of the third transistor T3 and the fourth transistor T4 of the last-stage comparison gate driving unit 101 are connected to the initial signal line STV, the gates of the third transistor T3 and the fourth transistor T4 of the other-stage comparison gate driving units 101 are connected to the output signal terminal of the next-stage comparison gate driving unit 101, the first electrodes of the third transistor T3 and the fourth transistor T4 are connected to the low potential line VSS0, the second electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, and the second electrode of the fourth transistor T4 is connected to the second electrode of the second transistor T2.

[0039] Specifically, Figure 2 、 Figure 3In the description, the comparison gate driving circuit includes 1080 levels of comparison gate driving units. Accordingly, there are 1080 output signal lines, including the first output signal line G0(1) of the first level comparison gate driving unit, the second output signal line G0(2) of the second level comparison gate driving unit, the third output signal line G0(3) of the third level comparison gate driving unit, the fourth output signal line G0(4) of the fourth level comparison gate driving unit, the 1079th output signal line G0(1079) of the 1079th level comparison gate driving unit and the 1080th output signal line G0(1079) of the 1080th level comparison gate driving unit. The timing is as follows: Figure 2 As shown in (a), it can be seen that when the signals output by each output signal line are normal, the gate drive circuit level is normal, but when the signals output by the output signal line are abnormal, such as Figure 3 As shown, taking the abnormal signal output by the third output signal line G0(3) as an example, it can be seen that the signal output by the third output signal line G0(3) will be used as the initial signal of the fourth-level comparison gate drive unit, which will cause the signal output by the fourth output signal line G0(4) to be abnormal, and then cause the output signals of all subsequent output signal lines to be abnormal. The output signals of each output signal line will be transmitted to the scan line to drive the pixel to emit light, which will cause the display device to have a poor display problem. Therefore, the existing gate drive circuit has a technical problem that the abnormal output signal of a row of gate drive units will cause abnormal level transmission.

[0040] In order to solve the above technical problems, the embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0041] like Figures 4 to 6 As shown, an embodiment of the present application provides a display panel, which includes a display portion 21 and a gate drive circuit 22 located on at least one side of the display portion 21, wherein the gate drive circuit 22 includes a plurality of cascaded gate drive units 120, and the gate drive unit 120 includes an input module 10, an output module 20 and a pull-down module 30, the output module 20 includes an output signal terminal (for example, a first output signal terminal G(1)), the output module 20 is connected to the input module 10, and the output module 20 is configured to control the output signal of the output signal terminal according to the output signal of the input module 10, and the pull-down module 30 is connected to the output module 20.

[0042] In some embodiments, the display panel 2 further includes a compensation signal line STV-2, the input module 10 of the n+i-th level gate driving unit 120 is disconnected from the output signal end of the n-th level gate driving unit, the input module 10 of the n+i-th level gate driving unit 120 is connected to the compensation signal line STV-2, the pull-down module 30 of the nj-th level gate driving unit 120 is disconnected from the output signal end of the n-th level gate driving unit 120, the pull-down module 30 of the nj-th level gate driving unit 120 is connected to the compensation signal line STV-2, and the pulse width of the effective pulse of the output signal of the compensation signal line STV-2 is the same as that of the nj-th level. The pulse widths of the effective pulses of the output signals at the output signal ends of the gate drive units 120 are equal, the amplitudes of the effective pulses of the output signals of the compensation signal line STV-2 are equal to the amplitudes of the effective pulses of the output signals at the output signal ends of the nj-th gate drive units 120, and the phase difference between the effective pulses of the output signals of the compensation signal line STV-2 and the effective pulses of the output signals at the output signal ends of the nj-th gate drive units 120 is j*m unit time lengths H, where n is greater than or equal to 2, and n is less than the number of stages of the gate drive units, i is greater than or equal to 1, and i is less than n, j is greater than or equal to 1, and j is less than n, i, j, and n are all positive integers, and m is greater than 0.

[0043] Specifically, depending on the timing of the gate drive circuit, the phase difference between the output signals of the output signal ends of the two adjacent gate drive units may be greater than 1 unit time, less than 1 unit time, or 1 unit time. Therefore, according to different timings, the phase difference between the effective pulse of the output signal of the compensation signal line and the effective pulse of the output signal end of the gate drive unit 120 of the njth level is j*m unit time, where m can be a value greater than 1, a value less than 1, or 1. The embodiment of the present application is explained by taking m as 1 as an example.

[0044] An embodiment of the present application provides a display panel, which is provided with at least one compensation signal line, so that the input module of the n+i-th level gate driving unit and the pull-down module of the nj-th level gate driving unit are disconnected from the output signal end of the n-th level gate driving unit, and the input module of the n+i-th level gate driving unit and the pull-down module of the nj-th level gate driving unit are connected to the compensation signal line, the pulse width and amplitude of the effective pulse of the output signal of the compensation signal line are respectively equal to the pulse width and amplitude of the output signal of the output signal end of the nj-th level gate driving unit, and the effective pulse of the output signal of the compensation signal line differs from the effective pulse of the output signal end of the nj-th level gate driving unit by j*m unit time lengths, so that when the output signal of the output signal end of the n-th level gate driving unit is abnormal, the abnormal level transmission signal can be repaired through the compensation signal line, so that the output signals of the subsequent levels of gate driving units are normal, thereby making the level transmission of the gate driving circuit normal and making the display panel display normally.

[0045] Specifically, the position where the pull-down module 30 of the gate driving unit 120 of the nj-th stage is connected to the compensation signal line STV- 2 refers to the connection position of the gate of the transistor of the pull-down module of the nj-th stage gate driving unit.

[0046] In some embodiments, the display panel 2 further includes a start signal line STV-1 and a compensation signal line STV-2. When the output signal of the start signal line STV-1 is normal, the input module 10 of the first-level gate driving unit 120 is connected to the start signal line STV-1; when the output signal of the output signal end of the n-th level gate driving unit 120 is abnormal, the input module 10 of the n+i-th level gate driving unit 120 is disconnected from the output signal end of the n-th level gate driving unit, the input module 10 of the n+i-th level gate driving unit 120 is connected to the compensation signal line STV-2, the pull-down module 30 of the nj-th level gate driving unit 120 is disconnected from the output signal end of the n-th level gate driving unit 120, and the pull-down module 30 of the nj-th level gate driving unit 120 is disconnected from the output signal end of the n-th level gate driving unit 120. The pull module 30 is connected to the compensation signal line STV-2, and the pulse width of the effective pulse of the output signal of the compensation signal line STV-2 is equal to the pulse width of the effective pulse of the output signal of the output signal end of the nj-th gate driving unit 120, the amplitude of the effective pulse of the output signal of the compensation signal line STV-2 is equal to the amplitude of the effective pulse of the output signal of the output signal end of the nj-th gate driving unit 120, and the phase difference between the effective pulse of the output signal of the compensation signal line STV-2 and the effective pulse of the output signal of the output signal end of the nj-th gate driving unit 120 is j*m unit time lengths H, n is greater than or equal to 2, n is less than the number of levels of the gate driving unit, i is greater than or equal to 1, and i is less than n, j is greater than or equal to 1, and j is less than n, i, j, and n are all positive integers, and m is greater than 0. An embodiment of the present application provides a display panel; the display panel is provided with a starting signal line and a compensation signal line. When the output signal of the output signal end of the n-th gate driving unit is abnormal, the input module of the n+i-th gate driving unit is connected to the compensation signal line, and the pull-down module of the nj-th gate driving unit is connected to the compensation signal line. The output signal of the compensation signal line differs from the output signal of the output signal end of the nj-th gate driving unit by j unit time lengths. When the output signal of the output signal end of the n-th gate driving unit is abnormal, the abnormal level transmission signal can be repaired through the compensation signal line, so that the output signals of the subsequent gate driving units of each level are normal, thereby making the level transmission of the gate driving circuit normal and making the display panel display normally.

[0047] Specifically, the following embodiments are described using i and j as 1 as an example, but the embodiments of the present application are not limited thereto, and i and j can be other values.

[0048] Specifically, take n as 3 as an example, Figure 4 、 Figure 5 、 Figure 6As shown, the output signal of the third output signal terminal G(3) of the third-stage gate driving unit is abnormal ( Figure 6 In the example, the symbol “×” (cross) indicates that the timing of the third output signal terminal G (3) is abnormal), in order to prevent the output signal of the third output signal terminal G (3) from affecting the second-stage gate driving unit and the fourth-stage gate driving unit, the input module 10 of the fourth-stage gate driving unit and the output signal terminal ( Figure 5 The position of the break is shown by the reference numeral 40 in the figure), and at the same time, the pull-down module 30 of the second-level gate drive unit can be disconnected from the output signal end of the third-level gate drive unit; at the same time, in order to enable the second-level gate drive unit and the fourth-level gate drive unit to operate normally and to perform subsequent level transmission, the pull-down module 30 of the second-level gate drive unit and the input module 10 of the fourth-level gate drive unit are connected to the compensation signal line STV-2, and the output signal of the compensation signal line STV-2 differs from the output signal of the output signal end of the second-level gate drive unit by one unit time length, so that the signal output by the compensation signal line STV-2 is the same as the normal signal output by the output signal end of the third-level gate drive unit, thereby enabling the gate drive circuit to perform normal level transmission and normal output. Similarly, when the output signal end of the other-level gate drive unit is abnormal, the setting method when the output signal of the output signal end of the third-level gate drive unit is abnormal can be referred to, and no further details will be given here.

[0049] Specifically, taking the gate driving circuit including 1080-level gate driving units as an example, n is greater than or equal to 2, and n is less than 1080, and n can be any integer between 2 and 1079.

[0050] Specifically, when the output signal of the output signal end of the n-th gate driving unit is abnormal, the wiring between the output signal end of the n-th gate driving unit and the input module of the n+i-th gate driving unit can be disconnected by laser, and the wiring between the output signal end of the n-th gate driving unit and the pull-down module of the nj-th gate driving unit can be disconnected by laser; then, the wiring in the input module of the n+i-th gate driving unit and the wiring in the pull-down module of the nj-th gate driving unit are connected to the compensation signal line at the overlapping position by laser.

[0051] In some embodiments, as Figure 5 As shown, the input module 10 includes an input transistor T11, and the gate of the input transistor T11 is connected to the first electrode of the input transistor T11;

[0052] The output module 20 includes an output transistor T21, the gate of the output transistor T21 is connected to the second electrode of the input transistor T11, and the second electrode of the output transistor T21 is connected to the output signal terminal;

[0053] The pull-down module 30 includes a first pull-down transistor T31 and a second pull-down transistor T41. The gate of the first pull-down transistor T31 is connected to the gate of the second pull-down transistor T41. The second electrode of the first pull-down transistor T31 is connected to the second electrode of the input transistor T11. The second electrode of the second pull-down transistor T41 is connected to the output signal terminal. In some embodiments, the display panel 2 further includes a start signal line STV-1, a clock signal line, and a low-potential signal line VSS. The first electrode of the output transistor T21 is connected to the clock signal line CK, the first electrode of the first pull-down transistor T31 and the first electrode of the second pull-down transistor T41 are connected to the low-potential signal line VSS, the gate of the input transistor T11 in the first-stage gate driving unit 120 is connected to the start signal line STV-1, and the gate of the input transistor T11 of the gate driving unit 120 of other stages is connected to the output signal terminal of the gate driving unit 120 of the previous stage (for example, Figure 5 The gate of the input transistor of the second-stage gate driving unit is connected to the first output signal terminal G(1) of the first-stage gate driving unit), and the gate of the first pull-down transistor T31 in the last-stage gate driving unit 120 is connected to the start signal line STV-1 (for example Figure 5 The gate of the first pull-down transistor T31 of the 1080th gate driving unit is connected to the start signal line STV-1), and the gate of the first pull-down transistor T31 in the gate driving unit 120 of other levels is connected to the output signal terminal of the gate driving unit 120 of the next level (for example Figure 5 The gate of the first pull-down transistor T31 in the first-stage gate driving unit is connected to the output signal terminal in the second-stage gate driving unit).

[0054] In some embodiments, when the output signal of the output signal terminal of the gate driving unit 120 at each stage, the output signal of the clock signal line, and the output signal of the low potential signal line VSS are normal, the first electrode of the output transistor T21 is connected to the clock signal line CK, the first electrode of the first pull-down transistor T31 and the first electrode of the second pull-down transistor T41 are connected to the low potential signal line VSS, the gate of the input transistor T11 in the first stage of the gate driving unit 120 is connected to the start signal line STV-1, and the gates of the input transistors T11 of the gate driving units 120 at other stages are connected to the output signal terminal of the gate driving unit 120 at the previous stage (for example, Figure 5 The gate of the input transistor of the second-stage gate driving unit is connected to the first output signal terminal G(1) of the first-stage gate driving unit), and the gate of the first pull-down transistor T31 in the last-stage gate driving unit 120 is connected to the start signal line STV-1 (for example Figure 5 The gate of the first pull-down transistor T31 of the 1080th gate driving unit is connected to the start signal line STV-1), and the gate of the first pull-down transistor T31 in the gate driving unit 120 of other levels is connected to the output signal terminal of the gate driving unit 120 of the next level (for example Figure 5 The gate of the first pull-down transistor T31 in the first-stage gate driving unit is connected to the output signal terminal of the second-stage gate driving unit. Specifically, the above embodiment is described by taking the gate driving unit including the input transistor T11, the output transistor T21, the first pull-down transistor T31, and the second pull-down transistor T41 as an example. It is understandable that the design of the gate driving unit can be other designs. As long as the output signal of the output signal terminal of the first-stage gate driving unit is used as the starting signal of the gate driving units of other stages, the design described in the embodiment of the present application can be adopted, and no further details are given here.

[0055] Specifically, such as Figure 5As shown, the output signal terminal includes a first output signal terminal G(1) of the first-level gate driving unit, a second output signal terminal G(2) of the second-level gate driving unit, a third output signal terminal G(3) of the third-level gate driving unit, a fourth output signal terminal G(4) of the fourth-level gate driving unit, a fourth output signal terminal G(5) of the fifth-level gate driving unit, ..., a first output signal terminal G(1079) of the one thousand and seventy-ninth-level gate driving unit, and a first output signal terminal G(1080) of the one thousand and eighty-level gate driving unit. The output transistor T21 of the first-level gate driving unit is connected to the first output signal terminal G(1), the output transistor T21 of the second-level gate driving unit is connected to the second output signal terminal G(2), the output transistor T21 of the third-level gate driving unit is connected to the third output signal terminal G(3), the output transistor T21 of the fourth-level gate driving unit is connected to the fourth output signal terminal G(4), ..., the output transistor T21 of the one thousand and eighty-level gate driving unit is connected to the one thousand and eighty-level output signal terminal G(1080).

[0056] In some embodiments, when the output signals of the output signal terminals of each gate drive unit 120, the output signals of the start signal line STV-1, the output signals of the clock signal line, and the output signal of the low-potential signal line VSS are normal, the compensation signal line STV-2 is left floating. By providing a compensation signal line in the display panel, the compensation signal line operates normally when other signal lines and the output signal terminals are normal. When other signal lines and / or the output signal terminals are abnormal, the gate drive circuit is repaired via the compensation signal line, allowing the display panel to operate normally.

[0057] In some embodiments, the display panel includes at least two compensation signal lines, one of which is connected to the input module of the n+i-th gate driver unit and the pull-down module of the nj-th gate driver unit, and the other is connected to other modules, and the timing of the two compensation signal lines is different. By providing at least two compensation signal lines, one of which is connected to the input module of the n+i-th gate driver unit and the pull-down module of the nj-th gate driver unit, an abnormal output signal at the output signal terminal of the n-th gate driver unit can be repaired. Another compensation signal line can also be connected to other modules to repair abnormal output signals at other signal terminals or signal lines.

[0058] Specifically, the other modules include various modules of the gate driving units of other levels, other modules except the output module in the gate driving unit of the n+i level, and other modules except the pull-down module in the gate driving unit of the nj level.

[0059] In some embodiments, as Figure 5 As shown, the clock signal lines include a first clock signal line CK and a second clock signal line XCK. In two adjacent stages of the gate driving units 120, the output module 20 of one stage of the gate driving unit 120 is connected to the first clock signal line CK, and the output module 20 of the other stage of the gate driving unit 120 is connected to the second clock signal line XCK. When the output signal at the output signal end of each stage of the gate driving unit 120 is normal and the output signal of one of the first clock signal line CK and the second clock signal line XCK is abnormal, the output module 20 of the gate driving unit 120 is disconnected from the abnormal output signal of the first clock signal line CK or the second clock signal line XCK, and the compensation signal line STV-2 is connected to the output module of the gate driving unit 120. When the output signal at the output signal end of the gate driving unit is normal and the output signal of one of the first clock signal line and the second clock signal line is abnormal, the output module of the gate driving unit can be disconnected from the abnormal first clock signal line or the second clock signal line, and the compensation signal line can be connected to the output module of the gate driving unit. This can avoid output signal abnormalities caused by the abnormal first clock signal line or the second clock signal line, allowing the display panel to display normally.

[0060] Specifically, for example, if the output signals of the output signal terminals of each gate drive unit are normal, but the output signal of the first clock signal line is abnormal, the first clock signal line can be disconnected from the output module of the corresponding gate drive unit, and the output module of the gate drive unit can be connected to the compensation signal line. This prevents the abnormal output signal of the first clock signal line from causing abnormal output signals of the gate drive unit, thereby ensuring normal display of the display panel. Similarly, if the output signal of the second clock signal line is abnormal, the second clock signal line and the compensation signal line can also be processed accordingly.

[0061] In some embodiments, the display panel further includes clock signal lines, including a first clock signal line CK and a second clock signal line XCK. In two adjacent stages of the gate driving units 120, the output module 20 of one stage of the gate driving unit 120 is disconnected from the first clock signal line CK, and the output module 20 of the gate driving unit 120 is connected to another compensation signal line, while the output module 20 of the other stage of the gate driving unit 120 is connected to the second clock signal line XCK. By disconnecting the output module of one of the two adjacent stages of the gate driving units from the first clock signal line and connecting the output module of the gate driving unit to another compensation signal line, the output signal terminal with an abnormal output and the first clock signal line with an abnormal output can be repaired via the two compensation signal lines, respectively, to enable the display panel to operate normally.

[0062] In some embodiments, as Figure 5 As shown, when the output signal of the output signal terminal of the last-stage gate driving unit 120 is abnormal, the pull-down module 30 of the previous-stage gate driving unit 120 is disconnected from the output signal terminal of the last-stage gate driving unit 120, and the pull-down module 30 of the previous-stage gate driving unit 120 is connected to the compensation signal line STV-2. When the output signal of the output signal terminal of the last-stage gate driving unit is abnormal, the pull-down module of the previous-stage gate driving unit is disconnected from the output signal terminal of the last-stage gate driving unit, and the pull-down module of the previous-stage gate driving unit is connected to the compensation signal line, so that the pull-down module of the previous-stage gate driving unit can operate normally and pull down the output signal of the previous-stage gate driving unit, thereby preventing the scan line corresponding to the previous-stage gate driving unit from being in the on state for a long time, causing the pixel unit of the corresponding row to be constantly bright, and avoiding poor display.

[0063] In some embodiments, the output signal terminal of the last-stage gate driving unit is disconnected from the pull-down module of the previous-stage gate driving unit, and the pull-down module of the previous-stage gate driving unit is connected to another compensation signal line. This allows the pull-down module of the previous-stage gate driving unit to operate normally, pulls down the output signal of the previous-stage gate driving unit, and prevents the scanning line corresponding to the previous-stage gate driving unit from being in the on state for a long time, causing the pixel unit of the corresponding row to be constantly bright, thereby avoiding poor display. Specifically, taking the gate driving unit as an example, the last-stage gate driving unit is the 1,080-stage gate driving unit. When the output signal of the 1,080-stage output signal terminal G (1080) of the 1,080-stage gate driving unit is abnormal, the 1,080-stage output signal terminal G (1080) can be disconnected from the pull-down module 30 of the 1,079-stage gate driving unit, and the pull-down module 30 of the 1,079-stage gate driving unit is connected to the compensation signal line STV-2, thereby making the output signal of the 1,079-stage gate driving unit normal, so that the display panel displays normally.

[0064] In some embodiments, as Figure 5As shown, when the output signal of the starting signal line STV-1 is abnormal, the input module 10 of the first-level gate driving unit 120 is disconnected from the starting signal line STV-1, and the pull-down module 30 of the last-level gate driving unit 120 is disconnected from the starting signal line STV-1. The input module 10 of the first-level gate driving unit 120 is connected to the compensation signal line STV-2, and the pull-down module 30 of the last-level gate driving unit 120 is connected to the compensation signal line STV-2. When the output signal of the starting signal line is abnormal, the input module of the first-stage gate driving unit is disconnected from the starting signal line, the pull-down module of the last-stage gate driving unit is disconnected from the starting signal line, and the input module of the first-stage gate driving unit is connected to the compensation signal line, and the pull-down module of the last-stage gate driving unit is connected to the compensation signal line. The abnormal first-stage gate driving unit can be repaired through the compensation signal line, so that the first-stage gate driving unit can operate normally, and the stage transmission of the gate driving circuit can be normal, and the abnormal last-stage gate driving unit can be repaired, so that the display signal is normal and the display panel displays normally.

[0065] In some embodiments, the display panel also includes a starting signal line STV-1, the input module 10 of the first-level gate driving unit 120 is disconnected from the starting signal line STV-1, the pull-down module 30 of the last-level gate driving unit 120 is disconnected from the starting signal line STV-1, the input module 10 of the first-level gate driving unit 120 is connected to another compensation signal line STV-2, and the pull-down module 30 of the last-level gate driving unit 120 is connected to another compensation signal line STV-2. When the output signal of the starting signal line is abnormal, the input module of the first-stage gate driving unit is disconnected from the starting signal line, the pull-down module of the last-stage gate driving unit is disconnected from the starting signal line, and the input module of the first-stage gate driving unit is connected to another compensation signal line, and the pull-down module of the last-stage gate driving unit is connected to another compensation signal line. The abnormal first-stage gate driving unit can be repaired through the compensation signal line, so that the first-stage gate driving unit can operate normally, and the stage transmission of the gate driving circuit can be normal, and the abnormal last-stage gate driving unit can be repaired, so that the display signal is normal and the display panel displays normally.

[0066] In some embodiments, as Figure 5As shown, when the output signal of the low-potential signal line VSS is abnormal, the pull-down modules 30 of the gate drive units 120 at each level are disconnected from the low-potential signal line VSS, and the pull-down modules 30 of the gate drive units 120 at each level are connected to the compensation signal line STV-2. By disconnecting the pull-down modules of the gate drive units at each level from the low-potential signal line and connecting the pull-down modules of the gate drive units at each level to the compensation signal line when the output signal of the low-potential signal line is abnormal, each gate drive unit can pull down the potential via the compensation signal line, thereby normalizing the output signal of each gate drive unit, the display signal, and the display panel.

[0067] In some embodiments, the display panel further includes a low-potential signal line VSS, and the pull-down modules 30 of the gate drive units 120 at each level are disconnected from the low-potential signal line VSS, while the pull-down modules 30 of the gate drive units 120 at each level are connected to another compensation signal line. When the output signal of the low-potential signal line is abnormal, the pull-down modules of the gate drive units at each level are disconnected from the low-potential signal line and connected to the compensation signal line. This allows each gate drive unit to pull down the potential via the compensation signal line, thereby normalizing the output signal of each gate drive unit, the display signal, and the display panel to display normally.

[0068] Specifically, the position where the pull-down module of each level of the gate driving unit is connected to another compensation signal line is the connection point of the first electrodes of the transistors of each level of the gate driving unit.

[0069] Specifically, the above embodiments illustrate the display panel including one and two compensation signal lines as examples, but the embodiments of the present application are not limited thereto. The display panel may include multiple compensation signal lines. By inputting different signals through the multiple compensation signal lines, signal anomalies caused by multiple signal lines and output signal terminals with abnormal outputs can be repaired to restore normal display. For example, the display panel may include three compensation signal lines, one compensation signal line connected to the input module of the (n+i)th level gate driver unit and the pull-down module of the (nj)th level gate driver unit, one compensation signal line connected to the output module of the first level gate driver unit, and one compensation signal line connected to the pull-down modules of each level of the gate driver unit.

[0070] In some embodiments, the display panel 2 includes a plurality of compensation signal lines STV-2 disposed at intervals. When the output signals at the output signal terminals of the multiple gate drive units 120 are abnormal, the pull-down modules 30 of the gate drive units of the previous stage of the multiple gate drive units 120 are respectively connected to the plurality of compensation signal lines STV-2, and the input modules 10 of the gate drive units of the next stage of the multiple gate drive units 120 are respectively connected to the plurality of compensation signal lines STV-2. By providing a plurality of compensation signal lines disposed at intervals, when the output signals at the output signal terminals of the multiple gate drive units are abnormal, the plurality of compensation signal lines can be connected to the plurality of gate drive units respectively, thereby ensuring that the output signals of the gate drive units are normal, thereby ensuring normal display of the display panel.

[0071] Specifically, for example, the display panel 2 includes two compensation signal lines STV-2. When the output signals of the second output signal terminal G(2) of the second-level gate driving unit and the third output signal terminal G(3) of the third-level gate driving unit are both abnormal, the pull-down module of the first-level gate driving unit can be disconnected from the second output signal terminal G(2), the input module of the third-level gate driving unit can be disconnected from the second output signal terminal G(2), the pull-down module of the first-level gate driving unit and the input module of the third-level gate driving unit can be connected to a compensation signal line STV-2, and the compensation signal line STV-2 outputs a normal signal of the second output signal terminal; at the same time, the pull-down module of the second-level gate driving unit can be disconnected from the third output signal terminal G(3), the input module of the fourth-level gate driving unit can be disconnected from the third output signal terminal G(3), the pull-down module of the second-level gate driving unit and the input module of the fourth-level gate driving unit can be connected to another compensation signal line, and the compensation signal line STV-2 inputs a normal signal of the third output signal terminal, thereby repairing the output abnormality caused by multiple abnormal output signal terminals through multiple compensation signal lines, so as to make the display abnormal. Similarly, for output abnormalities of other signal lines and output signal terminals, or for output abnormalities of more signal lines and output signal terminals, the number of compensation signal lines can be increased accordingly to repair the output signal, so that the gate drive circuit can be transmitted normally and the display panel can work normally.

[0072] In some embodiments, the display panel 2 includes a plurality of compensation signal lines STV-2 disposed at intervals. The pull-down modules of the gate drive units 120 of the previous stage of the multiple gate drive units 120 are respectively connected to the plurality of compensation signal lines STV-2, and the input modules of the gate drive units of the next stage of the multiple gate drive units 120 are respectively connected to the plurality of compensation signal lines STV-2. By providing a plurality of compensation signal lines disposed at intervals, when the output signals of the output signal terminals of the plurality of gate drive units are abnormal, the plurality of compensation signal lines can be connected to the plurality of gate drive units respectively to ensure that the output signals of the gate drive units are normal, thereby ensuring normal display of the display panel.

[0073] In some embodiments, as Figure 4 As shown, the display unit 21 is provided with scan lines, and the gate drive circuit 22 is provided on both sides of the display unit 21. When the output signal of the output signal terminal of the gate drive unit 120 on one side is abnormal, the output signal terminal of the gate drive unit 120 on one side is disconnected from the scan line, and the output signal terminal of the gate drive unit 120 on the other side is connected to the scan line. By providing gate drive circuits on both sides of the display unit, each scan line can be connected to the output signal terminal of the gate drive unit on both sides, which can reduce the voltage drop of the signal. When the output signal terminal of the gate drive unit on one side is abnormal, a normal signal can still be output through the output signal terminal of the gate drive unit on the other side, thereby allowing the display panel to operate normally.

[0074] In some embodiments, as Figure 4 As shown, the display portion 21 is provided with a scan line, and the gate drive circuit 22 is arranged on both sides of the display portion 21, the output signal end of the gate drive unit 120 on one side is disconnected from the scan line, and the output signal end of the gate drive unit 120 on the other side is connected to the scan line.

[0075] Specifically, it can be understood that, since in multiple display panels, there may be no signal line and output signal abnormality, there may be one signal line and / or output signal terminal output signal abnormality, and there may be multiple signal lines and / or multiple output signal terminals output signal abnormality, therefore, in different display panels, the connection method of the compensation signal line may be different, but different display panels will have compensation signal lines. For example, in a certain display panel, there is no signal line and output signal abnormality at the output signal terminal, then the compensation signal line in this display panel is suspended, while in another display panel, there is a signal line or an output signal abnormality at an output signal terminal, then the compensation signal line in this display panel will be connected to the corresponding module, then the connection method of the compensation signal lines in the two display panels is different, but the two display panels are both provided with compensation signal lines, therefore, the above two display panels both belong to the display panels described in the embodiment of the present application.

[0076] Specifically, it can be understood that when there is only one compensation signal line in the display panel, the compensation signal line can repair the abnormality of any signal line and the output signal end. For specific instructions, please refer to the above embodiment. When there are multiple compensation signal lines in the display panel, the multiple compensation signal lines can repair the abnormality of multiple signal lines and the output signal end.

[0077] Specifically, it can be understood that when the output signal of the signal end or signal line connected to a certain module is abnormal and the module is disconnected from the signal end or signal line, when the module is connected to the compensation signal line, the connection between the certain module, the compensation signal line and the module refers to the connection between the signal end or signal line with the output abnormality in the module. For example, if the output signal of the low-potential signal line VSS connected to the pull-down module is abnormal, the compensation signal line will be used to connect to the pull-down module, and the connection between the compensation transistor and the pull-down module refers to the connection between the pull-down module and the low-potential signal line.

[0078] Specifically, in the above-mentioned embodiment, a compensation signal line is set to repair the stage transmission failure caused by the abnormal output of each signal line and the output signal terminal, but the abnormality of the scan line caused by the output abnormality of the output signal terminal is not repaired. This is because the display panel will have gate drive circuits on both sides of the display part. When the output of the gate drive unit on one side is abnormal, the gate drive circuit on the other side can also be used for normal output, so that the signal of each scan line is normal, thereby allowing the display panel to display normally. However, the embodiments of the present application are not limited to this. When the gate drive circuit is only set on one side of the display part, or when the output signal terminals of the gate drive units connected to the same scan line on both sides output abnormalities, the connection between the output signal terminal and the scan line can also be disconnected to input the signal to the scan line through the compensation signal line.

[0079] Specifically, it can be understood that the output signals of each signal line and / or output signal end described in the embodiments of the present application are abnormal, and by disconnecting each signal line and / or output signal end with an abnormal output signal from the corresponding gate drive unit, and connecting the compensation signal line to the corresponding gate drive unit, the compensation signal line can be made the same as the normal signal of the corresponding signal line and / or output signal end. For example, when the output signal of the first clock signal line is abnormal, the first clock signal line can be disconnected from the corresponding gate drive unit, and the compensation signal line can be connected to the corresponding gate drive unit, and the output signal of the compensation signal line can be the same as the normal output signal of the first clock signal line.

[0080] Specifically, it is understood that the output signal anomaly of each signal line and / or output signal terminal described in the embodiments of the present application may be that the output signal is abnormal in a certain frame or that the output signal is abnormal in all frames. The embodiments of the present application do not limit the cause of the output signal anomaly of each signal line and output signal terminal, but only define the output signal as not meeting the requirements as an abnormal signal. Specific causes may include short circuits or open circuits in the signal line and output signal terminal, interference from other signal lines, or interference from external signals, which will not be detailed here.

[0081] In some embodiments, the display panel includes a substrate and at least two metal layers disposed on one side of the substrate, the output signal terminal is disposed on one metal layer, the compensation signal line is disposed on another metal layer, and the projection of the output signal terminal on the substrate and the projection of the compensation signal line on the substrate overlap. By causing the projection of the output signal terminal on the substrate to overlap with the projection of the compensation signal line on the substrate, when the output signal of the output signal terminal is abnormal, the connection between the output signal terminal and the other signal terminals or traces can be interrupted by laser, and the portion of the output signal terminal connected to the other signal terminals or traces can be connected to the compensation signal line by laser, so that the gate drive circuit can transmit normally.

[0082] Specifically, it can be understood that since the pull-down module of the previous-level gate driving unit and the input module of the next-level gate driving unit are both connected to the output signal end of the current-level gate driving unit, in actual design, the connection between the pull-down module of the previous-level gate driving unit and the output signal end of the current-level gate driving unit, the connection between the input module of the next-level gate driving unit and the output signal end of the current-level gate driving unit, and the output signal end of the current-level gate driving unit can be three parts of the same routing. It can be understood that in order to repair the level transmission abnormality caused by the output abnormality of the output signal end of the current-level gate driving unit, the overlap between the projection of the output signal end on the substrate and the projection of the compensation signal line on the substrate means that the projection of the compensation signal line on the substrate and the projection of the output signal end corresponding to the connection between the pull-down module of the previous-level gate driving unit and the output signal end of the current-level gate driving unit overlap on the substrate, and the projection of the compensation signal line on the substrate and the projection of the output signal end corresponding to the connection between the input module of the next-level gate driving unit and the output signal end of the current-level gate driving unit overlap on the substrate.

[0083] Specifically, it can be understood that when the projection of the output signal end and the compensation signal line on the substrate do not overlap, in order to achieve the connection between the compensation signal line and a part of the output signal line, a connecting line will be set so that the connecting line and the projection of the compensation signal line on the substrate overlap. At this time, the connecting line can be regarded as a part of the output signal line, and it can still be regarded that the projection of the output signal end on the substrate and the projection of the compensation signal line on the substrate overlap.

[0084] Specifically, when the compensation signal line and the output signal end are located in the same film layer, the compensation signal line can be directly connected to the part of the output signal end corresponding to the connection between the pull-down module of the previous level gate driving unit and the output signal end of the current level gate driving unit, and the compensation signal line can be directly connected to the part of the output signal end corresponding to the connection between the input module of the next level gate driving unit and the output signal end of the current level gate driving unit.

[0085] Specifically, such as Figure 4 As shown, the display panel 2 includes a display area AA and a non-display area NA, the display portion 21 is disposed in the display area AA, the gate driving circuit 22 is disposed in the non-display area NA, and the display panel 2 further includes a terminal portion 23 .

[0086] At the same time, an embodiment of the present application provides a display device, which includes the display panel as described in any of the above embodiments.

[0087] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0088] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The device comprises a display portion and a gate driving circuit located on at least one side of the display portion, wherein the gate driving circuit comprises a plurality of cascaded gate driving units, and the gate driving unit comprises: Input module; an output module, comprising an output signal terminal, the output module being connected to the input module, and the output module being configured to control an output signal of the output signal terminal according to an output signal of the input module; A pull-down module connected to the output module; Wherein, the display panel further includes at least one compensation signal line, the input module of the n+i-th level gate driving unit is disconnected from the output signal end of the n-th level gate driving unit, the input module of the n+i-th level gate driving unit is connected to the compensation signal line, the pull-down module of the nj-th level gate driving unit is disconnected from the output signal end of the n-th level gate driving unit, the pull-down module of the nj-th level gate driving unit is connected to the compensation signal line, and the pulse width of the effective pulse of the output signal of the compensation signal line is the same as the output signal end of the nj-th level gate driving unit. The pulse widths of the effective pulses of the output signals of the signal terminals are equal, the amplitude of the effective pulses of the output signals of the compensation signal line is equal to the amplitude of the effective pulses of the output signals of the output signal terminals of the nj-th level gate driving units, the phase difference between the effective pulses of the output signals of the compensation signal line and the effective pulses of the output signals of the output signal terminals of the nj-th level gate driving units is j*m unit time lengths, n is greater than or equal to 2, n is less than the number of levels of the gate driving units, i is greater than or equal to 1, and i is less than n, j is greater than or equal to 1, and j is less than n, i, j, and n are all positive integers, and m is greater than 0.

2. The display panel according to claim 1, wherein The input module includes an input transistor, wherein the gate of the input transistor is connected to the first electrode of the input transistor; The output module includes an output transistor, the gate of the output transistor is connected to the second electrode of the input transistor, and the second electrode of the output transistor is connected to the output signal terminal; The pull-down module includes a first pull-down transistor and a second pull-down transistor, wherein the gate of the first pull-down transistor is connected to the gate of the second pull-down transistor, the second electrode of the first pull-down transistor is connected to the second electrode of the input transistor, and the second electrode of the second pull-down transistor is connected to the output signal terminal; In which, the display panel also includes a start signal line, a clock signal line and a low-potential signal line, the first electrode of the output transistor is connected to the clock signal line, the first electrode of the first pull-down transistor and the first electrode of the second pull-down transistor are connected to the low-potential signal line, the gate of the input transistor in the first-level gate driving unit is connected to the start signal line, the gate of the input transistor of the gate driving unit of other levels is connected to the output signal end of the gate driving unit of the previous level, the gate of the first pull-down transistor in the gate driving unit of the last level is connected to the start signal line, and the gate of the first pull-down transistor in the gate driving unit of other levels is connected to the output signal end of the gate driving unit of the next level.

3. The display panel according to claim 1, wherein The display panel includes at least two compensation signal lines, one compensation signal line is connected to the input module of the n+i-th level gate driving unit and the pull-down module of the nj-th level gate driving unit, and the other compensation signal line is connected to other modules, and the timing of the two compensation signal lines is different.

4. The display panel according to claim 3, wherein: The display panel also includes a clock signal line, which includes a first clock signal line and a second clock signal line. In two adjacent gate driving units, the output module of one gate driving unit is disconnected from the first clock signal line, and the output module of the gate driving unit is connected to the other compensation signal line, and the output module of the other gate driving unit is connected to the second clock signal line.

5. The display panel according to claim 3, wherein: The display panel further includes a low-potential signal line. The pull-down modules of the gate driving units at each stage are disconnected from the low-potential signal line, and the pull-down modules of the gate driving units at each stage are connected to another compensation signal line.

6. The display panel according to claim 3, wherein: The output signal end of the gate driving unit of the last stage is disconnected from the pull-down module of the gate driving unit of the previous stage, and the pull-down module of the gate driving unit of the previous stage is connected to another compensation signal line.

7. The display panel according to claim 3, wherein: The display panel also includes a starting signal line, the input module of the first-level gate driving unit is disconnected from the starting signal line, the pull-down module of the last-level gate driving unit is disconnected from the starting signal line, the input module of the first-level gate driving unit is connected to another compensation signal line, and the pull-down module of the last-level gate driving unit is connected to another compensation signal line.

8. The display panel according to claim 1, wherein: The display panel includes a plurality of compensation signal lines arranged at intervals, the pull-down modules of the upper-level gate driving units of the multi-level gate driving units are respectively connected to the plurality of compensation signal lines, and the input modules of the lower-level gate driving units of the multi-level gate driving units are respectively connected to the plurality of compensation signal lines.

9. The display panel according to claim 1, wherein: The display portion is provided with a scan line, and the gate driving circuit is arranged on both sides of the display portion. The output signal end of the gate driving unit on one side is disconnected from the scan line, and the output signal end of the gate driving unit on the other side is connected to the scan line.

10. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 9.

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