Semiconductor structure and method of forming the same
By performing testing and connection in the contact area of the redistribution layer, and merging the testing and connection areas, the problems of process complexity and high cost in semiconductor structures are solved, enabling efficient manufacturing and miniaturization.
Patent Information
- Application Number
- CN202310386016.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-04-07
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2043-04-07
AI Technical Summary
In existing semiconductor structures, the formation processes of test pads and bonding pads are complex, increasing process costs and reducing manufacturing efficiency.
Electrical testing is performed in the contact area of the redistribution layer, and the first substrate and the second substrate are electrically connected through this area. The test area and the connection area are merged, simplifying the process flow and reducing the number of photomasks and process steps.
It simplifies the manufacturing process of semiconductor structures, improves manufacturing efficiency, reduces manufacturing costs, and shrinks structural size.
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Figure CN118824987B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor structure and a forming method thereof. BACKGROUND
[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth for the past several decades. Progress in IC design and materials technology has produced generations of ICs, each providing more functionality at lower cost than its predecessor. As a result, the field of IC technology has evolved into an incredibly dynamic and competitive industry. In the drive to increase densities of ICs and reduce their cost, the size of the individual features that can be created has been steadily decreased while the number of such features that can be created has been increased. In addition to making IC features smaller and more complex, the wafers on which the ICs are fabricated have become larger, making the integration of semiconductor devices an important direction of current development.
[0003] Test pads are usually provided in a semiconductor structure to test the performance of the semiconductor structure, and bonding pads are provided to perform packaging bonding of the semiconductor structure. However, the process of forming the test pads and the bonding pads is complex, and a large number of masks are required, which greatly increases the process cost of the semiconductor structure and reduces the manufacturing efficiency of the semiconductor structure.
[0004] Therefore, how to simplify the manufacturing process of the semiconductor structure, improve the manufacturing efficiency of the semiconductor structure, and reduce the manufacturing cost of the semiconductor structure is a technical problem to be solved at present. SUMMARY
[0005] Some embodiments of the present disclosure provide a semiconductor structure and a forming method thereof, for simplifying the manufacturing process of the semiconductor structure, improving the manufacturing efficiency of the semiconductor structure, and reducing the manufacturing cost of the semiconductor structure.
[0006] According to some embodiments, the present disclosure provides a forming method of a semiconductor structure, comprising the following steps:
[0007] providing a first substrate, the first substrate comprising a conductive structure therein;
[0008] forming a redistribution layer on the first substrate and electrically connected to the conductive structure, the redistribution layer comprising a contact area;
[0009] electrically testing the conductive structure at the contact area;
[0010] forming a protection layer on the redistribution layer;
[0011] electrically connecting the first substrate and a second substrate through the contact area.
[0012] In some embodiments, the specific steps of forming the redistribution layer on the first substrate and electrically connected to the conductive structure comprise:
[0013] forming a first dielectric layer on a top surface of the first substrate;
[0014] forming a first trench through the first dielectric layer and exposing the conductive structure;
[0015] forming a re-distribution layer covering inner walls of the first trench and a top surface of the first dielectric layer, and electrically connected with the conductive structure.
[0016] In some embodiments, the step of forming a re-distribution layer covering inner walls of the first trench and a top surface of the first dielectric layer, and electrically connected with the conductive structure comprises:
[0017] depositing a re-distribution material on the first dielectric layer to form an initial re-distribution layer covering inner walls of the first trench and a top surface of the first dielectric layer, and electrically connected with the conductive structure;
[0018] patterning the initial re-distribution layer to form a second trench exposing the first dielectric layer, and the remaining initial re-distribution layer as the re-distribution layer, the second trench separating the re-distribution layer into a plurality of contact areas.
[0019] In some embodiments, the step of electrically testing the conductive structure at the contact areas comprises:
[0020] transmitting a test signal to the contact areas through a probe to perform a probe test on the conductive structure.
[0021] In some embodiments, the step of forming a protection layer on the re-distribution layer comprises:
[0022] forming a first protection layer covering the re-distribution layer;
[0023] forming a second protection layer covering the first protection layer, the first protection layer and the second protection layer together forming the protection layer.
[0024] In some embodiments, the step of electrically connecting the first substrate and the second substrate through the contact areas comprises:
[0025] bonding electrically connecting the first substrate and the second substrate through the contact areas by a bonding structure.
[0026] In some embodiments, the step of bonding electrically connecting the first substrate and the second substrate through the contact areas by a bonding structure comprises:
[0027] providing a second substrate;
[0028] forming a bonding structure on the first substrate or the second substrate;
[0029] applying a bonding force on the first substrate or the second substrate, the bonding structure penetrating the protection layer and contacting and electrically connecting with the re-distribution layer of the contact areas under the action of the bonding force.
[0030] According to some embodiments, the present disclosure provides a semiconductor structure, comprising:
[0031] a first substrate, the first substrate comprising a conductive structure therein;
[0032] a redistribution layer on the first substrate and electrically connected with the conductive structure, the redistribution layer comprising a contact area, the contact area having a test trace;
[0033] a protective layer covering the redistribution layer;
[0034] a second substrate on the protective layer, and the second substrate being electrically connected with the first substrate through the contact area.
[0035] In some embodiments, further comprising:
[0036] a bonding structure between the first substrate and the second substrate, one end of the bonding structure penetrating through the protective layer and being electrically connected with the redistribution layer of the contact area, and the other end of the bonding structure being electrically connected with the second substrate.
[0037] In some embodiments, the position where the bonding structure contacts the contact area is outside the test trace; or,
[0038] the position where the bonding structure contacts the contact area at least partially overlaps with the test trace.
[0039] The semiconductor structure and the forming method thereof provided by some embodiments of the present disclosure, by testing the contact area of the redistribution layer and taking the contact area as the connecting area of the first substrate and the second substrate, on one hand, the test area and the connecting area are combined into one, and there is no need to separately form an area for probe testing and an area for connecting the second substrate, thereby simplifying the manufacturing process of the semiconductor structure and improving the manufacturing efficiency of the semiconductor structure; on the other hand, the combination of the test area and the connecting area helps to reduce the area of the redistribution layer, thereby reducing the manufacturing cost of the semiconductor structure and reducing the size of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS
[0040] FIG. 1 is a flow chart of a forming method of a semiconductor structure according to some embodiments of the present disclosure; Figure 1
[0041] FIG. 2 is a schematic diagram of a main process structure in the process of forming a semiconductor structure according to some embodiments of the present disclosure; Figure 2 - FIG. 3 is a schematic diagram of a main process structure in the process of forming a semiconductor structure according to some embodiments of the present disclosure; Figure 9 DETAILED DESCRIPTION
[0042] The specific embodiments of the semiconductor structure and the forming method thereof provided by the present disclosure will be described in detail below with reference to the accompanying drawings.
[0043] This specific embodiment provides a method for forming a semiconductor structure, with appended... Figure 1 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figure 2 - Appendix Figure 9 This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to a specific embodiment of this disclosure. For example... Figures 1-9 As shown, the method for forming a semiconductor structure includes the following steps:
[0044] Step S11: Provide a first substrate 20, the first substrate 20 including a conductive structure 21, such as... Figure 2 As shown;
[0045] Step S12: A redistribution layer 42 electrically connected to the conductive structure 21 is formed on the first substrate 20. The redistribution layer 42 includes a contact region 41, such as... Figure 4 As shown;
[0046] Step S13: Perform an electrical test on the conductive structure 21 in the contact area 41, such as... Figure 5 As shown;
[0047] Step S14, forming a protective layer on the redistribution layer 42, such as Figure 7 As shown;
[0048] Step S15, the first substrate 20 and the second substrate 90 are electrically connected through the contact area 41, such as... Figure 9 As shown.
[0049] In one example, the first substrate 20 can be a semiconductor device such as DRAM (Dynamic Random Access Memory). Taking DRAM as an example, the first substrate 20 can include a substrate and a conductive structure 21 located above the substrate. The substrate can be, but is not limited to, a silicon substrate; this specific embodiment uses a silicon substrate as an example for illustration. In other embodiments, the substrate can also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate is used to support the device structure located thereon. The conductive structure 21 can include a structure located above the substrate and along a direction perpendicular to the top surface of the substrate (e.g., Figure 2 Multiple conductive interconnect layers are arranged at intervals and electrically connected (in the Z-axis direction). The material of the conductive interconnect layers can be conductive materials such as copper or aluminum.
[0050] In some embodiments, the specific steps of forming a redistribution layer 42 electrically connected to the conductive structure 21 on the first substrate 20 include:
[0051] A first dielectric layer 22 is formed on the top surface of the first substrate 20;
[0052] forming a first trench 24 through the first dielectric layer 22 and exposing the conductive structure 21;
[0053] forming a re-wiring layer 42 covering the inner wall of the first trench 24 and the top surface of the first dielectric layer 22, and electrically connecting with the conductive structure 21, as shown in Figure 4
[0054] Specifically, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process can be used to deposit a dielectric material such as TEOS (Tetraethyl orthosilicate) on the first substrate 20 to form the first dielectric layer 22. The first dielectric layer 22 is used to protect the first substrate 20 from damage caused by subsequent processes. Then, a photolithography process can be used to pattern the first dielectric layer 22 to form the first trench 24 through the first dielectric layer 22 along the Z-axis direction and exposing the conductive structure 21 in the first substrate 20, as shown in Figure 2 The specific shape of the first trench 24 can be selected by those skilled in the art according to actual needs. In an example, the projection of the first trench 24 on the top surface of the first substrate 20 is annular, thereby fully exposing the conductive structure to increase the contact area between the re-wiring layer 42 in the first trench 24 and the conductive structure 21.
[0055] In some embodiments, the specific steps of forming the re-wiring layer 42 covering the inner wall of the first trench 24 and the top surface of the first dielectric layer 22, and electrically connecting with the conductive structure 21 include:
[0056] depositing a re-wiring material on the first dielectric layer 22 to form an initial re-wiring layer 23 covering the inner wall of the first trench 24 and the top surface of the first dielectric layer 22, and electrically connecting with the conductive structure 21, as shown in Figure 2
[0057] patterning the initial re-wiring layer 23 to form a second trench 40 exposing the first dielectric layer 22, and the remaining initial re-wiring layer 23 as the re-wiring layer 42, the second trench 40 separating the re-wiring layer 42 into multiple contact areas 41, as shown in Figure 4
[0058] Specifically, after forming the first trench 24 exposing the conductive structure 21, an atomic layer deposition process can be used to deposit a conductive material such as an alloy on the first dielectric layer 22 to form an initial re-wiring layer 23 continuously covering the inner wall of the first trench 24 and the top surface of the first dielectric layer 22, and electrically connecting with the conductive structure 21, as shown in Figure 2 Figure 3 The initial redistribution layer 23 is then etched down along the etching windows 31 to form second trenches 40 exposing the first dielectric layer 22, and the remaining initial redistribution layer 23 serves as a redistribution layer 42, and the second trenches 40 separate the redistribution layer 42 into a plurality of contact areas 41, as shown in FIG. 4B. Figure 4 The redistribution layer 42 is used to lead signals of the conductive structures 21 out of the first substrate 20, or to lead external control signals into the conductive structures 21.
[0059] The electrical test on the conductive structures 21 at the contact areas 41 can be a WAT (Wafer Acceptable Test) or a CP (Chip Probe) test. In some embodiments, the specific steps of the electrical test on the conductive structures 21 at the contact areas 41 include:
[0060] The test signal is transmitted to the contact areas 41 by the probe 50 to perform the probe test on the conductive structures 21.
[0061] Specifically, during the patterning of the initial redistribution layer 23, the position coordinates of the contact areas 41 in the redistribution layer 42 are obtained and stored for subsequent positioning of the contact areas 41. After the initial redistribution layer 23 is etched to form the redistribution layer 42 including the contact areas 41, the probe 50 is directly moved to above the contact areas 41 by the stored position coordinates of the contact areas 41, and the performance of the conductive structures 21 in the first substrate 20 is electrically tested by direct contact between the probe 50 and the contact areas 41. After the electrical test on the conductive structures 21 is completed by the contact between the probe 50 and the contact areas 41, the contact areas 41 remain the probe test marks caused by the contact between the probe 50 and the contact areas 41.
[0062] In some embodiments, the specific steps of forming the protective layer on the redistribution layer 42 include:
[0063] The protective layer is formed to cover the surface of the redistribution layer 42 and cover the inner wall of the second trenches 40.
[0064] In some embodiments, the specific steps of forming the protective layer on the redistribution layer 42 include:
[0065] The first protective layer 60 is formed to cover the redistribution layer 42, as shown in FIG. 6B. Figure 6
[0066] The second protective layer 70 is formed to cover the first protective layer 60, as shown in FIG. 6C, and the first protective layer 60 and the second protective layer 70 together form the protective layer. Figure 7
[0067] Specifically, after the redistribution layer 42 is formed, a first insulating medium material such as silicon nitride can be deposited on the redistribution layer 42 by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process to form a first protective layer 60 that continuously covers the surface of the redistribution layer 42 (including the top surface of the redistribution layer 42 and the sidewall of the redistribution layer 42) and the inner wall of the second trench 40 (including the sidewall of the second trench 40 and the bottom wall of the second trench 40). The first protective layer 60 covers the probe test marks on the contact area 41. In an example, the first protective layer 60 does not fill the first trench 24 and the second trench 40. The first protective layer 60 is used to protect the redistribution layer 42 and the first substrate 20 from damage caused by harmful substances in the external environment. Then, a second insulating medium material such as polyimide can be deposited on the first protective layer 60 by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process to form a second protective layer 70 that covers the first protective layer 60 and fills the first trench 24 and the second trench 40, as shown in FIG. 6. The second protective layer 70 is used to prevent water vapor in the external environment from entering to avoid affecting the redistribution layer 42. Figure 7
[0068] The present specific embodiment is described by taking the protective layer as an example including the first protective layer 60 and the second protective layer 70. In other embodiments, the protective layer can also be a single-layer structure to further simplify the manufacturing process of the semiconductor structure.
[0069] In some embodiments, the specific steps of electrically connecting the first substrate 20 and the second substrate 90 through the contact area 41 include:
[0070] The first substrate 20 and the second substrate 90 are electrically connected by the bonding structure at the contact area 41.
[0071] In some embodiments, the specific steps of electrically connecting the first substrate 20 and the second substrate 90 through the bonding structure at the contact area 41 include:
[0072] The bonding structure is formed on the first substrate 20 or the second substrate 90.
[0073] A bonding force is applied to the first substrate 20 or the second substrate 90, and the bonding structure penetrates the protective layer and is in contact with the redistribution layer 42 of the contact area 41 under the action of the bonding force.
[0074] The present embodiment directly electrically connects the second substrate 90 and the first substrate 20 through the contact area 41, integrates the area for testing (i.e., the testing area) and the area for electrically connecting the second substrate 90 (i.e., the connecting area), not only ensures the smooth execution of the testing process on the conductive structure 21 and the process of connecting the first substrate 20 and the second substrate 90, but also can reduce the size of the redistribution layer 42, thereby helping to reduce the manufacturing cost of the semiconductor structure and further reducing the size of the semiconductor structure. In addition, after forming the protective layer, no etching or other patterning process is required on the protective layer. Instead, the bonding structure above the protective layer is directly pressed into the contact area 41 in the redistribution layer 42 by external force, so that the bonding structure penetrates the protective layer along the Z-axis direction and is in electrical connection with the contact area 41 in the redistribution layer 42, thereby reducing the number of masks in the semiconductor structure forming process and reducing the process steps in the semiconductor structure forming process, simplifying the manufacturing process of the semiconductor structure and improving the manufacturing efficiency of the semiconductor structure.
[0075] In some embodiments, the specific steps of electrically connecting the first substrate 20 and the second substrate 90 through the bonding structure in the contact area 41 include:
[0076] forming the first bonding structure 80 on the surface of the protective layer to form the bonding structure including the first bonding structure 80;
[0077] providing the second substrate 90 and making the second substrate 90 face the first bonding structure 80;
[0078] applying a bonding force on the first substrate 20 or the second substrate 90, and the first bonding structure 80 penetrates the protective layer and is in electrical connection with the redistribution layer 42 of the contact area 41 under the action of the bonding force.
[0079] For example, after forming the first protective layer 60 and the second protective layer 70, forming the first bonding layer 92 on the top surface of the second protective layer 70 and the first bonding structure 80 such as a solder ball on the first bonding layer 92, and forming the second bonding layer 93 on the second substrate 90 and the second bonding structure 91 such as a solder ball on the second bonding layer 93, and the projection of the first bonding structure 80 on the top surface of the first substrate 20 and the projection of the contact area 41 on the top surface of the first substrate 20 at least distribute overlap. In an example, the projection of the first bonding structure 80 on the top surface of the first substrate 20 is entirely located inside the projection of the contact area 41 on the top surface of the first substrate 20. Then, bond the first substrate 20 and the second substrate 90 in the direction of the first bonding structure 80 facing the second bonding structure 91 (for example Figure 9In the Z-axis direction in the first bonding layer 92), during the bonding process, a bonding force for bonding the first substrate 20 and the second substrate 90 is applied to the surface of the second substrate 90 away from the first substrate 20, and the bonding force can press the first bonding structure 80 inward from the surface of the first bonding layer 92 through the second substrate 90, so that the first bonding structure 80 can be directed along the second substrate 90 to the direction of the first substrate 20 (for example Figure 9 In the Z-axis direction in the first bonding layer 92), during the bonding process, a bonding force for bonding the first substrate 20 and the second substrate 90 is applied to the surface of the second substrate 90 away from the first substrate 20, and the bonding force can press the first bonding structure 80 inward from the surface of the first bonding layer 92 through the second substrate 90, so that the first bonding structure 80 can be directed along the second substrate 90 to the direction of the first substrate 20 (for example
[0080] In other embodiments, the specific steps of electrically connecting the first substrate 20 and the second substrate 90 through the bonding structure at the contact area 41 include:
[0081] providing the second substrate 90;
[0082] forming the first bonding structure 80 on the second substrate 90 to form a bonding structure including the first bonding structure 80;
[0083] applying a bonding force to the first substrate 20 or the second substrate 90, and the first bonding structure 80 is pressed into the protective layer by the bonding force and is in contact with the contact area 41 for electrical connection.
[0084] For example, the first bonding structure 80 (such as a solder ball) can also be formed only on the second substrate 90, and no bonding structure such as a solder ball is formed on the first substrate 20. During the bonding process of the first substrate 20 and the second substrate 90, the first bonding structure 80 is pressed into the protective layer by the bonding force, so that the first bonding structure 80 can be in contact with the contact area 41 in the redistribution layer 42 for electrical connection. At this time, not only can the alignment requirement during the bonding process of the first substrate 20 and the second substrate 90 be reduced, but also the process of forming the bonding structure on the first substrate 20 can be saved, thereby further improving the manufacturing efficiency of the semiconductor structure.
[0085] The specific embodiments are described by taking the bonding connection of the first substrate 20 and the second substrate 90 through the bonding structure as an example. In other specific embodiments, other ways can be used to realize the electrical connection of the first substrate 20 and the second substrate 90, such as by providing a connection structure electrically connected to the redistribution layer 42 at the contact area 41, and depositing the second substrate 90 above the connection structure, so as to meet the process requirements of different types of semiconductor structures.
[0086] The specific embodiments also provide a semiconductor structure. The semiconductor structure provided by the specific embodiments can be used in the semiconductor structure provided by the specific embodiments. Figures 1-9The method for forming the semiconductor structure shown forms a schematic diagram of the semiconductor structure, which can be seen from Figure 9 As shown in Figures 1-9 The semiconductor structure includes:
[0087] The first substrate 20 includes the conductive structure 21 in the first substrate 20;
[0088] The redistribution layer 42 is located on the first substrate 20 and is electrically connected with the conductive structure 21, and the redistribution layer 42 includes the contact area 41 having the test trace in the redistribution layer 42;
[0089] The protective layer covers the redistribution layer 42;
[0090] The second substrate 90 is located on the protective layer, and the second substrate 90 is electrically connected with the first substrate 20 through the contact area 41.
[0091] Specifically, the first substrate 20 can be a semiconductor device such as a DRAM (Dynamic Random Access Memory). Taking the first substrate 20 as an example of a DRAM, the first substrate 20 can include a substrate and the conductive structure 21 located above the substrate. The substrate can be, but is not limited to, a silicon substrate, and the present embodiment takes the substrate as a silicon substrate for example. In other embodiments, the substrate can also be a gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI semiconductor substrate. The second substrate 90 can be a packaging substrate such as a PCB (Printed Circuit Board). In an example, the material of the redistribution layer 42 is a conductive material such as an alloy. The redistribution layer 42 is used to lead the signal of the conductive structure 21 out of the first substrate 20 or to lead the external control signal into the conductive structure 21. The test trace can be formed by testing (for example, WAT (Wafer Acceptable Test) or CP (Chip Probe)) the conductive structure 21 at the contact area 41.
[0092] The present embodiment directly electrically connects the second substrate 90 and the first substrate 20 through the contact area 41, combines the area for testing (i.e., the test area having the test trace) and the area for electrically connecting the second substrate 90 (i.e., the connection area), not only ensures the smooth execution of the test process of the conductive structure 21 and the process of connecting the first substrate 20 and the second substrate 90, but also can reduce the size of the redistribution layer 42, thereby helping to reduce the manufacturing cost of the semiconductor structure and further reducing the size of the semiconductor structure.
[0093] In some embodiments, the redistribution layer 42 includes a plurality of spaced contact areas 41 and a second groove 40 located between adjacent contact areas 41.
[0094] The protective layer continuously covers the inner wall of the second trench 40 and the surface of the contact area 41.
[0095] Specifically, when the semiconductor structure is formed by the method for forming a semiconductor structure as shown in Figures 1-9 The re-distribution layer 42 including the contact area 41 is formed before the protective layer is formed, and the re-distribution layer 42 is no longer etched after the protective layer is formed, so that the protective layer in the formed semiconductor structure can continuously cover the inner wall of the second trench 40 and the surface of the contact area 41, thereby better protecting the sidewall of the re-distribution layer 42 and ensuring the yield of the re-distribution layer 42. By arranging a plurality of contact areas 41 (for example, the plurality of contact areas 41 are arranged at intervals along the X-axis direction in Figure 4 On the one hand, it is convenient to test the plurality of areas in the conductive structure 21 respectively; on the other hand, it is also convenient to connect the second substrate 90 with the first substrate 20 through the plurality of contact areas 41, so as to further enhance the connection stability between the first substrate 20 and the second substrate 90.
[0096] In some embodiments, the protective layer includes:
[0097] The first protective layer 60 continuously covers the inner wall of the second trench 40 and the surface of the contact area 41.
[0098] The second protective layer 70 covers the surface of the first protective layer 60.
[0099] In an example, the material of the first protective layer 60 is silicon nitride. The first protective layer 60 is used to protect the re-distribution layer 42 and the first substrate 20 from damage caused by harmful substances in the external environment. The material of the second protective layer 70 can be polyimide. The second protective layer 70 is used to prevent water vapor in the external environment from entering, so as to avoid affecting the re-distribution layer 42. In other examples, the protective layer can also be a single-layer structure covering the re-distribution layer 42.
[0100] In some embodiments, the semiconductor structure further includes:
[0101] The bonding structure is located between the first substrate 20 and the second substrate 90, and one end of the bonding structure penetrates the protective layer and is electrically connected with the re-distribution layer 42 of the contact area 41, and the other end is electrically connected with the second substrate 90.
[0102] For example, after the protective layer is formed, no further patterning process such as etching is needed for the protective layer. Instead, the bonding structure above the protective layer is directly pressed to the contact area 41 in the redistribution layer 42 by an external force, so that the bonding structure penetrates the protective layer along the Z-axis direction and is in contact with the contact area 41 in the redistribution layer 42 for electrical connection. In this way, the number of masks and the number of process steps in the process of forming the semiconductor structure are reduced, the manufacturing process of the semiconductor structure is simplified, and the manufacturing efficiency of the semiconductor structure is improved. In an example, the bonding structure is in contact with the top surface of the redistribution layer 42 to avoid damage to the first substrate 20 during the pressing of the bonding structure. In another example, the bonding structure is partially embedded in the redistribution layer 42 to increase the contact area between the bonding structure and the redistribution layer 42 and reduce the contact resistance between the bonding structure and the redistribution layer 42. In an example, the bonding structure can be a solder ball.
[0103] In an example, the bonding structure can include a first bonding structure 80 formed on the first substrate 20 and a second bonding structure 91 formed on the second substrate 90. The first bonding structure 80 is in electrical connection with the redistribution layer 42, and the projection of the first bonding structure 80 on the top surface of the first substrate 20 at least partially overlaps with the projection of the contact area 41 on the top surface of the first substrate 20. The first substrate 20 and the second substrate 90 are bonded in a direction in which the first bonding structure 80 faces the second bonding structure 91. During the bonding process, the bonding force for bonding the first substrate 20 and the second substrate 90 is applied to the surface of the second substrate 90 away from the first substrate 20 and / or to the surface of the first substrate 20 away from the second substrate 90. The bonding force can cause the first bonding structure 80 to penetrate the protective layer in a direction (e.g., the Z-axis direction in FIG. 1) from the second substrate 90 to the first substrate 20 through the protective layer and be in direct contact with the contact area 41 in the redistribution layer 42 for electrical connection. Figure 9 In an example, the second substrate 90 can be a packaging substrate. The first bonding structure 80 and the second bonding structure 91 can both be solder balls.
[0104] In another example, the bonding structure can only include the first bonding structure 80 formed on the first substrate 20. During the bonding of the first substrate 20 and the second substrate 90, the first bonding structure 80 is pressed into the protective layer by the bonding force, so that the first bonding structure 80 can be in contact with the contact area 41 in the redistribution layer 42 for electrical connection.
[0105] In some embodiments, the position at which the bonding structure contacts the contact area 41 is outside the test mark, to further enhance the stability of the connection between the bonding structure and the redistribution layer 42; or,
[0106] The position of the bonding structure contacting the contact area 41 at least partially coincides with the test mark, thereby helping to further reduce the size of the redistribution layer 42.
[0107] The semiconductor structure and the forming method thereof provided by some embodiments of the present embodiment have the following advantages. By testing the contact area of the redistribution layer and using the contact area as the connecting area of the first substrate and the second substrate, on one hand, the test area and the connecting area are combined into one, and there is no need to separately form an area for probe testing and an area for connecting the second substrate, thereby simplifying the manufacturing process of the semiconductor structure and improving the manufacturing efficiency of the semiconductor structure; on the other hand, the combination of the test area and the connecting area helps to reduce the area of the redistribution layer, thereby being able to reduce the manufacturing cost of the semiconductor structure and reduce the size of the semiconductor structure.
[0108] The above merely describes the preferred embodiments of the present disclosure, and it should be noted that, for those skilled in the art, some improvements and refinements can be made without departing from the principles of the present disclosure, and these improvements and refinements should also be considered as the protection scope of the present disclosure.
Claims
1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a first substrate, the first substrate comprising a conductive structure therein; forming a redistribution layer on the first substrate, the redistribution layer being electrically connected to the conductive structure, the redistribution layer comprising a contact area; electrically testing the conductive structure at the contact area; after the electrical testing, forming a first protective layer on the redistribution layer, the first protective layer being silicon nitride; forming a second protective layer on the first protective layer, the second protective layer being polyimide; forming a first bonding layer on a top surface of the second protective layer, and forming a first bonding structure on the first bonding layer; providing a second substrate, and forming a second bonding layer on the second substrate, and forming a second bonding structure on the second bonding layer; applying a bonding force for bonding the first substrate and the second substrate on a surface of the second substrate away from the first substrate, one end of the first bonding structure penetrating the first bonding layer, the second protective layer and the first protective layer in a direction of the first substrate along the second substrate under the action of the bonding force, and directly electrically connected to the contact area in the redistribution layer, the other end of the first bonding structure being electrically connected to the second bonding structure.
2. The method according to claim 1, wherein the step of forming the redistribution layer on the first substrate comprises: forming a first dielectric layer on a top surface of the first substrate; forming a first trench penetrating the first dielectric layer and exposing the conductive structure; forming the redistribution layer covering an inner wall of the first trench and a top surface of the first dielectric layer, and being electrically connected to the conductive structure.
3. The method according to claim 2, wherein the step of forming the redistribution layer covering the inner wall of the first trench and the top surface of the first dielectric layer, and being electrically connected to the conductive structure comprises: depositing a redistribution material on the first dielectric layer to form an initial redistribution layer covering the inner wall of the first trench and the top surface of the first dielectric layer, and being electrically connected to the conductive structure; patterning the initial redistribution layer to form a second trench exposing the first dielectric layer, the remaining initial redistribution layer being the redistribution layer, and the second trench separating the redistribution layer into a plurality of contact areas.
4. The method according to claim 1, wherein the step of electrically testing the conductive structure at the contact area comprises: transmitting a test signal to the contact area through a probe to perform a probe test on the conductive structure. The method comprises the following steps: providing a first substrate, the first substrate comprising a conductive structure therein; forming a redistribution layer on the first substrate, the redistribution layer being electrically connected to the conductive structure, the redistribution layer comprising a contact area having an electrical test trace; 5. A semiconductor structure, characterized by forming a first protective layer on the redistribution layer, the first protective layer being silicon nitride; forming a second protective layer on the first protective layer, the second protective layer being polyimide; forming a first bonding layer on the second protective layer; a first bonding structure on the first bonding layer; a second substrate; a second bonding layer on the second substrate, and a second bonding structure on the second bonding layer; one end of the first bonding structure penetrates through the first bonding layer, the second protective layer and the first protective layer, and is directly connected with a contact area having an electrical test trace in the re-distribution layer; the other end is connected with the second bonding structure.
6. The semiconductor structure according to claim 5, wherein the position where the bonding structure contacts the contact area is outside the test trace; or the position where the bonding structure contacts the contact area at least partially coincides with the test trace.
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