A BOOST circuit and a device having the BOOST circuit

Abstract

The present invention discloses a BOOST circuit and a device having the BOOST circuit, belonging to the field of electronic technology. The BOOST circuit includes: a main circuit module, used to charge an energy storage element according to a first input voltage, and to generate an output voltage higher than the first input voltage by discharging the energy storage element; a switch module, used to control the switching of the main circuit module between a charging mode and a discharging mode under the action of a control signal; a control module, used to determine the output of a feedback voltage generated by a resistor feedback unit or a switch capacitor feedback unit according to a first enable signal, and to determine a difference signal between the feedback voltage and a reference signal, and to generate the control signal according to the difference signal and a sampled voltage signal representing the current signal of the switch module. The present invention reduces the power consumption of the feedback network and the area of ​​the chip.

Description

Technical Field

[0001] The invention belongs to the field of electronic technology, and in particular relates to a BOOST circuit and a device having the BOOST circuit. Background Art

[0002] BOOST boost circuits are widely used in low-power devices such as signal modulation and high-voltage sensor power supplies. For the application requirements in wearable devices, the BOOST boost chip is required to reduce power consumption as much as possible. However, when the output voltage of the BOOST boost chip is relatively high, such as 3.3V to 60V or 80V, since the feedback resistor is directly hung under the high voltage, it consumes the current on the high-voltage output side. Therefore, the traditional resistor feedback network requires a very large resistor, otherwise it will consume a lot of power. Therefore, it is necessary to improve the traditional resistor feedback network to reduce the power consumption of the high-voltage BOOST chip in low-power mode. The traditional way to reduce power consumption is generally to reduce the power consumption of the control loop, and the power consumption of the feedback resistor is directly achieved by increasing the resistance. The power consumption of the loop is achieved by adding low-power modes such as BURST mode and skip cycle mode, but reducing the power consumption on the high-voltage side by increasing the resistance will waste a lot of chip area. Summary of the invention

[0003] The object of the present invention is to overcome the deficiencies of the prior art and to provide a BOOST circuit and a device having the BOOST circuit.

[0004] The objective of the present invention is achieved through the following technical solutions:

[0005] A first aspect of the present invention discloses a BOOST circuit, comprising:

[0006] A main circuit module, used for charging the energy storage element according to a first input voltage, and generating an output voltage higher than the first input voltage by discharging the energy storage element;

[0007] A switch module, used for controlling the switching of the main circuit module between a charging mode and a discharging mode under the action of a control signal;

[0008] A control module is used to determine the output of a feedback voltage generated by a resistor feedback unit or a switch capacitor feedback unit according to a first enable signal, determine a difference signal between the feedback voltage and a reference signal, and generate the control signal according to the difference signal and a sampled voltage signal representing the current signal of the switch module.

[0009] Furthermore, the control module comprises:

[0010] A resistance feedback unit, used for attenuating the second input voltage to generate a feedback voltage;

[0011] A switched capacitor feedback unit, used for attenuating the second input voltage to generate a feedback voltage;

[0012] A first selector, used for determining a feedback voltage generated by an output resistor feedback unit or a feedback voltage generated by a switch capacitor feedback unit by a first enable signal;

[0013] A first amplifier, used for determining a difference between the feedback voltage and a reference signal, and amplifying the difference to generate a difference signal;

[0014] The PWM comparison module is used to generate a control signal according to the difference signal and a sampled voltage signal representing the current signal of the switch module.

[0015] Furthermore, the BOOST circuit further includes:

[0016] A current sampling module, used for sampling the current signal in the switch module to obtain a sampled voltage signal representing the current signal of the switch module, and outputting the sampled voltage signal to the control module;

[0017] When the control module outputs the feedback voltage generated by the switch capacitor feedback unit, the current sampling module and the PWM comparison module are intermittently turned on, and the turn-on timing of the current sampling module is the same as the turn-on timing of the PWM comparison module.

[0018] Furthermore, the main circuit module includes:

[0019] Voltage output terminal;

[0020] an inductor, wherein a first end of the inductor is connected to a first input voltage, and a second end of the inductor is grounded via a switch module;

[0021] a diode, wherein an anode of the diode is connected to the second end of the inductor, and a cathode of the diode is connected to the voltage output end;

[0022] A first capacitor, wherein a first end of the first capacitor is connected to the cathode of the diode, and a second end of the first capacitor is grounded.

[0023] Furthermore, the switch module comprises:

[0024] A second selector is used to determine the first clock signal or the second clock signal as the clock signal of the register under the action of the second enable signal, and the frequency of the first clock signal is higher than the frequency of the second clock signal; wherein, when the control module outputs the feedback voltage generated by the resistor feedback unit, the second selector determines the clock signal of the register with the first clock signal, and when the control module outputs the feedback voltage generated by the switch capacitor feedback unit, the second selector determines the second clock signal as the clock signal of the register;

[0025] A register, configured to output a first signal according to the control signal and the clock signal;

[0026] The power driving module is used to connect or disconnect the connection between the second end of the inductor and the ground end under the action of the first signal and the third enable signal.

[0027] Furthermore, the power driving module includes:

[0028] A plurality of driving units, each driving unit is connected in series between the second end of the inductor and the ground end, and the driving unit is used to connect the second end of the inductor and the ground end when the driving unit is turned on, and disconnect the second end of the inductor and the ground end when the driving unit is turned off;

[0029] When the control module outputs the feedback voltage generated by the switch capacitor feedback unit, some of the plurality of drive units are turned off under the action of the corresponding third enable signal.

[0030] Furthermore, the driving unit comprises:

[0031] A driver, configured to be turned on or off under the action of a third enable signal;

[0032] A power tube is connected in series between the second end of the inductor and a ground terminal, and is used to connect the second end of the inductor and the ground terminal when the driver is turned on, and disconnect the second end of the inductor and the ground terminal when the driver is turned off.

[0033] Furthermore, the resistance feedback unit comprises:

[0034] a first resistor, wherein a first end of the first resistor is connected to a second input voltage;

[0035] A second resistor, wherein a first end of the second resistor and a second end of the first resistor are connected to a first common point, the first common point is configured as an output end of the resistor feedback unit, and a second end of the second resistor is grounded.

[0036] Furthermore, the switched capacitor feedback unit comprises:

[0037] a first NMOS transistor, wherein a drain of the first NMOS transistor is connected to a first input voltage, a source and a drain of the first NMOS transistor are connected via a first switch, and a gate of the first NMOS transistor is connected to its drain;

[0038] a second NMOS tube, wherein a gate of the second NMOS tube is connected to a gate of the first NMOS tube;

[0039] a third NMOS tube, wherein the source of the first NMOS tube, the source of the second NMOS tube and the source of the third NMOS tube are connected to a second common point, and the gate of the third NMOS tube is connected to a clock control signal;

[0040] a fourth NMOS tube, wherein the source of the fourth NMOS tube is connected to the drain of the second NMOS tube;

[0041] a fifth NMOS tube, wherein the source of the fifth NMOS tube is connected to the drain of the third NMOS tube, the gate of the fifth NMOS tube is connected to the gate of the fourth NMOS tube at a third common point, and the third common point is connected to the clamping voltage;

[0042] A first PMOS transistor, wherein the gate of the first PMOS transistor is connected to the drain thereof;

[0043] a second PMOS tube, wherein a gate of the second PMOS tube is connected to a gate of the first PMOS tube, a source of the second PMOS tube is connected to a source of the first PMOS tube at a fourth common point, and the fourth common point is connected to a second input voltage;

[0044] a third PMOS tube, wherein the source of the third PMOS tube is connected to the drain of the first PMOS tube, the drain of the third PMOS tube is connected to the drain of the fourth NMOS tube, and the gate of the third PMOS tube is connected to the drain thereof;

[0045] a fourth PMOS tube, wherein the source of the fourth PMOS tube is connected to the drain of the second PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the third PMOS tube, and the drain of the fourth PMOS tube and the drain of the fifth PMOS tube are connected to a fifth common point;

[0046] a second capacitor, wherein a first end of the second capacitor is connected to the fifth common point, and a second end of the second capacitor is connected to a common mode voltage via a second switch;

[0047] a second amplifier, wherein an inverting input terminal of the second amplifier is connected to a second end of a second capacitor via a third switch, an output terminal of the second amplifier is connected to an inverting input terminal thereof via a fourth switch, and a non-inverting input terminal of the second amplifier is connected to a common mode voltage;

[0048] a third capacitor, wherein a first end of the third capacitor is connected to the inverting input end of the second amplifier, a second end of the third capacitor is connected to the output end of the second amplifier via a fifth switch, and a second end of the third capacitor is grounded via a sixth switch;

[0049] A fourth capacitor, wherein a first end of the fourth capacitor is connected to the output end of the second amplifier via a seventh switch, the first end of the fourth capacitor is configured as the output end of the switch capacitor feedback unit, and a second end of the fourth capacitor is grounded.

[0050] A second aspect of the present invention discloses a device comprising the BOOST circuit described in the first aspect of the present invention.

[0051] The beneficial effect of the present invention is that the present invention greatly reduces the power consumption of the feedback network and the chip area in the high-voltage BOOST circuit by reducing the frequency and adding the voltage feedback mode of the switch capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A circuit schematic diagram of the BOOST circuit in the present invention;

[0053] Figure 2 A circuit schematic diagram of a switched capacitor feedback unit in the present invention;

[0054] Figure 3 Schematic diagram of current sampling for multiple power tubes. DETAILED DESCRIPTION

[0055] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0056] See also Figures 1 to 3 The present invention provides a BOOST circuit and a device having the BOOST circuit:

[0057] The first aspect of the present invention discloses a BOOST circuit, such as Figure 1 As shown, the BOOST circuit includes a main circuit module, a control module and a switch module.

[0058] The main circuit module is used for charging the energy storage element according to the first input voltage, and generating an output voltage higher than the first input voltage by discharging the energy storage element.

[0059] In some embodiments, the main circuit module includes an inductor L, a diode D, a first capacitor C1 and a voltage output terminal, the first terminal of the inductor L is connected to the first input voltage, and the second terminal of the inductor L is grounded through a switch module; the anode of the diode D is connected to the second terminal of the inductor L, and the cathode of the diode D is connected to the voltage output terminal; the first terminal of the first capacitor C1 is connected to the cathode of the diode D, and the second terminal of the first capacitor C1 is grounded. When the switch module is turned on, the second terminal of the inductor L is grounded, the first input voltage charges the inductor L, and as time goes by, the current on the inductor L increases continuously, at this time the diode D is reversely cut off, the capacitor is discharged outward through the voltage output terminal, and as time goes by, the voltage across the capacitor decreases continuously; when the switch module is turned off, the second terminal of the inductor L is disconnected from the ground, at this time the diode D is turned on, the first input voltage and the voltage on the inductor L together charge the capacitor, and at the same time discharge outward through the voltage output terminal, and as time goes by, the voltage across the capacitor increases continuously. Figure 1 and Figure 2 HVDD is the high voltage and AVDD is the low voltage.

[0060] The switch module is used to control the switching of the main circuit module between the charging mode and the discharging mode under the action of the control signal.

[0061] In some embodiments, the switch module includes a second selector U4, a register U5 and a power driving module.

[0062] The second selector U4 is used to determine the first clock signal or the second clock signal as the clock signal of the register U5 under the action of the second enable signal. The frequency of the first clock signal is higher than the frequency of the second clock signal. For example, the first clock signal is 500KHz and the second clock signal is 30KHz. When the control module outputs the feedback voltage generated by the resistor feedback unit, the second selector U4 determines the clock signal of the register U5 with the first clock signal. When the control module outputs the feedback voltage generated by the switch capacitor feedback unit SCFB, the second selector U4 determines the second clock signal as the clock signal of the register U5.

[0063] Register U5 is used to output the first signal according to the control signal and the clock signal. Specifically, the R end of register U5 is connected to the output end of the first amplifier U2, the S end of register U5 is connected to the output end of the second selector U4, and the Q end of register U5 is connected to the input end of the power driving module.

[0064] The power driving module is used to connect or disconnect the connection between the second end of the inductor L and the ground end under the action of the first signal and the third enable signal.

[0065] In some embodiments, the power driving module includes a plurality of driving units, each of which is connected in series between the second end of the inductor L and a ground terminal; the driving unit is used to connect the second end of the inductor L to the ground terminal when it is turned on, and disconnect the second end of the inductor L from the ground terminal when it is turned off; wherein, when the control module outputs the feedback voltage generated by the switch capacitor feedback unit SCFB, some of the plurality of driving units are turned off under the action of the corresponding third enable signal. The power driving module uses a plurality of low-power driving units in parallel, turns off some of the driving units in the low power consumption mode, and keeps only another part of the driving units turned on, thereby reducing power consumption.

[0066] In some embodiments, the driving unit includes a power tube and a driver. The driver is used to turn on or off under the action of a third enable signal. The power tube is connected in series between the second end of the inductor L and a ground terminal, and the power tube is used to connect the second end of the inductor L to the ground terminal when the driver is turned on, and disconnect the second end of the inductor L from the ground terminal when the driver is turned off. For example, Figure 1 In the figure, DRIVER1 and DRIVER2 are both drivers, Q1 and Q1 are both power tubes, DRIVER1 and Q1 constitute a driver unit, and DRIVER and Q2 constitute a driver unit.

[0067] The control module is used to determine the output of the feedback voltage generated by the resistor feedback unit or the switch capacitor feedback unit SCFB according to the first enable signal, determine the difference signal between the feedback voltage and the reference signal, and generate a control signal of the switch module according to the difference signal and the sampled voltage signal representing the current signal of the switch module.

[0068] Specifically, the BOOST circuit has two working modes: normal mode and low power mode. When the BOOST circuit is required to be in normal mode, the feedback voltage generated by the resistor feedback unit is used. When the BOOST circuit is required to be in low power mode, the feedback voltage generated by the switch capacitor feedback unit SCFB is used.

[0069] In some embodiments, the control module includes a resistor feedback unit, a switch capacitor feedback unit SCFB, a first selector U1, a first amplifier U2 and a PWM comparison module U3, wherein the first amplifier U2 is an error amplifier. The resistor feedback unit is used to attenuate the second input voltage to generate a feedback voltage; the switch capacitor feedback unit SCFB is used to attenuate the second input voltage to generate a feedback voltage; the first selector U1 is used to determine the feedback voltage generated by the output resistor feedback unit or the feedback voltage generated by the switch capacitor feedback unit SCFB by a first enable signal; the first amplifier U2 is used to determine the difference between the feedback voltage and a reference signal, and amplify the difference to generate a difference signal; the PWM comparison module U3 is used to generate a control signal according to the difference signal and a sampled voltage signal representing the current signal of the switch module.

[0070] The resistor feedback unit uses two resistors in series to divide the voltage, directly dividing the second input voltage by a certain proportion to form a feedback voltage. The switched capacitor feedback unit SCFB uses the switched capacitor technology to attenuate the second input voltage to form a feedback voltage.

[0071] In some embodiments, Figure 1 As shown, the resistance feedback unit includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the second input voltage; the first end of the second resistor R2 and the second end of the first resistor R1 are connected to a first common point, the first common point is configured as the output end of the resistance feedback unit, and the second end of the second resistor R2 is grounded.

[0072] In some embodiments, Figure 2 As shown, the switch capacitor feedback unit SCFB includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a second amplifier OP2, and the second amplifier OP2 is an operational amplifier.

[0073] The drain of the first NMOS transistor MN1 is connected to the first input voltage, the source and drain of the first NMOS transistor MN1 are connected via the first switch T1, and the gate of the first NMOS transistor MN1 is connected to its drain; the gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1; the source of the first NMOS transistor MN1, the source of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3 are connected to a second common point, and the gate of the third NMOS transistor is connected to a clock control signal; the source of the fourth NMOS transistor MN4 is connected to the drain of the second NMOS transistor MN2; the source of the fifth NMOS transistor MN5 is connected to the drain of the third NMOS transistor MN3; The gate of the fifth NMOS tube MN5 and the gate of the fourth NMOS tube MN4 are connected to a third common point, and the third common point is connected to a clamping voltage VCLP (the clamping voltage is used to clamp the source voltage of the fourth NMOS tube MN4 and the fifth NMOS tube MN5 to ensure that the second NMOS tube MN2 and the third NMOS tube MN3 will not be broken down, wherein the third PMOS tube MP3, the fourth PMOS tube MP4, the fourth NMOS tube MN4 and the fifth NMOS tube MN5 are high-voltage tubes, and the remaining MOS tubes are low-voltage tubes); the gate of the first PMOS tube MP1 is connected to its drain; the gate of the second PMOS tube MP2 is connected to the gate of the first PMOS tube MP1 The source of the second PMOS tube MP2 is connected to the source of the first PMOS tube MP1 at a fourth common point, and the fourth common point is connected to the second input voltage; the source of the third PMOS tube MP3 is connected to the drain of the first PMOS tube MP1, the drain of the third PMOS tube MP3 is connected to the drain of the fourth NMOS tube MN4, and the gate of the third PMOS tube MP3 is connected to its drain; the source of the fourth PMOS tube MP4 is connected to the drain of the second PMOS tube MP2, the gate of the fourth PMOS tube MP4 is connected to the gate of the third PMOS tube MP3, and the drain of the fourth PMOS tube MP4 is connected to the drain of the fifth PMOS tube a fifth common point; a first end of the second capacitor C2 is connected to the fifth common point, and a second end of the second capacitor C2 is connected to a common mode voltage VCM via a second switch T2; an inverting input end of the second amplifier OP2 is connected to a second end of the second capacitor C2 via a third switch T3, an output end of the second amplifier OP2 is connected to an inverting input end thereof via a fourth switch T4, and a non-inverting input end of the second amplifier OP2 is connected to a common mode voltage VCM; a first end of the third capacitor C3 is connected to an inverting input end of the second amplifier OP2, a second end of the third capacitor C3 is connected to an output end of the second amplifier OP2 via a fifth switch T5, and a second end of the third capacitor C3 is grounded via a sixth switch T6;The first end of the fourth capacitor C4 is connected to the output end of the second amplifier OP2 via the seventh switch T7, the first end of the fourth capacitor C4 is configured as the output end of the switch capacitor feedback unit SCFB, and the second end of the fourth capacitor C4 is grounded. The first switch T1, the third switch T3 and the fifth switch T5 are connected to the same clock control signal, and the second switch T2, the fourth switch T4 and the sixth switch T6 are connected to the same clock control signal. The gate of the third NMOS tube MN3 is connected to the same clock control signal as the first switch T1. ;

[0074] The first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3 and the fourth PMOS tube MP4 form a current mirror, the first NMOS tube MN1 and the second NMOS tube MN2 form a current mirror, the second capacitor C2 is a sampling capacitor, the third capacitor C3 is an integrating capacitor, and the fourth capacitor C4 is an output holding capacitor.

[0075] The work of the switched capacitor feedback unit SCFB mainly includes a sampling stage, an amplification stage and a holding stage.

[0076] In the sampling phase, the second switch T2, the fourth switch T4 and the sixth switch T6 are closed, and the first switch T1, the third switch T3 and the fifth switch T5 are opened. At this time, the current flowing through the first NMOS tube MN1 is I, the current flowing through the second NMOS tube MN2 is also I, the current of the first PMOS tube MP1 and the second PMOS tube MP2 is also I, and the current of the second PMOS tube MP2 all flows to the second capacitor C2, so the voltage of the first end of the second capacitor C2 will gradually rise to the second input voltage, and the second end of the second capacitor C2 is connected to the common mode voltage VCM. When the voltage of the first end of the second capacitor C2 rises to the second input voltage, the sampling phase ends.

[0077] In the amplification and holding stage, the second switch T2, the fourth switch T4 and the sixth switch T6 are first opened, and then the first switch T1, the third switch T3 and the fifth switch T5 are closed. When the first switch T1, the third switch T3 and the fifth switch T5 are closed, the gate of the first NMOS transistor MN1 is pulled to the ground, and the current of the first NMOS transistor MN1 and the second NMOS transistor MN2 is 0. The first PMOS transistor MP1 and the second PMOS transistor MP2 are also closed, and the third NMOS transistor MN3 is closed. At this time, the voltage at the first end of the second capacitor C2 is discharged through the third MOS transistor and the fifth NMOS transistor MN5, and the charge flows from the third capacitor C3 to the second capacitor C2. At this time, the output voltage of the second amplifier OP2 is Vout = HVDD*C1 / C2, so only the capacitance ratio N of the second capacitor C2 and the third capacitor C3 needs to be set to obtain a feedback voltage with an attenuation of N. The seventh switch T7 is a sampling and holding switch. When the amplification stage is over, the seventh switch T7 will receive a narrow pulse signal, and the input of the second amplifier OP2 is sampled to the fourth capacitor C4, and enter the holding stage. After entering the holding stage, the second amplifier OP2 can be turned off to further reduce power consumption, and the second amplifier OP2 will not be turned on again until the next amplification stage. The clock signal for controlling sampling, amplification and holding is a 30KHz clock, and the sampling clock can be adaptively controlled through the output of the first amplifier U2.

[0078] The first amplifier U2 is used to amplify the difference between the feedback voltage and the reference signal to control the current of the energy storage element. Figure 1 The first amplifier U2 will reduce its own operating power consumption in the low power consumption mode, and will appropriately increase the power consumption in the holding phase of the switched capacitor feedback unit SCFB to enhance the response to the feedback voltage.

[0079] The PWM comparison module U3 is used to compare the difference signal output by the first amplifier U2 and the charging current of the energy storage element, and the output signal of the PWM comparison module U3 is used to control the opening and closing of the power tube in the switch module. The PWM comparison module is turned on intermittently in the low power consumption mode. When the power tube is turned on, the PWM comparison module starts to work. After completing a comparison, the power tube is turned off. At this time, the PWM comparison module U3 will enter the dormant state again until the next time the power tube is turned on. Therefore, in each switching cycle, the working time of the PWM comparison module U3 is very short, and its power consumption is greatly reduced.

[0080] In some embodiments, the BOOST circuit further includes a current sampling module CS. The current sampling module CS is used to sample the current signal in the switch module to obtain a sampled voltage signal representing the current signal of the switch module, and output the sampled voltage signal to the control module; wherein, when the control module outputs the feedback voltage generated by the switch capacitor feedback unit SCFB, the current sampling module CS and the PWM comparison module U3 are intermittently turned on, and the turn-on timing of the current sampling module CS is the same as the turn-on timing of the PWM comparison module. The current sampling module CS will be turned on intermittently in the low power consumption mode, and its turn-on timing is the same as the turn-on timing of the PWM comparison module U3, thereby further reducing power consumption.

[0081] The current signal in the switch module collected by the current sampling module CS is the current signal passing through the power tube. Figure 3 As shown, when there are multiple power tubes, each power tube has a corresponding current sampling tube, which collects the current signal passing through each power tube respectively, and the current signals of all power tubes are superimposed to obtain the current signal of the switch module. Figure 3 As shown, Q3 and Q4 are current sampling tubes, Q1, Q2, Q3 and Q4 are all NMOS tubes, and ISEN1 and ISEN2 are current signals sampled by Q3 and Q4 respectively.

[0082] In some embodiments, the BOOST circuit further includes a MUX module, and the MUX is used to generate corresponding first enable signal, second enable signal, third enable signal, etc., so as to realize switching of the BOOST circuit between normal mode and low power consumption mode.

[0083] A second aspect of this embodiment discloses a device, which includes the BOOST circuit described in the first aspect of this embodiment.

[0084] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A BOOST circuit, characterized in that: include: A main circuit module, used for charging the energy storage element according to a first input voltage, and discharging the energy storage element to generate an output voltage higher than the first input voltage; A switch module, used for controlling the switching of the main circuit module between a charging mode and a discharging mode under the action of a control signal; A control module, configured to determine, according to a first enable signal, to output a feedback voltage generated by a resistor feedback unit or a switch capacitor feedback unit, determine a difference signal between the feedback voltage and a reference signal, and generate the control signal according to the difference signal and a sampled voltage signal representing a current signal of the switch module; The BOOST circuit has two working modes: normal mode and low power mode. When the BOOST circuit is required to be in normal mode, the feedback voltage generated by the resistor feedback unit is used. When the BOOST circuit is required to be in low power mode, the feedback voltage generated by the switch capacitor feedback unit is used. The switched capacitor feedback unit comprises: a first NMOS transistor, wherein a drain of the first NMOS transistor is connected to a first input voltage, a source and a drain of the first NMOS transistor are connected via a first switch, and a gate of the first NMOS transistor is connected to its drain; a second NMOS tube, wherein a gate of the second NMOS tube is connected to a gate of the first NMOS tube; a third NMOS tube, wherein the source of the first NMOS tube, the source of the second NMOS tube and the source of the third NMOS tube are connected to a second common point, and the gate of the third NMOS tube is connected to a clock control signal; a fourth NMOS tube, wherein the source of the fourth NMOS tube is connected to the drain of the second NMOS tube; a fifth NMOS tube, wherein the source of the fifth NMOS tube is connected to the drain of the third NMOS tube, the gate of the fifth NMOS tube is connected to the gate of the fourth NMOS tube at a third common point, and the third common point is connected to the clamping voltage; A first PMOS transistor, wherein the gate of the first PMOS transistor is connected to the drain thereof; a second PMOS tube, wherein a gate of the second PMOS tube is connected to a gate of the first PMOS tube, a source of the second PMOS tube is connected to a source of the first PMOS tube at a fourth common point, and the fourth common point is connected to a second input voltage; a third PMOS tube, wherein the source of the third PMOS tube is connected to the drain of the first PMOS tube, the drain of the third PMOS tube is connected to the drain of the fourth NMOS tube, and the gate of the third PMOS tube is connected to the drain thereof; a fourth PMOS tube, wherein the source of the fourth PMOS tube is connected to the drain of the second PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the third PMOS tube, and the drain of the fourth PMOS tube and the drain of the fifth PMOS tube are connected to a fifth common point; a second capacitor, wherein a first end of the second capacitor is connected to the fifth common point, and a second end of the second capacitor is connected to a common mode voltage via a second switch; a second amplifier, wherein an inverting input terminal of the second amplifier is connected to a second end of a second capacitor via a third switch, an output terminal of the second amplifier is connected to an inverting input terminal thereof via a fourth switch, and a non-inverting input terminal of the second amplifier is connected to a common mode voltage; a third capacitor, wherein a first end of the third capacitor is connected to the inverting input end of the second amplifier, a second end of the third capacitor is connected to the output end of the second amplifier via a fifth switch, and a second end of the third capacitor is grounded via a sixth switch; A fourth capacitor, wherein a first end of the fourth capacitor is connected to the output end of the second amplifier via a seventh switch, the first end of the fourth capacitor is configured as the output end of the switch capacitor feedback unit, and a second end of the fourth capacitor is grounded.

2. A BOOST circuit according to claim 1, characterized in that: The control module comprises: A resistance feedback unit, used for attenuating the second input voltage to generate a feedback voltage; A switched capacitor feedback unit, used for attenuating the second input voltage to generate a feedback voltage; A first selector, used for determining a feedback voltage generated by an output resistor feedback unit or a feedback voltage generated by a switch capacitor feedback unit by a first enable signal; A first amplifier, used for determining a difference between the feedback voltage and a reference signal, and amplifying the difference to generate a difference signal; The PWM comparison module is used to generate a control signal according to the difference signal and a sampled voltage signal representing the current signal of the switch module.

3. A BOOST circuit according to claim 2, characterized in that: The BOOST circuit further includes: A current sampling module, used for sampling the current signal in the switch module to obtain a sampling voltage signal representing the current signal of the switch module, and outputting the sampling voltage signal to the control module; When the control module outputs the feedback voltage generated by the switched capacitor feedback unit, the current sampling module and the PWM comparison module are intermittently turned on, and the turn-on timing of the current sampling module is the same as the turn-on timing of the PWM comparison module.

4. A BOOST circuit according to claim 1, characterized in that: The main circuit module comprises: Voltage output terminal; an inductor, wherein a first end of the inductor is connected to a first input voltage, and a second end of the inductor is grounded via a switch module; a diode, wherein an anode of the diode is connected to the second end of the inductor, and a cathode of the diode is connected to the voltage output end; A first capacitor, wherein a first end of the first capacitor is connected to the cathode of the diode, and a second end of the first capacitor is grounded.

5. A BOOST circuit according to claim 4, characterized in that: The switch module comprises: A second selector is used to determine the first clock signal or the second clock signal as the clock signal of the register under the action of the second enable signal, and the frequency of the first clock signal is higher than the frequency of the second clock signal; wherein, when the control module outputs the feedback voltage generated by the resistor feedback unit, the second selector determines the clock signal of the register with the first clock signal, and when the control module outputs the feedback voltage generated by the switch capacitor feedback unit, the second selector determines the second clock signal as the clock signal of the register; A register, configured to output a first signal according to the control signal and the clock signal; The power driving module is used to connect or disconnect the connection between the second end of the inductor and the ground end under the action of the first signal and the third enable signal.

6. A BOOST circuit according to claim 5, characterized in that: The power driving module comprises: A plurality of driving units, each driving unit is connected in series between the second end of the inductor and the ground end, and the driving unit is used to connect the second end of the inductor and the ground end when the driving unit is turned on, and disconnect the second end of the inductor and the ground end when the driving unit is turned off; When the control module outputs the feedback voltage generated by the switch capacitor feedback unit, some of the plurality of drive units are turned off under the action of the corresponding third enable signal.

7. A BOOST circuit according to claim 6, characterized in that: The driving unit comprises: A driver, configured to be turned on or off under the action of a third enable signal; A power tube is connected in series between the second end of the inductor and a ground terminal, and is used to connect the second end of the inductor and the ground terminal when the driver is turned on, and disconnect the second end of the inductor and the ground terminal when the driver is turned off.

8. A BOOST circuit according to claim 1, characterized in that: The resistance feedback unit comprises: a first resistor, wherein a first end of the first resistor is connected to a second input voltage; A second resistor, wherein a first end of the second resistor and a second end of the first resistor are connected to a first common point, the first common point is configured as an output end of the resistor feedback unit, and a second end of the second resistor is grounded.

9. A device, characterized in that: Comprising the BOOST circuit as described in any one of claims 1-8.

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