Minimum High-Frequency Zero-Sequence Circulating Current Modulation Method Based on Vector Redundancy

Abstract

The present invention discloses a minimum high-frequency zero-sequence circulating current modulation method based on vector redundancy, belonging to the technical field of high-frequency zero-sequence circulating current suppression. The method comprises the following steps: sub-sector division, dividing each 60-degree sector into 4 sub-sectors and marking them; determination strategy formulation, deriving the boundary conditions of the sub-sectors according to the division of the sub-sectors, and formulating a sub-sector determination strategy for determining the type of the sub-sector where the reference voltage vector is located according to the boundary conditions; optimal vector sequence design, selecting an equivalent voltage vector with the switching state function ΔS being 0 to design the vector sequence of the sub-sector; calculating the three-phase duty ratios of different sectors. Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention makes full use of the redundancy characteristics of the equivalent voltage vector, thereby improving the current sharing degree of the load current, reducing the loss and improving the efficiency; it also reduces the impact of the load current on the power devices and improves the system reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-frequency zero-sequence circulating current suppression, and particularly relates to a minimum high-frequency zero-sequence circulating current modulation method based on vector redundancy. Background Art

[0002] When modulation techniques such as carrier interleaving are applied to a parallel inverter system, although the equivalent switching frequency is increased, there are differences in the switching states of power devices, resulting in high-frequency circulating current. The high-frequency circulating current can cause the system load current to be unbalanced and the efficiency to decrease. When the circulating current is too large, the load current will exceed the current limit of the power device, thus breaking down the power device. The current research on high-frequency circulating current suppression can be divided into two categories: the carrier interleaving method and the three-level modulation method. The processing object of the carrier interleaving method is the carrier of the modulation technique. The implementation method is simple, the circulating current suppression effect is good, and it can be adapted to parallel systems with more modules. The three-level modulation method is mainly aimed at a dual-parallel inverter. Based on the equivalent voltage vector to synthesize the reference voltage vector, while reducing the high-frequency zero-sequence circulating current, it can optimize the switching loss, harmonics and other performances. However, the vector sequence design and implementation process are relatively complex.

[0003] Common high-frequency zero-sequence circulating current suppression methods include Interleaved SVPWM (ISVPWM), Active Zero-State PWM (AZSPWM), Interleaved Carrier Phase-Shift (ICPS PWM), Modified Discontinuous PWM (MDPWM), Optimal Discontinuous PWM (ODPWM), Three-level SVPWM (TLSVPWM), Comprehensive Optimization Discontinuous PWM (CODPWM), High-Performance Discontinuous PWM (HPDPWM), etc. The above common methods will generate high-frequency zero-sequence circulating current in the entire modulation range, and will generate a large amount of high-frequency zero-sequence circulating current at medium and high modulation degrees.

[0004] However, the existing high-frequency zero-sequence circulating current suppression methods do not make full use of the redundancy characteristics of the equivalent voltage vector, and select some vector combinations that will generate high-frequency zero-sequence circulating current for modulation, so that the minimum high-frequency zero-sequence circulating current peak cannot be generated in the entire modulation range. Summary of the Invention

[0005] The purpose of the embodiment of the present invention is to provide a minimum high-frequency zero-sequence circulating current modulation method based on vector redundancy. Based on the redundancy characteristics of the equivalent voltage vector, 20 equivalent voltage vectors with a high-frequency zero-sequence circulating current change rate of 0 are selected, and theoretically, no high-frequency zero-sequence circulating current will be generated. Compared with the existing methods, the present invention will generate the minimum high-frequency zero-sequence circulating current within the entire modulation range, improving the system reliability, and thus can solve at least one technical problem involved in the background technology.

[0006] In order to solve the above technical problems, the present invention is implemented as follows:

[0007] The embodiment of the present invention provides a minimum high-frequency zero-sequence circulating current modulation method based on vector redundancy, including the following steps:

[0008] Step S1, sub-sector division, divide each 60-degree sector into 4 sub-sectors and mark them;

[0009] Step S2, determination strategy formulation, according to the sub-sector division situation, deduce the boundary conditions of the sub-sectors, and formulate a sub-sector determination strategy for determining the sub-sector type where the reference voltage vector is located according to the boundary conditions;

[0010] Step S3, optimal vector sequence design, select the equivalent voltage vector with the switching state function ΔS being 0 to design the vector sequence of the sub-sector;

[0011] Step S4, calculate the three-phase duty ratios of different sectors.

[0012] Optionally, in step S1, the 4 sub-sectors are respectively marked as r1, r2, r3, r4. Among them, in sub-sector r1, the equivalent voltage vectors U0 (U 0(000) -U 0(000) ), U 13 (U 2(110) -U 6(101) ) and U 14 (U 3(010) -U 1(100) ) are used; in sub-sector r2, the equivalent voltage vectors U1 (U 1(100) -U 1(100) ), U 13 (U 2(110) -U 6(101) ) and U 14 (U 3(010) -U 1(100) ) are used; in sub-sector r3, the equivalent voltage vectors U2 (U 2(110) -U 2(110) ), U 13 (U 2(110) -U 6(101) ) and U 14 (U 3(010) -U1(100) ); in sub-sector r4, the equivalent voltage vectors U0 (U 0(000) -U 0(000) ), U1 (U 1(100) -U 1(100) ), U2 (U 2(110) -U 2(110) ) and U0 (U 7(111) -U 7(111) ) are used.

[0013] Optionally, in step S1, after marking the sub-sectors, variable definitions are also included. Define variables and as:

[0014]

[0015] Wherein, and are the reference voltages after per-unitization using V dc ; max, mid, and min represent the maximum value, median value, and minimum value functions.

[0016] Optionally, in step S2, the determination strategy specifically includes:

[0017] Step 1, calculate and

[0018] using the reference voltage

[0019] Step 2, define

[0020] Step 3, judge whether a > 1, b > 1. If so, it is sub-sector r4; if not, execute step 4;

[0021] Step 4, judge whether b <= 1, d <= 1, c >= 1. If so, it is sub-sector r2; if not, execute step 5;

[0022] Step 5, judge whether c < 1. If so, it is sub-sector r1; if not, it is sub-sector r3.

[0023] Optionally, in step S3, the vector sequence for half a cycle of the sub-sectors in sector I is shown in the following table:

[0024] Vector sequence for half a cycle of sector I

[0025]

[0026] αβ-axis reference voltage and Expressed as:

[0027]

[0028] If the reference voltage vector is located in sub - sector r1 of sector I, the volt - second relationship is:

[0029]

[0030] where d0, d 13 and d 14 are the duty cycles of the equivalent voltage vectors U0, U 13 and U 14 respectively;

[0031] Then the duty cycles d0, d 13 and d 14 are expressed as:

[0032]

[0033] According to the vector sequence of half - cycle in sector I, the three - phase duty cycles d a 、d b 、d c in sub - sector r1 of sector I are:

[0034]

[0035] In addition, in sector I, the volt - second relationships of sub - sectors r2, r3 and r4 are respectively expressed as:

[0036]

[0037] where d1 and d2 are the duty cycles of U1 and U2 respectively;

[0038] Derive the three - phase duty cycles d a 、d b 、d c in sub - sectors r2, r3 and r4 of sector I are respectively:

[0039]

[0040]

[0041] Optionally, the three - phase duty cycles of sector I, sector II, sector III, sector IV, sector V, and sector VI are shown in the following table:

[0042] Three - phase duty cycles of different sectors

[0043]

[0044] The beneficial effects of the present invention compared with the prior art are as follows:

[0045] 1. The present invention makes full use of the redundancy characteristics of the equivalent voltage vector, thereby improving the current sharing degree of the load current, reducing the loss, and improving the efficiency; it also reduces the impact of the load current on the power device and improves the system reliability.

[0046] 2. The method provided by the present invention uses a parallel two-level inverter to achieve the output effect of the three-level modulation technology, reducing the current ripple, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to these drawings, where:

[0048] Figure 1 is the sub-sector division diagram provided by the present invention;

[0049] Figure 2 is the topology diagram of the common bus parallel inverter system provided by the present invention;

[0050] Figure 3 is the spatial voltage vector distribution comparison diagram provided by the present invention, where Figure 3 (a) is the spatial voltage vector distribution diagram of a single inverter, Figure 3 (b) is the spatial voltage vector distribution diagram of a dual parallel inverter;

[0051] Figure 4 is the high-frequency zero-sequence circulating current peak value comparison diagram provided by the present invention;

[0052] Figure 5 is the waveform diagram of the gate drive signal of sub-sector r1 (M = 0.4) provided by the present invention;

[0053] Figure 6 is the waveform diagram of the gate drive signal of sub-sector r2 (M = 0.4) provided by the present invention;

[0054] Figure 7 is the waveform diagram of the gate drive signal of sub-sector r3 (M = 0.7) provided by the present invention;

[0055] Figure 8 is the waveform diagram of the gate drive signal of sub-sector r4 (M = 1) provided by the present invention;

[0056] Figure 9 is the current, duty cycle and sector waveform diagram when M = 0.3 provided by the present invention;

[0057] Figure 10 Current, duty cycle and sector waveform diagram when M = 0.6 provided by the present invention;

[0058] Figure 11 Current and circulating current waveform diagram when M = 0.3 provided by the present invention. Specific embodiments

[0059] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0060] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention can be implemented in an order different from those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category and do not limit the number of objects. For example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally represents an "or" relationship between the associated objects before and after.

[0061] The embodiments of the present invention provide a minimum high-frequency zero-sequence circulating current modulation method based on vector redundancy, including the following steps:

[0062] Step S1, sub-sector division, dividing each 60-degree sector into 4 sub-sectors and marking them;

[0063] Step S2, determination strategy formulation, deriving the boundary conditions of the sub-sectors according to the division of the sub-sectors, and formulating a sub-sector determination strategy for determining the type of the sub-sector where the reference voltage vector is located according to the boundary conditions;

[0064] Step S3, optimal vector sequence design, selecting the equivalent voltage vector with the switching state function ΔS being 0 to design the vector sequence of the sub-sector;

[0065] Step S4, calculating the three-phase duty cycles of different sectors.

[0066] In step S1, as shown in Figure 1 , the 4 sub-sectors are respectively marked as r1, r2, r3, r4. Among them, in sub-sector r1, the equivalent voltage vectors U0 (U 0(000) -U 0(000) ) and U13 (U 2(110) -U 6(101) ) and U 14 (U 3(010) -U 1(100) );In sub-sector r2, the equivalent voltage vectors U1 (U 1(100) -U 1(100) ), U 13 (U 2(110) -U 6(101) ) and U 14 (U 3(010) -U 1(100) ) are used; in sub-sector r3, the equivalent voltage vectors U2 (U 2(110) -U 2(110) ), U 13 (U 2(110) -U 6(101) ) and U 14 (U 3(010) -U 1(100) ) are used; in sub-sector r4, the equivalent voltage vectors U0 (U 0(000) -U 0(000) ), U1 (U 1(100) -U 1(100) ), U2 (U 2(110) -U 2(110) ) and U0 (U 7(111) -U 7(111) ) are used.

[0067] It should be further noted that for the parallel inverter system topology as shown in Figure 2 , the instantaneous common-mode voltages of the two inverters are expressed as:

[0068]

[0069] The instantaneous common-mode voltage difference is the excitation source of the high-frequency zero-sequence circulating current, and the change rate of the high-frequency zero-sequence circulating current is:

[0070]

[0071] Analyzing Equation (2), it can be seen that the switching states of the two inverters determine the change rate of the high-frequency zero-sequence circulating current, and the greater the difference in the switching states between the two inverters, the larger the high-frequency zero-sequence circulating current generated. To characterize the change rate of the high-frequency zero-sequence circulating current, the switching state function ΔS is defined as:

[0072] ΔS = S a1 + S b1 + S c1 - S a2 - S b2 - S c2 (3)

[0073] As can be seen from Equation (3), the larger the absolute value of ΔS, the greater the change rate of the high-frequency zero-sequence circulating current, and the greater the peak value of the high-frequency zero-sequence circulating current within one switching period. According to the definition of ΔS, ΔS ranges from -3 to +3.

[0074] A single inverter has 8 voltage vectors, as Figure 3 (a) shows. The dual-parallel inverter has 64 vector combinations, generating more equivalent voltage vectors, as Figure 3 (b) shows. U1, U2, U3, U4, U5, and U6 are called large vectors, and the magnitudes of the large vectors are the same as those of the non-zero vectors of a single inverter. Compared with a single inverter, the dual-parallel inverter has additional medium vectors and small vectors. The medium vectors include U7, U8, U9, U 10 、U 11 、U 12 , and the small vectors include U 13 、U 14 、U 15 、U 16 、U 17 、U 18 .

[0075] The dual-parallel inverter has 64 vector combinations, but only 19 types of equivalent voltage vectors. It can be seen that different vector combinations can generate the same equivalent voltage vector. The corresponding relationships between the vector combinations and the equivalent voltage vectors of the two inverters are summarized in Table 1.

[0076] Table 1 Equivalent Voltage Vectors of Dual-Parallel Inverters

[0077]

[0078] As can be seen from Table 1, an equivalent voltage vector has different vector combinations, which is called the redundancy characteristic of the equivalent voltage vector. This redundancy characteristic is a unique advantage of the dual-parallel inverter, which provides more possibilities for developing advanced modulation techniques.

[0079] In addition, the corresponding relationships between the vector combinations of the two inverters and the switching state function ΔS are shown in Table 2.

[0080] Table 2 Switching State Function ΔS of Different Vector Combinations

[0081]

[0082] In step S1, after marking the sub-sectors, it also includes variable definition. The defined variables and are:

[0083]

[0084] where and For using V dc The per-unit reference voltage; max, mid, and min represent the maximum, median, and minimum value functions.

[0085] In step S2, the determination strategy specifically includes:

[0086] Step 1, calculate using the reference voltage and

[0087] Step 2, define

[0088] Step 3, determine whether a > 1 and b > 1. If so, it is sub-sector r4; if not, execute step 4;

[0089] Step 4, determine whether b <= 1, d <= 1, and c >= 1. If so, it is sub-sector r2; if not, execute step 5;

[0090] Step 5, determine whether c < 1. If so, it is sub-sector r1; if not, it is sub-sector r3.

[0091] In step S3, the smaller the absolute value of the switching state function ΔS, the smaller the high-frequency zero-sequence circulating current generated. Based on this principle, the present invention selects the vector combination with ΔS = 0 for modulation. The equivalent voltage vector and ΔS are marked with background colors in Tables 1 and 2 respectively, and 20 equivalent voltage vectors are marked in Table 1.

[0092] The vector sequence of half a cycle of the sub-sector in sector I is shown in Table 3 below:

[0093] Table 3 Vector sequence of half a cycle of sector I

[0094]

[0095]

[0096] In step S4, calculate the three-phase duty cycles of different sectors, specifically including:

[0097] αβ-axis reference voltage and are expressed as:

[0098]

[0099] If the reference voltage vector is located in sub-sector r1 of sector I, the volt-second relationship is:

[0100]

[0101] Among them, d0, d 13 and d 14 are the duty cycles of the equivalent voltage vectors U0, U 13 and U 14 respectively;

[0102] According to Equations (5) and (6), the duty cycles d0, d 13 and d 14 are expressed as:

[0103]

[0104] According to the vector sequence of the half cycle of Sector I, the three-phase duty cycles d a , d b , d c of Sub-sector r1 in Sector I are:

[0105]

[0106] In addition, in Sector I, the volt-second relationships of Sub-sectors r2, r3, and r4 are respectively expressed as:

[0107]

[0108] Among them, d1 and d2 are the duty cycles of U1 and U2 respectively;

[0109] According to Equations (5) and (9)-(11), the three-phase duty cycles d a , d b , d c of Sub-sectors r2, r3, and r4 in Sector I are respectively:

[0110]

[0111] Similarly, the three-phase duty cycles of other sectors can be deduced. Among them, the three-phase duty cycles of Sector I, Sector II, Sector III, Sector IV, Sector V, and Sector VI are shown in Table 4 below:

[0112] Table 4 Three-phase duty cycles of different sectors

[0113]

[0114]

[0115] The minimum high-frequency zero-sequence circulating current modulation method based on vector redundancy provided by the present invention selects a vector combination with a switching state function ΔS of 0, and theoretically does not generate high-frequency zero-sequence circulating current. Define the modulation degree M as:

[0116]

[0117] Among them, Vm is the amplitude of the reference voltage vector.

[0118] The proposed method theoretically does not generate high-frequency zero-sequence circulating current. Therefore, the peak value expression of the high-frequency zero-sequence circulating current of the proposed method is:

[0119] i0_peak_ISVPWM = 0

[0120] The peak value of the high-frequency zero-sequence circulating current of ISVPWM control under different modulation degrees is expressed as:

[0121]

[0122] The peak value of the zero-sequence circulating current of HPWM is:

[0123]

[0124] The peak value of the zero-sequence circulating current of IDPWM is expressed as:

[0125]

[0126] The peak value of the zero-sequence circulating current of MDPWM is expressed as:

[0127]

[0128] The peak value of the zero-sequence circulating current of AZSPWM is expressed as:

[0129]

[0130] The peak value of the zero-sequence circulating current of TLSVPWM is expressed as:

[0131]

[0132] The peak value of the zero-sequence circulating current of HPDPWM is expressed as:

[0133]

[0134] The peak value of the zero-sequence circulating current of ODPWM is expressed as:

[0135]

[0136] The peak value of the zero-sequence circulating current of CODPWM is expressed as:

[0137]

[0138] A comparison chart of the peak values of the high-frequency zero-sequence circulating current of common PWM methods and the proposed method is obtained, as shown in Figure 4As shown, under the entire modulation depth, the peak values of the circulating currents of ISVPWM, HPWM, and IDPWM are relatively large, while those of HPDPWM, ODPWM, and CODPWM are relatively small. Therefore, the proposed method of the present invention has the smallest peak value of the circulating current.

[0139] (1) Measured gate drive signals

[0140] The IGBT gate drive signals of different sub-sectors were measured, as Figures 5 - 8 shown.

[0141] Figure 5 is the waveform of the gate drive signal of sub-sector r1 in sector I. From Figure 5 it can be seen that the gate drive signals of the 6 upper-bridge-arm IGBTs are very stable without abnormal fluctuations. In addition, the measured vector sequence is consistent with the vector sequence designed in Table 3, and each inverter switches 8 times in one cycle.

[0142] Figure 6 and Figure 7 respectively show the waveforms of the gate drive signals of sub-sector r2 and sub-sector r3 in sector I. From Figure 6 and Figure 7 it can be seen that the low-level and high-level gate drive signals of sub-sector r2 and sub-sector r3 are stable. By comparing with Table 3, it can be known that the measured vector sequence is consistent with the vector sequence designed in Table 3. In addition, each inverter switches 8 times in one cycle.

[0143] Figure 8 is the waveform of the gate drive signal of sub-sector r4 in sector I. From Figure 8 it can be seen that the measured vector sequence is consistent with the vector sequence designed in Table 3, and each inverter switches 6 times in one cycle. In addition, the gate drive signal of the proposed modulation method in sub-sector r4 is the same as that of the carrier-synchronous continuous SVPWM. Since the switching states of the two inverters are the same, no high-frequency zero-sequence circulating current will be caused.

[0144] (2) Duty ratio and sector waveforms

[0145] When the modulation depth M is less than 0.577, the reference voltage vector is always located in sub-sector r1. Figure 9 shows the current, duty ratio, and sector waveforms at modulation depth M = 0.3. From Figure 9 it can be seen that at modulation depth M = 0.3, the sub-sector is always in r1, the three-phase duty ratios are less than 0.5, and the modulation waveforms are continuous.

[0146] When the modulation depth M is between 0.577 and 0.667, the reference voltage vector will pass through sub-sectors r1, r2, and r3. Figure 10 shows the current, duty ratio, and sector waveforms at modulation depth M = 0.6. FromFigure 10 It can be seen that the reference voltage vector has been rotating between sub-sectors r1, r2, and r3. During the sub-sector switching process, the duty cycle signal has a step change, but the three-phase current has no obvious distortion. In addition, from the corresponding relationship between sectors and sub-sectors, it can be seen that the proposed sub-sector determination strategy is accurate.

[0147] (3) Zero-sequence annular manifold

[0148] The current and circulating current waveforms of the modulation method provided by the present invention under the low-profile system (M=0.3) are as follows: Figure 11 As shown. Figure 11 It can be seen that the peak value of the high-frequency zero-sequence circulating current of the proposed modulation method is 0.017A, and the THD of the a-phase current is 4.02%. The proposed modulation method has a very small peak value of the high-frequency zero-sequence circulating current under the low-profile system and generates relatively few current harmonics.

[0149] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0150] In addition, it should be noted that the scope of the methods and systems in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.

[0151] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A minimum high-frequency zero-sequence circulating current modulation method based on vector redundancy, characterized in that, Including the following steps: Step S1, sub-sector division: Divide each 60-degree sector into 4 sub-sectors and label them. After labeling the sub-sectors, variable definitions are also included. Define variables u* max , u* mid and u* min as: Among them, u* a , u* b and u* c are the reference voltages after per-unit normalization using V dc ; max , mid and min represent the maximum, median, and minimum value functions. Step S2, determination strategy formulation. According to the division of sub-sectors, the boundary conditions of the sub-sectors are deduced, and a sub-sector determination strategy for determining the type of sub-sector where the reference voltage vector is located is formulated according to the boundary conditions. The determination strategy specifically includes: Step 1, calculate using the reference voltage u* max , u* mid and u* min ; Step 2, define , , , ; Step 3, determine whether , if so, it is sub-sector r4; if not, execute Step 4; Step 4, determine whether b <= 1, d <= 1, c >= 1. If so, it is sub-sector r2; if not, execute Step 5; Step 5, determine whether c < 1. If so, it is sub-sector r1; if not, it is sub-sector r3; Step S3, optimal vector sequence design, select the vector sequence of the equivalent voltage vector with the switching state function ∆S being 0 in the sub-sector, where, which is the switching state difference between the two inverters and is used to characterize the change rate of the high-frequency zero-sequence circulating current; Step S4, calculate the three-phase duty cycles of different sectors.

2. The method according to claim 1, wherein In step S1, the 4 sub-sectors are respectively labeled as r1, r2, r3, and r4. Among them, in sub-sector r1, the equivalent voltage vectors U 0( U 0(000) - U 0(000) )、 U 13 ( U 2(110) - U 6(101) ) and U 14 ( U 3(010) - U 1(100) ) are used; in sub-sector r2, the equivalent voltage vectors U 1( U 1(100) - U 1(100) )、 U 13 ( U 2(110) - U 6(101) ) and U 14 ( U 3(010) - U 1(100) ) are used; in sub-sector r3, the equivalent voltage vectors U 2( U 2(110) - U 2(110) )、 U 13 ( U 2(110) - U 6(101) ) and U 14 ( U 3(010) - U 1(100) ) are used; in sub-sector r4, the equivalent voltage vectors U 0( U 0(000) - U 0(000) )、 U 1( U 1(100) - U 1(100) )、 U 2( U 2(110) - U 2(110) ) and U 0( U 7(111) - U 7(111) )。 3. The method according to claim 2, wherein In Step S3, the vector sequence of a half cycle of the sub-sectors in Sector I is shown in the following table: Vector sequence of a half cycle of Sector I 4. The method according to claim 3, characterized in that In Step S4, calculating the three-phase duty cycles of different sectors specifically includes: αβ Axis reference voltage u* α and u* β is expressed as: If the reference voltage vector is located in sub-sector r1 of Sector I, the volt-second relationship is: Among them, d 0, d 13, and d 14 are the equivalent voltage vectors U 0, U 13, and U 14 are the duty cycles, respectively; The duty cycle d 0, d 13, and d 14 are represented as: According to the vector sequence of the half cycle of Sector I, the three-phase duty ratios of Sub-sector r1 of Sector I da , db , dc are as follows: In addition, in Sector I, the volt-second relationships of sub-sectors r2, r3, and r4 are respectively expressed as: Among them, d 1 and d 2 are respectively U 1 and U the duty cycles of 1 and 2; Derive the three-phase duty cycles of sub-sectors r2, r3, and r4 in sector I da , db , dc respectively as follows: 。 5. The method according to claim 4, wherein The three-phase duty cycles of Sector I, Sector II, Sector III, Sector IV, Sector V, and Sector VI are shown in the following table: Three-phase duty cycles of different sectors

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