Configuration register group circuit with arbitrary bit write operation

Abstract

The present invention relates to a configuration register group circuit capable of arbitrary bit write operation. The configuration register group circuit capable of arbitrary bit write operation includes: a configuration register group circuit capable of arbitrary bit write operation, including: a write bit filter instruction decoding circuit, the input end of which is used to receive the write bit filter instruction; a write data multiplexer, the first input end of which is connected to the output end of the write bit filter instruction decoding circuit; a configuration register group, the first input end of which is connected to the output end of the write data multiplexer, and the output end of which is connected to the second input end of the write data multiplexer; a read data right alignment circuit, the first input end of which is connected to the output end of the configuration register group, and the second input end of which is connected to the output end of the write bit filter instruction decoding circuit. The configuration register group circuit capable of arbitrary bit write operation in the above-mentioned embodiment has the advantages of short write operation steps, short modification time, fast operation, low test cost and good foolproof mechanism.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a configuration register group circuit capable of arbitrary bit write operations. Background Art

[0002] Integrated circuits often contain some quasi-static storage elements. These quasi-static storage elements are one-dimensional storage structures, and their outputs are directly connected to each IP or EX unit. Common ones include the special function configuration register bank (SFR) in the GPCPU (General-Purpose Central Processing Unit) and the functional configuration register bank in the ASIC (Application Specific Integrated Circuit). These register banks are composed of multiple configuration registers.

[0003] However, the above configuration register group has the following limitations: if you want to change one or more bits of a register, you need to read out the configuration register first, change it to the desired bit value, and then write back the value. However, the above method has the following defects: the write operation steps are long, you need to read out first and then write, the modification time for multiple configuration registers is long, the operation is slow, the testing cost is high, the anti-fool mechanism is poor, etc. Summary of the invention

[0004] Based on this, it is necessary to provide a configuration register group circuit that can perform arbitrary bit write operations in response to the technical problems in the above-mentioned background technology, which has the advantages of short write operation steps, short modification time, fast operation, low testing cost and good anti-fool mechanism.

[0005] To achieve the above-mentioned purpose and other purposes, the present invention provides a configuration register group circuit capable of arbitrary bit write operations, comprising: a write bit filter instruction decoding circuit, comprising an input end and an output end; the input end of the write bit filter instruction decoding circuit is used to receive a write bit filter instruction, and the write bit filter instruction includes an arbitrary bit write operation instruction; a write data multiplexer, comprising a first input end, a second input end and an output end; the first input end of the write data multiplexer is connected to the output end of the write bit filter instruction decoding circuit; a configuration register group, comprising a first input end and an output end; the first input end of the configuration register group is connected to the output end of the write data multiplexer; the output end of the configuration register group is connected to the second input end of the write data multiplexer; a read data right alignment circuit, comprising a first input end, a second input end and an output end; the first input end of the read data right alignment circuit is connected to the output end of the configuration register group; the second input end of the read data right alignment circuit is connected to the output end of the write bit filter instruction decoding circuit.

[0006] In the configuration register group circuit capable of arbitrary bit write operations in the above-mentioned embodiment, a write bit filter instruction decoding circuit is set to receive and decode a write bit filter instruction. The write bit filter instruction is an instruction capable of arbitrary bit write operations. Any bit write operation on the configuration register in the configuration register group can be implemented without reading. This has the advantages of short write operation steps, short modification time, fast operation, low testing cost and a good anti-fool mechanism.

[0007] In some embodiments, the write bit filter instruction includes a custom header or a custom instruction.

[0008] In some embodiments, the configuration register group circuit capable of arbitrary bit write operation further includes: an interface bus for at least receiving a write bit filter instruction and transmitting the received write bit filter instruction to a write bit filter instruction decoding circuit.

[0009] In some embodiments, the configuration register group circuit capable of arbitrary bit write operations also includes: a write enable instruction decoding circuit, including an input end, a first output end and a second output end; the input end of the write enable instruction decoding circuit is connected to the output end of the interface bus; the first output end of the write enable instruction decoding circuit is connected to the write bit filtering instruction decoding circuit.

[0010] In some embodiments, the configuration register group further includes a second input terminal; the configuration register group circuit capable of arbitrary bit write operation further includes: a gate connected to both the second output terminal of the write enable instruction decoding circuit and the second input terminal of the configuration register group.

[0011] In some embodiments, the interface bus is also used to receive address instructions; the configuration register group circuit that can perform arbitrary bit write operations also includes: an address instruction decoding circuit, including an input end and an output end; the input end of the address instruction decoding circuit is connected to the output end of the interface bus.

[0012] In some embodiments, the configuration register group circuit capable of arbitrary bit write operations also includes: a page address instruction decoding circuit, including an input end and an output end; the input end of the page address instruction decoding circuit is connected to the output end of the address instruction decoding circuit; the output end of the page address instruction decoding circuit is connected to the selector.

[0013] In some embodiments, the configuration register group also includes a third input terminal; the configuration register group circuit that can perform arbitrary bit write operations also includes: an offset address instruction decoding circuit, including an input terminal and an output terminal; the input terminal of the offset address instruction decoding circuit is connected to the output terminal of the address instruction decoding circuit; the output terminal of the offset address instruction decoding circuit is connected to the third input terminal of the configuration register group.

[0014] In some embodiments, the write data multiplexer also includes a third input terminal; the interface bus is also used to receive data instructions; the configuration register group circuit that can perform arbitrary bit write operations also includes: a data instruction decoding circuit, including an input terminal and an output terminal; the input terminal of the data instruction decoding circuit is connected to the output terminal of the interface bus; the output terminal of the data instruction decoding circuit is connected to the third input terminal of the write data multiplexer.

[0015] In some embodiments, the configuration register set includes a plurality of configuration registers. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0017] Figure 1 A circuit diagram of a configuration register group circuit capable of arbitrary bit write operation provided in one embodiment of the present invention.

[0018] Figure 2 A circuit diagram of a configuration register group circuit capable of arbitrary bit write operation provided in another embodiment of the present invention.

[0019] Description of reference numerals:

[0020] 10. Interface bus; 11. Write bit filter instruction decoding circuit; 12. Write data multiplexer; 13. Configuration register group; 14. Read data right alignment circuit; 15. Write enable instruction decoding circuit; 16. Selector; 17. Address instruction decoding circuit; 18. Page address instruction decoding circuit; 19. Offset address instruction decoding circuit; 20. Data instruction decoding circuit. DETAILED DESCRIPTION

[0021] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0023] In addition, certain terms used throughout the specification and the claims that follow refer to specific components. Those skilled in the art will understand that manufacturers may refer to components by different names. This document does not intend to distinguish between components that have different names but the same function. In the following description and embodiments, the terms "comprises" and "includes" are used in an open manner and should be interpreted as "including, but not limited to...". Similarly, the term "connected" is intended to express an indirect or direct electrical connection. Accordingly, if one device is connected to another device, the connection can be completed through a direct electrical connection, or through an indirect electrical connection through other devices and connectors.

[0024] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present invention.

[0025] Integrated circuits often contain some quasi-static storage elements, which are usually one-dimensional storage structures, and their outputs are directly connected to various IP or EX units. Common ones include the special function configuration register bank (SFR) in the GPCPU (General-Purpose Central Processing Unit) and the functional configuration register bank in the ASIC (Application Specific Integrated Circuit). These register banks are composed of multiple configuration registers.

[0026] However, the above configuration register group has the following limitations: if you want to change one or more bits of a register, you need to read out the configuration register first, change it to the desired bit value, and then write back the value. However, the above method has the following defects: the write operation steps are long, you need to read it out first and then write it, the modification time for multiple configuration registers is long, the operation is slow, and the testing cost is high; the anti-fool mechanism is poor, if you only modify the desired position without realizing that the initial position has been rewritten, it is very likely that other positions will be written by mistake at the same time; after the read and write operations, you need to shift it by yourself, and then judge and calculate after obtaining the value; it causes a waste of configuration register resources. For some key positions, such as the IP switch enable bit, in order to prevent the bit values ​​from being spliced ​​into a byte or word length with other bits, which may cause possible erroneous write operations, often one bit value occupies the entire configuration register, and other useless bit values ​​waste resources.

[0027] Please refer to Figure 1The present invention provides a configuration register group circuit capable of arbitrary bit write operation. The configuration register group circuit capable of arbitrary bit write operation may include: a write bit filter instruction decoding circuit 11, a write data multiplexer 12, a configuration register group 13 and a read data right alignment circuit. align) 14; wherein, the write bit filter instruction decoding circuit 11 may include an input end and an output end; the input end of the write bit filter instruction decoding circuit 11 is used to receive the write bit filter instruction, and the write bit filter instruction may include but is not limited to any bit write operation instruction; the write data multiplexer 12 may include a first input end, a second input end and an output end; the first input end of the write data multiplexer 12 is connected to the output end of the write bit filter instruction decoding circuit 11; the configuration register group 13 may include a first input end and an output end; the first input end of the configuration register group 13 is connected to the output end of the write data multiplexer 12; the output end of the configuration register group 13 is connected to the second input end of the write data multiplexer 12; the read data right alignment circuit 14 may include a first input end, a second input end and an output end; the first input end of the read data right alignment circuit 14 is connected to the output end of the configuration register group 13; the second input end of the read data right alignment circuit 14 is connected to the output end of the write bit filter instruction decoding circuit 11.

[0028] In the configuration register group circuit capable of arbitrary bit write operations in the above-mentioned embodiment, a write bit filter instruction decoding circuit 11 is set to receive and decode a write bit filter instruction. The write bit filter instruction is an instruction capable of arbitrary bit write operations. Any bit write operations on each configuration register in the configuration register group 13 can be implemented without reading. This has the advantages of short write operation steps, short modification time, fast operation, low testing cost, and a good anti-fool mechanism.

[0029] As an example, the write bit filter instruction may include but is not limited to a custom header or a custom instruction, such as an address instruction.

[0030] Specifically, simple interface protocols (such as IIC SPI) can be decoded by users to identify instructions; complex interface protocols (such as MIPI DSC DP protocol) retain the packets of custom commands, and users can add arbitrary bit write operation instructions according to protocol rules.

[0031] As an example, the write bit filter instruction decoding circuit 11 can realize the following functions: 1) write the bit filter initial bit reset state, which is equivalent to the traditional configuration register read and write operation, compatible with the original design; 2) if there is no write bit filter instruction, this is equivalent to the traditional configuration register read and write operation, compatible with the original design; 3) after each read and write operation, the write bit filter instruction decoding is reset. For the next operation, if no write bit filter instruction is issued, this is equivalent to the traditional configuration register read and write operation, compatible with the original design; 4) issue a write bit filter instruction plus a traditional configuration register read and write instruction to realize a configuration register that can perform arbitrary bit write operations.

[0032] As an example, see Figure 1 The configuration register group circuit capable of arbitrary bit write operation may further include: an interface bus 10, the interface bus 10 is used to at least receive a write bit filter instruction, and transmit the received write bit filter instruction to a write bit filter instruction decoding circuit 11.

[0033] As an example, see Figure 2 The configuration register group circuit capable of arbitrary bit write operation may also include: a write enable instruction decoding circuit 15, which may include an input end, a first output end and a second output end; the input end of the write enable instruction decoding circuit 15 is connected to the output end of the interface bus; the first output end of the write enable instruction decoding circuit 15 is connected to the write bit filtering instruction decoding circuit 11.

[0034] As an example, see Figure 2 , the configuration register group may further include a second input terminal; the configuration register group circuit capable of arbitrary bit write operation may further include: a gate 16, the gate 16 may be connected to both the second output terminal of the write enable instruction decoding circuit 15 and the second input terminal of the configuration register group 13.

[0035] As an example, the gate 16 may be any gate having an enable gate function, such as a MUX or a PASS GATE.

[0036] As an example, see Figure 2 The interface bus 10 can also be used to receive address instructions; the configuration register group circuit that can perform arbitrary bit write operations can also include: an address instruction decoding circuit 17, the address instruction decoding circuit 17 can include an input end and an output end; the input end of the address instruction decoding circuit 17 is connected to the output end of the interface bus 10.

[0037] As an example, see Figure 2The configuration register group circuit capable of arbitrary bit write operation may also include: a page address instruction decoding circuit 18, the page address instruction decoding circuit 18 may include an input end and an output end; the input end of the page address instruction decoding circuit 18 may be connected to the output end of the address instruction decoding circuit 17; the output end of the page address instruction decoding circuit 18 may be connected to the selector 16.

[0038] As an example, the configuration register group 13 also includes a third input terminal; the configuration register group circuit that can perform arbitrary bit write operations may also include: an offset address instruction decoding circuit 19, the offset address instruction decoding circuit 19 may include an input terminal and an output terminal; the input terminal of the offset address instruction decoding circuit 19 is connected to the output terminal of the address instruction decoding circuit 17; the output terminal of the offset address instruction decoding circuit 19 is connected to the third input terminal of the configuration register group 13.

[0039] As an example, the write data multiplexer 12 may also include a third input terminal; the interface bus 10 is also used to receive data instructions; the configuration register group circuit that can perform arbitrary bit write operations may also include: a data instruction decoding circuit 20, the data instruction decoding circuit 20 may include an input terminal and an output terminal; the input terminal of the data instruction decoding circuit 20 is connected to the output terminal of the interface bus 10; the output terminal of the data instruction decoding circuit 20 is connected to the third input terminal of the write data multiplexer 12.

[0040] As an example, the configuration register set 13 may include multiple configuration registers. Specifically, the number of the configuration register set 13 may be set according to actual needs.

[0041] The working principle of the configuration register group circuit structure capable of arbitrary bit write operation of the present invention is as follows: the host sends write and read address instructions (i.e. address instructions), write and read data instructions (i.e. data instructions) and write bit filter instructions; the address instruction decoding circuit 17 decodes the write and read address instructions; the write enable instruction decoding circuit 15 decodes the write enable instruction; the data instruction decoding circuit 20 decodes the data instruction; the write bit filter instruction decoding circuit 11 selects the bit value to be rewritten according to the write bit filter, and the other bit values ​​use the original value; the configuration register in the configuration register group 13 writes the expected data according to the selected bit value during the write operation; the configuration register in the configuration register group 13 shifts the selected position to the bottom right during the read operation to obtain data or value. If the host does not send a write bit filter instruction, the write bit filter instruction filtering circuit does not perform the bit selection operation, just like the original function. The host does not need to clear the write bit filter instruction, and can reset the write bit filter instruction before the next operation.

[0042] The configuration register group circuit capable of arbitrary bit write operation of the present invention issues a write bit filter instruction and then issues a traditional read instruction when it is necessary to right-shift a number of read bits to head alignment or treat them as values, which can omit the work of the tester to calculate the right shift to head alignment by himself, thereby improving the work efficiency. When the write bit filter instruction is not issued and only the traditional read instruction is issued, it is equivalent to the traditional configuration register read operation and is compatible with the original design.

[0043] In the configuration register group circuit of the present invention that can perform arbitrary bit write operations, if only the desired bit value is modified without realizing that the initial bit value has been rewritten, it is very likely that other bit values ​​will be written by mistake at the same time. If there is no write bit filter instruction, all can only be written at once. If only a few bits are to be changed, without knowing other irrelevant values ​​to be written and without knowing that the system has such restrictions, only the desired bit value is modified, and it is very likely that other bit values ​​will be written by mistake at the same time. This is an erroneous operation caused by blind writing. By adding a write bit filter instruction, even if it is an uninformed operation, the basic logic of writing what the write bit filter instruction points to will prevent errors from occurring, thereby having a better anti-fool mechanism.

[0044] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present invention.

[0045] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0046] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A configuration register group circuit capable of arbitrary bit write operation, characterized in that: include: A write bit filter instruction decoding circuit comprises an input end and an output end; the input end of the write bit filter instruction decoding circuit is used to receive a write bit filter instruction, wherein the write bit filter instruction comprises an arbitrary bit write operation instruction; A write data multiplexer, comprising a first input end, a second input end and an output end; the first input end of the write data multiplexer is connected to the output end of the write bit filter instruction decoding circuit; A configuration register group, comprising a first input terminal and an output terminal; the first input terminal of the configuration register group is connected to the output terminal of the write data multiplexer; the output terminal of the configuration register group is connected to the second input terminal of the write data multiplexer; A read data right alignment circuit comprises a first input terminal, a second input terminal and an output terminal; the first input terminal of the read data right alignment circuit is connected to the output terminal of the configuration register group; the second input terminal of the read data right alignment circuit is connected to the output terminal of the write bit filter instruction decoding circuit; Among them, by setting the write bit filter instruction decoding circuit to receive and decode the write bit filter instruction, the write bit filter instruction is the arbitrary bit write operation instruction, and the arbitrary bit write operation of each configuration register in the configuration register group is realized without reading.

2. The configuration register group circuit capable of arbitrary bit write operation according to claim 1, characterized in that: The write bit filtering instruction includes a custom header or a custom instruction.

3. The configuration register group circuit capable of arbitrary bit write operation according to claim 1, characterized in that: The configuration register group circuit capable of arbitrary bit write operation further includes: an interface bus, which is used for at least receiving a write bit filter instruction and transmitting the received write bit filter instruction to the write bit filter instruction decoding circuit.

4. The configuration register group circuit capable of arbitrary bit write operation according to claim 3, characterized in that: The interface bus is also used to receive a write enable instruction; the configuration register group circuit capable of arbitrary bit write operation also includes: The write enable instruction decoding circuit comprises an input end, a first output end and a second output end; the input end of the write enable instruction decoding circuit is connected to the output end of the interface bus; the first output end of the write enable instruction decoding circuit is connected to the write bit filtering instruction decoding circuit.

5. The configuration register group circuit capable of arbitrary bit write operation according to claim 4, characterized in that: The configuration register group further includes a second input terminal; the configuration register group circuit capable of arbitrary bit write operation further includes: A gate is connected to the second output terminal of the write enable instruction decoding circuit and the second input terminal of the configuration register group.

6. The configuration register group circuit capable of arbitrary bit write operation according to claim 5, characterized in that: The interface bus is also used to receive address instructions; the configuration register group circuit capable of arbitrary bit write operation also includes: The address instruction decoding circuit comprises an input end and an output end; the input end of the address instruction decoding circuit is connected to the output end of the interface bus.

7. The configuration register group circuit capable of arbitrary bit write operation according to claim 6, characterized in that: The configuration register group circuit capable of arbitrary bit write operation also includes: The page address instruction decoding circuit comprises an input end and an output end; the input end of the page address instruction decoding circuit is connected to the output end of the address instruction decoding circuit; the output end of the page address instruction decoding circuit is connected to the gate.

8. The configuration register group circuit capable of arbitrary bit write operation according to claim 6, characterized in that: The configuration register group also includes a third input terminal; the configuration register group circuit capable of arbitrary bit write operation also includes: The offset address instruction decoding circuit comprises an input end and an output end; the input end of the offset address instruction decoding circuit is connected to the output end of the address instruction decoding circuit; the output end of the offset address instruction decoding circuit is connected to the third input end of the configuration register group.

9. The configuration register group circuit capable of arbitrary bit write operation according to claim 3, characterized in that: The write data multiplexer also includes a third input terminal; the interface bus is also used to receive data instructions; the configuration register group circuit capable of arbitrary bit write operation also includes: The data instruction decoding circuit comprises an input end and an output end; the input end of the data instruction decoding circuit is connected to the output end of the interface bus; the output end of the data instruction decoding circuit is connected to the third input end of the write data multiplexer.

10. The configuration register group circuit capable of arbitrary bit write operation according to claim 9, characterized in that: The configuration register group includes a plurality of configuration registers.

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