A method for timing prediction before circuit wiring based on graph neural network

Abstract

The present invention discloses a method for timing prediction before circuit wiring based on graph neural network, including constructing a directed graph according to a real reference circuit; obtaining a timing report of the real reference circuit, and screening out characteristic parameters related to arrival time; constructing a data set of the directed graph and the characteristic parameters related to arrival time, and setting labels at the same time; constructing a graph neural network model based on RGAT, and performing training and testing. The present invention adopts RGAT to update node features in the graph embedding stage, and assigns different weights to different relationships by considering the influence of different neighbor nodes and multiple types of edges in the directed graph. This refined weight processing mechanism improves the model's ability to predict the influence of complex factors such as crosstalk in the circuit diagram, and enhances the accuracy of arrival time prediction, especially considering the influence of neighbor node and neighbor edge information on arrival time.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic design automation, and specifically is a method for predicting timing before wiring based on a graph neural network. Background Art

[0002] Static timing analysis engines are often used in various stages of physical design to guide design optimization and achieve timing closure. In the layout stage, the timing estimation results of the static timing analysis engine are inaccurate due to the lack of information such as wire parasitics. Inaccurate results will lead to suboptimal layout quality and greatly affect the quality of downstream routing tasks, resulting in an increase in the number of design iterations.

[0003] To solve the above problems, an accurate and efficient pre-routing timing prediction model based on layout results is crucial, which helps to achieve effective timing-driven layout and avoid redundant routing processes. Current pre-routing timing prediction methods simulate the calculation process of static timing analysis engines, first generate wire net embedding, and then predict layer by layer according to the topological order. The wire net embedding methods of these methods are limited to aggregating the local information of the current connection edge, ignoring the effects of crosstalk between adjacent edges or points, lacking the ability to model global information, and using overly complex algorithms in the prediction of unit delays, which increases the complexity and computational cost of the model, thereby affecting the prediction performance and reasoning speed of the model. Summary of the invention

[0004] The purpose of the present invention is to solve the problems that the current pre-wiring timing prediction work lacks the ability to model global information and uses overly complex algorithms in the prediction of unit delays, and provides a pre-wiring timing prediction method based on graph neural networks.

[0005] In order to solve the above problems, the present invention provides a method for timing prediction before circuit wiring based on graph neural network, the method comprising:

[0006] Step S1: Construct a data set; specifically:

[0007] Construct a directed graph based on real benchmark circuits;

[0008] Obtain timing reports of real benchmark circuits and filter out characteristic parameters related to arrival time;

[0009] Construct a data set with the directed graph and characteristic parameters related to the arrival time, and set labels at the same time; the labels include the arrival time, unit delay time, connection delay time, and conversion time of each device unit pin in the timing report;

[0010] Step S2: Perform data cleaning and normalization on the generated data set, and divide the processed data set into a training set and a test set;

[0011] Step S3: Build a graph neural network model based on RGAT, and train and test it using the training set and test set;

[0012] Step S4: Use the trained and tested RGAT-based graph neural network model to predict the post-routing timing results of the circuit.

[0013] Preferably, step S1 specifically comprises:

[0014] S101: using the pins of the device units in the real reference circuit as nodes of the directed graph, and using the connection edges and unit edges of the device units as edges between the nodes of the directed graph, that is, the connection relationship between the nodes; wherein the connection edge is the connection between two device units, and the connection edge is set as a bidirectional edge; the unit edge is the connection relationship between the input pin and the output pin of the device unit itself, and the unit edge is set as a unidirectional edge;

[0015] S102: Obtaining an adjacency matrix A of the directed graph according to the connection relationship between the nodes of the directed graph;

[0016] S103: Generate a timing report of a real reference circuit; and screen out characteristic parameters related to the arrival time according to the timing report.

[0017] Preferably, the characteristic parameters related to the arrival time in step S103 include node characteristics and unit edge characteristics.

[0018] More preferably, the node features in step S103 include the distance relative to the four boundaries of the chip in the real reference circuit, the pin capacitance, the pin type, and the node type; the pin type includes the PI pin and the PO pin; the node type includes the fan-in node and the fan-out node; the unit edge features include the index value and the delay value of the LUT lookup table.

[0019] Preferably, the RGAT-based graph neural network model in step S3 includes a graph embedding stage and a delay propagation stage;

[0020] The graph embedding stage is to update the node features of all nodes in the directed graph using RGAT with multi-layer residual connections;

[0021] The delay propagation stage analyzes the topological level of the directed graph, and starts from the starting level of the topological level, and realizes the information propagation of the line-out edge or the unit edge layer by layer; the information propagation of the line-out edge and the unit edge is realized by the line delay propagation layer and the unit delay propagation layer respectively, until reaching the termination layer of the topological level;

[0022] More preferably, in the graph embedding stage of step S3, the first layer input of the multi-layer residual connected RGAT is the node feature; the input of the other layers except the first layer is the output of the previous layer; each layer of RGAT updates the input feature, and adds the input feature to the updated feature through the residual connection, and uses the addition result as the output of this layer; the result of the output of the last layer of RGAT is obtained by a multi-layer perceptron MLP to obtain the updated node feature, and the front ɑ vector dimension of the updated node feature is set as the connection delay time prediction value;

[0023] The update of the input features by each layer of RGAT includes the attention head feature fusion stage, the relation head feature fusion stage, and the fusion stage;

[0024] In the fusion stage, the feature vector after the attention head feature fusion and the feature vector after the relation head feature fusion are concatenated, and the linear transformation and The result after the activation function is residually connected with the input of the current layer to obtain the updated node features.

[0025] More preferably, in the delayed propagation stage of step S3, the initial layers of the topological layers of the directed graph are all composed of source nodes of the connected outgoing edges.

[0026] More preferably, in the wire delay propagation layer in the delayed propagation stage of step S3, the input of each wire delay propagation layer is the source node prediction value of the current wire outgoing edge, the embedded fusion feature of the source node, and the embedded fusion feature of the target node; wherein the source node prediction value of the wire outgoing edge adopts the target node prediction value of the previous unit delay propagation layer, and the source node prediction value of the first wire delay propagation layer is initialized to 0; the embedded fusion feature of the source node is the result of the concatenation of the initial node feature of the source node and the node feature after the update in the graph embedding stage; the embedded fusion feature of the target node is the result of the concatenation of the initial node feature of the target node and the node feature after the update in the graph embedding stage;

[0027] The source node prediction value of the current outgoing edge, the embedded fusion features of the source node, and the embedded fusion features of the target node are concatenated, and finally the target node prediction value is obtained through the multi-layer perceptron MLP output, which includes the predicted value of the arrival time and the predicted value of the conversion time.

[0028] More preferably, in the unit delay propagation layer in the delay propagation stage of step S3, the input of each unit delay propagation layer is the source node prediction value of the current unit edge, the embedded fusion feature of the source node, the embedded fusion feature of the target node, and the unit edge feature; the source node prediction value of the unit edge adopts the target node prediction value of the previous line delay propagation layer; the embedded fusion feature of the source node is the result of the concatenation of the initial node feature of the source node and the node feature after the update in the graph embedding stage; the embedded fusion feature of the target node is the result of the concatenation of the initial node feature of the target node and the node feature after the update in the graph embedding stage;

[0029] The source node prediction value of the current cell edge, the embedded fusion feature of the source node, the embedded fusion feature of the target node, and the cell edge feature are concatenated and then output through the multi-layer perceptron MLP;

[0030] Then the output vector of the multi-layer perceptron MLP is split into four parts: the first part is the weight parameter with a length of 1, the second and third parts are two groups of intermediate features of equal length, and the fourth part is the unit delay time prediction value;

[0031] The first part of the results After the activation function is processed, it is multiplied with the second part and the third part respectively to obtain two sets of weighted intermediate features; then the two sets of weighted intermediate features of all unit edges connected to the same target node are summed and maximized respectively, and then the summation and maximum operation results are concatenated, and finally the target node prediction value of the unit delay propagation layer is obtained through the multi-layer perceptron MLP output.

[0032] More preferably, the loss function of the RGAT-based graph neural network model training in step S3 is composed of a loss function for predicting arrival time and conversion time, a loss function for predicting connection delay time, and a loss function for predicting unit delay time, and the formula is as follows:

[0033] Formula (1)

[0034] in is the loss function for predicting arrival time and transition time, , They are the loss function for predicting the connection delay time and the loss function for predicting the unit delay time;

[0035] Formula (2)

[0036] in is the number of all nodes in the directed graph, It is the concatenation of the true value of the arrival time and the true value of the conversion time. It is the concatenation of the arrival time prediction value and the conversion time prediction value;

[0037] Formula (3)

[0038] in is the number of fan-in nodes in the directed graph, is the actual value of the connection delay time, is the predicted value of connection delay time;

[0039] Formula (4)

[0040] in is the number of unit edges in the directed graph, is the actual value of the unit delay time, is the predicted value of the unit delay time.

[0041] The beneficial effects of the present invention are:

[0042] The present invention uses RGAT (Relational Graph Attention Network) technology to update node features in the graph embedding stage. By considering the influence of different neighbor nodes and multiple types of edges (relationships) in the directed graph, different weights are assigned to different relationships, effectively extracting the features required for predicting arrival time. RGAT can assign different weights to different relationships in the circuit diagram. This refined weight processing mechanism improves the model's ability to predict the impact of complex factors such as crosstalk in the circuit diagram, and enhances the accuracy of arrival time prediction, especially considering the impact of neighbor node and neighbor edge information on arrival time.

[0043] The present invention uses the predicted values ​​of the arrival time and conversion time of the previous layer of wire propagation layer, the graph embedding information of the target node, and the characteristic vector of the unit edge in the unit delay propagation layer of the delay propagation stage to predict the unit delay and arrival time. This process simulates the process of modern static timing analysis (STA) unit delay search: the conversion time, i.e. the predicted value of the conversion time of the previous layer of wire propagation layer, and the output capacitance, i.e. the graph embedding information of the target node, are used as the index value input of the unit delay search process, and the index value of the lookup table LUT and the unit delay value, i.e. the unit edge characteristic vector, are matched and searched to obtain the predicted unit delay. The lookup table LUT has high dimensionality, and the characteristic dimension of the unit edge is as high as 512. Compared with the simulation of modern STA using the interpolation algorithm to calculate the unit delay, the model simulates the process of direct table lookup of modern STA, which no longer involves high-dimensional matrix multiplication operations, greatly reduces the complexity of the model and the reasoning time of the model, and increases the accuracy of the model in predicting the unit delay and arrival time. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a flow chart of the pre-wiring timing prediction method based on graph neural network provided by the present invention.

[0045] Figure 2 In the pre-wiring timing prediction method based on graph neural network provided by the present invention, S1 divides the circuit diagram into graph nodes and edges.

[0046] Figure 3 This is a schematic diagram of S301 graph embedding in the pre-wiring timing prediction method based on graph neural network provided by the present invention.

[0047] Figure 4 It is a schematic diagram of the connection delay propagation layer of S302 in the pre-wiring timing prediction method based on graph neural network provided by the present invention.

[0048] Figure 5 It is a schematic diagram of the unit delay propagation layer of S302 in the pre-wiring timing prediction method based on graph neural network provided by the present invention. DETAILED DESCRIPTION

[0049] The principles and features of the pre-wiring timing prediction method based on graph neural network proposed in the present invention are further described in detail below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention, not to limit the scope of the present invention. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.

[0050] The present invention provides a method for timing prediction before wiring based on graph neural network, and its solution flow chart is as follows: Figure 1 As shown, the method includes:

[0051] S1: Constructing the dataset:

[0052] Construct a directed graph based on real benchmark circuits;

[0053] Use the open source software OpenROAD to obtain the timing report of the real benchmark circuit and filter out the characteristic parameters related to the arrival time;

[0054] The directed graph and characteristic parameters related to the arrival time are used to construct a data set, and labels are set at the same time; the labels are the arrival time, unit delay time, connection delay time, and conversion time of each device unit pin in the timing report;

[0055] The specific steps include:

[0056] S101: using the pins of the device units in the real reference circuit as nodes of the directed graph, and using the wire edges of the device units and the unit edges as edges between the nodes of the directed graph, that is, the connection relationship between the nodes; wherein the wire edge is the wire between the two device units, and the wire edge is set as a bidirectional edge, namely a wire out edge and a wire in edge; the wire out edge refers to the edge where the output pin of the device unit is connected to the input pin of another device unit, and the wire in edge is opposite to the wire out edge, which refers to the edge where the input pin of the device unit is connected to the output pin of another device unit; the unit edge is the connection relationship between the input pin and the output pin of the device unit itself, and the unit edge is set as a unidirectional edge from the input pin of one unit to the output pin;

[0057] Figure 2 The schematic diagram of converting a circuit into a graph neural network graph format is shown, with the pins of the units in the circuit as the nodes of the graph, the lines between the units as the line edges, and the connection relationship between the input pins and output pins of the units as the unit edges. The line edges are bidirectional edges, and the unit edges are unidirectional edges from the input pins to the output pins.

[0058] S102: Obtaining an adjacency matrix A of the directed graph according to the connection relationship between the nodes of the directed graph; wherein the adjacency matrix reflects the connection relationship between the nodes, 1 indicates connection, and 0 indicates disconnection;

[0059] S104: generating a timing report of a real reference circuit; and screening out characteristic parameters related to the arrival time according to the timing report;

[0060] The characteristic parameters related to the arrival time include node characteristics, wire edge characteristics, and unit edge characteristics, wherein the node characteristics include the distance relative to four boundaries (upper boundary, left boundary, right boundary, and lower boundary) of the chip in the real benchmark circuit, pin capacitance, pin type, and node type; the pin type includes PI pins and PO pins; the node type includes fan-in nodes and fan-out nodes; the wire edge characteristics include the distance between two nodes along the X-axis or Y-axis direction; the unit edge characteristics include the index value of the LUT lookup table and the delay value of the LUT lookup table.

[0061] S2: Clean and normalize the generated data set, and divide the processed data set into 2 / 3 training set and 1 / 3 test set;

[0062] The data cleaning includes processing abnormal values ​​of characteristic parameters related to the arrival time, and setting all abnormal values ​​to 0; wherein the abnormal values ​​include values ​​that are obviously beyond the normal range and invalid values.

[0063] The normalization is to perform Min-Max normalization on the label, and the Min-Max normalization calculation formula is:

[0064]

[0065] in is the original data value, is the maximum value in the data, is the minimum value in the data, is the normalized data value.

[0066] S3: Build a graph neural network model based on RGAT. The model is divided into two stages: graph embedding and delayed propagation, and initialize the parameters of the model;

[0067] Specifically, the RGAT-based graph neural network model includes a graph embedding stage and a delay propagation stage;

[0068] (1) If Figure 3 The graph embedding stage is to update the node features of all nodes in the directed graph using RGAT with three layers of residual connections;

[0069] The input of the first layer of the multi-layer residual connection RGAT is the node feature. The input of other layers except the first layer is the output of the previous layer. Each layer of RGAT updates the input feature and adds the input feature to the updated feature through the residual connection, and the result is used as the output of this layer.

[0070] The update of the input features by each layer of RGAT includes the attention head feature fusion stage, the relation head feature fusion stage, and the fusion stage;

[0071] The mathematical description of the attention head feature fusion stage is as follows:

[0072]

[0073]

[0074] in, Indicates Layer Node The node features of are the new features after being fused with the attention head features; Indicates the number of heads that are paying attention; Express The attention results of different heads are spliced; Representation Node Neighbor nodes of By A pair of neighboring nodes of a layer and No. The attention weights calculated by the attention heads; It is Tier The weight matrix of the attention heads; Indicates Layer Node The feature vector of .

[0075] The mathematical description of the relation head feature fusion stage is as follows:

[0076]

[0077]

[0078]

[0079] in, Representation Node In the The feature vector of the layer after the features of the relation head are fused; Indicates the number of relationship heads; By A pair of neighboring nodes of a layer and No. The normalized attention coefficient calculated by the relation head; Indicates Tier The weight matrix of the relation head; Representation Node With Node Feature vectors for dependency embedding; express Activation function; , is the learnable weight matrix, , is the bias term;

[0080] In the fusion stage, the feature vector after the attention head feature fusion and the feature vector after the relation head feature fusion are concatenated, and the linear transformation and The result after the activation function is residually connected with the input of the current layer to obtain the updated node features, which is mathematically described as follows:

[0081]

[0082]

[0083] in, It is the concatenation operation between features; Indicates Layer Node Updated features; is the learnable weight matrix, is the bias term; Indicates Layer Node The updated feature, i.e. The input of the layer.

[0084] The mathematical description of the residual connection is as follows:

[0085]

[0086] in, is the input, is the output obtained by the transformation of the current layer, is the output of this layer after residual connection.

[0087] The result of the last layer of RGAT output is used to obtain the updated node features through a multi-layer perceptron MLP, and the front ɑ vector dimension of the updated node features is set as the connection delay time prediction value, and the present invention takes ɑ=4.

[0088] (2) The delay propagation stage is after the graph embedding stage. It analyzes the topological level of the directed graph, takes the embedded fusion feature as input, and realizes the information propagation of the wire-out edge or the unit edge layer by layer starting from the starting layer of the topological layer; the information propagation of the wire-out edge and the unit edge is realized by the set wire delay propagation layer and the unit delay propagation layer respectively until reaching the termination layer of the topological level; the embedded fusion feature is the result of the concatenation of the initial node feature and the node feature updated in the graph embedding stage. In the wire delay propagation layer, the model takes the source node prediction value of the wire-out edge, the embedded fusion feature of the source node, and the embedded fusion feature of the target node as input, and obtains the predicted value of the pin arrival time and conversion time through the MLP output. This process realizes the information transmission on the wire edge and simulates the influence of signal propagation and delay in the actual circuit; in the unit delay propagation layer, the target node prediction value of the wire delay propagation layer, the source node of the unit edge, the embedded fusion feature of the target node, and the unit edge feature are used as input to learn and select the unit table delay value. This method is similar to the unit delay search method in static timing analysis. Then, the calculated unit edge information is sent to the two restoration channels for summation and maximum calculation. The pin feature vector after calculation is output through MLP to obtain the predicted values ​​of the pin's arrival time and conversion time.

[0089] The path of the timing report analysis is composed of alternating circuit connections and device units. Therefore, after the circuit is converted into a directed graph, the topological hierarchy of the directed graph is arranged alternately according to the connection edges and unit edges. The starting point of the timing report analysis is usually set to the starting position of the signal transmission in the circuit connection. Therefore, the initial layer of the topological layer of the directed graph is composed of the source nodes of the outgoing edges of the connection. The source node is the starting point of the edge in the directed graph; the target node is the end point of the edge in the directed graph.

[0090] (2.1) In the connection delay propagation layer, the input of each connection delay propagation layer is the source node prediction value of the current connection outgoing edge, the embedded fusion feature of the source node, and the embedded fusion feature of the target node; wherein the source node prediction value of the connection outgoing edge adopts the target node prediction value of the previous unit delay propagation layer, and the source node prediction value of the first connection delay propagation layer is initialized to 0;

[0091] like Figure 4 The source node prediction value of the current outgoing edge, the embedded fusion features of the source node, and the embedded fusion features of the target node are concatenated, and finally the target node prediction value is obtained through the multi-layer perceptron MLP output. The target node prediction value includes the predicted value of the arrival time and the predicted value of the conversion time.

[0092] The mathematical description of the wire delay propagation layer is as follows:

[0093]

[0094] in, Indicates the predicted value of the target node of the outgoing edge; Indicates the predicted value of the source node of the outgoing edge; and They represent the embedded fusion features of the source node of the outgoing edge and the embedded fusion features of the target node of the outgoing edge, respectively.

[0095] (2.2) In the unit delay propagation layer, the input of each unit delay propagation layer is the source node prediction value of the current unit edge, the embedded fusion feature of the source node, the embedded fusion feature of the target node, and the unit edge feature; as described in (2), the topological hierarchy of the directed graph is arranged alternately according to the connection edge and the unit edge, and the initial layer of the topological layer of the directed graph is composed of the source node of the connection outgoing edge. Therefore, the first unit delay propagation layer must have the previous connection delay propagation layer, and the source node prediction value of the unit edge adopts the target node prediction value of the previous connection delay propagation layer;

[0096] like Figure 5 The source node prediction value of the current outgoing edge, the embedded fusion feature of the source node, the embedded fusion feature of the target node, and the unit edge feature are concatenated and then output through the multi-layer perceptron MLP.

[0097] The mathematical description of the splicing operation is as follows:

[0098]

[0099] in, Represents the predicted value of the unit edge source node; and They represent the embedded fusion features of the source node of the unit edge and the embedded fusion features of the target node of the unit edge respectively; Represents the element edge feature.

[0100] Then the output vector of MLP is split into four parts according to the set ratio: the first part is the weight parameter with a length of 1, the second and third parts are two groups of intermediate features of equal length, and the fourth part is used as the unit delay time prediction value.

[0101] The mathematical description of the splitting operation of the output vector of MLP is as follows:

[0102]

[0103]

[0104]

[0105]

[0106] in, Represents the segmentation vector The first value of Represents the vector The segmentation starts from the second value of ; Represents the vector No. The segmentation starts from the value, and the segmentation length is ; represents the predicted value of the cell delay of the cell edge; Represents the vector No. The value starts to split, and the split length is the vector dimension of the unit delay .

[0107] The first part of the result (i.e. weight parameter) is passed After the activation function is processed, the second and third parts (i.e., two sets of intermediate features) are multiplied respectively to obtain two sets of weighted intermediate features, and the two sets of weighted intermediate features of all unit edges connected to the same target node are summed and maximized respectively, and the values ​​obtained by the summation and maximum operations are concatenated, and finally the target node prediction value of the unit delay propagation layer is obtained through the multi-layer perceptron MLP output; the mathematical description of this process is as follows:

[0108]

[0109]

[0110]

[0111]

[0112] in, Represents the predicted value of the target node of the unit edge; Indicates that all connections are to the same target node The set of unit edges of ; and They represent summing and maximum value operations on feature sets respectively; express Activation function; u represents the edge source node;

[0113] S4: Input the training set into the RGAT-based graph neural network model, and then perform iterative training based on the Adam optimization algorithm to obtain a trained graph neural network model; specifically:

[0114] Use Adam optimization algorithm to optimize the overall loss function For optimization, the overall loss function is composed of the loss function of predicting arrival time and conversion time, the loss function of predicting connection delay time, and the loss function of predicting unit delay time. The formula is as follows:

[0115]

[0116] in is the loss function for predicting arrival time and transition time, , They are respectively the loss function for predicting the connection delay time and the loss function for predicting the unit delay time.

[0117]

[0118] in is the number of all nodes in the directed graph, It is the concatenation of the true value of the arrival time and the true value of the conversion time (label value). It is the concatenation of the arrival time prediction value and the conversion time prediction value.

[0119]

[0120] in is the number of fan-in nodes in the directed graph, is the actual value of the connection delay time, is the predicted value of the connection delay time.

[0121]

[0122] in is the number of unit edges in the directed graph, is the actual value of the unit delay time, is the predicted value of the unit delay time.

[0123] The post-routing timing result of the circuit can be obtained based on the arrival time prediction value and conversion time prediction value obtained by the connection delay propagation layer, the unit delay time prediction value obtained by the unit delay propagation layer, and the connection delay time prediction value predicted in the graph embedding stage.

[0124] S5: Model evaluation: input the test set into the trained graph neural network model, obtain the comparison results of the predicted arrival time and the actual arrival time of the graph neural network model based on RGAT, and calculate the evaluation index to evaluate the performance of the graph neural network model. The evaluation index adopts the determination coefficient ( ).when The closer it is to 1, the better the model fits the data and the predicted values ​​are highly correlated with the actual observed values.

[0125] The experimental environment parameters of the graph neural network model proposed in the present invention for predicting the arrival time of the timing endpoint after wiring are as follows in Table 1:

[0126] Table 1

[0127]

[0128] The prediction results of the trained model on the test set and the time it takes for the model to reach inference time are shown in Table 2:

[0129] Table 2

[0130]

[0131] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the attached claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention. Any figure mark in the claims should not be regarded as limiting the claims involved.

Claims

1. A method for timing prediction before circuit wiring based on graph neural network, characterized in that: The method comprises: Step S1: Construct a data set; specifically: Construct a directed graph based on real benchmark circuits; Obtain timing reports of real benchmark circuits and filter out characteristic parameters related to arrival time; Construct a data set with the directed graph and characteristic parameters related to the arrival time, and set labels at the same time; the labels include the arrival time, unit delay time, connection delay time, and conversion time of each device unit pin in the timing report; Step S2: Perform data cleaning and normalization on the generated data set, and divide the processed data set into a training set and a test set; Step S3: Build a graph neural network model based on RGAT, and train and test it using the training set and test set; Step S4: predicting the post-routing timing results of the circuit using the trained and tested RGAT-based graph neural network model; Step S1 specifically includes: S101: using the pins of the device units in the real reference circuit as nodes of the directed graph, and using the connection edges and unit edges of the device units as edges between the nodes of the directed graph, that is, the connection relationship between the nodes; wherein the connection edge is the connection between two device units, and the connection edge is set as a bidirectional edge; the unit edge is the connection relationship between the input pin and the output pin of the device unit itself, and the unit edge is set as a unidirectional edge; S102: Obtaining an adjacency matrix A of the directed graph according to the connection relationship between the nodes of the directed graph; S103: Generate a timing report of a real reference circuit; and select characteristic parameters related to the arrival time according to the timing report; The RGAT-based graph neural network model in step S3 includes a graph embedding stage and a delay propagation stage; The graph embedding stage is to update the node features of all nodes in the directed graph using RGAT with multi-layer residual connections; The delay propagation stage analyzes the topological level of the directed graph, and starts from the starting level of the topological level, and realizes the information propagation of the line-out edge or the unit edge layer by layer; the information propagation of the line-out edge and the unit edge is realized by the line delay propagation layer and the unit delay propagation layer respectively, until reaching the termination layer of the topological level; In the graph embedding stage of step S3, the first layer input of the multi-layer residual connection RGAT is the node feature; the input of the other layers except the first layer is the output of the previous layer; each layer of RGAT updates the input feature, and adds the input feature to the updated feature through the residual connection, and uses the addition result as the output of this layer; the result of the output of the last layer of RGAT is obtained by a multi-layer perceptron MLP to obtain the updated node feature, and the front ɑ vector dimension of the updated node feature is set as the connection delay time prediction value; The update of the input features by each layer of RGAT includes the attention head feature fusion stage, the relation head feature fusion stage, and the fusion stage; In the fusion stage, the feature vector after the attention head feature fusion and the feature vector after the relation head feature fusion are concatenated, and the result after linear transformation and relu activation function is residually connected with the input of the current layer to obtain the updated node feature; In the delayed propagation stage of step S3, in the wire delay propagation layer, the input of each wire delay propagation layer is the source node prediction value of the current wire outgoing edge, the embedded fusion feature of the source node, and the embedded fusion feature of the target node; wherein the source node prediction value of the wire outgoing edge adopts the target node prediction value of the previous unit delayed propagation layer, and the source node prediction value of the first wire delay propagation layer is initialized to 0; the embedded fusion feature of the source node is the result of the concatenation of the initial node feature of the source node and the node feature after the update in the graph embedding stage; the embedded fusion feature of the target node is the result of the concatenation of the initial node feature of the target node and the node feature after the update in the graph embedding stage; The source node prediction value of the current outgoing edge, the embedded fusion feature of the source node, and the embedded fusion feature of the target node are concatenated, and finally the target node prediction value is obtained through the multi-layer perceptron MLP output, which includes the predicted value of the arrival time and the predicted value of the conversion time; In the delayed propagation stage of step S3, in the unit delayed propagation layer, the input of each unit delayed propagation layer is the source node prediction value of the current unit edge, the embedded fusion feature of the source node, the embedded fusion feature of the target node, and the unit edge feature; the source node prediction value of the unit edge adopts the target node prediction value of the previous line delayed propagation layer; the embedded fusion feature of the source node is the result of the concatenation of the initial node feature of the source node and the node feature after the update in the graph embedding stage; the embedded fusion feature of the target node is the result of the concatenation of the initial node feature of the target node and the node feature after the update in the graph embedding stage; The source node prediction value of the current cell edge, the embedded fusion feature of the source node, the embedded fusion feature of the target node, and the cell edge feature are concatenated and then output through the multi-layer perceptron MLP; Then the output vector of the multi-layer perceptron MLP is split into four parts: the first part is the weight parameter with a length of 1, the second and third parts are two groups of intermediate features of equal length, and the fourth part is the unit delay time prediction value; The first part of the results After the activation function is processed, the second and third parts are multiplied respectively to obtain two sets of weighted intermediate features; then the two sets of weighted intermediate features of all unit edges connected to the same target node are summed and maximized respectively, and then the summation and maximum operation results are concatenated, and finally the target node prediction value of the unit delay propagation layer is obtained through the multi-layer perceptron MLP output; The loss function of the RGAT-based graph neural network model training in step S3 consists of the loss function of predicting the arrival time and the conversion time, the loss function of predicting the connection delay time, and the loss function of predicting the unit delay time. The formula is as follows: Formula (1) in is the loss function for predicting arrival time and transition time, , They are the loss function for predicting the connection delay time and the loss function for predicting the unit delay time; Formula (2) in is the number of all nodes in the directed graph, It is the concatenation of the true value of the arrival time and the true value of the conversion time. It is the concatenation of the arrival time prediction value and the conversion time prediction value; Formula (3) in is the number of fan-in nodes in the directed graph, is the actual value of the connection delay time, is the predicted value of connection delay time; Formula (4) in is the number of unit edges in the directed graph, is the actual value of the unit delay time, is the predicted value of the unit delay time.

2. The method according to claim 1, characterized in that: The characteristic parameters related to the arrival time in step S103 include node characteristics and unit edge characteristics.

3. The method according to claim 1, characterized in that: The node features in step S103 include the distance relative to the four boundaries of the chip in the real benchmark circuit, the pin capacitance, the pin type, and the node type; the pin type includes the PI pin and the PO pin; the node type includes the fan-in node and the fan-out node; the unit edge features include the index value and the delay value of the LUT lookup table.

4. The method according to claim 1, characterized in that: In the delayed propagation phase of step S3, the initial layers of the topological layers of the directed graph are all composed of source nodes of the connected outgoing edges.

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